omap-dmic.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549
  1. /*
  2. * omap-dmic.c -- OMAP ASoC DMIC DAI driver
  3. *
  4. * Copyright (C) 2010 - 2011 Texas Instruments
  5. *
  6. * Author: David Lambert <dlambert@ti.com>
  7. * Misael Lopez Cruz <misael.lopez@ti.com>
  8. * Liam Girdwood <lrg@ti.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. *
  25. */
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/err.h>
  30. #include <linux/clk.h>
  31. #include <linux/io.h>
  32. #include <linux/slab.h>
  33. #include <linux/pm_runtime.h>
  34. #include <plat/dma.h>
  35. #include <sound/core.h>
  36. #include <sound/pcm.h>
  37. #include <sound/pcm_params.h>
  38. #include <sound/initval.h>
  39. #include <sound/soc.h>
  40. #include "omap-pcm.h"
  41. #include "omap-dmic.h"
  42. struct omap_dmic {
  43. struct device *dev;
  44. void __iomem *io_base;
  45. struct clk *fclk;
  46. int fclk_freq;
  47. int out_freq;
  48. int clk_div;
  49. int sysclk;
  50. int threshold;
  51. u32 ch_enabled;
  52. bool active;
  53. struct mutex mutex;
  54. };
  55. /*
  56. * Stream DMA parameters
  57. */
  58. static struct omap_pcm_dma_data omap_dmic_dai_dma_params = {
  59. .name = "DMIC capture",
  60. .data_type = OMAP_DMA_DATA_TYPE_S32,
  61. .sync_mode = OMAP_DMA_SYNC_PACKET,
  62. };
  63. static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
  64. {
  65. __raw_writel(val, dmic->io_base + reg);
  66. }
  67. static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
  68. {
  69. return __raw_readl(dmic->io_base + reg);
  70. }
  71. static inline void omap_dmic_start(struct omap_dmic *dmic)
  72. {
  73. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  74. /* Configure DMA controller */
  75. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
  76. OMAP_DMIC_DMA_ENABLE);
  77. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
  78. }
  79. static inline void omap_dmic_stop(struct omap_dmic *dmic)
  80. {
  81. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  82. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  83. ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
  84. /* Disable DMA request generation */
  85. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
  86. OMAP_DMIC_DMA_ENABLE);
  87. }
  88. static inline int dmic_is_enabled(struct omap_dmic *dmic)
  89. {
  90. return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
  91. OMAP_DMIC_UP_ENABLE_MASK;
  92. }
  93. static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
  94. struct snd_soc_dai *dai)
  95. {
  96. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  97. int ret = 0;
  98. mutex_lock(&dmic->mutex);
  99. if (!dai->active) {
  100. pm_runtime_get_sync(dmic->dev);
  101. snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24);
  102. dmic->active = 1;
  103. } else {
  104. ret = -EBUSY;
  105. }
  106. mutex_unlock(&dmic->mutex);
  107. return ret;
  108. }
  109. static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
  110. struct snd_soc_dai *dai)
  111. {
  112. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  113. mutex_lock(&dmic->mutex);
  114. if (!dai->active) {
  115. pm_runtime_put_sync(dmic->dev);
  116. dmic->active = 0;
  117. }
  118. mutex_unlock(&dmic->mutex);
  119. }
  120. static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
  121. {
  122. int divider = -EINVAL;
  123. /*
  124. * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
  125. * configuration.
  126. */
  127. if (sample_rate == 192000) {
  128. if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
  129. divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
  130. else
  131. dev_err(dmic->dev,
  132. "invalid clock configuration for 192KHz\n");
  133. return divider;
  134. }
  135. switch (dmic->out_freq) {
  136. case 1536000:
  137. if (dmic->fclk_freq != 24576000)
  138. goto div_err;
  139. divider = 0x4; /* Divider: 16 */
  140. break;
  141. case 2400000:
  142. switch (dmic->fclk_freq) {
  143. case 12000000:
  144. divider = 0x5; /* Divider: 5 */
  145. break;
  146. case 19200000:
  147. divider = 0x0; /* Divider: 8 */
  148. break;
  149. case 24000000:
  150. divider = 0x2; /* Divider: 10 */
  151. break;
  152. default:
  153. goto div_err;
  154. }
  155. break;
  156. case 3072000:
  157. if (dmic->fclk_freq != 24576000)
  158. goto div_err;
  159. divider = 0x3; /* Divider: 8 */
  160. break;
  161. case 3840000:
  162. if (dmic->fclk_freq != 19200000)
  163. goto div_err;
  164. divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
  165. break;
  166. default:
  167. dev_err(dmic->dev, "invalid out frequency: %dHz\n",
  168. dmic->out_freq);
  169. break;
  170. }
  171. return divider;
  172. div_err:
  173. dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
  174. dmic->out_freq, dmic->fclk_freq);
  175. return -EINVAL;
  176. }
  177. static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
  178. struct snd_pcm_hw_params *params,
  179. struct snd_soc_dai *dai)
  180. {
  181. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  182. int channels;
  183. dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
  184. if (dmic->clk_div < 0) {
  185. dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
  186. dmic->out_freq, dmic->fclk_freq);
  187. return -EINVAL;
  188. }
  189. dmic->ch_enabled = 0;
  190. channels = params_channels(params);
  191. switch (channels) {
  192. case 6:
  193. dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
  194. case 4:
  195. dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
  196. case 2:
  197. dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
  198. break;
  199. default:
  200. dev_err(dmic->dev, "invalid number of legacy channels\n");
  201. return -EINVAL;
  202. }
  203. /* packet size is threshold * channels */
  204. omap_dmic_dai_dma_params.packet_size = dmic->threshold * channels;
  205. snd_soc_dai_set_dma_data(dai, substream, &omap_dmic_dai_dma_params);
  206. return 0;
  207. }
  208. static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
  209. struct snd_soc_dai *dai)
  210. {
  211. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  212. u32 ctrl;
  213. /* Configure uplink threshold */
  214. omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
  215. ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  216. /* Set dmic out format */
  217. ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
  218. ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  219. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  220. /* Configure dmic clock divider */
  221. ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
  222. ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
  223. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
  224. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  225. ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  226. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  227. return 0;
  228. }
  229. static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
  230. int cmd, struct snd_soc_dai *dai)
  231. {
  232. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  233. switch (cmd) {
  234. case SNDRV_PCM_TRIGGER_START:
  235. omap_dmic_start(dmic);
  236. break;
  237. case SNDRV_PCM_TRIGGER_STOP:
  238. omap_dmic_stop(dmic);
  239. break;
  240. default:
  241. break;
  242. }
  243. return 0;
  244. }
  245. static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
  246. unsigned int freq)
  247. {
  248. struct clk *parent_clk;
  249. char *parent_clk_name;
  250. int ret = 0;
  251. switch (freq) {
  252. case 12000000:
  253. case 19200000:
  254. case 24000000:
  255. case 24576000:
  256. break;
  257. default:
  258. dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
  259. dmic->fclk_freq = 0;
  260. return -EINVAL;
  261. }
  262. if (dmic->sysclk == clk_id) {
  263. dmic->fclk_freq = freq;
  264. return 0;
  265. }
  266. /* re-parent not allowed if a stream is ongoing */
  267. if (dmic->active && dmic_is_enabled(dmic)) {
  268. dev_err(dmic->dev, "can't re-parent when DMIC active\n");
  269. return -EBUSY;
  270. }
  271. switch (clk_id) {
  272. case OMAP_DMIC_SYSCLK_PAD_CLKS:
  273. parent_clk_name = "pad_clks_ck";
  274. break;
  275. case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
  276. parent_clk_name = "slimbus_clk";
  277. break;
  278. case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
  279. parent_clk_name = "dmic_sync_mux_ck";
  280. break;
  281. default:
  282. dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
  283. return -EINVAL;
  284. }
  285. parent_clk = clk_get(dmic->dev, parent_clk_name);
  286. if (IS_ERR(parent_clk)) {
  287. dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
  288. return -ENODEV;
  289. }
  290. mutex_lock(&dmic->mutex);
  291. if (dmic->active) {
  292. /* disable clock while reparenting */
  293. pm_runtime_put_sync(dmic->dev);
  294. ret = clk_set_parent(dmic->fclk, parent_clk);
  295. pm_runtime_get_sync(dmic->dev);
  296. } else {
  297. ret = clk_set_parent(dmic->fclk, parent_clk);
  298. }
  299. mutex_unlock(&dmic->mutex);
  300. if (ret < 0) {
  301. dev_err(dmic->dev, "re-parent failed\n");
  302. goto err_busy;
  303. }
  304. dmic->sysclk = clk_id;
  305. dmic->fclk_freq = freq;
  306. err_busy:
  307. clk_put(parent_clk);
  308. return ret;
  309. }
  310. static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
  311. unsigned int freq)
  312. {
  313. int ret = 0;
  314. if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
  315. dev_err(dmic->dev, "output clk_id (%d) not supported\n",
  316. clk_id);
  317. return -EINVAL;
  318. }
  319. switch (freq) {
  320. case 1536000:
  321. case 2400000:
  322. case 3072000:
  323. case 3840000:
  324. dmic->out_freq = freq;
  325. break;
  326. default:
  327. dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
  328. dmic->out_freq = 0;
  329. ret = -EINVAL;
  330. }
  331. return ret;
  332. }
  333. static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  334. unsigned int freq, int dir)
  335. {
  336. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  337. if (dir == SND_SOC_CLOCK_IN)
  338. return omap_dmic_select_fclk(dmic, clk_id, freq);
  339. else if (dir == SND_SOC_CLOCK_OUT)
  340. return omap_dmic_select_outclk(dmic, clk_id, freq);
  341. dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
  342. return -EINVAL;
  343. }
  344. static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
  345. .startup = omap_dmic_dai_startup,
  346. .shutdown = omap_dmic_dai_shutdown,
  347. .hw_params = omap_dmic_dai_hw_params,
  348. .prepare = omap_dmic_dai_prepare,
  349. .trigger = omap_dmic_dai_trigger,
  350. .set_sysclk = omap_dmic_set_dai_sysclk,
  351. };
  352. static int omap_dmic_probe(struct snd_soc_dai *dai)
  353. {
  354. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  355. pm_runtime_enable(dmic->dev);
  356. /* Disable lines while request is ongoing */
  357. pm_runtime_get_sync(dmic->dev);
  358. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
  359. pm_runtime_put_sync(dmic->dev);
  360. /* Configure DMIC threshold value */
  361. dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
  362. return 0;
  363. }
  364. static int omap_dmic_remove(struct snd_soc_dai *dai)
  365. {
  366. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  367. pm_runtime_disable(dmic->dev);
  368. return 0;
  369. }
  370. static struct snd_soc_dai_driver omap_dmic_dai = {
  371. .name = "omap-dmic",
  372. .probe = omap_dmic_probe,
  373. .remove = omap_dmic_remove,
  374. .capture = {
  375. .channels_min = 2,
  376. .channels_max = 6,
  377. .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
  378. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  379. },
  380. .ops = &omap_dmic_dai_ops,
  381. };
  382. static __devinit int asoc_dmic_probe(struct platform_device *pdev)
  383. {
  384. struct omap_dmic *dmic;
  385. struct resource *res;
  386. int ret;
  387. dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
  388. if (!dmic)
  389. return -ENOMEM;
  390. platform_set_drvdata(pdev, dmic);
  391. dmic->dev = &pdev->dev;
  392. dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
  393. mutex_init(&dmic->mutex);
  394. dmic->fclk = clk_get(dmic->dev, "dmic_fck");
  395. if (IS_ERR(dmic->fclk)) {
  396. dev_err(dmic->dev, "cant get dmic_fck\n");
  397. return -ENODEV;
  398. }
  399. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  400. if (!res) {
  401. dev_err(dmic->dev, "invalid dma memory resource\n");
  402. ret = -ENODEV;
  403. goto err_put_clk;
  404. }
  405. omap_dmic_dai_dma_params.port_addr = res->start + OMAP_DMIC_DATA_REG;
  406. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  407. if (!res) {
  408. dev_err(dmic->dev, "invalid dma resource\n");
  409. ret = -ENODEV;
  410. goto err_put_clk;
  411. }
  412. omap_dmic_dai_dma_params.dma_req = res->start;
  413. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  414. if (!res) {
  415. dev_err(dmic->dev, "invalid memory resource\n");
  416. ret = -ENODEV;
  417. goto err_put_clk;
  418. }
  419. if (!devm_request_mem_region(&pdev->dev, res->start,
  420. resource_size(res), pdev->name)) {
  421. dev_err(dmic->dev, "memory region already claimed\n");
  422. ret = -ENODEV;
  423. goto err_put_clk;
  424. }
  425. dmic->io_base = devm_ioremap(&pdev->dev, res->start,
  426. resource_size(res));
  427. if (!dmic->io_base) {
  428. ret = -ENOMEM;
  429. goto err_put_clk;
  430. }
  431. ret = snd_soc_register_dai(&pdev->dev, &omap_dmic_dai);
  432. if (ret)
  433. goto err_put_clk;
  434. return 0;
  435. err_put_clk:
  436. clk_put(dmic->fclk);
  437. return ret;
  438. }
  439. static int __devexit asoc_dmic_remove(struct platform_device *pdev)
  440. {
  441. struct omap_dmic *dmic = platform_get_drvdata(pdev);
  442. snd_soc_unregister_dai(&pdev->dev);
  443. clk_put(dmic->fclk);
  444. return 0;
  445. }
  446. static struct platform_driver asoc_dmic_driver = {
  447. .driver = {
  448. .name = "omap-dmic",
  449. .owner = THIS_MODULE,
  450. },
  451. .probe = asoc_dmic_probe,
  452. .remove = __devexit_p(asoc_dmic_remove),
  453. };
  454. module_platform_driver(asoc_dmic_driver);
  455. MODULE_ALIAS("platform:omap-dmic");
  456. MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
  457. MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
  458. MODULE_LICENSE("GPL");