mthca_srq.c 17 KB

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  1. /*
  2. * Copyright (c) 2005 Cisco Systems. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. * $Id: mthca_srq.c 3047 2005-08-10 03:59:35Z roland $
  33. */
  34. #include <linux/slab.h>
  35. #include <linux/string.h>
  36. #include "mthca_dev.h"
  37. #include "mthca_cmd.h"
  38. #include "mthca_memfree.h"
  39. #include "mthca_wqe.h"
  40. enum {
  41. MTHCA_MAX_DIRECT_SRQ_SIZE = 4 * PAGE_SIZE
  42. };
  43. struct mthca_tavor_srq_context {
  44. __be64 wqe_base_ds; /* low 6 bits is descriptor size */
  45. __be32 state_pd;
  46. __be32 lkey;
  47. __be32 uar;
  48. __be16 limit_watermark;
  49. __be16 wqe_cnt;
  50. u32 reserved[2];
  51. };
  52. struct mthca_arbel_srq_context {
  53. __be32 state_logsize_srqn;
  54. __be32 lkey;
  55. __be32 db_index;
  56. __be32 logstride_usrpage;
  57. __be64 wqe_base;
  58. __be32 eq_pd;
  59. __be16 limit_watermark;
  60. __be16 wqe_cnt;
  61. u16 reserved1;
  62. __be16 wqe_counter;
  63. u32 reserved2[3];
  64. };
  65. static void *get_wqe(struct mthca_srq *srq, int n)
  66. {
  67. if (srq->is_direct)
  68. return srq->queue.direct.buf + (n << srq->wqe_shift);
  69. else
  70. return srq->queue.page_list[(n << srq->wqe_shift) >> PAGE_SHIFT].buf +
  71. ((n << srq->wqe_shift) & (PAGE_SIZE - 1));
  72. }
  73. /*
  74. * Return a pointer to the location within a WQE that we're using as a
  75. * link when the WQE is in the free list. We use the imm field
  76. * because in the Tavor case, posting a WQE may overwrite the next
  77. * segment of the previous WQE, but a receive WQE will never touch the
  78. * imm field. This avoids corrupting our free list if the previous
  79. * WQE has already completed and been put on the free list when we
  80. * post the next WQE.
  81. */
  82. static inline int *wqe_to_link(void *wqe)
  83. {
  84. return (int *) (wqe + offsetof(struct mthca_next_seg, imm));
  85. }
  86. static void mthca_tavor_init_srq_context(struct mthca_dev *dev,
  87. struct mthca_pd *pd,
  88. struct mthca_srq *srq,
  89. struct mthca_tavor_srq_context *context)
  90. {
  91. memset(context, 0, sizeof *context);
  92. context->wqe_base_ds = cpu_to_be64(1 << (srq->wqe_shift - 4));
  93. context->state_pd = cpu_to_be32(pd->pd_num);
  94. context->lkey = cpu_to_be32(srq->mr.ibmr.lkey);
  95. if (pd->ibpd.uobject)
  96. context->uar =
  97. cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index);
  98. else
  99. context->uar = cpu_to_be32(dev->driver_uar.index);
  100. }
  101. static void mthca_arbel_init_srq_context(struct mthca_dev *dev,
  102. struct mthca_pd *pd,
  103. struct mthca_srq *srq,
  104. struct mthca_arbel_srq_context *context)
  105. {
  106. int logsize;
  107. memset(context, 0, sizeof *context);
  108. logsize = long_log2(srq->max) + srq->wqe_shift;
  109. context->state_logsize_srqn = cpu_to_be32(logsize << 24 | srq->srqn);
  110. context->lkey = cpu_to_be32(srq->mr.ibmr.lkey);
  111. context->db_index = cpu_to_be32(srq->db_index);
  112. context->logstride_usrpage = cpu_to_be32((srq->wqe_shift - 4) << 29);
  113. if (pd->ibpd.uobject)
  114. context->logstride_usrpage |=
  115. cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index);
  116. else
  117. context->logstride_usrpage |= cpu_to_be32(dev->driver_uar.index);
  118. context->eq_pd = cpu_to_be32(MTHCA_EQ_ASYNC << 24 | pd->pd_num);
  119. }
  120. static void mthca_free_srq_buf(struct mthca_dev *dev, struct mthca_srq *srq)
  121. {
  122. mthca_buf_free(dev, srq->max << srq->wqe_shift, &srq->queue,
  123. srq->is_direct, &srq->mr);
  124. kfree(srq->wrid);
  125. }
  126. static int mthca_alloc_srq_buf(struct mthca_dev *dev, struct mthca_pd *pd,
  127. struct mthca_srq *srq)
  128. {
  129. struct mthca_data_seg *scatter;
  130. void *wqe;
  131. int err;
  132. int i;
  133. if (pd->ibpd.uobject)
  134. return 0;
  135. srq->wrid = kmalloc(srq->max * sizeof (u64), GFP_KERNEL);
  136. if (!srq->wrid)
  137. return -ENOMEM;
  138. err = mthca_buf_alloc(dev, srq->max << srq->wqe_shift,
  139. MTHCA_MAX_DIRECT_SRQ_SIZE,
  140. &srq->queue, &srq->is_direct, pd, 1, &srq->mr);
  141. if (err) {
  142. kfree(srq->wrid);
  143. return err;
  144. }
  145. /*
  146. * Now initialize the SRQ buffer so that all of the WQEs are
  147. * linked into the list of free WQEs. In addition, set the
  148. * scatter list L_Keys to the sentry value of 0x100.
  149. */
  150. for (i = 0; i < srq->max; ++i) {
  151. wqe = get_wqe(srq, i);
  152. *wqe_to_link(wqe) = i < srq->max - 1 ? i + 1 : -1;
  153. for (scatter = wqe + sizeof (struct mthca_next_seg);
  154. (void *) scatter < wqe + (1 << srq->wqe_shift);
  155. ++scatter)
  156. scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
  157. }
  158. srq->last = get_wqe(srq, srq->max - 1);
  159. return 0;
  160. }
  161. int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
  162. struct ib_srq_attr *attr, struct mthca_srq *srq)
  163. {
  164. struct mthca_mailbox *mailbox;
  165. u8 status;
  166. int ds;
  167. int err;
  168. /* Sanity check SRQ size before proceeding */
  169. if (attr->max_wr > dev->limits.max_srq_wqes ||
  170. attr->max_sge > dev->limits.max_sg)
  171. return -EINVAL;
  172. srq->max = attr->max_wr;
  173. srq->max_gs = attr->max_sge;
  174. srq->counter = 0;
  175. if (mthca_is_memfree(dev))
  176. srq->max = roundup_pow_of_two(srq->max + 1);
  177. ds = max(64UL,
  178. roundup_pow_of_two(sizeof (struct mthca_next_seg) +
  179. srq->max_gs * sizeof (struct mthca_data_seg)));
  180. srq->wqe_shift = long_log2(ds);
  181. srq->srqn = mthca_alloc(&dev->srq_table.alloc);
  182. if (srq->srqn == -1)
  183. return -ENOMEM;
  184. if (mthca_is_memfree(dev)) {
  185. err = mthca_table_get(dev, dev->srq_table.table, srq->srqn);
  186. if (err)
  187. goto err_out;
  188. if (!pd->ibpd.uobject) {
  189. srq->db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SRQ,
  190. srq->srqn, &srq->db);
  191. if (srq->db_index < 0) {
  192. err = -ENOMEM;
  193. goto err_out_icm;
  194. }
  195. }
  196. }
  197. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  198. if (IS_ERR(mailbox)) {
  199. err = PTR_ERR(mailbox);
  200. goto err_out_db;
  201. }
  202. err = mthca_alloc_srq_buf(dev, pd, srq);
  203. if (err)
  204. goto err_out_mailbox;
  205. spin_lock_init(&srq->lock);
  206. atomic_set(&srq->refcount, 1);
  207. init_waitqueue_head(&srq->wait);
  208. if (mthca_is_memfree(dev))
  209. mthca_arbel_init_srq_context(dev, pd, srq, mailbox->buf);
  210. else
  211. mthca_tavor_init_srq_context(dev, pd, srq, mailbox->buf);
  212. err = mthca_SW2HW_SRQ(dev, mailbox, srq->srqn, &status);
  213. if (err) {
  214. mthca_warn(dev, "SW2HW_SRQ failed (%d)\n", err);
  215. goto err_out_free_buf;
  216. }
  217. if (status) {
  218. mthca_warn(dev, "SW2HW_SRQ returned status 0x%02x\n",
  219. status);
  220. err = -EINVAL;
  221. goto err_out_free_buf;
  222. }
  223. spin_lock_irq(&dev->srq_table.lock);
  224. if (mthca_array_set(&dev->srq_table.srq,
  225. srq->srqn & (dev->limits.num_srqs - 1),
  226. srq)) {
  227. spin_unlock_irq(&dev->srq_table.lock);
  228. goto err_out_free_srq;
  229. }
  230. spin_unlock_irq(&dev->srq_table.lock);
  231. mthca_free_mailbox(dev, mailbox);
  232. srq->first_free = 0;
  233. srq->last_free = srq->max - 1;
  234. attr->max_wr = (mthca_is_memfree(dev)) ? srq->max - 1 : srq->max;
  235. attr->max_sge = srq->max_gs;
  236. return 0;
  237. err_out_free_srq:
  238. err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status);
  239. if (err)
  240. mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err);
  241. else if (status)
  242. mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status);
  243. err_out_free_buf:
  244. if (!pd->ibpd.uobject)
  245. mthca_free_srq_buf(dev, srq);
  246. err_out_mailbox:
  247. mthca_free_mailbox(dev, mailbox);
  248. err_out_db:
  249. if (!pd->ibpd.uobject && mthca_is_memfree(dev))
  250. mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index);
  251. err_out_icm:
  252. mthca_table_put(dev, dev->srq_table.table, srq->srqn);
  253. err_out:
  254. mthca_free(&dev->srq_table.alloc, srq->srqn);
  255. return err;
  256. }
  257. void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq)
  258. {
  259. struct mthca_mailbox *mailbox;
  260. int err;
  261. u8 status;
  262. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  263. if (IS_ERR(mailbox)) {
  264. mthca_warn(dev, "No memory for mailbox to free SRQ.\n");
  265. return;
  266. }
  267. err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status);
  268. if (err)
  269. mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err);
  270. else if (status)
  271. mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status);
  272. spin_lock_irq(&dev->srq_table.lock);
  273. mthca_array_clear(&dev->srq_table.srq,
  274. srq->srqn & (dev->limits.num_srqs - 1));
  275. spin_unlock_irq(&dev->srq_table.lock);
  276. atomic_dec(&srq->refcount);
  277. wait_event(srq->wait, !atomic_read(&srq->refcount));
  278. if (!srq->ibsrq.uobject) {
  279. mthca_free_srq_buf(dev, srq);
  280. if (mthca_is_memfree(dev))
  281. mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index);
  282. }
  283. mthca_table_put(dev, dev->srq_table.table, srq->srqn);
  284. mthca_free(&dev->srq_table.alloc, srq->srqn);
  285. mthca_free_mailbox(dev, mailbox);
  286. }
  287. int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
  288. enum ib_srq_attr_mask attr_mask)
  289. {
  290. struct mthca_dev *dev = to_mdev(ibsrq->device);
  291. struct mthca_srq *srq = to_msrq(ibsrq);
  292. int ret;
  293. u8 status;
  294. /* We don't support resizing SRQs (yet?) */
  295. if (attr_mask & IB_SRQ_MAX_WR)
  296. return -EINVAL;
  297. if (attr_mask & IB_SRQ_LIMIT) {
  298. ret = mthca_ARM_SRQ(dev, srq->srqn, attr->srq_limit, &status);
  299. if (ret)
  300. return ret;
  301. if (status)
  302. return -EINVAL;
  303. }
  304. return 0;
  305. }
  306. int mthca_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr)
  307. {
  308. struct mthca_dev *dev = to_mdev(ibsrq->device);
  309. struct mthca_srq *srq = to_msrq(ibsrq);
  310. struct mthca_mailbox *mailbox;
  311. struct mthca_arbel_srq_context *arbel_ctx;
  312. struct mthca_tavor_srq_context *tavor_ctx;
  313. u8 status;
  314. int err;
  315. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  316. if (IS_ERR(mailbox))
  317. return PTR_ERR(mailbox);
  318. err = mthca_QUERY_SRQ(dev, srq->srqn, mailbox, &status);
  319. if (err)
  320. goto out;
  321. if (mthca_is_memfree(dev)) {
  322. arbel_ctx = mailbox->buf;
  323. srq_attr->srq_limit = be16_to_cpu(arbel_ctx->limit_watermark);
  324. } else {
  325. tavor_ctx = mailbox->buf;
  326. srq_attr->srq_limit = be16_to_cpu(tavor_ctx->limit_watermark);
  327. }
  328. srq_attr->max_wr = (mthca_is_memfree(dev)) ? srq->max - 1 : srq->max;
  329. srq_attr->max_sge = srq->max_gs;
  330. out:
  331. mthca_free_mailbox(dev, mailbox);
  332. return err;
  333. }
  334. void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
  335. enum ib_event_type event_type)
  336. {
  337. struct mthca_srq *srq;
  338. struct ib_event event;
  339. spin_lock(&dev->srq_table.lock);
  340. srq = mthca_array_get(&dev->srq_table.srq, srqn & (dev->limits.num_srqs - 1));
  341. if (srq)
  342. atomic_inc(&srq->refcount);
  343. spin_unlock(&dev->srq_table.lock);
  344. if (!srq) {
  345. mthca_warn(dev, "Async event for bogus SRQ %08x\n", srqn);
  346. return;
  347. }
  348. if (!srq->ibsrq.event_handler)
  349. goto out;
  350. event.device = &dev->ib_dev;
  351. event.event = event_type;
  352. event.element.srq = &srq->ibsrq;
  353. srq->ibsrq.event_handler(&event, srq->ibsrq.srq_context);
  354. out:
  355. if (atomic_dec_and_test(&srq->refcount))
  356. wake_up(&srq->wait);
  357. }
  358. /*
  359. * This function must be called with IRQs disabled.
  360. */
  361. void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr)
  362. {
  363. int ind;
  364. ind = wqe_addr >> srq->wqe_shift;
  365. spin_lock(&srq->lock);
  366. if (likely(srq->first_free >= 0))
  367. *wqe_to_link(get_wqe(srq, srq->last_free)) = ind;
  368. else
  369. srq->first_free = ind;
  370. *wqe_to_link(get_wqe(srq, ind)) = -1;
  371. srq->last_free = ind;
  372. spin_unlock(&srq->lock);
  373. }
  374. int mthca_tavor_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
  375. struct ib_recv_wr **bad_wr)
  376. {
  377. struct mthca_dev *dev = to_mdev(ibsrq->device);
  378. struct mthca_srq *srq = to_msrq(ibsrq);
  379. __be32 doorbell[2];
  380. unsigned long flags;
  381. int err = 0;
  382. int first_ind;
  383. int ind;
  384. int next_ind;
  385. int nreq;
  386. int i;
  387. void *wqe;
  388. void *prev_wqe;
  389. spin_lock_irqsave(&srq->lock, flags);
  390. first_ind = srq->first_free;
  391. for (nreq = 0; wr; ++nreq, wr = wr->next) {
  392. if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
  393. nreq = 0;
  394. doorbell[0] = cpu_to_be32(first_ind << srq->wqe_shift);
  395. doorbell[1] = cpu_to_be32(srq->srqn << 8);
  396. /*
  397. * Make sure that descriptors are written
  398. * before doorbell is rung.
  399. */
  400. wmb();
  401. mthca_write64(doorbell,
  402. dev->kar + MTHCA_RECEIVE_DOORBELL,
  403. MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
  404. first_ind = srq->first_free;
  405. }
  406. ind = srq->first_free;
  407. if (ind < 0) {
  408. mthca_err(dev, "SRQ %06x full\n", srq->srqn);
  409. err = -ENOMEM;
  410. *bad_wr = wr;
  411. break;
  412. }
  413. wqe = get_wqe(srq, ind);
  414. next_ind = *wqe_to_link(wqe);
  415. if (next_ind < 0) {
  416. mthca_err(dev, "SRQ %06x full\n", srq->srqn);
  417. err = -ENOMEM;
  418. *bad_wr = wr;
  419. break;
  420. }
  421. prev_wqe = srq->last;
  422. srq->last = wqe;
  423. ((struct mthca_next_seg *) wqe)->nda_op = 0;
  424. ((struct mthca_next_seg *) wqe)->ee_nds = 0;
  425. /* flags field will always remain 0 */
  426. wqe += sizeof (struct mthca_next_seg);
  427. if (unlikely(wr->num_sge > srq->max_gs)) {
  428. err = -EINVAL;
  429. *bad_wr = wr;
  430. srq->last = prev_wqe;
  431. break;
  432. }
  433. for (i = 0; i < wr->num_sge; ++i) {
  434. ((struct mthca_data_seg *) wqe)->byte_count =
  435. cpu_to_be32(wr->sg_list[i].length);
  436. ((struct mthca_data_seg *) wqe)->lkey =
  437. cpu_to_be32(wr->sg_list[i].lkey);
  438. ((struct mthca_data_seg *) wqe)->addr =
  439. cpu_to_be64(wr->sg_list[i].addr);
  440. wqe += sizeof (struct mthca_data_seg);
  441. }
  442. if (i < srq->max_gs) {
  443. ((struct mthca_data_seg *) wqe)->byte_count = 0;
  444. ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
  445. ((struct mthca_data_seg *) wqe)->addr = 0;
  446. }
  447. ((struct mthca_next_seg *) prev_wqe)->nda_op =
  448. cpu_to_be32((ind << srq->wqe_shift) | 1);
  449. wmb();
  450. ((struct mthca_next_seg *) prev_wqe)->ee_nds =
  451. cpu_to_be32(MTHCA_NEXT_DBD);
  452. srq->wrid[ind] = wr->wr_id;
  453. srq->first_free = next_ind;
  454. }
  455. if (likely(nreq)) {
  456. doorbell[0] = cpu_to_be32(first_ind << srq->wqe_shift);
  457. doorbell[1] = cpu_to_be32((srq->srqn << 8) | nreq);
  458. /*
  459. * Make sure that descriptors are written before
  460. * doorbell is rung.
  461. */
  462. wmb();
  463. mthca_write64(doorbell,
  464. dev->kar + MTHCA_RECEIVE_DOORBELL,
  465. MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
  466. }
  467. spin_unlock_irqrestore(&srq->lock, flags);
  468. return err;
  469. }
  470. int mthca_arbel_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
  471. struct ib_recv_wr **bad_wr)
  472. {
  473. struct mthca_dev *dev = to_mdev(ibsrq->device);
  474. struct mthca_srq *srq = to_msrq(ibsrq);
  475. unsigned long flags;
  476. int err = 0;
  477. int ind;
  478. int next_ind;
  479. int nreq;
  480. int i;
  481. void *wqe;
  482. spin_lock_irqsave(&srq->lock, flags);
  483. for (nreq = 0; wr; ++nreq, wr = wr->next) {
  484. ind = srq->first_free;
  485. if (ind < 0) {
  486. mthca_err(dev, "SRQ %06x full\n", srq->srqn);
  487. err = -ENOMEM;
  488. *bad_wr = wr;
  489. break;
  490. }
  491. wqe = get_wqe(srq, ind);
  492. next_ind = *wqe_to_link(wqe);
  493. if (next_ind < 0) {
  494. mthca_err(dev, "SRQ %06x full\n", srq->srqn);
  495. err = -ENOMEM;
  496. *bad_wr = wr;
  497. break;
  498. }
  499. ((struct mthca_next_seg *) wqe)->nda_op =
  500. cpu_to_be32((next_ind << srq->wqe_shift) | 1);
  501. ((struct mthca_next_seg *) wqe)->ee_nds = 0;
  502. /* flags field will always remain 0 */
  503. wqe += sizeof (struct mthca_next_seg);
  504. if (unlikely(wr->num_sge > srq->max_gs)) {
  505. err = -EINVAL;
  506. *bad_wr = wr;
  507. break;
  508. }
  509. for (i = 0; i < wr->num_sge; ++i) {
  510. ((struct mthca_data_seg *) wqe)->byte_count =
  511. cpu_to_be32(wr->sg_list[i].length);
  512. ((struct mthca_data_seg *) wqe)->lkey =
  513. cpu_to_be32(wr->sg_list[i].lkey);
  514. ((struct mthca_data_seg *) wqe)->addr =
  515. cpu_to_be64(wr->sg_list[i].addr);
  516. wqe += sizeof (struct mthca_data_seg);
  517. }
  518. if (i < srq->max_gs) {
  519. ((struct mthca_data_seg *) wqe)->byte_count = 0;
  520. ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
  521. ((struct mthca_data_seg *) wqe)->addr = 0;
  522. }
  523. srq->wrid[ind] = wr->wr_id;
  524. srq->first_free = next_ind;
  525. }
  526. if (likely(nreq)) {
  527. srq->counter += nreq;
  528. /*
  529. * Make sure that descriptors are written before
  530. * we write doorbell record.
  531. */
  532. wmb();
  533. *srq->db = cpu_to_be32(srq->counter);
  534. }
  535. spin_unlock_irqrestore(&srq->lock, flags);
  536. return err;
  537. }
  538. int __devinit mthca_init_srq_table(struct mthca_dev *dev)
  539. {
  540. int err;
  541. if (!(dev->mthca_flags & MTHCA_FLAG_SRQ))
  542. return 0;
  543. spin_lock_init(&dev->srq_table.lock);
  544. err = mthca_alloc_init(&dev->srq_table.alloc,
  545. dev->limits.num_srqs,
  546. dev->limits.num_srqs - 1,
  547. dev->limits.reserved_srqs);
  548. if (err)
  549. return err;
  550. err = mthca_array_init(&dev->srq_table.srq,
  551. dev->limits.num_srqs);
  552. if (err)
  553. mthca_alloc_cleanup(&dev->srq_table.alloc);
  554. return err;
  555. }
  556. void __devexit mthca_cleanup_srq_table(struct mthca_dev *dev)
  557. {
  558. if (!(dev->mthca_flags & MTHCA_FLAG_SRQ))
  559. return;
  560. mthca_array_cleanup(&dev->srq_table.srq, dev->limits.num_srqs);
  561. mthca_alloc_cleanup(&dev->srq_table.alloc);
  562. }