solos-pci.c 32 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #define VERSION "0.07"
  42. #define PTAG "solos-pci"
  43. #define CONFIG_RAM_SIZE 128
  44. #define FLAGS_ADDR 0x7C
  45. #define IRQ_EN_ADDR 0x78
  46. #define FPGA_VER 0x74
  47. #define IRQ_CLEAR 0x70
  48. #define WRITE_FLASH 0x6C
  49. #define PORTS 0x68
  50. #define FLASH_BLOCK 0x64
  51. #define FLASH_BUSY 0x60
  52. #define FPGA_MODE 0x5C
  53. #define FLASH_MODE 0x58
  54. #define TX_DMA_ADDR(port) (0x40 + (4 * (port)))
  55. #define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
  56. #define DATA_RAM_SIZE 32768
  57. #define BUF_SIZE 4096
  58. #define FPGA_PAGE 528 /* FPGA flash page size*/
  59. #define SOLOS_PAGE 512 /* Solos flash page size*/
  60. #define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
  61. #define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
  62. #define RX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2)
  63. #define TX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2 + BUF_SIZE)
  64. #define RX_DMA_SIZE 2048
  65. static int atmdebug = 0;
  66. static int firmware_upgrade = 0;
  67. static int fpga_upgrade = 0;
  68. struct pkt_hdr {
  69. __le16 size;
  70. __le16 vpi;
  71. __le16 vci;
  72. __le16 type;
  73. };
  74. struct solos_skb_cb {
  75. struct atm_vcc *vcc;
  76. uint32_t dma_addr;
  77. };
  78. #define SKB_CB(skb) ((struct solos_skb_cb *)skb->cb)
  79. #define PKT_DATA 0
  80. #define PKT_COMMAND 1
  81. #define PKT_POPEN 3
  82. #define PKT_PCLOSE 4
  83. #define PKT_STATUS 5
  84. struct solos_card {
  85. void __iomem *config_regs;
  86. void __iomem *buffers;
  87. int nr_ports;
  88. int tx_mask;
  89. struct pci_dev *dev;
  90. struct atm_dev *atmdev[4];
  91. struct tasklet_struct tlet;
  92. spinlock_t tx_lock;
  93. spinlock_t tx_queue_lock;
  94. spinlock_t cli_queue_lock;
  95. spinlock_t param_queue_lock;
  96. struct list_head param_queue;
  97. struct sk_buff_head tx_queue[4];
  98. struct sk_buff_head cli_queue[4];
  99. struct sk_buff *tx_skb[4];
  100. struct sk_buff *rx_skb[4];
  101. wait_queue_head_t param_wq;
  102. wait_queue_head_t fw_wq;
  103. int using_dma;
  104. };
  105. struct solos_param {
  106. struct list_head list;
  107. pid_t pid;
  108. int port;
  109. struct sk_buff *response;
  110. wait_queue_head_t wq;
  111. };
  112. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  113. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  114. MODULE_DESCRIPTION("Solos PCI driver");
  115. MODULE_VERSION(VERSION);
  116. MODULE_LICENSE("GPL");
  117. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  118. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  119. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  120. module_param(atmdebug, int, 0644);
  121. module_param(firmware_upgrade, int, 0444);
  122. module_param(fpga_upgrade, int, 0444);
  123. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  124. struct atm_vcc *vcc);
  125. static int fpga_tx(struct solos_card *);
  126. static irqreturn_t solos_irq(int irq, void *dev_id);
  127. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  128. static int list_vccs(int vci);
  129. static void release_vccs(struct atm_dev *dev);
  130. static int atm_init(struct solos_card *);
  131. static void atm_remove(struct solos_card *);
  132. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  133. static void solos_bh(unsigned long);
  134. static int print_buffer(struct sk_buff *buf);
  135. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  136. {
  137. if (vcc->pop)
  138. vcc->pop(vcc, skb);
  139. else
  140. dev_kfree_skb_any(skb);
  141. }
  142. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  143. char *buf)
  144. {
  145. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  146. struct solos_card *card = atmdev->dev_data;
  147. struct solos_param prm;
  148. struct sk_buff *skb;
  149. struct pkt_hdr *header;
  150. int buflen;
  151. buflen = strlen(attr->attr.name) + 10;
  152. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  153. if (!skb) {
  154. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  155. return -ENOMEM;
  156. }
  157. header = (void *)skb_put(skb, sizeof(*header));
  158. buflen = snprintf((void *)&header[1], buflen - 1,
  159. "L%05d\n%s\n", current->pid, attr->attr.name);
  160. skb_put(skb, buflen);
  161. header->size = cpu_to_le16(buflen);
  162. header->vpi = cpu_to_le16(0);
  163. header->vci = cpu_to_le16(0);
  164. header->type = cpu_to_le16(PKT_COMMAND);
  165. prm.pid = current->pid;
  166. prm.response = NULL;
  167. prm.port = SOLOS_CHAN(atmdev);
  168. spin_lock_irq(&card->param_queue_lock);
  169. list_add(&prm.list, &card->param_queue);
  170. spin_unlock_irq(&card->param_queue_lock);
  171. fpga_queue(card, prm.port, skb, NULL);
  172. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  173. spin_lock_irq(&card->param_queue_lock);
  174. list_del(&prm.list);
  175. spin_unlock_irq(&card->param_queue_lock);
  176. if (!prm.response)
  177. return -EIO;
  178. buflen = prm.response->len;
  179. memcpy(buf, prm.response->data, buflen);
  180. kfree_skb(prm.response);
  181. return buflen;
  182. }
  183. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  184. const char *buf, size_t count)
  185. {
  186. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  187. struct solos_card *card = atmdev->dev_data;
  188. struct solos_param prm;
  189. struct sk_buff *skb;
  190. struct pkt_hdr *header;
  191. int buflen;
  192. ssize_t ret;
  193. buflen = strlen(attr->attr.name) + 11 + count;
  194. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  195. if (!skb) {
  196. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  197. return -ENOMEM;
  198. }
  199. header = (void *)skb_put(skb, sizeof(*header));
  200. buflen = snprintf((void *)&header[1], buflen - 1,
  201. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  202. skb_put(skb, buflen);
  203. header->size = cpu_to_le16(buflen);
  204. header->vpi = cpu_to_le16(0);
  205. header->vci = cpu_to_le16(0);
  206. header->type = cpu_to_le16(PKT_COMMAND);
  207. prm.pid = current->pid;
  208. prm.response = NULL;
  209. prm.port = SOLOS_CHAN(atmdev);
  210. spin_lock_irq(&card->param_queue_lock);
  211. list_add(&prm.list, &card->param_queue);
  212. spin_unlock_irq(&card->param_queue_lock);
  213. fpga_queue(card, prm.port, skb, NULL);
  214. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  215. spin_lock_irq(&card->param_queue_lock);
  216. list_del(&prm.list);
  217. spin_unlock_irq(&card->param_queue_lock);
  218. skb = prm.response;
  219. if (!skb)
  220. return -EIO;
  221. buflen = skb->len;
  222. /* Sometimes it has a newline, sometimes it doesn't. */
  223. if (skb->data[buflen - 1] == '\n')
  224. buflen--;
  225. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  226. ret = count;
  227. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  228. ret = -EIO;
  229. else {
  230. /* We know we have enough space allocated for this; we allocated
  231. it ourselves */
  232. skb->data[buflen] = 0;
  233. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  234. skb->data);
  235. ret = -EIO;
  236. }
  237. kfree_skb(skb);
  238. return ret;
  239. }
  240. static char *next_string(struct sk_buff *skb)
  241. {
  242. int i = 0;
  243. char *this = skb->data;
  244. while (i < skb->len) {
  245. if (this[i] == '\n') {
  246. this[i] = 0;
  247. skb_pull(skb, i);
  248. return this;
  249. }
  250. }
  251. return NULL;
  252. }
  253. /*
  254. * Status packet has fields separated by \n, starting with a version number
  255. * for the information therein. Fields are....
  256. *
  257. * packet version
  258. * TxBitRate (version >= 1)
  259. * RxBitRate (version >= 1)
  260. * State (version >= 1)
  261. */
  262. static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
  263. {
  264. char *str, *end, *state_str;
  265. int ver, rate_up, rate_down, state, snr, attn;
  266. if (!card->atmdev[port])
  267. return -ENODEV;
  268. str = next_string(skb);
  269. if (!str)
  270. return -EIO;
  271. ver = simple_strtol(str, NULL, 10);
  272. if (ver < 1) {
  273. dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
  274. ver);
  275. return -EIO;
  276. }
  277. str = next_string(skb);
  278. rate_up = simple_strtol(str, &end, 10);
  279. if (*end)
  280. return -EIO;
  281. str = next_string(skb);
  282. rate_down = simple_strtol(str, &end, 10);
  283. if (*end)
  284. return -EIO;
  285. state_str = next_string(skb);
  286. if (!strcmp(state_str, "Showtime"))
  287. state = ATM_PHY_SIG_FOUND;
  288. else {
  289. state = ATM_PHY_SIG_LOST;
  290. release_vccs(card->atmdev[port]);
  291. }
  292. str = next_string(skb);
  293. snr = simple_strtol(str, &end, 10);
  294. if (*end)
  295. return -EIO;
  296. str = next_string(skb);
  297. attn = simple_strtol(str, &end, 10);
  298. if (*end)
  299. return -EIO;
  300. if (state == ATM_PHY_SIG_LOST && !rate_up && !rate_down)
  301. dev_info(&card->dev->dev, "Port %d ATM state: %s\n",
  302. port, state_str);
  303. else
  304. dev_info(&card->dev->dev, "Port %d ATM state: %s (%d/%d kb/s, SNR %ddB, Attn %ddB)\n",
  305. port, state_str, rate_up/1000, rate_down/1000,
  306. snr, attn);
  307. card->atmdev[port]->link_rate = rate_down;
  308. card->atmdev[port]->signal = state;
  309. return 0;
  310. }
  311. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  312. {
  313. struct solos_param *prm;
  314. unsigned long flags;
  315. int cmdpid;
  316. int found = 0;
  317. if (skb->len < 7)
  318. return 0;
  319. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  320. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  321. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  322. skb->data[6] != '\n')
  323. return 0;
  324. cmdpid = simple_strtol(&skb->data[1], NULL, 10);
  325. spin_lock_irqsave(&card->param_queue_lock, flags);
  326. list_for_each_entry(prm, &card->param_queue, list) {
  327. if (prm->port == port && prm->pid == cmdpid) {
  328. prm->response = skb;
  329. skb_pull(skb, 7);
  330. wake_up(&card->param_wq);
  331. found = 1;
  332. break;
  333. }
  334. }
  335. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  336. return found;
  337. }
  338. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  339. char *buf)
  340. {
  341. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  342. struct solos_card *card = atmdev->dev_data;
  343. struct sk_buff *skb;
  344. spin_lock(&card->cli_queue_lock);
  345. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  346. spin_unlock(&card->cli_queue_lock);
  347. if(skb == NULL)
  348. return sprintf(buf, "No data.\n");
  349. memcpy(buf, skb->data, skb->len);
  350. dev_dbg(&card->dev->dev, "len: %d\n", skb->len);
  351. kfree_skb(skb);
  352. return skb->len;
  353. }
  354. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  355. {
  356. struct sk_buff *skb;
  357. struct pkt_hdr *header;
  358. // dev_dbg(&card->dev->dev, "size: %d\n", size);
  359. if (size > (BUF_SIZE - sizeof(*header))) {
  360. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  361. return 0;
  362. }
  363. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  364. if (!skb) {
  365. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  366. return 0;
  367. }
  368. header = (void *)skb_put(skb, sizeof(*header));
  369. header->size = cpu_to_le16(size);
  370. header->vpi = cpu_to_le16(0);
  371. header->vci = cpu_to_le16(0);
  372. header->type = cpu_to_le16(PKT_COMMAND);
  373. memcpy(skb_put(skb, size), buf, size);
  374. fpga_queue(card, dev, skb, NULL);
  375. return 0;
  376. }
  377. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  378. const char *buf, size_t count)
  379. {
  380. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  381. struct solos_card *card = atmdev->dev_data;
  382. int err;
  383. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  384. return err?:count;
  385. }
  386. static DEVICE_ATTR(console, 0644, console_show, console_store);
  387. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  388. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  389. #include "solos-attrlist.c"
  390. #undef SOLOS_ATTR_RO
  391. #undef SOLOS_ATTR_RW
  392. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  393. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  394. static struct attribute *solos_attrs[] = {
  395. #include "solos-attrlist.c"
  396. NULL
  397. };
  398. static struct attribute_group solos_attr_group = {
  399. .attrs = solos_attrs,
  400. .name = "parameters",
  401. };
  402. static int flash_upgrade(struct solos_card *card, int chip)
  403. {
  404. const struct firmware *fw;
  405. const char *fw_name;
  406. uint32_t data32 = 0;
  407. int blocksize = 0;
  408. int numblocks = 0;
  409. int offset;
  410. if (chip == 0) {
  411. fw_name = "solos-FPGA.bin";
  412. blocksize = FPGA_BLOCK;
  413. } else {
  414. fw_name = "solos-Firmware.bin";
  415. blocksize = SOLOS_BLOCK;
  416. }
  417. if (request_firmware(&fw, fw_name, &card->dev->dev))
  418. return -ENOENT;
  419. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  420. numblocks = fw->size / blocksize;
  421. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  422. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  423. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  424. iowrite32(1, card->config_regs + FPGA_MODE);
  425. data32 = ioread32(card->config_regs + FPGA_MODE);
  426. /* Set mode to Chip Erase */
  427. dev_info(&card->dev->dev, "Set FPGA Flash mode to %s Chip Erase\n",
  428. chip?"Solos":"FPGA");
  429. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  430. iowrite32(1, card->config_regs + WRITE_FLASH);
  431. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  432. for (offset = 0; offset < fw->size; offset += blocksize) {
  433. int i;
  434. /* Clear write flag */
  435. iowrite32(0, card->config_regs + WRITE_FLASH);
  436. /* Set mode to Block Write */
  437. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  438. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  439. /* Copy block to buffer, swapping each 16 bits */
  440. for(i = 0; i < blocksize; i += 4) {
  441. uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i));
  442. iowrite32(word, RX_BUF(card, 3) + i);
  443. }
  444. /* Specify block number and then trigger flash write */
  445. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  446. iowrite32(1, card->config_regs + WRITE_FLASH);
  447. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  448. }
  449. release_firmware(fw);
  450. iowrite32(0, card->config_regs + WRITE_FLASH);
  451. iowrite32(0, card->config_regs + FPGA_MODE);
  452. iowrite32(0, card->config_regs + FLASH_MODE);
  453. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  454. return 0;
  455. }
  456. static irqreturn_t solos_irq(int irq, void *dev_id)
  457. {
  458. struct solos_card *card = dev_id;
  459. int handled = 1;
  460. //ACK IRQ
  461. iowrite32(0, card->config_regs + IRQ_CLEAR);
  462. if (card->atmdev[0])
  463. tasklet_schedule(&card->tlet);
  464. else
  465. wake_up(&card->fw_wq);
  466. return IRQ_RETVAL(handled);
  467. }
  468. void solos_bh(unsigned long card_arg)
  469. {
  470. struct solos_card *card = (void *)card_arg;
  471. int port;
  472. uint32_t card_flags;
  473. uint32_t rx_done = 0;
  474. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  475. /* The TX bits are set if the channel is busy; clear if not. We want to
  476. invoke fpga_tx() unless _all_ the bits for active channels are set */
  477. if ((card_flags & card->tx_mask) != card->tx_mask)
  478. fpga_tx(card);
  479. for (port = 0; port < card->nr_ports; port++) {
  480. if (card_flags & (0x10 << port)) {
  481. struct pkt_hdr _hdr, *header;
  482. struct sk_buff *skb;
  483. struct atm_vcc *vcc;
  484. int size;
  485. if (card->using_dma) {
  486. skb = card->rx_skb[port];
  487. card->rx_skb[port] = NULL;
  488. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  489. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  490. header = (void *)skb->data;
  491. size = le16_to_cpu(header->size);
  492. skb_put(skb, size + sizeof(*header));
  493. skb_pull(skb, sizeof(*header));
  494. } else {
  495. header = &_hdr;
  496. rx_done |= 0x10 << port;
  497. memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
  498. size = le16_to_cpu(header->size);
  499. skb = alloc_skb(size + 1, GFP_ATOMIC);
  500. if (!skb) {
  501. if (net_ratelimit())
  502. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  503. continue;
  504. }
  505. memcpy_fromio(skb_put(skb, size),
  506. RX_BUF(card, port) + sizeof(*header),
  507. size);
  508. }
  509. if (atmdebug) {
  510. dev_info(&card->dev->dev, "Received: device %d\n", port);
  511. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  512. size, le16_to_cpu(header->vpi),
  513. le16_to_cpu(header->vci));
  514. print_buffer(skb);
  515. }
  516. switch (le16_to_cpu(header->type)) {
  517. case PKT_DATA:
  518. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),
  519. le16_to_cpu(header->vci));
  520. if (!vcc) {
  521. if (net_ratelimit())
  522. dev_warn(&card->dev->dev, "Received packet for unknown VCI.VPI %d.%d on port %d\n",
  523. le16_to_cpu(header->vci), le16_to_cpu(header->vpi),
  524. port);
  525. continue;
  526. }
  527. atm_charge(vcc, skb->truesize);
  528. vcc->push(vcc, skb);
  529. atomic_inc(&vcc->stats->rx);
  530. break;
  531. case PKT_STATUS:
  532. process_status(card, port, skb);
  533. dev_kfree_skb_any(skb);
  534. break;
  535. case PKT_COMMAND:
  536. default: /* FIXME: Not really, surely? */
  537. if (process_command(card, port, skb))
  538. break;
  539. spin_lock(&card->cli_queue_lock);
  540. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  541. if (net_ratelimit())
  542. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  543. port);
  544. dev_kfree_skb_any(skb);
  545. } else
  546. skb_queue_tail(&card->cli_queue[port], skb);
  547. spin_unlock(&card->cli_queue_lock);
  548. break;
  549. }
  550. }
  551. /* Allocate RX skbs for any ports which need them */
  552. if (card->using_dma && card->atmdev[port] &&
  553. !card->rx_skb[port]) {
  554. struct sk_buff *skb = alloc_skb(RX_DMA_SIZE, GFP_ATOMIC);
  555. if (skb) {
  556. SKB_CB(skb)->dma_addr =
  557. pci_map_single(card->dev, skb->data,
  558. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  559. iowrite32(SKB_CB(skb)->dma_addr,
  560. card->config_regs + RX_DMA_ADDR(port));
  561. card->rx_skb[port] = skb;
  562. } else {
  563. if (net_ratelimit())
  564. dev_warn(&card->dev->dev, "Failed to allocate RX skb");
  565. /* We'll have to try again later */
  566. tasklet_schedule(&card->tlet);
  567. }
  568. }
  569. }
  570. if (rx_done)
  571. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  572. return;
  573. }
  574. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  575. {
  576. struct hlist_head *head;
  577. struct atm_vcc *vcc = NULL;
  578. struct hlist_node *node;
  579. struct sock *s;
  580. read_lock(&vcc_sklist_lock);
  581. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  582. sk_for_each(s, node, head) {
  583. vcc = atm_sk(s);
  584. if (vcc->dev == dev && vcc->vci == vci &&
  585. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE)
  586. goto out;
  587. }
  588. vcc = NULL;
  589. out:
  590. read_unlock(&vcc_sklist_lock);
  591. return vcc;
  592. }
  593. static int list_vccs(int vci)
  594. {
  595. struct hlist_head *head;
  596. struct atm_vcc *vcc;
  597. struct hlist_node *node;
  598. struct sock *s;
  599. int num_found = 0;
  600. int i;
  601. read_lock(&vcc_sklist_lock);
  602. if (vci != 0){
  603. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  604. sk_for_each(s, node, head) {
  605. num_found ++;
  606. vcc = atm_sk(s);
  607. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  608. vcc->dev->number,
  609. vcc->vpi,
  610. vcc->vci);
  611. }
  612. } else {
  613. for(i = 0; i < VCC_HTABLE_SIZE; i++){
  614. head = &vcc_hash[i];
  615. sk_for_each(s, node, head) {
  616. num_found ++;
  617. vcc = atm_sk(s);
  618. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  619. vcc->dev->number,
  620. vcc->vpi,
  621. vcc->vci);
  622. }
  623. }
  624. }
  625. read_unlock(&vcc_sklist_lock);
  626. return num_found;
  627. }
  628. static void release_vccs(struct atm_dev *dev)
  629. {
  630. int i;
  631. write_lock_irq(&vcc_sklist_lock);
  632. for (i = 0; i < VCC_HTABLE_SIZE; i++) {
  633. struct hlist_head *head = &vcc_hash[i];
  634. struct hlist_node *node, *tmp;
  635. struct sock *s;
  636. struct atm_vcc *vcc;
  637. sk_for_each_safe(s, node, tmp, head) {
  638. vcc = atm_sk(s);
  639. if (vcc->dev == dev) {
  640. vcc_release_async(vcc, -EPIPE);
  641. sk_del_node_init(s);
  642. }
  643. }
  644. }
  645. write_unlock_irq(&vcc_sklist_lock);
  646. }
  647. static int popen(struct atm_vcc *vcc)
  648. {
  649. struct solos_card *card = vcc->dev->dev_data;
  650. struct sk_buff *skb;
  651. struct pkt_hdr *header;
  652. if (vcc->qos.aal != ATM_AAL5) {
  653. dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
  654. vcc->qos.aal);
  655. return -EINVAL;
  656. }
  657. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  658. if (!skb && net_ratelimit()) {
  659. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  660. return -ENOMEM;
  661. }
  662. header = (void *)skb_put(skb, sizeof(*header));
  663. header->size = cpu_to_le16(0);
  664. header->vpi = cpu_to_le16(vcc->vpi);
  665. header->vci = cpu_to_le16(vcc->vci);
  666. header->type = cpu_to_le16(PKT_POPEN);
  667. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  668. // dev_dbg(&card->dev->dev, "Open for vpi %d and vci %d on interface %d\n", vcc->vpi, vcc->vci, SOLOS_CHAN(vcc->dev));
  669. set_bit(ATM_VF_ADDR, &vcc->flags); // accept the vpi / vci
  670. set_bit(ATM_VF_READY, &vcc->flags);
  671. list_vccs(0);
  672. return 0;
  673. }
  674. static void pclose(struct atm_vcc *vcc)
  675. {
  676. struct solos_card *card = vcc->dev->dev_data;
  677. struct sk_buff *skb;
  678. struct pkt_hdr *header;
  679. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  680. if (!skb) {
  681. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  682. return;
  683. }
  684. header = (void *)skb_put(skb, sizeof(*header));
  685. header->size = cpu_to_le16(0);
  686. header->vpi = cpu_to_le16(vcc->vpi);
  687. header->vci = cpu_to_le16(vcc->vci);
  688. header->type = cpu_to_le16(PKT_PCLOSE);
  689. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  690. // dev_dbg(&card->dev->dev, "Close for vpi %d and vci %d on interface %d\n", vcc->vpi, vcc->vci, SOLOS_CHAN(vcc->dev));
  691. clear_bit(ATM_VF_ADDR, &vcc->flags);
  692. clear_bit(ATM_VF_READY, &vcc->flags);
  693. return;
  694. }
  695. static int print_buffer(struct sk_buff *buf)
  696. {
  697. int len,i;
  698. char msg[500];
  699. char item[10];
  700. len = buf->len;
  701. for (i = 0; i < len; i++){
  702. if(i % 8 == 0)
  703. sprintf(msg, "%02X: ", i);
  704. sprintf(item,"%02X ",*(buf->data + i));
  705. strcat(msg, item);
  706. if(i % 8 == 7) {
  707. sprintf(item, "\n");
  708. strcat(msg, item);
  709. printk(KERN_DEBUG "%s", msg);
  710. }
  711. }
  712. if (i % 8 != 0) {
  713. sprintf(item, "\n");
  714. strcat(msg, item);
  715. printk(KERN_DEBUG "%s", msg);
  716. }
  717. printk(KERN_DEBUG "\n");
  718. return 0;
  719. }
  720. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  721. struct atm_vcc *vcc)
  722. {
  723. int old_len;
  724. unsigned long flags;
  725. SKB_CB(skb)->vcc = vcc;
  726. spin_lock_irqsave(&card->tx_queue_lock, flags);
  727. old_len = skb_queue_len(&card->tx_queue[port]);
  728. skb_queue_tail(&card->tx_queue[port], skb);
  729. if (!old_len) {
  730. card->tx_mask |= (1 << port);
  731. }
  732. spin_unlock_irqrestore(&card->tx_queue_lock, flags);
  733. /* Theoretically we could just schedule the tasklet here, but
  734. that introduces latency we don't want -- it's noticeable */
  735. if (!old_len)
  736. fpga_tx(card);
  737. }
  738. static int fpga_tx(struct solos_card *card)
  739. {
  740. uint32_t tx_pending;
  741. uint32_t tx_started = 0;
  742. struct sk_buff *skb;
  743. struct atm_vcc *vcc;
  744. unsigned char port;
  745. unsigned long flags;
  746. spin_lock_irqsave(&card->tx_lock, flags);
  747. tx_pending = ioread32(card->config_regs + FLAGS_ADDR) & card->tx_mask;
  748. dev_vdbg(&card->dev->dev, "TX Flags are %X\n", tx_pending);
  749. for (port = 0; port < card->nr_ports; port++) {
  750. if (card->atmdev[port] && !(tx_pending & (1 << port))) {
  751. struct sk_buff *oldskb = card->tx_skb[port];
  752. if (oldskb)
  753. pci_unmap_single(card->dev, SKB_CB(oldskb)->dma_addr,
  754. oldskb->len, PCI_DMA_TODEVICE);
  755. spin_lock(&card->tx_queue_lock);
  756. skb = skb_dequeue(&card->tx_queue[port]);
  757. if (!skb)
  758. card->tx_mask &= ~(1 << port);
  759. spin_unlock(&card->tx_queue_lock);
  760. if (skb && !card->using_dma) {
  761. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  762. tx_started |= 1 << port; //Set TX full flag
  763. oldskb = skb; /* We're done with this skb already */
  764. } else if (skb && card->using_dma) {
  765. SKB_CB(skb)->dma_addr = pci_map_single(card->dev, skb->data,
  766. skb->len, PCI_DMA_TODEVICE);
  767. iowrite32(SKB_CB(skb)->dma_addr,
  768. card->config_regs + TX_DMA_ADDR(port));
  769. }
  770. if (!oldskb)
  771. continue;
  772. /* Clean up and free oldskb now it's gone */
  773. if (atmdebug) {
  774. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  775. port);
  776. print_buffer(oldskb);
  777. }
  778. vcc = SKB_CB(oldskb)->vcc;
  779. if (vcc) {
  780. atomic_inc(&vcc->stats->tx);
  781. solos_pop(vcc, oldskb);
  782. } else
  783. dev_kfree_skb_irq(oldskb);
  784. }
  785. }
  786. if (tx_started)
  787. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  788. spin_unlock_irqrestore(&card->tx_lock, flags);
  789. return 0;
  790. }
  791. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  792. {
  793. struct solos_card *card = vcc->dev->dev_data;
  794. struct pkt_hdr *header;
  795. int pktlen;
  796. //dev_dbg(&card->dev->dev, "psend called.\n");
  797. //dev_dbg(&card->dev->dev, "dev,vpi,vci = %d,%d,%d\n",SOLOS_CHAN(vcc->dev),vcc->vpi,vcc->vci);
  798. pktlen = skb->len;
  799. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  800. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  801. solos_pop(vcc, skb);
  802. return 0;
  803. }
  804. if (!skb_clone_writable(skb, sizeof(*header))) {
  805. int expand_by = 0;
  806. int ret;
  807. if (skb_headroom(skb) < sizeof(*header))
  808. expand_by = sizeof(*header) - skb_headroom(skb);
  809. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  810. if (ret) {
  811. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  812. solos_pop(vcc, skb);
  813. return ret;
  814. }
  815. }
  816. header = (void *)skb_push(skb, sizeof(*header));
  817. /* This does _not_ include the size of the header */
  818. header->size = cpu_to_le16(pktlen);
  819. header->vpi = cpu_to_le16(vcc->vpi);
  820. header->vci = cpu_to_le16(vcc->vci);
  821. header->type = cpu_to_le16(PKT_DATA);
  822. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  823. return 0;
  824. }
  825. static struct atmdev_ops fpga_ops = {
  826. .open = popen,
  827. .close = pclose,
  828. .ioctl = NULL,
  829. .getsockopt = NULL,
  830. .setsockopt = NULL,
  831. .send = psend,
  832. .send_oam = NULL,
  833. .phy_put = NULL,
  834. .phy_get = NULL,
  835. .change_qos = NULL,
  836. .proc_read = NULL,
  837. .owner = THIS_MODULE
  838. };
  839. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  840. {
  841. int err, i;
  842. uint16_t fpga_ver;
  843. uint8_t major_ver, minor_ver;
  844. uint32_t data32;
  845. struct solos_card *card;
  846. card = kzalloc(sizeof(*card), GFP_KERNEL);
  847. if (!card)
  848. return -ENOMEM;
  849. card->dev = dev;
  850. init_waitqueue_head(&card->fw_wq);
  851. init_waitqueue_head(&card->param_wq);
  852. err = pci_enable_device(dev);
  853. if (err) {
  854. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  855. goto out;
  856. }
  857. err = pci_set_dma_mask(dev, DMA_32BIT_MASK);
  858. if (err) {
  859. dev_warn(&dev->dev, "Failed to set 32-bit DMA mask\n");
  860. goto out;
  861. }
  862. err = pci_request_regions(dev, "solos");
  863. if (err) {
  864. dev_warn(&dev->dev, "Failed to request regions\n");
  865. goto out;
  866. }
  867. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  868. if (!card->config_regs) {
  869. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  870. goto out_release_regions;
  871. }
  872. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  873. if (!card->buffers) {
  874. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  875. goto out_unmap_config;
  876. }
  877. // for(i=0;i<64 ;i+=4){
  878. // data32=ioread32(card->buffers + i);
  879. // dev_dbg(&card->dev->dev, "%08lX\n",(unsigned long)data32);
  880. // }
  881. //Fill Config Mem with zeros
  882. for(i = 0; i < 128; i += 4)
  883. iowrite32(0, card->config_regs + i);
  884. //Set RX empty flags
  885. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  886. data32 = ioread32(card->config_regs + FPGA_VER);
  887. fpga_ver = (data32 & 0x0000FFFF);
  888. major_ver = ((data32 & 0xFF000000) >> 24);
  889. minor_ver = ((data32 & 0x00FF0000) >> 16);
  890. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  891. major_ver, minor_ver, fpga_ver);
  892. if (fpga_ver > 27)
  893. card->using_dma = 1;
  894. card->nr_ports = 2; /* FIXME: Detect daughterboard */
  895. pci_set_drvdata(dev, card);
  896. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  897. spin_lock_init(&card->tx_lock);
  898. spin_lock_init(&card->tx_queue_lock);
  899. spin_lock_init(&card->cli_queue_lock);
  900. spin_lock_init(&card->param_queue_lock);
  901. INIT_LIST_HEAD(&card->param_queue);
  902. /*
  903. // Set Loopback mode
  904. data32 = 0x00010000;
  905. iowrite32(data32,card->config_regs + FLAGS_ADDR);
  906. */
  907. /*
  908. // Fill Buffers with zeros
  909. for (i = 0; i < BUF_SIZE * 8; i += 4)
  910. iowrite32(0, card->buffers + i);
  911. */
  912. /*
  913. for(i = 0; i < (BUF_SIZE * 1); i += 4)
  914. iowrite32(0x12345678, card->buffers + i + (0*BUF_SIZE));
  915. for(i = 0; i < (BUF_SIZE * 1); i += 4)
  916. iowrite32(0xabcdef98, card->buffers + i + (1*BUF_SIZE));
  917. // Read Config Memory
  918. printk(KERN_DEBUG "Reading Config MEM\n");
  919. i = 0;
  920. for(i = 0; i < 16; i++) {
  921. data32=ioread32(card->buffers + i*(BUF_SIZE/2));
  922. printk(KERN_ALERT "Addr: %lX Data: %08lX\n",
  923. (unsigned long)(addr_start + i*(BUF_SIZE/2)),
  924. (unsigned long)data32);
  925. }
  926. */
  927. //dev_dbg(&card->dev->dev, "Requesting IRQ: %d\n",dev->irq);
  928. err = request_irq(dev->irq, solos_irq, IRQF_SHARED,
  929. "solos-pci", card);
  930. if (err) {
  931. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  932. goto out_unmap_both;
  933. }
  934. // Enable IRQs
  935. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  936. if (fpga_upgrade)
  937. flash_upgrade(card, 0);
  938. if (firmware_upgrade)
  939. flash_upgrade(card, 1);
  940. err = atm_init(card);
  941. if (err)
  942. goto out_free_irq;
  943. return 0;
  944. out_free_irq:
  945. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  946. free_irq(dev->irq, card);
  947. tasklet_kill(&card->tlet);
  948. out_unmap_both:
  949. pci_set_drvdata(dev, NULL);
  950. pci_iounmap(dev, card->config_regs);
  951. out_unmap_config:
  952. pci_iounmap(dev, card->buffers);
  953. out_release_regions:
  954. pci_release_regions(dev);
  955. out:
  956. return err;
  957. }
  958. static int atm_init(struct solos_card *card)
  959. {
  960. int i;
  961. for (i = 0; i < card->nr_ports; i++) {
  962. struct sk_buff *skb;
  963. struct pkt_hdr *header;
  964. skb_queue_head_init(&card->tx_queue[i]);
  965. skb_queue_head_init(&card->cli_queue[i]);
  966. card->atmdev[i] = atm_dev_register("solos-pci", &fpga_ops, -1, NULL);
  967. if (!card->atmdev[i]) {
  968. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  969. atm_remove(card);
  970. return -ENODEV;
  971. }
  972. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  973. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  974. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  975. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  976. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  977. card->atmdev[i]->ci_range.vpi_bits = 8;
  978. card->atmdev[i]->ci_range.vci_bits = 16;
  979. card->atmdev[i]->dev_data = card;
  980. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  981. card->atmdev[i]->signal = ATM_PHY_SIG_UNKNOWN;
  982. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  983. if (!skb) {
  984. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
  985. continue;
  986. }
  987. header = (void *)skb_put(skb, sizeof(*header));
  988. header->size = cpu_to_le16(0);
  989. header->vpi = cpu_to_le16(0);
  990. header->vci = cpu_to_le16(0);
  991. header->type = cpu_to_le16(PKT_STATUS);
  992. fpga_queue(card, i, skb, NULL);
  993. }
  994. return 0;
  995. }
  996. static void atm_remove(struct solos_card *card)
  997. {
  998. int i;
  999. for (i = 0; i < card->nr_ports; i++) {
  1000. if (card->atmdev[i]) {
  1001. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  1002. sysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);
  1003. atm_dev_deregister(card->atmdev[i]);
  1004. }
  1005. }
  1006. }
  1007. static void fpga_remove(struct pci_dev *dev)
  1008. {
  1009. struct solos_card *card = pci_get_drvdata(dev);
  1010. atm_remove(card);
  1011. dev_vdbg(&dev->dev, "Freeing IRQ\n");
  1012. // Disable IRQs from FPGA
  1013. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1014. free_irq(dev->irq, card);
  1015. tasklet_kill(&card->tlet);
  1016. // iowrite32(0x01,pciregs);
  1017. dev_vdbg(&dev->dev, "Unmapping PCI resource\n");
  1018. pci_iounmap(dev, card->buffers);
  1019. pci_iounmap(dev, card->config_regs);
  1020. dev_vdbg(&dev->dev, "Releasing PCI Region\n");
  1021. pci_release_regions(dev);
  1022. pci_disable_device(dev);
  1023. pci_set_drvdata(dev, NULL);
  1024. kfree(card);
  1025. // dev_dbg(&card->dev->dev, "fpga_remove\n");
  1026. return;
  1027. }
  1028. static struct pci_device_id fpga_pci_tbl[] __devinitdata = {
  1029. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1030. { 0, }
  1031. };
  1032. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  1033. static struct pci_driver fpga_driver = {
  1034. .name = "solos",
  1035. .id_table = fpga_pci_tbl,
  1036. .probe = fpga_probe,
  1037. .remove = fpga_remove,
  1038. };
  1039. static int __init solos_pci_init(void)
  1040. {
  1041. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  1042. return pci_register_driver(&fpga_driver);
  1043. }
  1044. static void __exit solos_pci_exit(void)
  1045. {
  1046. pci_unregister_driver(&fpga_driver);
  1047. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  1048. }
  1049. module_init(solos_pci_init);
  1050. module_exit(solos_pci_exit);