irq_emma2rh.c 2.7 KB

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  1. /*
  2. * arch/mips/emma2rh/common/irq_emma2rh.c
  3. * This file defines the irq handler for EMMA2RH.
  4. *
  5. * Copyright (C) NEC Electronics Corporation 2005-2006
  6. *
  7. * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
  8. *
  9. * Copyright 2001 MontaVista Software Inc.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. */
  25. /*
  26. * EMMA2RH defines 64 IRQs.
  27. *
  28. * This file exports one function:
  29. * emma2rh_irq_init(u32 irq_base);
  30. */
  31. #include <linux/interrupt.h>
  32. #include <linux/types.h>
  33. #include <linux/ptrace.h>
  34. #include <asm/debug.h>
  35. #include <asm/emma/emma2rh.h>
  36. /* number of total irqs supported by EMMA2RH */
  37. #define NUM_EMMA2RH_IRQ 96
  38. void ll_emma2rh_irq_enable(int);
  39. void ll_emma2rh_irq_disable(int);
  40. static void emma2rh_irq_enable(unsigned int irq)
  41. {
  42. ll_emma2rh_irq_enable(irq - EMMA2RH_IRQ_BASE);
  43. }
  44. static void emma2rh_irq_disable(unsigned int irq)
  45. {
  46. ll_emma2rh_irq_disable(irq - EMMA2RH_IRQ_BASE);
  47. }
  48. struct irq_chip emma2rh_irq_controller = {
  49. .name = "emma2rh_irq",
  50. .ack = emma2rh_irq_disable,
  51. .mask = emma2rh_irq_disable,
  52. .mask_ack = emma2rh_irq_disable,
  53. .unmask = emma2rh_irq_enable,
  54. };
  55. void emma2rh_irq_init(void)
  56. {
  57. u32 i;
  58. for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
  59. set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i,
  60. &emma2rh_irq_controller,
  61. handle_level_irq);
  62. }
  63. void ll_emma2rh_irq_enable(int emma2rh_irq)
  64. {
  65. u32 reg_value;
  66. u32 reg_bitmask;
  67. u32 reg_index;
  68. reg_index = EMMA2RH_BHIF_INT_EN_0
  69. + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
  70. * (emma2rh_irq / 32);
  71. reg_value = emma2rh_in32(reg_index);
  72. reg_bitmask = 0x1 << (emma2rh_irq % 32);
  73. db_assert((reg_value & reg_bitmask) == 0);
  74. emma2rh_out32(reg_index, reg_value | reg_bitmask);
  75. }
  76. void ll_emma2rh_irq_disable(int emma2rh_irq)
  77. {
  78. u32 reg_value;
  79. u32 reg_bitmask;
  80. u32 reg_index;
  81. reg_index = EMMA2RH_BHIF_INT_EN_0
  82. + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
  83. * (emma2rh_irq / 32);
  84. reg_value = emma2rh_in32(reg_index);
  85. reg_bitmask = 0x1 << (emma2rh_irq % 32);
  86. db_assert((reg_value & reg_bitmask) != 0);
  87. emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
  88. }