qeth_core_main.c 124 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/ipv6.h>
  19. #include <linux/tcp.h>
  20. #include <linux/mii.h>
  21. #include <linux/kthread.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include <asm/s390_rdev.h>
  25. #include "qeth_core.h"
  26. #include "qeth_core_offl.h"
  27. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  28. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  29. /* N P A M L V H */
  30. [QETH_DBF_SETUP] = {"qeth_setup",
  31. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_QERR] = {"qeth_qerr",
  33. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  34. [QETH_DBF_TRACE] = {"qeth_trace",
  35. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  36. [QETH_DBF_MSG] = {"qeth_msg",
  37. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  38. [QETH_DBF_SENSE] = {"qeth_sense",
  39. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  40. [QETH_DBF_MISC] = {"qeth_misc",
  41. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  42. [QETH_DBF_CTRL] = {"qeth_control",
  43. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  44. };
  45. EXPORT_SYMBOL_GPL(qeth_dbf);
  46. struct qeth_card_list_struct qeth_core_card_list;
  47. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  48. struct kmem_cache *qeth_core_header_cache;
  49. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  50. static struct device *qeth_core_root_dev;
  51. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  52. static struct lock_class_key qdio_out_skb_queue_key;
  53. static void qeth_send_control_data_cb(struct qeth_channel *,
  54. struct qeth_cmd_buffer *);
  55. static int qeth_issue_next_read(struct qeth_card *);
  56. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  57. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  58. static void qeth_free_buffer_pool(struct qeth_card *);
  59. static int qeth_qdio_establish(struct qeth_card *);
  60. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  61. struct qdio_buffer *buffer, int is_tso,
  62. int *next_element_to_fill)
  63. {
  64. struct skb_frag_struct *frag;
  65. int fragno;
  66. unsigned long addr;
  67. int element, cnt, dlen;
  68. fragno = skb_shinfo(skb)->nr_frags;
  69. element = *next_element_to_fill;
  70. dlen = 0;
  71. if (is_tso)
  72. buffer->element[element].flags =
  73. SBAL_FLAGS_MIDDLE_FRAG;
  74. else
  75. buffer->element[element].flags =
  76. SBAL_FLAGS_FIRST_FRAG;
  77. dlen = skb->len - skb->data_len;
  78. if (dlen) {
  79. buffer->element[element].addr = skb->data;
  80. buffer->element[element].length = dlen;
  81. element++;
  82. }
  83. for (cnt = 0; cnt < fragno; cnt++) {
  84. frag = &skb_shinfo(skb)->frags[cnt];
  85. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  86. frag->page_offset;
  87. buffer->element[element].addr = (char *)addr;
  88. buffer->element[element].length = frag->size;
  89. if (cnt < (fragno - 1))
  90. buffer->element[element].flags =
  91. SBAL_FLAGS_MIDDLE_FRAG;
  92. else
  93. buffer->element[element].flags =
  94. SBAL_FLAGS_LAST_FRAG;
  95. element++;
  96. }
  97. *next_element_to_fill = element;
  98. }
  99. static inline const char *qeth_get_cardname(struct qeth_card *card)
  100. {
  101. if (card->info.guestlan) {
  102. switch (card->info.type) {
  103. case QETH_CARD_TYPE_OSAE:
  104. return " Guest LAN QDIO";
  105. case QETH_CARD_TYPE_IQD:
  106. return " Guest LAN Hiper";
  107. default:
  108. return " unknown";
  109. }
  110. } else {
  111. switch (card->info.type) {
  112. case QETH_CARD_TYPE_OSAE:
  113. return " OSD Express";
  114. case QETH_CARD_TYPE_IQD:
  115. return " HiperSockets";
  116. case QETH_CARD_TYPE_OSN:
  117. return " OSN QDIO";
  118. default:
  119. return " unknown";
  120. }
  121. }
  122. return " n/a";
  123. }
  124. /* max length to be returned: 14 */
  125. const char *qeth_get_cardname_short(struct qeth_card *card)
  126. {
  127. if (card->info.guestlan) {
  128. switch (card->info.type) {
  129. case QETH_CARD_TYPE_OSAE:
  130. return "GuestLAN QDIO";
  131. case QETH_CARD_TYPE_IQD:
  132. return "GuestLAN Hiper";
  133. default:
  134. return "unknown";
  135. }
  136. } else {
  137. switch (card->info.type) {
  138. case QETH_CARD_TYPE_OSAE:
  139. switch (card->info.link_type) {
  140. case QETH_LINK_TYPE_FAST_ETH:
  141. return "OSD_100";
  142. case QETH_LINK_TYPE_HSTR:
  143. return "HSTR";
  144. case QETH_LINK_TYPE_GBIT_ETH:
  145. return "OSD_1000";
  146. case QETH_LINK_TYPE_10GBIT_ETH:
  147. return "OSD_10GIG";
  148. case QETH_LINK_TYPE_LANE_ETH100:
  149. return "OSD_FE_LANE";
  150. case QETH_LINK_TYPE_LANE_TR:
  151. return "OSD_TR_LANE";
  152. case QETH_LINK_TYPE_LANE_ETH1000:
  153. return "OSD_GbE_LANE";
  154. case QETH_LINK_TYPE_LANE:
  155. return "OSD_ATM_LANE";
  156. default:
  157. return "OSD_Express";
  158. }
  159. case QETH_CARD_TYPE_IQD:
  160. return "HiperSockets";
  161. case QETH_CARD_TYPE_OSN:
  162. return "OSN";
  163. default:
  164. return "unknown";
  165. }
  166. }
  167. return "n/a";
  168. }
  169. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  170. int clear_start_mask)
  171. {
  172. unsigned long flags;
  173. spin_lock_irqsave(&card->thread_mask_lock, flags);
  174. card->thread_allowed_mask = threads;
  175. if (clear_start_mask)
  176. card->thread_start_mask &= threads;
  177. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  178. wake_up(&card->wait_q);
  179. }
  180. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  181. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  182. {
  183. unsigned long flags;
  184. int rc = 0;
  185. spin_lock_irqsave(&card->thread_mask_lock, flags);
  186. rc = (card->thread_running_mask & threads);
  187. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  188. return rc;
  189. }
  190. EXPORT_SYMBOL_GPL(qeth_threads_running);
  191. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  192. {
  193. return wait_event_interruptible(card->wait_q,
  194. qeth_threads_running(card, threads) == 0);
  195. }
  196. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  197. void qeth_clear_working_pool_list(struct qeth_card *card)
  198. {
  199. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  200. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  201. list_for_each_entry_safe(pool_entry, tmp,
  202. &card->qdio.in_buf_pool.entry_list, list){
  203. list_del(&pool_entry->list);
  204. }
  205. }
  206. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  207. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  208. {
  209. struct qeth_buffer_pool_entry *pool_entry;
  210. void *ptr;
  211. int i, j;
  212. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  213. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  214. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  215. if (!pool_entry) {
  216. qeth_free_buffer_pool(card);
  217. return -ENOMEM;
  218. }
  219. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  220. ptr = (void *) __get_free_page(GFP_KERNEL);
  221. if (!ptr) {
  222. while (j > 0)
  223. free_page((unsigned long)
  224. pool_entry->elements[--j]);
  225. kfree(pool_entry);
  226. qeth_free_buffer_pool(card);
  227. return -ENOMEM;
  228. }
  229. pool_entry->elements[j] = ptr;
  230. }
  231. list_add(&pool_entry->init_list,
  232. &card->qdio.init_pool.entry_list);
  233. }
  234. return 0;
  235. }
  236. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  237. {
  238. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  239. if ((card->state != CARD_STATE_DOWN) &&
  240. (card->state != CARD_STATE_RECOVER))
  241. return -EPERM;
  242. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  243. qeth_clear_working_pool_list(card);
  244. qeth_free_buffer_pool(card);
  245. card->qdio.in_buf_pool.buf_count = bufcnt;
  246. card->qdio.init_pool.buf_count = bufcnt;
  247. return qeth_alloc_buffer_pool(card);
  248. }
  249. int qeth_set_large_send(struct qeth_card *card,
  250. enum qeth_large_send_types type)
  251. {
  252. int rc = 0;
  253. if (card->dev == NULL) {
  254. card->options.large_send = type;
  255. return 0;
  256. }
  257. if (card->state == CARD_STATE_UP)
  258. netif_tx_disable(card->dev);
  259. card->options.large_send = type;
  260. switch (card->options.large_send) {
  261. case QETH_LARGE_SEND_EDDP:
  262. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  263. NETIF_F_HW_CSUM;
  264. break;
  265. case QETH_LARGE_SEND_TSO:
  266. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  267. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  268. NETIF_F_HW_CSUM;
  269. } else {
  270. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  271. NETIF_F_HW_CSUM);
  272. card->options.large_send = QETH_LARGE_SEND_NO;
  273. rc = -EOPNOTSUPP;
  274. }
  275. break;
  276. default: /* includes QETH_LARGE_SEND_NO */
  277. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  278. NETIF_F_HW_CSUM);
  279. break;
  280. }
  281. if (card->state == CARD_STATE_UP)
  282. netif_wake_queue(card->dev);
  283. return rc;
  284. }
  285. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  286. static int qeth_issue_next_read(struct qeth_card *card)
  287. {
  288. int rc;
  289. struct qeth_cmd_buffer *iob;
  290. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  291. if (card->read.state != CH_STATE_UP)
  292. return -EIO;
  293. iob = qeth_get_buffer(&card->read);
  294. if (!iob) {
  295. dev_warn(&card->gdev->dev, "The qeth device driver "
  296. "failed to recover an error on the device\n");
  297. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  298. "available\n", dev_name(&card->gdev->dev));
  299. return -ENOMEM;
  300. }
  301. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  302. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  303. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  304. (addr_t) iob, 0, 0);
  305. if (rc) {
  306. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  307. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  308. atomic_set(&card->read.irq_pending, 0);
  309. qeth_schedule_recovery(card);
  310. wake_up(&card->wait_q);
  311. }
  312. return rc;
  313. }
  314. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  315. {
  316. struct qeth_reply *reply;
  317. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  318. if (reply) {
  319. atomic_set(&reply->refcnt, 1);
  320. atomic_set(&reply->received, 0);
  321. reply->card = card;
  322. };
  323. return reply;
  324. }
  325. static void qeth_get_reply(struct qeth_reply *reply)
  326. {
  327. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  328. atomic_inc(&reply->refcnt);
  329. }
  330. static void qeth_put_reply(struct qeth_reply *reply)
  331. {
  332. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  333. if (atomic_dec_and_test(&reply->refcnt))
  334. kfree(reply);
  335. }
  336. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  337. struct qeth_card *card)
  338. {
  339. char *ipa_name;
  340. int com = cmd->hdr.command;
  341. ipa_name = qeth_get_ipa_cmd_name(com);
  342. if (rc)
  343. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  344. ipa_name, com, QETH_CARD_IFNAME(card),
  345. rc, qeth_get_ipa_msg(rc));
  346. else
  347. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  348. ipa_name, com, QETH_CARD_IFNAME(card));
  349. }
  350. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  351. struct qeth_cmd_buffer *iob)
  352. {
  353. struct qeth_ipa_cmd *cmd = NULL;
  354. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  355. if (IS_IPA(iob->data)) {
  356. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  357. if (IS_IPA_REPLY(cmd)) {
  358. if (cmd->hdr.command < IPA_CMD_SETCCID ||
  359. cmd->hdr.command > IPA_CMD_MODCCID)
  360. qeth_issue_ipa_msg(cmd,
  361. cmd->hdr.return_code, card);
  362. return cmd;
  363. } else {
  364. switch (cmd->hdr.command) {
  365. case IPA_CMD_STOPLAN:
  366. dev_warn(&card->gdev->dev,
  367. "The link for interface %s on CHPID"
  368. " 0x%X failed\n",
  369. QETH_CARD_IFNAME(card),
  370. card->info.chpid);
  371. card->lan_online = 0;
  372. if (card->dev && netif_carrier_ok(card->dev))
  373. netif_carrier_off(card->dev);
  374. return NULL;
  375. case IPA_CMD_STARTLAN:
  376. dev_info(&card->gdev->dev,
  377. "The link for %s on CHPID 0x%X has"
  378. " been restored\n",
  379. QETH_CARD_IFNAME(card),
  380. card->info.chpid);
  381. netif_carrier_on(card->dev);
  382. card->lan_online = 1;
  383. qeth_schedule_recovery(card);
  384. return NULL;
  385. case IPA_CMD_MODCCID:
  386. return cmd;
  387. case IPA_CMD_REGISTER_LOCAL_ADDR:
  388. QETH_DBF_TEXT(TRACE, 3, "irla");
  389. break;
  390. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  391. QETH_DBF_TEXT(TRACE, 3, "urla");
  392. break;
  393. default:
  394. QETH_DBF_MESSAGE(2, "Received data is IPA "
  395. "but not a reply!\n");
  396. break;
  397. }
  398. }
  399. }
  400. return cmd;
  401. }
  402. void qeth_clear_ipacmd_list(struct qeth_card *card)
  403. {
  404. struct qeth_reply *reply, *r;
  405. unsigned long flags;
  406. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  407. spin_lock_irqsave(&card->lock, flags);
  408. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  409. qeth_get_reply(reply);
  410. reply->rc = -EIO;
  411. atomic_inc(&reply->received);
  412. list_del_init(&reply->list);
  413. wake_up(&reply->wait_q);
  414. qeth_put_reply(reply);
  415. }
  416. spin_unlock_irqrestore(&card->lock, flags);
  417. }
  418. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  419. static int qeth_check_idx_response(unsigned char *buffer)
  420. {
  421. if (!buffer)
  422. return 0;
  423. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  424. if ((buffer[2] & 0xc0) == 0xc0) {
  425. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  426. "with cause code 0x%02x%s\n",
  427. buffer[4],
  428. ((buffer[4] == 0x22) ?
  429. " -- try another portname" : ""));
  430. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  431. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  432. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  433. return -EIO;
  434. }
  435. return 0;
  436. }
  437. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  438. __u32 len)
  439. {
  440. struct qeth_card *card;
  441. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  442. card = CARD_FROM_CDEV(channel->ccwdev);
  443. if (channel == &card->read)
  444. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  445. else
  446. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  447. channel->ccw.count = len;
  448. channel->ccw.cda = (__u32) __pa(iob);
  449. }
  450. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  451. {
  452. __u8 index;
  453. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  454. index = channel->io_buf_no;
  455. do {
  456. if (channel->iob[index].state == BUF_STATE_FREE) {
  457. channel->iob[index].state = BUF_STATE_LOCKED;
  458. channel->io_buf_no = (channel->io_buf_no + 1) %
  459. QETH_CMD_BUFFER_NO;
  460. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  461. return channel->iob + index;
  462. }
  463. index = (index + 1) % QETH_CMD_BUFFER_NO;
  464. } while (index != channel->io_buf_no);
  465. return NULL;
  466. }
  467. void qeth_release_buffer(struct qeth_channel *channel,
  468. struct qeth_cmd_buffer *iob)
  469. {
  470. unsigned long flags;
  471. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  472. spin_lock_irqsave(&channel->iob_lock, flags);
  473. memset(iob->data, 0, QETH_BUFSIZE);
  474. iob->state = BUF_STATE_FREE;
  475. iob->callback = qeth_send_control_data_cb;
  476. iob->rc = 0;
  477. spin_unlock_irqrestore(&channel->iob_lock, flags);
  478. }
  479. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  480. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  481. {
  482. struct qeth_cmd_buffer *buffer = NULL;
  483. unsigned long flags;
  484. spin_lock_irqsave(&channel->iob_lock, flags);
  485. buffer = __qeth_get_buffer(channel);
  486. spin_unlock_irqrestore(&channel->iob_lock, flags);
  487. return buffer;
  488. }
  489. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  490. {
  491. struct qeth_cmd_buffer *buffer;
  492. wait_event(channel->wait_q,
  493. ((buffer = qeth_get_buffer(channel)) != NULL));
  494. return buffer;
  495. }
  496. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  497. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  498. {
  499. int cnt;
  500. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  501. qeth_release_buffer(channel, &channel->iob[cnt]);
  502. channel->buf_no = 0;
  503. channel->io_buf_no = 0;
  504. }
  505. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  506. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  507. struct qeth_cmd_buffer *iob)
  508. {
  509. struct qeth_card *card;
  510. struct qeth_reply *reply, *r;
  511. struct qeth_ipa_cmd *cmd;
  512. unsigned long flags;
  513. int keep_reply;
  514. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  515. card = CARD_FROM_CDEV(channel->ccwdev);
  516. if (qeth_check_idx_response(iob->data)) {
  517. qeth_clear_ipacmd_list(card);
  518. if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
  519. dev_err(&card->gdev->dev,
  520. "The qeth device is not configured "
  521. "for the OSI layer required by z/VM\n");
  522. qeth_schedule_recovery(card);
  523. goto out;
  524. }
  525. cmd = qeth_check_ipa_data(card, iob);
  526. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  527. goto out;
  528. /*in case of OSN : check if cmd is set */
  529. if (card->info.type == QETH_CARD_TYPE_OSN &&
  530. cmd &&
  531. cmd->hdr.command != IPA_CMD_STARTLAN &&
  532. card->osn_info.assist_cb != NULL) {
  533. card->osn_info.assist_cb(card->dev, cmd);
  534. goto out;
  535. }
  536. spin_lock_irqsave(&card->lock, flags);
  537. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  538. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  539. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  540. qeth_get_reply(reply);
  541. list_del_init(&reply->list);
  542. spin_unlock_irqrestore(&card->lock, flags);
  543. keep_reply = 0;
  544. if (reply->callback != NULL) {
  545. if (cmd) {
  546. reply->offset = (__u16)((char *)cmd -
  547. (char *)iob->data);
  548. keep_reply = reply->callback(card,
  549. reply,
  550. (unsigned long)cmd);
  551. } else
  552. keep_reply = reply->callback(card,
  553. reply,
  554. (unsigned long)iob);
  555. }
  556. if (cmd)
  557. reply->rc = (u16) cmd->hdr.return_code;
  558. else if (iob->rc)
  559. reply->rc = iob->rc;
  560. if (keep_reply) {
  561. spin_lock_irqsave(&card->lock, flags);
  562. list_add_tail(&reply->list,
  563. &card->cmd_waiter_list);
  564. spin_unlock_irqrestore(&card->lock, flags);
  565. } else {
  566. atomic_inc(&reply->received);
  567. wake_up(&reply->wait_q);
  568. }
  569. qeth_put_reply(reply);
  570. goto out;
  571. }
  572. }
  573. spin_unlock_irqrestore(&card->lock, flags);
  574. out:
  575. memcpy(&card->seqno.pdu_hdr_ack,
  576. QETH_PDU_HEADER_SEQ_NO(iob->data),
  577. QETH_SEQ_NO_LENGTH);
  578. qeth_release_buffer(channel, iob);
  579. }
  580. static int qeth_setup_channel(struct qeth_channel *channel)
  581. {
  582. int cnt;
  583. QETH_DBF_TEXT(SETUP, 2, "setupch");
  584. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  585. channel->iob[cnt].data = (char *)
  586. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  587. if (channel->iob[cnt].data == NULL)
  588. break;
  589. channel->iob[cnt].state = BUF_STATE_FREE;
  590. channel->iob[cnt].channel = channel;
  591. channel->iob[cnt].callback = qeth_send_control_data_cb;
  592. channel->iob[cnt].rc = 0;
  593. }
  594. if (cnt < QETH_CMD_BUFFER_NO) {
  595. while (cnt-- > 0)
  596. kfree(channel->iob[cnt].data);
  597. return -ENOMEM;
  598. }
  599. channel->buf_no = 0;
  600. channel->io_buf_no = 0;
  601. atomic_set(&channel->irq_pending, 0);
  602. spin_lock_init(&channel->iob_lock);
  603. init_waitqueue_head(&channel->wait_q);
  604. return 0;
  605. }
  606. static int qeth_set_thread_start_bit(struct qeth_card *card,
  607. unsigned long thread)
  608. {
  609. unsigned long flags;
  610. spin_lock_irqsave(&card->thread_mask_lock, flags);
  611. if (!(card->thread_allowed_mask & thread) ||
  612. (card->thread_start_mask & thread)) {
  613. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  614. return -EPERM;
  615. }
  616. card->thread_start_mask |= thread;
  617. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  618. return 0;
  619. }
  620. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  621. {
  622. unsigned long flags;
  623. spin_lock_irqsave(&card->thread_mask_lock, flags);
  624. card->thread_start_mask &= ~thread;
  625. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  626. wake_up(&card->wait_q);
  627. }
  628. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  629. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  630. {
  631. unsigned long flags;
  632. spin_lock_irqsave(&card->thread_mask_lock, flags);
  633. card->thread_running_mask &= ~thread;
  634. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  635. wake_up(&card->wait_q);
  636. }
  637. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  638. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  639. {
  640. unsigned long flags;
  641. int rc = 0;
  642. spin_lock_irqsave(&card->thread_mask_lock, flags);
  643. if (card->thread_start_mask & thread) {
  644. if ((card->thread_allowed_mask & thread) &&
  645. !(card->thread_running_mask & thread)) {
  646. rc = 1;
  647. card->thread_start_mask &= ~thread;
  648. card->thread_running_mask |= thread;
  649. } else
  650. rc = -EPERM;
  651. }
  652. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  653. return rc;
  654. }
  655. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  656. {
  657. int rc = 0;
  658. wait_event(card->wait_q,
  659. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  660. return rc;
  661. }
  662. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  663. void qeth_schedule_recovery(struct qeth_card *card)
  664. {
  665. QETH_DBF_TEXT(TRACE, 2, "startrec");
  666. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  667. schedule_work(&card->kernel_thread_starter);
  668. }
  669. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  670. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  671. {
  672. int dstat, cstat;
  673. char *sense;
  674. sense = (char *) irb->ecw;
  675. cstat = irb->scsw.cmd.cstat;
  676. dstat = irb->scsw.cmd.dstat;
  677. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  678. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  679. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  680. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  681. dev_warn(&cdev->dev, "The qeth device driver "
  682. "failed to recover an error on the device\n");
  683. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
  684. dev_name(&cdev->dev), dstat, cstat);
  685. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  686. 16, 1, irb, 64, 1);
  687. return 1;
  688. }
  689. if (dstat & DEV_STAT_UNIT_CHECK) {
  690. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  691. SENSE_RESETTING_EVENT_FLAG) {
  692. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  693. return 1;
  694. }
  695. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  696. SENSE_COMMAND_REJECT_FLAG) {
  697. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  698. return 1;
  699. }
  700. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  701. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  702. return 1;
  703. }
  704. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  705. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  706. return 0;
  707. }
  708. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  709. return 1;
  710. }
  711. return 0;
  712. }
  713. static long __qeth_check_irb_error(struct ccw_device *cdev,
  714. unsigned long intparm, struct irb *irb)
  715. {
  716. if (!IS_ERR(irb))
  717. return 0;
  718. switch (PTR_ERR(irb)) {
  719. case -EIO:
  720. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  721. dev_name(&cdev->dev));
  722. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  723. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  724. break;
  725. case -ETIMEDOUT:
  726. dev_warn(&cdev->dev, "A hardware operation timed out"
  727. " on the device\n");
  728. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  729. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  730. if (intparm == QETH_RCD_PARM) {
  731. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  732. if (card && (card->data.ccwdev == cdev)) {
  733. card->data.state = CH_STATE_DOWN;
  734. wake_up(&card->wait_q);
  735. }
  736. }
  737. break;
  738. default:
  739. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  740. dev_name(&cdev->dev), PTR_ERR(irb));
  741. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  742. QETH_DBF_TEXT(TRACE, 2, " rc???");
  743. }
  744. return PTR_ERR(irb);
  745. }
  746. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  747. struct irb *irb)
  748. {
  749. int rc;
  750. int cstat, dstat;
  751. struct qeth_cmd_buffer *buffer;
  752. struct qeth_channel *channel;
  753. struct qeth_card *card;
  754. struct qeth_cmd_buffer *iob;
  755. __u8 index;
  756. QETH_DBF_TEXT(TRACE, 5, "irq");
  757. if (__qeth_check_irb_error(cdev, intparm, irb))
  758. return;
  759. cstat = irb->scsw.cmd.cstat;
  760. dstat = irb->scsw.cmd.dstat;
  761. card = CARD_FROM_CDEV(cdev);
  762. if (!card)
  763. return;
  764. if (card->read.ccwdev == cdev) {
  765. channel = &card->read;
  766. QETH_DBF_TEXT(TRACE, 5, "read");
  767. } else if (card->write.ccwdev == cdev) {
  768. channel = &card->write;
  769. QETH_DBF_TEXT(TRACE, 5, "write");
  770. } else {
  771. channel = &card->data;
  772. QETH_DBF_TEXT(TRACE, 5, "data");
  773. }
  774. atomic_set(&channel->irq_pending, 0);
  775. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  776. channel->state = CH_STATE_STOPPED;
  777. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  778. channel->state = CH_STATE_HALTED;
  779. /*let's wake up immediately on data channel*/
  780. if ((channel == &card->data) && (intparm != 0) &&
  781. (intparm != QETH_RCD_PARM))
  782. goto out;
  783. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  784. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  785. /* we don't have to handle this further */
  786. intparm = 0;
  787. }
  788. if (intparm == QETH_HALT_CHANNEL_PARM) {
  789. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  790. /* we don't have to handle this further */
  791. intparm = 0;
  792. }
  793. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  794. (dstat & DEV_STAT_UNIT_CHECK) ||
  795. (cstat)) {
  796. if (irb->esw.esw0.erw.cons) {
  797. dev_warn(&channel->ccwdev->dev,
  798. "The qeth device driver failed to recover "
  799. "an error on the device\n");
  800. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  801. "0x%X dstat 0x%X\n",
  802. dev_name(&channel->ccwdev->dev), cstat, dstat);
  803. print_hex_dump(KERN_WARNING, "qeth: irb ",
  804. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  805. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  806. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  807. }
  808. if (intparm == QETH_RCD_PARM) {
  809. channel->state = CH_STATE_DOWN;
  810. goto out;
  811. }
  812. rc = qeth_get_problem(cdev, irb);
  813. if (rc) {
  814. qeth_clear_ipacmd_list(card);
  815. qeth_schedule_recovery(card);
  816. goto out;
  817. }
  818. }
  819. if (intparm == QETH_RCD_PARM) {
  820. channel->state = CH_STATE_RCD_DONE;
  821. goto out;
  822. }
  823. if (intparm) {
  824. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  825. buffer->state = BUF_STATE_PROCESSED;
  826. }
  827. if (channel == &card->data)
  828. return;
  829. if (channel == &card->read &&
  830. channel->state == CH_STATE_UP)
  831. qeth_issue_next_read(card);
  832. iob = channel->iob;
  833. index = channel->buf_no;
  834. while (iob[index].state == BUF_STATE_PROCESSED) {
  835. if (iob[index].callback != NULL)
  836. iob[index].callback(channel, iob + index);
  837. index = (index + 1) % QETH_CMD_BUFFER_NO;
  838. }
  839. channel->buf_no = index;
  840. out:
  841. wake_up(&card->wait_q);
  842. return;
  843. }
  844. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  845. struct qeth_qdio_out_buffer *buf)
  846. {
  847. int i;
  848. struct sk_buff *skb;
  849. /* is PCI flag set on buffer? */
  850. if (buf->buffer->element[0].flags & 0x40)
  851. atomic_dec(&queue->set_pci_flags_count);
  852. skb = skb_dequeue(&buf->skb_list);
  853. while (skb) {
  854. atomic_dec(&skb->users);
  855. dev_kfree_skb_any(skb);
  856. skb = skb_dequeue(&buf->skb_list);
  857. }
  858. qeth_eddp_buf_release_contexts(buf);
  859. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  860. if (buf->buffer->element[i].addr && buf->is_header[i])
  861. kmem_cache_free(qeth_core_header_cache,
  862. buf->buffer->element[i].addr);
  863. buf->is_header[i] = 0;
  864. buf->buffer->element[i].length = 0;
  865. buf->buffer->element[i].addr = NULL;
  866. buf->buffer->element[i].flags = 0;
  867. }
  868. buf->next_element_to_fill = 0;
  869. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  870. }
  871. void qeth_clear_qdio_buffers(struct qeth_card *card)
  872. {
  873. int i, j;
  874. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  875. /* clear outbound buffers to free skbs */
  876. for (i = 0; i < card->qdio.no_out_queues; ++i)
  877. if (card->qdio.out_qs[i]) {
  878. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  879. qeth_clear_output_buffer(card->qdio.out_qs[i],
  880. &card->qdio.out_qs[i]->bufs[j]);
  881. }
  882. }
  883. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  884. static void qeth_free_buffer_pool(struct qeth_card *card)
  885. {
  886. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  887. int i = 0;
  888. QETH_DBF_TEXT(TRACE, 5, "freepool");
  889. list_for_each_entry_safe(pool_entry, tmp,
  890. &card->qdio.init_pool.entry_list, init_list){
  891. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  892. free_page((unsigned long)pool_entry->elements[i]);
  893. list_del(&pool_entry->init_list);
  894. kfree(pool_entry);
  895. }
  896. }
  897. static void qeth_free_qdio_buffers(struct qeth_card *card)
  898. {
  899. int i, j;
  900. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  901. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  902. QETH_QDIO_UNINITIALIZED)
  903. return;
  904. kfree(card->qdio.in_q);
  905. card->qdio.in_q = NULL;
  906. /* inbound buffer pool */
  907. qeth_free_buffer_pool(card);
  908. /* free outbound qdio_qs */
  909. if (card->qdio.out_qs) {
  910. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  911. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  912. qeth_clear_output_buffer(card->qdio.out_qs[i],
  913. &card->qdio.out_qs[i]->bufs[j]);
  914. kfree(card->qdio.out_qs[i]);
  915. }
  916. kfree(card->qdio.out_qs);
  917. card->qdio.out_qs = NULL;
  918. }
  919. }
  920. static void qeth_clean_channel(struct qeth_channel *channel)
  921. {
  922. int cnt;
  923. QETH_DBF_TEXT(SETUP, 2, "freech");
  924. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  925. kfree(channel->iob[cnt].data);
  926. }
  927. static int qeth_is_1920_device(struct qeth_card *card)
  928. {
  929. int single_queue = 0;
  930. struct ccw_device *ccwdev;
  931. struct channelPath_dsc {
  932. u8 flags;
  933. u8 lsn;
  934. u8 desc;
  935. u8 chpid;
  936. u8 swla;
  937. u8 zeroes;
  938. u8 chla;
  939. u8 chpp;
  940. } *chp_dsc;
  941. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  942. ccwdev = card->data.ccwdev;
  943. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  944. if (chp_dsc != NULL) {
  945. /* CHPP field bit 6 == 1 -> single queue */
  946. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  947. kfree(chp_dsc);
  948. }
  949. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  950. return single_queue;
  951. }
  952. static void qeth_init_qdio_info(struct qeth_card *card)
  953. {
  954. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  955. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  956. /* inbound */
  957. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  958. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  959. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  960. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  961. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  962. }
  963. static void qeth_set_intial_options(struct qeth_card *card)
  964. {
  965. card->options.route4.type = NO_ROUTER;
  966. card->options.route6.type = NO_ROUTER;
  967. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  968. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  969. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  970. card->options.fake_broadcast = 0;
  971. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  972. card->options.performance_stats = 0;
  973. card->options.rx_sg_cb = QETH_RX_SG_CB;
  974. }
  975. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  976. {
  977. unsigned long flags;
  978. int rc = 0;
  979. spin_lock_irqsave(&card->thread_mask_lock, flags);
  980. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  981. (u8) card->thread_start_mask,
  982. (u8) card->thread_allowed_mask,
  983. (u8) card->thread_running_mask);
  984. rc = (card->thread_start_mask & thread);
  985. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  986. return rc;
  987. }
  988. static void qeth_start_kernel_thread(struct work_struct *work)
  989. {
  990. struct qeth_card *card = container_of(work, struct qeth_card,
  991. kernel_thread_starter);
  992. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  993. if (card->read.state != CH_STATE_UP &&
  994. card->write.state != CH_STATE_UP)
  995. return;
  996. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  997. kthread_run(card->discipline.recover, (void *) card,
  998. "qeth_recover");
  999. }
  1000. static int qeth_setup_card(struct qeth_card *card)
  1001. {
  1002. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1003. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1004. card->read.state = CH_STATE_DOWN;
  1005. card->write.state = CH_STATE_DOWN;
  1006. card->data.state = CH_STATE_DOWN;
  1007. card->state = CARD_STATE_DOWN;
  1008. card->lan_online = 0;
  1009. card->use_hard_stop = 0;
  1010. card->dev = NULL;
  1011. spin_lock_init(&card->vlanlock);
  1012. spin_lock_init(&card->mclock);
  1013. card->vlangrp = NULL;
  1014. spin_lock_init(&card->lock);
  1015. spin_lock_init(&card->ip_lock);
  1016. spin_lock_init(&card->thread_mask_lock);
  1017. card->thread_start_mask = 0;
  1018. card->thread_allowed_mask = 0;
  1019. card->thread_running_mask = 0;
  1020. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1021. INIT_LIST_HEAD(&card->ip_list);
  1022. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1023. if (!card->ip_tbd_list) {
  1024. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1025. return -ENOMEM;
  1026. }
  1027. INIT_LIST_HEAD(card->ip_tbd_list);
  1028. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1029. init_waitqueue_head(&card->wait_q);
  1030. /* intial options */
  1031. qeth_set_intial_options(card);
  1032. /* IP address takeover */
  1033. INIT_LIST_HEAD(&card->ipato.entries);
  1034. card->ipato.enabled = 0;
  1035. card->ipato.invert4 = 0;
  1036. card->ipato.invert6 = 0;
  1037. /* init QDIO stuff */
  1038. qeth_init_qdio_info(card);
  1039. return 0;
  1040. }
  1041. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1042. {
  1043. struct qeth_card *card = container_of(slr, struct qeth_card,
  1044. qeth_service_level);
  1045. seq_printf(m, "qeth: %s firmware level %s\n", CARD_BUS_ID(card),
  1046. card->info.mcl_level);
  1047. }
  1048. static struct qeth_card *qeth_alloc_card(void)
  1049. {
  1050. struct qeth_card *card;
  1051. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1052. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1053. if (!card)
  1054. return NULL;
  1055. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1056. if (qeth_setup_channel(&card->read)) {
  1057. kfree(card);
  1058. return NULL;
  1059. }
  1060. if (qeth_setup_channel(&card->write)) {
  1061. qeth_clean_channel(&card->read);
  1062. kfree(card);
  1063. return NULL;
  1064. }
  1065. card->options.layer2 = -1;
  1066. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1067. register_service_level(&card->qeth_service_level);
  1068. return card;
  1069. }
  1070. static int qeth_determine_card_type(struct qeth_card *card)
  1071. {
  1072. int i = 0;
  1073. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1074. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1075. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1076. while (known_devices[i][4]) {
  1077. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1078. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1079. card->info.type = known_devices[i][4];
  1080. card->qdio.no_out_queues = known_devices[i][8];
  1081. card->info.is_multicast_different = known_devices[i][9];
  1082. if (qeth_is_1920_device(card)) {
  1083. dev_info(&card->gdev->dev,
  1084. "Priority Queueing not supported\n");
  1085. card->qdio.no_out_queues = 1;
  1086. card->qdio.default_out_queue = 0;
  1087. }
  1088. return 0;
  1089. }
  1090. i++;
  1091. }
  1092. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1093. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1094. "unknown type\n");
  1095. return -ENOENT;
  1096. }
  1097. static int qeth_clear_channel(struct qeth_channel *channel)
  1098. {
  1099. unsigned long flags;
  1100. struct qeth_card *card;
  1101. int rc;
  1102. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1103. card = CARD_FROM_CDEV(channel->ccwdev);
  1104. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1105. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1106. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1107. if (rc)
  1108. return rc;
  1109. rc = wait_event_interruptible_timeout(card->wait_q,
  1110. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1111. if (rc == -ERESTARTSYS)
  1112. return rc;
  1113. if (channel->state != CH_STATE_STOPPED)
  1114. return -ETIME;
  1115. channel->state = CH_STATE_DOWN;
  1116. return 0;
  1117. }
  1118. static int qeth_halt_channel(struct qeth_channel *channel)
  1119. {
  1120. unsigned long flags;
  1121. struct qeth_card *card;
  1122. int rc;
  1123. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1124. card = CARD_FROM_CDEV(channel->ccwdev);
  1125. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1126. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1127. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1128. if (rc)
  1129. return rc;
  1130. rc = wait_event_interruptible_timeout(card->wait_q,
  1131. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1132. if (rc == -ERESTARTSYS)
  1133. return rc;
  1134. if (channel->state != CH_STATE_HALTED)
  1135. return -ETIME;
  1136. return 0;
  1137. }
  1138. static int qeth_halt_channels(struct qeth_card *card)
  1139. {
  1140. int rc1 = 0, rc2 = 0, rc3 = 0;
  1141. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1142. rc1 = qeth_halt_channel(&card->read);
  1143. rc2 = qeth_halt_channel(&card->write);
  1144. rc3 = qeth_halt_channel(&card->data);
  1145. if (rc1)
  1146. return rc1;
  1147. if (rc2)
  1148. return rc2;
  1149. return rc3;
  1150. }
  1151. static int qeth_clear_channels(struct qeth_card *card)
  1152. {
  1153. int rc1 = 0, rc2 = 0, rc3 = 0;
  1154. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1155. rc1 = qeth_clear_channel(&card->read);
  1156. rc2 = qeth_clear_channel(&card->write);
  1157. rc3 = qeth_clear_channel(&card->data);
  1158. if (rc1)
  1159. return rc1;
  1160. if (rc2)
  1161. return rc2;
  1162. return rc3;
  1163. }
  1164. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1165. {
  1166. int rc = 0;
  1167. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1168. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1169. if (halt)
  1170. rc = qeth_halt_channels(card);
  1171. if (rc)
  1172. return rc;
  1173. return qeth_clear_channels(card);
  1174. }
  1175. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1176. {
  1177. int rc = 0;
  1178. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1179. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1180. QETH_QDIO_CLEANING)) {
  1181. case QETH_QDIO_ESTABLISHED:
  1182. if (card->info.type == QETH_CARD_TYPE_IQD)
  1183. rc = qdio_cleanup(CARD_DDEV(card),
  1184. QDIO_FLAG_CLEANUP_USING_HALT);
  1185. else
  1186. rc = qdio_cleanup(CARD_DDEV(card),
  1187. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1188. if (rc)
  1189. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1190. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1191. break;
  1192. case QETH_QDIO_CLEANING:
  1193. return rc;
  1194. default:
  1195. break;
  1196. }
  1197. rc = qeth_clear_halt_card(card, use_halt);
  1198. if (rc)
  1199. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1200. card->state = CARD_STATE_DOWN;
  1201. return rc;
  1202. }
  1203. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1204. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1205. int *length)
  1206. {
  1207. struct ciw *ciw;
  1208. char *rcd_buf;
  1209. int ret;
  1210. struct qeth_channel *channel = &card->data;
  1211. unsigned long flags;
  1212. /*
  1213. * scan for RCD command in extended SenseID data
  1214. */
  1215. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1216. if (!ciw || ciw->cmd == 0)
  1217. return -EOPNOTSUPP;
  1218. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1219. if (!rcd_buf)
  1220. return -ENOMEM;
  1221. channel->ccw.cmd_code = ciw->cmd;
  1222. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1223. channel->ccw.count = ciw->count;
  1224. channel->ccw.flags = CCW_FLAG_SLI;
  1225. channel->state = CH_STATE_RCD;
  1226. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1227. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1228. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1229. QETH_RCD_TIMEOUT);
  1230. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1231. if (!ret)
  1232. wait_event(card->wait_q,
  1233. (channel->state == CH_STATE_RCD_DONE ||
  1234. channel->state == CH_STATE_DOWN));
  1235. if (channel->state == CH_STATE_DOWN)
  1236. ret = -EIO;
  1237. else
  1238. channel->state = CH_STATE_DOWN;
  1239. if (ret) {
  1240. kfree(rcd_buf);
  1241. *buffer = NULL;
  1242. *length = 0;
  1243. } else {
  1244. *length = ciw->count;
  1245. *buffer = rcd_buf;
  1246. }
  1247. return ret;
  1248. }
  1249. static int qeth_get_unitaddr(struct qeth_card *card)
  1250. {
  1251. int length;
  1252. char *prcd;
  1253. int rc;
  1254. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1255. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1256. if (rc) {
  1257. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  1258. dev_name(&card->gdev->dev), rc);
  1259. return rc;
  1260. }
  1261. card->info.chpid = prcd[30];
  1262. card->info.unit_addr2 = prcd[31];
  1263. card->info.cula = prcd[63];
  1264. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1265. (prcd[0x11] == _ascebc['M']));
  1266. kfree(prcd);
  1267. return 0;
  1268. }
  1269. static void qeth_init_tokens(struct qeth_card *card)
  1270. {
  1271. card->token.issuer_rm_w = 0x00010103UL;
  1272. card->token.cm_filter_w = 0x00010108UL;
  1273. card->token.cm_connection_w = 0x0001010aUL;
  1274. card->token.ulp_filter_w = 0x0001010bUL;
  1275. card->token.ulp_connection_w = 0x0001010dUL;
  1276. }
  1277. static void qeth_init_func_level(struct qeth_card *card)
  1278. {
  1279. if (card->ipato.enabled) {
  1280. if (card->info.type == QETH_CARD_TYPE_IQD)
  1281. card->info.func_level =
  1282. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1283. else
  1284. card->info.func_level =
  1285. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1286. } else {
  1287. if (card->info.type == QETH_CARD_TYPE_IQD)
  1288. /*FIXME:why do we have same values for dis and ena for
  1289. osae??? */
  1290. card->info.func_level =
  1291. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1292. else
  1293. card->info.func_level =
  1294. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1295. }
  1296. }
  1297. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1298. void (*idx_reply_cb)(struct qeth_channel *,
  1299. struct qeth_cmd_buffer *))
  1300. {
  1301. struct qeth_cmd_buffer *iob;
  1302. unsigned long flags;
  1303. int rc;
  1304. struct qeth_card *card;
  1305. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1306. card = CARD_FROM_CDEV(channel->ccwdev);
  1307. iob = qeth_get_buffer(channel);
  1308. iob->callback = idx_reply_cb;
  1309. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1310. channel->ccw.count = QETH_BUFSIZE;
  1311. channel->ccw.cda = (__u32) __pa(iob->data);
  1312. wait_event(card->wait_q,
  1313. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1314. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1315. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1316. rc = ccw_device_start(channel->ccwdev,
  1317. &channel->ccw, (addr_t) iob, 0, 0);
  1318. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1319. if (rc) {
  1320. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1321. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1322. atomic_set(&channel->irq_pending, 0);
  1323. wake_up(&card->wait_q);
  1324. return rc;
  1325. }
  1326. rc = wait_event_interruptible_timeout(card->wait_q,
  1327. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1328. if (rc == -ERESTARTSYS)
  1329. return rc;
  1330. if (channel->state != CH_STATE_UP) {
  1331. rc = -ETIME;
  1332. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1333. qeth_clear_cmd_buffers(channel);
  1334. } else
  1335. rc = 0;
  1336. return rc;
  1337. }
  1338. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1339. void (*idx_reply_cb)(struct qeth_channel *,
  1340. struct qeth_cmd_buffer *))
  1341. {
  1342. struct qeth_card *card;
  1343. struct qeth_cmd_buffer *iob;
  1344. unsigned long flags;
  1345. __u16 temp;
  1346. __u8 tmp;
  1347. int rc;
  1348. struct ccw_dev_id temp_devid;
  1349. card = CARD_FROM_CDEV(channel->ccwdev);
  1350. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1351. iob = qeth_get_buffer(channel);
  1352. iob->callback = idx_reply_cb;
  1353. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1354. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1355. channel->ccw.cda = (__u32) __pa(iob->data);
  1356. if (channel == &card->write) {
  1357. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1358. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1359. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1360. card->seqno.trans_hdr++;
  1361. } else {
  1362. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1363. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1364. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1365. }
  1366. tmp = ((__u8)card->info.portno) | 0x80;
  1367. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1368. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1369. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1370. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1371. &card->info.func_level, sizeof(__u16));
  1372. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1373. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1374. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1375. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1376. wait_event(card->wait_q,
  1377. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1378. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1379. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1380. rc = ccw_device_start(channel->ccwdev,
  1381. &channel->ccw, (addr_t) iob, 0, 0);
  1382. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1383. if (rc) {
  1384. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1385. rc);
  1386. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1387. atomic_set(&channel->irq_pending, 0);
  1388. wake_up(&card->wait_q);
  1389. return rc;
  1390. }
  1391. rc = wait_event_interruptible_timeout(card->wait_q,
  1392. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1393. if (rc == -ERESTARTSYS)
  1394. return rc;
  1395. if (channel->state != CH_STATE_ACTIVATING) {
  1396. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1397. " failed to recover an error on the device\n");
  1398. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1399. dev_name(&channel->ccwdev->dev));
  1400. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1401. qeth_clear_cmd_buffers(channel);
  1402. return -ETIME;
  1403. }
  1404. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1405. }
  1406. static int qeth_peer_func_level(int level)
  1407. {
  1408. if ((level & 0xff) == 8)
  1409. return (level & 0xff) + 0x400;
  1410. if (((level >> 8) & 3) == 1)
  1411. return (level & 0xff) + 0x200;
  1412. return level;
  1413. }
  1414. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1415. struct qeth_cmd_buffer *iob)
  1416. {
  1417. struct qeth_card *card;
  1418. __u16 temp;
  1419. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1420. if (channel->state == CH_STATE_DOWN) {
  1421. channel->state = CH_STATE_ACTIVATING;
  1422. goto out;
  1423. }
  1424. card = CARD_FROM_CDEV(channel->ccwdev);
  1425. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1426. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1427. dev_err(&card->write.ccwdev->dev,
  1428. "The adapter is used exclusively by another "
  1429. "host\n");
  1430. else
  1431. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1432. " negative reply\n",
  1433. dev_name(&card->write.ccwdev->dev));
  1434. goto out;
  1435. }
  1436. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1437. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1438. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1439. "function level mismatch (sent: 0x%x, received: "
  1440. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1441. card->info.func_level, temp);
  1442. goto out;
  1443. }
  1444. channel->state = CH_STATE_UP;
  1445. out:
  1446. qeth_release_buffer(channel, iob);
  1447. }
  1448. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1449. struct qeth_cmd_buffer *iob)
  1450. {
  1451. struct qeth_card *card;
  1452. __u16 temp;
  1453. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1454. if (channel->state == CH_STATE_DOWN) {
  1455. channel->state = CH_STATE_ACTIVATING;
  1456. goto out;
  1457. }
  1458. card = CARD_FROM_CDEV(channel->ccwdev);
  1459. if (qeth_check_idx_response(iob->data))
  1460. goto out;
  1461. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1462. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1463. dev_err(&card->write.ccwdev->dev,
  1464. "The adapter is used exclusively by another "
  1465. "host\n");
  1466. else
  1467. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1468. " negative reply\n",
  1469. dev_name(&card->read.ccwdev->dev));
  1470. goto out;
  1471. }
  1472. /**
  1473. * temporary fix for microcode bug
  1474. * to revert it,replace OR by AND
  1475. */
  1476. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1477. (card->info.type == QETH_CARD_TYPE_OSAE))
  1478. card->info.portname_required = 1;
  1479. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1480. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1481. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1482. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1483. dev_name(&card->read.ccwdev->dev),
  1484. card->info.func_level, temp);
  1485. goto out;
  1486. }
  1487. memcpy(&card->token.issuer_rm_r,
  1488. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1489. QETH_MPC_TOKEN_LENGTH);
  1490. memcpy(&card->info.mcl_level[0],
  1491. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1492. channel->state = CH_STATE_UP;
  1493. out:
  1494. qeth_release_buffer(channel, iob);
  1495. }
  1496. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1497. struct qeth_cmd_buffer *iob)
  1498. {
  1499. qeth_setup_ccw(&card->write, iob->data, len);
  1500. iob->callback = qeth_release_buffer;
  1501. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1502. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1503. card->seqno.trans_hdr++;
  1504. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1505. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1506. card->seqno.pdu_hdr++;
  1507. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1508. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1509. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1510. }
  1511. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1512. int qeth_send_control_data(struct qeth_card *card, int len,
  1513. struct qeth_cmd_buffer *iob,
  1514. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1515. unsigned long),
  1516. void *reply_param)
  1517. {
  1518. int rc;
  1519. unsigned long flags;
  1520. struct qeth_reply *reply = NULL;
  1521. unsigned long timeout;
  1522. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1523. reply = qeth_alloc_reply(card);
  1524. if (!reply) {
  1525. return -ENOMEM;
  1526. }
  1527. reply->callback = reply_cb;
  1528. reply->param = reply_param;
  1529. if (card->state == CARD_STATE_DOWN)
  1530. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1531. else
  1532. reply->seqno = card->seqno.ipa++;
  1533. init_waitqueue_head(&reply->wait_q);
  1534. spin_lock_irqsave(&card->lock, flags);
  1535. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1536. spin_unlock_irqrestore(&card->lock, flags);
  1537. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1538. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1539. qeth_prepare_control_data(card, len, iob);
  1540. if (IS_IPA(iob->data))
  1541. timeout = jiffies + QETH_IPA_TIMEOUT;
  1542. else
  1543. timeout = jiffies + QETH_TIMEOUT;
  1544. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1545. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1546. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1547. (addr_t) iob, 0, 0);
  1548. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1549. if (rc) {
  1550. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1551. "ccw_device_start rc = %i\n",
  1552. dev_name(&card->write.ccwdev->dev), rc);
  1553. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1554. spin_lock_irqsave(&card->lock, flags);
  1555. list_del_init(&reply->list);
  1556. qeth_put_reply(reply);
  1557. spin_unlock_irqrestore(&card->lock, flags);
  1558. qeth_release_buffer(iob->channel, iob);
  1559. atomic_set(&card->write.irq_pending, 0);
  1560. wake_up(&card->wait_q);
  1561. return rc;
  1562. }
  1563. while (!atomic_read(&reply->received)) {
  1564. if (time_after(jiffies, timeout)) {
  1565. spin_lock_irqsave(&reply->card->lock, flags);
  1566. list_del_init(&reply->list);
  1567. spin_unlock_irqrestore(&reply->card->lock, flags);
  1568. reply->rc = -ETIME;
  1569. atomic_inc(&reply->received);
  1570. wake_up(&reply->wait_q);
  1571. }
  1572. cpu_relax();
  1573. };
  1574. rc = reply->rc;
  1575. qeth_put_reply(reply);
  1576. return rc;
  1577. }
  1578. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1579. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1580. unsigned long data)
  1581. {
  1582. struct qeth_cmd_buffer *iob;
  1583. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1584. iob = (struct qeth_cmd_buffer *) data;
  1585. memcpy(&card->token.cm_filter_r,
  1586. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1587. QETH_MPC_TOKEN_LENGTH);
  1588. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1589. return 0;
  1590. }
  1591. static int qeth_cm_enable(struct qeth_card *card)
  1592. {
  1593. int rc;
  1594. struct qeth_cmd_buffer *iob;
  1595. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1596. iob = qeth_wait_for_buffer(&card->write);
  1597. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1598. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1599. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1600. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1601. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1602. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1603. qeth_cm_enable_cb, NULL);
  1604. return rc;
  1605. }
  1606. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1607. unsigned long data)
  1608. {
  1609. struct qeth_cmd_buffer *iob;
  1610. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1611. iob = (struct qeth_cmd_buffer *) data;
  1612. memcpy(&card->token.cm_connection_r,
  1613. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1614. QETH_MPC_TOKEN_LENGTH);
  1615. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1616. return 0;
  1617. }
  1618. static int qeth_cm_setup(struct qeth_card *card)
  1619. {
  1620. int rc;
  1621. struct qeth_cmd_buffer *iob;
  1622. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1623. iob = qeth_wait_for_buffer(&card->write);
  1624. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1625. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1626. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1627. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1628. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1629. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1630. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1631. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1632. qeth_cm_setup_cb, NULL);
  1633. return rc;
  1634. }
  1635. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1636. {
  1637. switch (card->info.type) {
  1638. case QETH_CARD_TYPE_UNKNOWN:
  1639. return 1500;
  1640. case QETH_CARD_TYPE_IQD:
  1641. return card->info.max_mtu;
  1642. case QETH_CARD_TYPE_OSAE:
  1643. switch (card->info.link_type) {
  1644. case QETH_LINK_TYPE_HSTR:
  1645. case QETH_LINK_TYPE_LANE_TR:
  1646. return 2000;
  1647. default:
  1648. return 1492;
  1649. }
  1650. default:
  1651. return 1500;
  1652. }
  1653. }
  1654. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1655. {
  1656. switch (cardtype) {
  1657. case QETH_CARD_TYPE_UNKNOWN:
  1658. case QETH_CARD_TYPE_OSAE:
  1659. case QETH_CARD_TYPE_OSN:
  1660. return 61440;
  1661. case QETH_CARD_TYPE_IQD:
  1662. return 57344;
  1663. default:
  1664. return 1500;
  1665. }
  1666. }
  1667. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1668. {
  1669. switch (cardtype) {
  1670. case QETH_CARD_TYPE_IQD:
  1671. return 1;
  1672. default:
  1673. return 0;
  1674. }
  1675. }
  1676. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1677. {
  1678. switch (framesize) {
  1679. case 0x4000:
  1680. return 8192;
  1681. case 0x6000:
  1682. return 16384;
  1683. case 0xa000:
  1684. return 32768;
  1685. case 0xffff:
  1686. return 57344;
  1687. default:
  1688. return 0;
  1689. }
  1690. }
  1691. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1692. {
  1693. switch (card->info.type) {
  1694. case QETH_CARD_TYPE_OSAE:
  1695. return ((mtu >= 576) && (mtu <= 61440));
  1696. case QETH_CARD_TYPE_IQD:
  1697. return ((mtu >= 576) &&
  1698. (mtu <= card->info.max_mtu + 4096 - 32));
  1699. case QETH_CARD_TYPE_OSN:
  1700. case QETH_CARD_TYPE_UNKNOWN:
  1701. default:
  1702. return 1;
  1703. }
  1704. }
  1705. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1706. unsigned long data)
  1707. {
  1708. __u16 mtu, framesize;
  1709. __u16 len;
  1710. __u8 link_type;
  1711. struct qeth_cmd_buffer *iob;
  1712. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1713. iob = (struct qeth_cmd_buffer *) data;
  1714. memcpy(&card->token.ulp_filter_r,
  1715. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1716. QETH_MPC_TOKEN_LENGTH);
  1717. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1718. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1719. mtu = qeth_get_mtu_outof_framesize(framesize);
  1720. if (!mtu) {
  1721. iob->rc = -EINVAL;
  1722. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1723. return 0;
  1724. }
  1725. card->info.max_mtu = mtu;
  1726. card->info.initial_mtu = mtu;
  1727. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1728. } else {
  1729. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1730. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1731. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1732. }
  1733. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1734. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1735. memcpy(&link_type,
  1736. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1737. card->info.link_type = link_type;
  1738. } else
  1739. card->info.link_type = 0;
  1740. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1741. return 0;
  1742. }
  1743. static int qeth_ulp_enable(struct qeth_card *card)
  1744. {
  1745. int rc;
  1746. char prot_type;
  1747. struct qeth_cmd_buffer *iob;
  1748. /*FIXME: trace view callbacks*/
  1749. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1750. iob = qeth_wait_for_buffer(&card->write);
  1751. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1752. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1753. (__u8) card->info.portno;
  1754. if (card->options.layer2)
  1755. if (card->info.type == QETH_CARD_TYPE_OSN)
  1756. prot_type = QETH_PROT_OSN2;
  1757. else
  1758. prot_type = QETH_PROT_LAYER2;
  1759. else
  1760. prot_type = QETH_PROT_TCPIP;
  1761. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1762. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1763. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1764. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1765. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1766. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1767. card->info.portname, 9);
  1768. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1769. qeth_ulp_enable_cb, NULL);
  1770. return rc;
  1771. }
  1772. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1773. unsigned long data)
  1774. {
  1775. struct qeth_cmd_buffer *iob;
  1776. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1777. iob = (struct qeth_cmd_buffer *) data;
  1778. memcpy(&card->token.ulp_connection_r,
  1779. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1780. QETH_MPC_TOKEN_LENGTH);
  1781. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1782. return 0;
  1783. }
  1784. static int qeth_ulp_setup(struct qeth_card *card)
  1785. {
  1786. int rc;
  1787. __u16 temp;
  1788. struct qeth_cmd_buffer *iob;
  1789. struct ccw_dev_id dev_id;
  1790. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1791. iob = qeth_wait_for_buffer(&card->write);
  1792. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1793. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1794. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1795. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1796. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1797. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1798. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1799. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1800. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1801. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1802. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1803. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1804. qeth_ulp_setup_cb, NULL);
  1805. return rc;
  1806. }
  1807. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1808. {
  1809. int i, j;
  1810. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1811. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1812. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1813. return 0;
  1814. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1815. GFP_KERNEL);
  1816. if (!card->qdio.in_q)
  1817. goto out_nomem;
  1818. QETH_DBF_TEXT(SETUP, 2, "inq");
  1819. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1820. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1821. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1822. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1823. card->qdio.in_q->bufs[i].buffer =
  1824. &card->qdio.in_q->qdio_bufs[i];
  1825. /* inbound buffer pool */
  1826. if (qeth_alloc_buffer_pool(card))
  1827. goto out_freeinq;
  1828. /* outbound */
  1829. card->qdio.out_qs =
  1830. kmalloc(card->qdio.no_out_queues *
  1831. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1832. if (!card->qdio.out_qs)
  1833. goto out_freepool;
  1834. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1835. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1836. GFP_KERNEL);
  1837. if (!card->qdio.out_qs[i])
  1838. goto out_freeoutq;
  1839. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1840. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1841. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1842. card->qdio.out_qs[i]->queue_no = i;
  1843. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1844. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1845. card->qdio.out_qs[i]->bufs[j].buffer =
  1846. &card->qdio.out_qs[i]->qdio_bufs[j];
  1847. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1848. skb_list);
  1849. lockdep_set_class(
  1850. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1851. &qdio_out_skb_queue_key);
  1852. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1853. }
  1854. }
  1855. return 0;
  1856. out_freeoutq:
  1857. while (i > 0)
  1858. kfree(card->qdio.out_qs[--i]);
  1859. kfree(card->qdio.out_qs);
  1860. card->qdio.out_qs = NULL;
  1861. out_freepool:
  1862. qeth_free_buffer_pool(card);
  1863. out_freeinq:
  1864. kfree(card->qdio.in_q);
  1865. card->qdio.in_q = NULL;
  1866. out_nomem:
  1867. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1868. return -ENOMEM;
  1869. }
  1870. static void qeth_create_qib_param_field(struct qeth_card *card,
  1871. char *param_field)
  1872. {
  1873. param_field[0] = _ascebc['P'];
  1874. param_field[1] = _ascebc['C'];
  1875. param_field[2] = _ascebc['I'];
  1876. param_field[3] = _ascebc['T'];
  1877. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1878. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1879. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1880. }
  1881. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1882. char *param_field)
  1883. {
  1884. param_field[16] = _ascebc['B'];
  1885. param_field[17] = _ascebc['L'];
  1886. param_field[18] = _ascebc['K'];
  1887. param_field[19] = _ascebc['T'];
  1888. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1889. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1890. *((unsigned int *) (&param_field[28])) =
  1891. card->info.blkt.inter_packet_jumbo;
  1892. }
  1893. static int qeth_qdio_activate(struct qeth_card *card)
  1894. {
  1895. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1896. return qdio_activate(CARD_DDEV(card));
  1897. }
  1898. static int qeth_dm_act(struct qeth_card *card)
  1899. {
  1900. int rc;
  1901. struct qeth_cmd_buffer *iob;
  1902. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1903. iob = qeth_wait_for_buffer(&card->write);
  1904. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1905. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1906. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1907. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1908. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1909. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1910. return rc;
  1911. }
  1912. static int qeth_mpc_initialize(struct qeth_card *card)
  1913. {
  1914. int rc;
  1915. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1916. rc = qeth_issue_next_read(card);
  1917. if (rc) {
  1918. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1919. return rc;
  1920. }
  1921. rc = qeth_cm_enable(card);
  1922. if (rc) {
  1923. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1924. goto out_qdio;
  1925. }
  1926. rc = qeth_cm_setup(card);
  1927. if (rc) {
  1928. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1929. goto out_qdio;
  1930. }
  1931. rc = qeth_ulp_enable(card);
  1932. if (rc) {
  1933. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1934. goto out_qdio;
  1935. }
  1936. rc = qeth_ulp_setup(card);
  1937. if (rc) {
  1938. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1939. goto out_qdio;
  1940. }
  1941. rc = qeth_alloc_qdio_buffers(card);
  1942. if (rc) {
  1943. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1944. goto out_qdio;
  1945. }
  1946. rc = qeth_qdio_establish(card);
  1947. if (rc) {
  1948. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1949. qeth_free_qdio_buffers(card);
  1950. goto out_qdio;
  1951. }
  1952. rc = qeth_qdio_activate(card);
  1953. if (rc) {
  1954. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1955. goto out_qdio;
  1956. }
  1957. rc = qeth_dm_act(card);
  1958. if (rc) {
  1959. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1960. goto out_qdio;
  1961. }
  1962. return 0;
  1963. out_qdio:
  1964. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1965. return rc;
  1966. }
  1967. static void qeth_print_status_with_portname(struct qeth_card *card)
  1968. {
  1969. char dbf_text[15];
  1970. int i;
  1971. sprintf(dbf_text, "%s", card->info.portname + 1);
  1972. for (i = 0; i < 8; i++)
  1973. dbf_text[i] =
  1974. (char) _ebcasc[(__u8) dbf_text[i]];
  1975. dbf_text[8] = 0;
  1976. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1977. "with link type %s (portname: %s)\n",
  1978. qeth_get_cardname(card),
  1979. (card->info.mcl_level[0]) ? " (level: " : "",
  1980. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1981. (card->info.mcl_level[0]) ? ")" : "",
  1982. qeth_get_cardname_short(card),
  1983. dbf_text);
  1984. }
  1985. static void qeth_print_status_no_portname(struct qeth_card *card)
  1986. {
  1987. if (card->info.portname[0])
  1988. dev_info(&card->gdev->dev, "Device is a%s "
  1989. "card%s%s%s\nwith link type %s "
  1990. "(no portname needed by interface).\n",
  1991. qeth_get_cardname(card),
  1992. (card->info.mcl_level[0]) ? " (level: " : "",
  1993. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1994. (card->info.mcl_level[0]) ? ")" : "",
  1995. qeth_get_cardname_short(card));
  1996. else
  1997. dev_info(&card->gdev->dev, "Device is a%s "
  1998. "card%s%s%s\nwith link type %s.\n",
  1999. qeth_get_cardname(card),
  2000. (card->info.mcl_level[0]) ? " (level: " : "",
  2001. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2002. (card->info.mcl_level[0]) ? ")" : "",
  2003. qeth_get_cardname_short(card));
  2004. }
  2005. void qeth_print_status_message(struct qeth_card *card)
  2006. {
  2007. switch (card->info.type) {
  2008. case QETH_CARD_TYPE_OSAE:
  2009. /* VM will use a non-zero first character
  2010. * to indicate a HiperSockets like reporting
  2011. * of the level OSA sets the first character to zero
  2012. * */
  2013. if (!card->info.mcl_level[0]) {
  2014. sprintf(card->info.mcl_level, "%02x%02x",
  2015. card->info.mcl_level[2],
  2016. card->info.mcl_level[3]);
  2017. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2018. break;
  2019. }
  2020. /* fallthrough */
  2021. case QETH_CARD_TYPE_IQD:
  2022. if ((card->info.guestlan) ||
  2023. (card->info.mcl_level[0] & 0x80)) {
  2024. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2025. card->info.mcl_level[0]];
  2026. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2027. card->info.mcl_level[1]];
  2028. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2029. card->info.mcl_level[2]];
  2030. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2031. card->info.mcl_level[3]];
  2032. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2033. }
  2034. break;
  2035. default:
  2036. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2037. }
  2038. if (card->info.portname_required)
  2039. qeth_print_status_with_portname(card);
  2040. else
  2041. qeth_print_status_no_portname(card);
  2042. }
  2043. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2044. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2045. {
  2046. struct qeth_buffer_pool_entry *entry;
  2047. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2048. list_for_each_entry(entry,
  2049. &card->qdio.init_pool.entry_list, init_list) {
  2050. qeth_put_buffer_pool_entry(card, entry);
  2051. }
  2052. }
  2053. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2054. struct qeth_card *card)
  2055. {
  2056. struct list_head *plh;
  2057. struct qeth_buffer_pool_entry *entry;
  2058. int i, free;
  2059. struct page *page;
  2060. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2061. return NULL;
  2062. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2063. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2064. free = 1;
  2065. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2066. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2067. free = 0;
  2068. break;
  2069. }
  2070. }
  2071. if (free) {
  2072. list_del_init(&entry->list);
  2073. return entry;
  2074. }
  2075. }
  2076. /* no free buffer in pool so take first one and swap pages */
  2077. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2078. struct qeth_buffer_pool_entry, list);
  2079. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2080. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2081. page = alloc_page(GFP_ATOMIC);
  2082. if (!page) {
  2083. return NULL;
  2084. } else {
  2085. free_page((unsigned long)entry->elements[i]);
  2086. entry->elements[i] = page_address(page);
  2087. if (card->options.performance_stats)
  2088. card->perf_stats.sg_alloc_page_rx++;
  2089. }
  2090. }
  2091. }
  2092. list_del_init(&entry->list);
  2093. return entry;
  2094. }
  2095. static int qeth_init_input_buffer(struct qeth_card *card,
  2096. struct qeth_qdio_buffer *buf)
  2097. {
  2098. struct qeth_buffer_pool_entry *pool_entry;
  2099. int i;
  2100. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2101. if (!pool_entry)
  2102. return 1;
  2103. /*
  2104. * since the buffer is accessed only from the input_tasklet
  2105. * there shouldn't be a need to synchronize; also, since we use
  2106. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2107. * buffers
  2108. */
  2109. buf->pool_entry = pool_entry;
  2110. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2111. buf->buffer->element[i].length = PAGE_SIZE;
  2112. buf->buffer->element[i].addr = pool_entry->elements[i];
  2113. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2114. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2115. else
  2116. buf->buffer->element[i].flags = 0;
  2117. }
  2118. return 0;
  2119. }
  2120. int qeth_init_qdio_queues(struct qeth_card *card)
  2121. {
  2122. int i, j;
  2123. int rc;
  2124. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2125. /* inbound queue */
  2126. memset(card->qdio.in_q->qdio_bufs, 0,
  2127. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2128. qeth_initialize_working_pool_list(card);
  2129. /*give only as many buffers to hardware as we have buffer pool entries*/
  2130. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2131. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2132. card->qdio.in_q->next_buf_to_init =
  2133. card->qdio.in_buf_pool.buf_count - 1;
  2134. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2135. card->qdio.in_buf_pool.buf_count - 1);
  2136. if (rc) {
  2137. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2138. return rc;
  2139. }
  2140. /* outbound queue */
  2141. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2142. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2143. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2144. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2145. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2146. &card->qdio.out_qs[i]->bufs[j]);
  2147. }
  2148. card->qdio.out_qs[i]->card = card;
  2149. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2150. card->qdio.out_qs[i]->do_pack = 0;
  2151. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2152. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2153. atomic_set(&card->qdio.out_qs[i]->state,
  2154. QETH_OUT_Q_UNLOCKED);
  2155. }
  2156. return 0;
  2157. }
  2158. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2159. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2160. {
  2161. switch (link_type) {
  2162. case QETH_LINK_TYPE_HSTR:
  2163. return 2;
  2164. default:
  2165. return 1;
  2166. }
  2167. }
  2168. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2169. struct qeth_ipa_cmd *cmd, __u8 command,
  2170. enum qeth_prot_versions prot)
  2171. {
  2172. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2173. cmd->hdr.command = command;
  2174. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2175. cmd->hdr.seqno = card->seqno.ipa;
  2176. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2177. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2178. if (card->options.layer2)
  2179. cmd->hdr.prim_version_no = 2;
  2180. else
  2181. cmd->hdr.prim_version_no = 1;
  2182. cmd->hdr.param_count = 1;
  2183. cmd->hdr.prot_version = prot;
  2184. cmd->hdr.ipa_supported = 0;
  2185. cmd->hdr.ipa_enabled = 0;
  2186. }
  2187. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2188. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2189. {
  2190. struct qeth_cmd_buffer *iob;
  2191. struct qeth_ipa_cmd *cmd;
  2192. iob = qeth_wait_for_buffer(&card->write);
  2193. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2194. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2195. return iob;
  2196. }
  2197. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2198. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2199. char prot_type)
  2200. {
  2201. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2202. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2203. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2204. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2205. }
  2206. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2207. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2208. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2209. unsigned long),
  2210. void *reply_param)
  2211. {
  2212. int rc;
  2213. char prot_type;
  2214. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2215. if (card->options.layer2)
  2216. if (card->info.type == QETH_CARD_TYPE_OSN)
  2217. prot_type = QETH_PROT_OSN2;
  2218. else
  2219. prot_type = QETH_PROT_LAYER2;
  2220. else
  2221. prot_type = QETH_PROT_TCPIP;
  2222. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2223. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2224. iob, reply_cb, reply_param);
  2225. return rc;
  2226. }
  2227. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2228. static int qeth_send_startstoplan(struct qeth_card *card,
  2229. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2230. {
  2231. int rc;
  2232. struct qeth_cmd_buffer *iob;
  2233. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2234. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2235. return rc;
  2236. }
  2237. int qeth_send_startlan(struct qeth_card *card)
  2238. {
  2239. int rc;
  2240. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2241. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2242. return rc;
  2243. }
  2244. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2245. int qeth_send_stoplan(struct qeth_card *card)
  2246. {
  2247. int rc = 0;
  2248. /*
  2249. * TODO: according to the IPA format document page 14,
  2250. * TCP/IP (we!) never issue a STOPLAN
  2251. * is this right ?!?
  2252. */
  2253. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2254. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2255. return rc;
  2256. }
  2257. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2258. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2259. struct qeth_reply *reply, unsigned long data)
  2260. {
  2261. struct qeth_ipa_cmd *cmd;
  2262. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2263. cmd = (struct qeth_ipa_cmd *) data;
  2264. if (cmd->hdr.return_code == 0)
  2265. cmd->hdr.return_code =
  2266. cmd->data.setadapterparms.hdr.return_code;
  2267. return 0;
  2268. }
  2269. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2270. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2271. struct qeth_reply *reply, unsigned long data)
  2272. {
  2273. struct qeth_ipa_cmd *cmd;
  2274. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2275. cmd = (struct qeth_ipa_cmd *) data;
  2276. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2277. card->info.link_type =
  2278. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2279. card->options.adp.supported_funcs =
  2280. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2281. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2282. }
  2283. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2284. __u32 command, __u32 cmdlen)
  2285. {
  2286. struct qeth_cmd_buffer *iob;
  2287. struct qeth_ipa_cmd *cmd;
  2288. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2289. QETH_PROT_IPV4);
  2290. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2291. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2292. cmd->data.setadapterparms.hdr.command_code = command;
  2293. cmd->data.setadapterparms.hdr.used_total = 1;
  2294. cmd->data.setadapterparms.hdr.seq_no = 1;
  2295. return iob;
  2296. }
  2297. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2298. int qeth_query_setadapterparms(struct qeth_card *card)
  2299. {
  2300. int rc;
  2301. struct qeth_cmd_buffer *iob;
  2302. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2303. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2304. sizeof(struct qeth_ipacmd_setadpparms));
  2305. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2306. return rc;
  2307. }
  2308. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2309. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2310. const char *dbftext)
  2311. {
  2312. if (qdio_error) {
  2313. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2314. QETH_DBF_TEXT(QERR, 2, dbftext);
  2315. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2316. buf->element[15].flags & 0xff);
  2317. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2318. buf->element[14].flags & 0xff);
  2319. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2320. return 1;
  2321. }
  2322. return 0;
  2323. }
  2324. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2325. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2326. {
  2327. struct qeth_qdio_q *queue = card->qdio.in_q;
  2328. int count;
  2329. int i;
  2330. int rc;
  2331. int newcount = 0;
  2332. count = (index < queue->next_buf_to_init)?
  2333. card->qdio.in_buf_pool.buf_count -
  2334. (queue->next_buf_to_init - index) :
  2335. card->qdio.in_buf_pool.buf_count -
  2336. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2337. /* only requeue at a certain threshold to avoid SIGAs */
  2338. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2339. for (i = queue->next_buf_to_init;
  2340. i < queue->next_buf_to_init + count; ++i) {
  2341. if (qeth_init_input_buffer(card,
  2342. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2343. break;
  2344. } else {
  2345. newcount++;
  2346. }
  2347. }
  2348. if (newcount < count) {
  2349. /* we are in memory shortage so we switch back to
  2350. traditional skb allocation and drop packages */
  2351. atomic_set(&card->force_alloc_skb, 3);
  2352. count = newcount;
  2353. } else {
  2354. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2355. }
  2356. /*
  2357. * according to old code it should be avoided to requeue all
  2358. * 128 buffers in order to benefit from PCI avoidance.
  2359. * this function keeps at least one buffer (the buffer at
  2360. * 'index') un-requeued -> this buffer is the first buffer that
  2361. * will be requeued the next time
  2362. */
  2363. if (card->options.performance_stats) {
  2364. card->perf_stats.inbound_do_qdio_cnt++;
  2365. card->perf_stats.inbound_do_qdio_start_time =
  2366. qeth_get_micros();
  2367. }
  2368. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2369. queue->next_buf_to_init, count);
  2370. if (card->options.performance_stats)
  2371. card->perf_stats.inbound_do_qdio_time +=
  2372. qeth_get_micros() -
  2373. card->perf_stats.inbound_do_qdio_start_time;
  2374. if (rc) {
  2375. dev_warn(&card->gdev->dev,
  2376. "QDIO reported an error, rc=%i\n", rc);
  2377. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2378. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2379. }
  2380. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2381. QDIO_MAX_BUFFERS_PER_Q;
  2382. }
  2383. }
  2384. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2385. static int qeth_handle_send_error(struct qeth_card *card,
  2386. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2387. {
  2388. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2389. int cc = qdio_err & 3;
  2390. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2391. qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
  2392. switch (cc) {
  2393. case 0:
  2394. if (qdio_err) {
  2395. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2396. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2397. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2398. (u16)qdio_err, (u8)sbalf15);
  2399. return QETH_SEND_ERROR_LINK_FAILURE;
  2400. }
  2401. return QETH_SEND_ERROR_NONE;
  2402. case 2:
  2403. if (qdio_err & QDIO_ERROR_SIGA_BUSY) {
  2404. QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B");
  2405. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2406. return QETH_SEND_ERROR_KICK_IT;
  2407. }
  2408. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2409. return QETH_SEND_ERROR_RETRY;
  2410. return QETH_SEND_ERROR_LINK_FAILURE;
  2411. /* look at qdio_error and sbalf 15 */
  2412. case 1:
  2413. QETH_DBF_TEXT(TRACE, 1, "SIGAcc1");
  2414. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2415. return QETH_SEND_ERROR_LINK_FAILURE;
  2416. case 3:
  2417. default:
  2418. QETH_DBF_TEXT(TRACE, 1, "SIGAcc3");
  2419. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2420. return QETH_SEND_ERROR_KICK_IT;
  2421. }
  2422. }
  2423. /*
  2424. * Switched to packing state if the number of used buffers on a queue
  2425. * reaches a certain limit.
  2426. */
  2427. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2428. {
  2429. if (!queue->do_pack) {
  2430. if (atomic_read(&queue->used_buffers)
  2431. >= QETH_HIGH_WATERMARK_PACK){
  2432. /* switch non-PACKING -> PACKING */
  2433. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2434. if (queue->card->options.performance_stats)
  2435. queue->card->perf_stats.sc_dp_p++;
  2436. queue->do_pack = 1;
  2437. }
  2438. }
  2439. }
  2440. /*
  2441. * Switches from packing to non-packing mode. If there is a packing
  2442. * buffer on the queue this buffer will be prepared to be flushed.
  2443. * In that case 1 is returned to inform the caller. If no buffer
  2444. * has to be flushed, zero is returned.
  2445. */
  2446. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2447. {
  2448. struct qeth_qdio_out_buffer *buffer;
  2449. int flush_count = 0;
  2450. if (queue->do_pack) {
  2451. if (atomic_read(&queue->used_buffers)
  2452. <= QETH_LOW_WATERMARK_PACK) {
  2453. /* switch PACKING -> non-PACKING */
  2454. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2455. if (queue->card->options.performance_stats)
  2456. queue->card->perf_stats.sc_p_dp++;
  2457. queue->do_pack = 0;
  2458. /* flush packing buffers */
  2459. buffer = &queue->bufs[queue->next_buf_to_fill];
  2460. if ((atomic_read(&buffer->state) ==
  2461. QETH_QDIO_BUF_EMPTY) &&
  2462. (buffer->next_element_to_fill > 0)) {
  2463. atomic_set(&buffer->state,
  2464. QETH_QDIO_BUF_PRIMED);
  2465. flush_count++;
  2466. queue->next_buf_to_fill =
  2467. (queue->next_buf_to_fill + 1) %
  2468. QDIO_MAX_BUFFERS_PER_Q;
  2469. }
  2470. }
  2471. }
  2472. return flush_count;
  2473. }
  2474. /*
  2475. * Called to flush a packing buffer if no more pci flags are on the queue.
  2476. * Checks if there is a packing buffer and prepares it to be flushed.
  2477. * In that case returns 1, otherwise zero.
  2478. */
  2479. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2480. {
  2481. struct qeth_qdio_out_buffer *buffer;
  2482. buffer = &queue->bufs[queue->next_buf_to_fill];
  2483. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2484. (buffer->next_element_to_fill > 0)) {
  2485. /* it's a packing buffer */
  2486. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2487. queue->next_buf_to_fill =
  2488. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2489. return 1;
  2490. }
  2491. return 0;
  2492. }
  2493. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2494. int count)
  2495. {
  2496. struct qeth_qdio_out_buffer *buf;
  2497. int rc;
  2498. int i;
  2499. unsigned int qdio_flags;
  2500. for (i = index; i < index + count; ++i) {
  2501. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2502. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2503. SBAL_FLAGS_LAST_ENTRY;
  2504. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2505. continue;
  2506. if (!queue->do_pack) {
  2507. if ((atomic_read(&queue->used_buffers) >=
  2508. (QETH_HIGH_WATERMARK_PACK -
  2509. QETH_WATERMARK_PACK_FUZZ)) &&
  2510. !atomic_read(&queue->set_pci_flags_count)) {
  2511. /* it's likely that we'll go to packing
  2512. * mode soon */
  2513. atomic_inc(&queue->set_pci_flags_count);
  2514. buf->buffer->element[0].flags |= 0x40;
  2515. }
  2516. } else {
  2517. if (!atomic_read(&queue->set_pci_flags_count)) {
  2518. /*
  2519. * there's no outstanding PCI any more, so we
  2520. * have to request a PCI to be sure the the PCI
  2521. * will wake at some time in the future then we
  2522. * can flush packed buffers that might still be
  2523. * hanging around, which can happen if no
  2524. * further send was requested by the stack
  2525. */
  2526. atomic_inc(&queue->set_pci_flags_count);
  2527. buf->buffer->element[0].flags |= 0x40;
  2528. }
  2529. }
  2530. }
  2531. queue->card->dev->trans_start = jiffies;
  2532. if (queue->card->options.performance_stats) {
  2533. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2534. queue->card->perf_stats.outbound_do_qdio_start_time =
  2535. qeth_get_micros();
  2536. }
  2537. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2538. if (atomic_read(&queue->set_pci_flags_count))
  2539. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2540. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2541. queue->queue_no, index, count);
  2542. if (queue->card->options.performance_stats)
  2543. queue->card->perf_stats.outbound_do_qdio_time +=
  2544. qeth_get_micros() -
  2545. queue->card->perf_stats.outbound_do_qdio_start_time;
  2546. if (rc) {
  2547. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2548. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2549. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2550. queue->card->stats.tx_errors += count;
  2551. /* this must not happen under normal circumstances. if it
  2552. * happens something is really wrong -> recover */
  2553. qeth_schedule_recovery(queue->card);
  2554. return;
  2555. }
  2556. atomic_add(count, &queue->used_buffers);
  2557. if (queue->card->options.performance_stats)
  2558. queue->card->perf_stats.bufs_sent += count;
  2559. }
  2560. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2561. {
  2562. int index;
  2563. int flush_cnt = 0;
  2564. int q_was_packing = 0;
  2565. /*
  2566. * check if weed have to switch to non-packing mode or if
  2567. * we have to get a pci flag out on the queue
  2568. */
  2569. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2570. !atomic_read(&queue->set_pci_flags_count)) {
  2571. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2572. QETH_OUT_Q_UNLOCKED) {
  2573. /*
  2574. * If we get in here, there was no action in
  2575. * do_send_packet. So, we check if there is a
  2576. * packing buffer to be flushed here.
  2577. */
  2578. netif_stop_queue(queue->card->dev);
  2579. index = queue->next_buf_to_fill;
  2580. q_was_packing = queue->do_pack;
  2581. /* queue->do_pack may change */
  2582. barrier();
  2583. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2584. if (!flush_cnt &&
  2585. !atomic_read(&queue->set_pci_flags_count))
  2586. flush_cnt +=
  2587. qeth_flush_buffers_on_no_pci(queue);
  2588. if (queue->card->options.performance_stats &&
  2589. q_was_packing)
  2590. queue->card->perf_stats.bufs_sent_pack +=
  2591. flush_cnt;
  2592. if (flush_cnt)
  2593. qeth_flush_buffers(queue, index, flush_cnt);
  2594. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2595. }
  2596. }
  2597. }
  2598. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2599. unsigned int qdio_error, int __queue, int first_element,
  2600. int count, unsigned long card_ptr)
  2601. {
  2602. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2603. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2604. struct qeth_qdio_out_buffer *buffer;
  2605. int i;
  2606. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2607. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2608. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2609. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2610. netif_stop_queue(card->dev);
  2611. qeth_schedule_recovery(card);
  2612. return;
  2613. }
  2614. if (card->options.performance_stats) {
  2615. card->perf_stats.outbound_handler_cnt++;
  2616. card->perf_stats.outbound_handler_start_time =
  2617. qeth_get_micros();
  2618. }
  2619. for (i = first_element; i < (first_element + count); ++i) {
  2620. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2621. /*we only handle the KICK_IT error by doing a recovery */
  2622. if (qeth_handle_send_error(card, buffer, qdio_error)
  2623. == QETH_SEND_ERROR_KICK_IT){
  2624. netif_stop_queue(card->dev);
  2625. qeth_schedule_recovery(card);
  2626. return;
  2627. }
  2628. qeth_clear_output_buffer(queue, buffer);
  2629. }
  2630. atomic_sub(count, &queue->used_buffers);
  2631. /* check if we need to do something on this outbound queue */
  2632. if (card->info.type != QETH_CARD_TYPE_IQD)
  2633. qeth_check_outbound_queue(queue);
  2634. netif_wake_queue(queue->card->dev);
  2635. if (card->options.performance_stats)
  2636. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2637. card->perf_stats.outbound_handler_start_time;
  2638. }
  2639. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2640. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2641. {
  2642. int cast_type = RTN_UNSPEC;
  2643. if (card->info.type == QETH_CARD_TYPE_OSN)
  2644. return cast_type;
  2645. if (skb->dst && skb->dst->neighbour) {
  2646. cast_type = skb->dst->neighbour->type;
  2647. if ((cast_type == RTN_BROADCAST) ||
  2648. (cast_type == RTN_MULTICAST) ||
  2649. (cast_type == RTN_ANYCAST))
  2650. return cast_type;
  2651. else
  2652. return RTN_UNSPEC;
  2653. }
  2654. /* try something else */
  2655. if (skb->protocol == ETH_P_IPV6)
  2656. return (skb_network_header(skb)[24] == 0xff) ?
  2657. RTN_MULTICAST : 0;
  2658. else if (skb->protocol == ETH_P_IP)
  2659. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2660. RTN_MULTICAST : 0;
  2661. /* ... */
  2662. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2663. return RTN_BROADCAST;
  2664. else {
  2665. u16 hdr_mac;
  2666. hdr_mac = *((u16 *)skb->data);
  2667. /* tr multicast? */
  2668. switch (card->info.link_type) {
  2669. case QETH_LINK_TYPE_HSTR:
  2670. case QETH_LINK_TYPE_LANE_TR:
  2671. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2672. (hdr_mac == QETH_TR_MAC_C))
  2673. return RTN_MULTICAST;
  2674. break;
  2675. /* eth or so multicast? */
  2676. default:
  2677. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2678. (hdr_mac == QETH_ETH_MAC_V6))
  2679. return RTN_MULTICAST;
  2680. }
  2681. }
  2682. return cast_type;
  2683. }
  2684. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2685. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2686. int ipv, int cast_type)
  2687. {
  2688. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2689. return card->qdio.default_out_queue;
  2690. switch (card->qdio.no_out_queues) {
  2691. case 4:
  2692. if (cast_type && card->info.is_multicast_different)
  2693. return card->info.is_multicast_different &
  2694. (card->qdio.no_out_queues - 1);
  2695. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2696. const u8 tos = ip_hdr(skb)->tos;
  2697. if (card->qdio.do_prio_queueing ==
  2698. QETH_PRIO_Q_ING_TOS) {
  2699. if (tos & IP_TOS_NOTIMPORTANT)
  2700. return 3;
  2701. if (tos & IP_TOS_HIGHRELIABILITY)
  2702. return 2;
  2703. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2704. return 1;
  2705. if (tos & IP_TOS_LOWDELAY)
  2706. return 0;
  2707. }
  2708. if (card->qdio.do_prio_queueing ==
  2709. QETH_PRIO_Q_ING_PREC)
  2710. return 3 - (tos >> 6);
  2711. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2712. /* TODO: IPv6!!! */
  2713. }
  2714. return card->qdio.default_out_queue;
  2715. case 1: /* fallthrough for single-out-queue 1920-device */
  2716. default:
  2717. return card->qdio.default_out_queue;
  2718. }
  2719. }
  2720. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2721. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2722. struct sk_buff *skb, int elems)
  2723. {
  2724. int elements_needed = 0;
  2725. if (skb_shinfo(skb)->nr_frags > 0)
  2726. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2727. if (elements_needed == 0)
  2728. elements_needed = 1 + (((((unsigned long) skb->data) %
  2729. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2730. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2731. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2732. "(Number=%d / Length=%d). Discarded.\n",
  2733. (elements_needed+elems), skb->len);
  2734. return 0;
  2735. }
  2736. return elements_needed;
  2737. }
  2738. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2739. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2740. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2741. int offset)
  2742. {
  2743. int length = skb->len;
  2744. int length_here;
  2745. int element;
  2746. char *data;
  2747. int first_lap ;
  2748. element = *next_element_to_fill;
  2749. data = skb->data;
  2750. first_lap = (is_tso == 0 ? 1 : 0);
  2751. if (offset >= 0) {
  2752. data = skb->data + offset;
  2753. length -= offset;
  2754. first_lap = 0;
  2755. }
  2756. while (length > 0) {
  2757. /* length_here is the remaining amount of data in this page */
  2758. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2759. if (length < length_here)
  2760. length_here = length;
  2761. buffer->element[element].addr = data;
  2762. buffer->element[element].length = length_here;
  2763. length -= length_here;
  2764. if (!length) {
  2765. if (first_lap)
  2766. buffer->element[element].flags = 0;
  2767. else
  2768. buffer->element[element].flags =
  2769. SBAL_FLAGS_LAST_FRAG;
  2770. } else {
  2771. if (first_lap)
  2772. buffer->element[element].flags =
  2773. SBAL_FLAGS_FIRST_FRAG;
  2774. else
  2775. buffer->element[element].flags =
  2776. SBAL_FLAGS_MIDDLE_FRAG;
  2777. }
  2778. data += length_here;
  2779. element++;
  2780. first_lap = 0;
  2781. }
  2782. *next_element_to_fill = element;
  2783. }
  2784. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2785. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2786. struct qeth_hdr *hdr, int offset, int hd_len)
  2787. {
  2788. struct qdio_buffer *buffer;
  2789. int flush_cnt = 0, hdr_len, large_send = 0;
  2790. buffer = buf->buffer;
  2791. atomic_inc(&skb->users);
  2792. skb_queue_tail(&buf->skb_list, skb);
  2793. /*check first on TSO ....*/
  2794. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2795. int element = buf->next_element_to_fill;
  2796. hdr_len = sizeof(struct qeth_hdr_tso) +
  2797. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2798. /*fill first buffer entry only with header information */
  2799. buffer->element[element].addr = skb->data;
  2800. buffer->element[element].length = hdr_len;
  2801. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2802. buf->next_element_to_fill++;
  2803. skb->data += hdr_len;
  2804. skb->len -= hdr_len;
  2805. large_send = 1;
  2806. }
  2807. if (offset >= 0) {
  2808. int element = buf->next_element_to_fill;
  2809. buffer->element[element].addr = hdr;
  2810. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2811. hd_len;
  2812. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2813. buf->is_header[element] = 1;
  2814. buf->next_element_to_fill++;
  2815. }
  2816. if (skb_shinfo(skb)->nr_frags == 0)
  2817. __qeth_fill_buffer(skb, buffer, large_send,
  2818. (int *)&buf->next_element_to_fill, offset);
  2819. else
  2820. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2821. (int *)&buf->next_element_to_fill);
  2822. if (!queue->do_pack) {
  2823. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2824. /* set state to PRIMED -> will be flushed */
  2825. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2826. flush_cnt = 1;
  2827. } else {
  2828. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2829. if (queue->card->options.performance_stats)
  2830. queue->card->perf_stats.skbs_sent_pack++;
  2831. if (buf->next_element_to_fill >=
  2832. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2833. /*
  2834. * packed buffer if full -> set state PRIMED
  2835. * -> will be flushed
  2836. */
  2837. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2838. flush_cnt = 1;
  2839. }
  2840. }
  2841. return flush_cnt;
  2842. }
  2843. int qeth_do_send_packet_fast(struct qeth_card *card,
  2844. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2845. struct qeth_hdr *hdr, int elements_needed,
  2846. struct qeth_eddp_context *ctx, int offset, int hd_len)
  2847. {
  2848. struct qeth_qdio_out_buffer *buffer;
  2849. int buffers_needed = 0;
  2850. int flush_cnt = 0;
  2851. int index;
  2852. /* spin until we get the queue ... */
  2853. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2854. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2855. /* ... now we've got the queue */
  2856. index = queue->next_buf_to_fill;
  2857. buffer = &queue->bufs[queue->next_buf_to_fill];
  2858. /*
  2859. * check if buffer is empty to make sure that we do not 'overtake'
  2860. * ourselves and try to fill a buffer that is already primed
  2861. */
  2862. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2863. goto out;
  2864. if (ctx == NULL)
  2865. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2866. QDIO_MAX_BUFFERS_PER_Q;
  2867. else {
  2868. buffers_needed = qeth_eddp_check_buffers_for_context(queue,
  2869. ctx);
  2870. if (buffers_needed < 0)
  2871. goto out;
  2872. queue->next_buf_to_fill =
  2873. (queue->next_buf_to_fill + buffers_needed) %
  2874. QDIO_MAX_BUFFERS_PER_Q;
  2875. }
  2876. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2877. if (ctx == NULL) {
  2878. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2879. qeth_flush_buffers(queue, index, 1);
  2880. } else {
  2881. flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
  2882. WARN_ON(buffers_needed != flush_cnt);
  2883. qeth_flush_buffers(queue, index, flush_cnt);
  2884. }
  2885. return 0;
  2886. out:
  2887. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2888. return -EBUSY;
  2889. }
  2890. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2891. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2892. struct sk_buff *skb, struct qeth_hdr *hdr,
  2893. int elements_needed, struct qeth_eddp_context *ctx)
  2894. {
  2895. struct qeth_qdio_out_buffer *buffer;
  2896. int start_index;
  2897. int flush_count = 0;
  2898. int do_pack = 0;
  2899. int tmp;
  2900. int rc = 0;
  2901. /* spin until we get the queue ... */
  2902. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2903. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2904. start_index = queue->next_buf_to_fill;
  2905. buffer = &queue->bufs[queue->next_buf_to_fill];
  2906. /*
  2907. * check if buffer is empty to make sure that we do not 'overtake'
  2908. * ourselves and try to fill a buffer that is already primed
  2909. */
  2910. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2911. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2912. return -EBUSY;
  2913. }
  2914. /* check if we need to switch packing state of this queue */
  2915. qeth_switch_to_packing_if_needed(queue);
  2916. if (queue->do_pack) {
  2917. do_pack = 1;
  2918. if (ctx == NULL) {
  2919. /* does packet fit in current buffer? */
  2920. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2921. buffer->next_element_to_fill) < elements_needed) {
  2922. /* ... no -> set state PRIMED */
  2923. atomic_set(&buffer->state,
  2924. QETH_QDIO_BUF_PRIMED);
  2925. flush_count++;
  2926. queue->next_buf_to_fill =
  2927. (queue->next_buf_to_fill + 1) %
  2928. QDIO_MAX_BUFFERS_PER_Q;
  2929. buffer = &queue->bufs[queue->next_buf_to_fill];
  2930. /* we did a step forward, so check buffer state
  2931. * again */
  2932. if (atomic_read(&buffer->state) !=
  2933. QETH_QDIO_BUF_EMPTY){
  2934. qeth_flush_buffers(queue, start_index,
  2935. flush_count);
  2936. atomic_set(&queue->state,
  2937. QETH_OUT_Q_UNLOCKED);
  2938. return -EBUSY;
  2939. }
  2940. }
  2941. } else {
  2942. /* check if we have enough elements (including following
  2943. * free buffers) to handle eddp context */
  2944. if (qeth_eddp_check_buffers_for_context(queue, ctx)
  2945. < 0) {
  2946. rc = -EBUSY;
  2947. goto out;
  2948. }
  2949. }
  2950. }
  2951. if (ctx == NULL)
  2952. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2953. else {
  2954. tmp = qeth_eddp_fill_buffer(queue, ctx,
  2955. queue->next_buf_to_fill);
  2956. if (tmp < 0) {
  2957. rc = -EBUSY;
  2958. goto out;
  2959. }
  2960. }
  2961. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2962. QDIO_MAX_BUFFERS_PER_Q;
  2963. flush_count += tmp;
  2964. out:
  2965. if (flush_count)
  2966. qeth_flush_buffers(queue, start_index, flush_count);
  2967. else if (!atomic_read(&queue->set_pci_flags_count))
  2968. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2969. /*
  2970. * queue->state will go from LOCKED -> UNLOCKED or from
  2971. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2972. * (switch packing state or flush buffer to get another pci flag out).
  2973. * In that case we will enter this loop
  2974. */
  2975. while (atomic_dec_return(&queue->state)) {
  2976. flush_count = 0;
  2977. start_index = queue->next_buf_to_fill;
  2978. /* check if we can go back to non-packing state */
  2979. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2980. /*
  2981. * check if we need to flush a packing buffer to get a pci
  2982. * flag out on the queue
  2983. */
  2984. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2985. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2986. if (flush_count)
  2987. qeth_flush_buffers(queue, start_index, flush_count);
  2988. }
  2989. /* at this point the queue is UNLOCKED again */
  2990. if (queue->card->options.performance_stats && do_pack)
  2991. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2992. return rc;
  2993. }
  2994. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2995. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2996. struct qeth_reply *reply, unsigned long data)
  2997. {
  2998. struct qeth_ipa_cmd *cmd;
  2999. struct qeth_ipacmd_setadpparms *setparms;
  3000. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  3001. cmd = (struct qeth_ipa_cmd *) data;
  3002. setparms = &(cmd->data.setadapterparms);
  3003. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3004. if (cmd->hdr.return_code) {
  3005. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3006. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3007. }
  3008. card->info.promisc_mode = setparms->data.mode;
  3009. return 0;
  3010. }
  3011. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3012. {
  3013. enum qeth_ipa_promisc_modes mode;
  3014. struct net_device *dev = card->dev;
  3015. struct qeth_cmd_buffer *iob;
  3016. struct qeth_ipa_cmd *cmd;
  3017. QETH_DBF_TEXT(TRACE, 4, "setprom");
  3018. if (((dev->flags & IFF_PROMISC) &&
  3019. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3020. (!(dev->flags & IFF_PROMISC) &&
  3021. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3022. return;
  3023. mode = SET_PROMISC_MODE_OFF;
  3024. if (dev->flags & IFF_PROMISC)
  3025. mode = SET_PROMISC_MODE_ON;
  3026. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  3027. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3028. sizeof(struct qeth_ipacmd_setadpparms));
  3029. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3030. cmd->data.setadapterparms.data.mode = mode;
  3031. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3032. }
  3033. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3034. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3035. {
  3036. struct qeth_card *card;
  3037. char dbf_text[15];
  3038. card = dev->ml_priv;
  3039. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  3040. sprintf(dbf_text, "%8x", new_mtu);
  3041. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  3042. if (new_mtu < 64)
  3043. return -EINVAL;
  3044. if (new_mtu > 65535)
  3045. return -EINVAL;
  3046. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3047. (!qeth_mtu_is_valid(card, new_mtu)))
  3048. return -EINVAL;
  3049. dev->mtu = new_mtu;
  3050. return 0;
  3051. }
  3052. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3053. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3054. {
  3055. struct qeth_card *card;
  3056. card = dev->ml_priv;
  3057. QETH_DBF_TEXT(TRACE, 5, "getstat");
  3058. return &card->stats;
  3059. }
  3060. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3061. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3062. struct qeth_reply *reply, unsigned long data)
  3063. {
  3064. struct qeth_ipa_cmd *cmd;
  3065. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  3066. cmd = (struct qeth_ipa_cmd *) data;
  3067. if (!card->options.layer2 ||
  3068. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3069. memcpy(card->dev->dev_addr,
  3070. &cmd->data.setadapterparms.data.change_addr.addr,
  3071. OSA_ADDR_LEN);
  3072. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3073. }
  3074. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3075. return 0;
  3076. }
  3077. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3078. {
  3079. int rc;
  3080. struct qeth_cmd_buffer *iob;
  3081. struct qeth_ipa_cmd *cmd;
  3082. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3083. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3084. sizeof(struct qeth_ipacmd_setadpparms));
  3085. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3086. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3087. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3088. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3089. card->dev->dev_addr, OSA_ADDR_LEN);
  3090. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3091. NULL);
  3092. return rc;
  3093. }
  3094. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3095. void qeth_tx_timeout(struct net_device *dev)
  3096. {
  3097. struct qeth_card *card;
  3098. card = dev->ml_priv;
  3099. card->stats.tx_errors++;
  3100. qeth_schedule_recovery(card);
  3101. }
  3102. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3103. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3104. {
  3105. struct qeth_card *card = dev->ml_priv;
  3106. int rc = 0;
  3107. switch (regnum) {
  3108. case MII_BMCR: /* Basic mode control register */
  3109. rc = BMCR_FULLDPLX;
  3110. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3111. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3112. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3113. rc |= BMCR_SPEED100;
  3114. break;
  3115. case MII_BMSR: /* Basic mode status register */
  3116. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3117. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3118. BMSR_100BASE4;
  3119. break;
  3120. case MII_PHYSID1: /* PHYS ID 1 */
  3121. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3122. dev->dev_addr[2];
  3123. rc = (rc >> 5) & 0xFFFF;
  3124. break;
  3125. case MII_PHYSID2: /* PHYS ID 2 */
  3126. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3127. break;
  3128. case MII_ADVERTISE: /* Advertisement control reg */
  3129. rc = ADVERTISE_ALL;
  3130. break;
  3131. case MII_LPA: /* Link partner ability reg */
  3132. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3133. LPA_100BASE4 | LPA_LPACK;
  3134. break;
  3135. case MII_EXPANSION: /* Expansion register */
  3136. break;
  3137. case MII_DCOUNTER: /* disconnect counter */
  3138. break;
  3139. case MII_FCSCOUNTER: /* false carrier counter */
  3140. break;
  3141. case MII_NWAYTEST: /* N-way auto-neg test register */
  3142. break;
  3143. case MII_RERRCOUNTER: /* rx error counter */
  3144. rc = card->stats.rx_errors;
  3145. break;
  3146. case MII_SREVISION: /* silicon revision */
  3147. break;
  3148. case MII_RESV1: /* reserved 1 */
  3149. break;
  3150. case MII_LBRERROR: /* loopback, rx, bypass error */
  3151. break;
  3152. case MII_PHYADDR: /* physical address */
  3153. break;
  3154. case MII_RESV2: /* reserved 2 */
  3155. break;
  3156. case MII_TPISTATUS: /* TPI status for 10mbps */
  3157. break;
  3158. case MII_NCONFIG: /* network interface config */
  3159. break;
  3160. default:
  3161. break;
  3162. }
  3163. return rc;
  3164. }
  3165. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3166. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3167. struct qeth_cmd_buffer *iob, int len,
  3168. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3169. unsigned long),
  3170. void *reply_param)
  3171. {
  3172. u16 s1, s2;
  3173. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3174. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3175. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3176. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3177. /* adjust PDU length fields in IPA_PDU_HEADER */
  3178. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3179. s2 = (u32) len;
  3180. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3181. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3182. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3183. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3184. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3185. reply_cb, reply_param);
  3186. }
  3187. static int qeth_snmp_command_cb(struct qeth_card *card,
  3188. struct qeth_reply *reply, unsigned long sdata)
  3189. {
  3190. struct qeth_ipa_cmd *cmd;
  3191. struct qeth_arp_query_info *qinfo;
  3192. struct qeth_snmp_cmd *snmp;
  3193. unsigned char *data;
  3194. __u16 data_len;
  3195. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3196. cmd = (struct qeth_ipa_cmd *) sdata;
  3197. data = (unsigned char *)((char *)cmd - reply->offset);
  3198. qinfo = (struct qeth_arp_query_info *) reply->param;
  3199. snmp = &cmd->data.setadapterparms.data.snmp;
  3200. if (cmd->hdr.return_code) {
  3201. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3202. return 0;
  3203. }
  3204. if (cmd->data.setadapterparms.hdr.return_code) {
  3205. cmd->hdr.return_code =
  3206. cmd->data.setadapterparms.hdr.return_code;
  3207. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3208. return 0;
  3209. }
  3210. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3211. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3212. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3213. else
  3214. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3215. /* check if there is enough room in userspace */
  3216. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3217. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3218. cmd->hdr.return_code = -ENOMEM;
  3219. return 0;
  3220. }
  3221. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3222. cmd->data.setadapterparms.hdr.used_total);
  3223. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3224. cmd->data.setadapterparms.hdr.seq_no);
  3225. /*copy entries to user buffer*/
  3226. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3227. memcpy(qinfo->udata + qinfo->udata_offset,
  3228. (char *)snmp,
  3229. data_len + offsetof(struct qeth_snmp_cmd, data));
  3230. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3231. } else {
  3232. memcpy(qinfo->udata + qinfo->udata_offset,
  3233. (char *)&snmp->request, data_len);
  3234. }
  3235. qinfo->udata_offset += data_len;
  3236. /* check if all replies received ... */
  3237. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3238. cmd->data.setadapterparms.hdr.used_total);
  3239. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3240. cmd->data.setadapterparms.hdr.seq_no);
  3241. if (cmd->data.setadapterparms.hdr.seq_no <
  3242. cmd->data.setadapterparms.hdr.used_total)
  3243. return 1;
  3244. return 0;
  3245. }
  3246. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3247. {
  3248. struct qeth_cmd_buffer *iob;
  3249. struct qeth_ipa_cmd *cmd;
  3250. struct qeth_snmp_ureq *ureq;
  3251. int req_len;
  3252. struct qeth_arp_query_info qinfo = {0, };
  3253. int rc = 0;
  3254. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3255. if (card->info.guestlan)
  3256. return -EOPNOTSUPP;
  3257. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3258. (!card->options.layer2)) {
  3259. return -EOPNOTSUPP;
  3260. }
  3261. /* skip 4 bytes (data_len struct member) to get req_len */
  3262. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3263. return -EFAULT;
  3264. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3265. if (!ureq) {
  3266. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3267. return -ENOMEM;
  3268. }
  3269. if (copy_from_user(ureq, udata,
  3270. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3271. kfree(ureq);
  3272. return -EFAULT;
  3273. }
  3274. qinfo.udata_len = ureq->hdr.data_len;
  3275. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3276. if (!qinfo.udata) {
  3277. kfree(ureq);
  3278. return -ENOMEM;
  3279. }
  3280. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3281. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3282. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3283. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3284. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3285. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3286. qeth_snmp_command_cb, (void *)&qinfo);
  3287. if (rc)
  3288. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3289. QETH_CARD_IFNAME(card), rc);
  3290. else {
  3291. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3292. rc = -EFAULT;
  3293. }
  3294. kfree(ureq);
  3295. kfree(qinfo.udata);
  3296. return rc;
  3297. }
  3298. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3299. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3300. {
  3301. switch (card->info.type) {
  3302. case QETH_CARD_TYPE_IQD:
  3303. return 2;
  3304. default:
  3305. return 0;
  3306. }
  3307. }
  3308. static int qeth_qdio_establish(struct qeth_card *card)
  3309. {
  3310. struct qdio_initialize init_data;
  3311. char *qib_param_field;
  3312. struct qdio_buffer **in_sbal_ptrs;
  3313. struct qdio_buffer **out_sbal_ptrs;
  3314. int i, j, k;
  3315. int rc = 0;
  3316. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3317. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3318. GFP_KERNEL);
  3319. if (!qib_param_field)
  3320. return -ENOMEM;
  3321. qeth_create_qib_param_field(card, qib_param_field);
  3322. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3323. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3324. GFP_KERNEL);
  3325. if (!in_sbal_ptrs) {
  3326. kfree(qib_param_field);
  3327. return -ENOMEM;
  3328. }
  3329. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3330. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3331. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3332. out_sbal_ptrs =
  3333. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3334. sizeof(void *), GFP_KERNEL);
  3335. if (!out_sbal_ptrs) {
  3336. kfree(in_sbal_ptrs);
  3337. kfree(qib_param_field);
  3338. return -ENOMEM;
  3339. }
  3340. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3341. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3342. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3343. card->qdio.out_qs[i]->bufs[j].buffer);
  3344. }
  3345. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3346. init_data.cdev = CARD_DDEV(card);
  3347. init_data.q_format = qeth_get_qdio_q_format(card);
  3348. init_data.qib_param_field_format = 0;
  3349. init_data.qib_param_field = qib_param_field;
  3350. init_data.no_input_qs = 1;
  3351. init_data.no_output_qs = card->qdio.no_out_queues;
  3352. init_data.input_handler = card->discipline.input_handler;
  3353. init_data.output_handler = card->discipline.output_handler;
  3354. init_data.int_parm = (unsigned long) card;
  3355. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3356. QDIO_OUTBOUND_0COPY_SBALS |
  3357. QDIO_USE_OUTBOUND_PCIS;
  3358. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3359. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3360. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3361. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3362. rc = qdio_initialize(&init_data);
  3363. if (rc)
  3364. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3365. }
  3366. kfree(out_sbal_ptrs);
  3367. kfree(in_sbal_ptrs);
  3368. kfree(qib_param_field);
  3369. return rc;
  3370. }
  3371. static void qeth_core_free_card(struct qeth_card *card)
  3372. {
  3373. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3374. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3375. qeth_clean_channel(&card->read);
  3376. qeth_clean_channel(&card->write);
  3377. if (card->dev)
  3378. free_netdev(card->dev);
  3379. kfree(card->ip_tbd_list);
  3380. qeth_free_qdio_buffers(card);
  3381. unregister_service_level(&card->qeth_service_level);
  3382. kfree(card);
  3383. }
  3384. static struct ccw_device_id qeth_ids[] = {
  3385. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3386. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3387. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3388. {},
  3389. };
  3390. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3391. static struct ccw_driver qeth_ccw_driver = {
  3392. .name = "qeth",
  3393. .ids = qeth_ids,
  3394. .probe = ccwgroup_probe_ccwdev,
  3395. .remove = ccwgroup_remove_ccwdev,
  3396. };
  3397. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3398. unsigned long driver_id)
  3399. {
  3400. return ccwgroup_create_from_string(root_dev, driver_id,
  3401. &qeth_ccw_driver, 3, buf);
  3402. }
  3403. int qeth_core_hardsetup_card(struct qeth_card *card)
  3404. {
  3405. struct qdio_ssqd_desc *ssqd;
  3406. int retries = 3;
  3407. int mpno = 0;
  3408. int rc;
  3409. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3410. atomic_set(&card->force_alloc_skb, 0);
  3411. retry:
  3412. if (retries < 3) {
  3413. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3414. dev_name(&card->gdev->dev));
  3415. ccw_device_set_offline(CARD_DDEV(card));
  3416. ccw_device_set_offline(CARD_WDEV(card));
  3417. ccw_device_set_offline(CARD_RDEV(card));
  3418. ccw_device_set_online(CARD_RDEV(card));
  3419. ccw_device_set_online(CARD_WDEV(card));
  3420. ccw_device_set_online(CARD_DDEV(card));
  3421. }
  3422. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3423. if (rc == -ERESTARTSYS) {
  3424. QETH_DBF_TEXT(SETUP, 2, "break1");
  3425. return rc;
  3426. } else if (rc) {
  3427. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3428. if (--retries < 0)
  3429. goto out;
  3430. else
  3431. goto retry;
  3432. }
  3433. rc = qeth_get_unitaddr(card);
  3434. if (rc) {
  3435. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3436. return rc;
  3437. }
  3438. ssqd = kmalloc(sizeof(struct qdio_ssqd_desc), GFP_KERNEL);
  3439. if (!ssqd) {
  3440. rc = -ENOMEM;
  3441. goto out;
  3442. }
  3443. rc = qdio_get_ssqd_desc(CARD_DDEV(card), ssqd);
  3444. if (rc == 0)
  3445. mpno = ssqd->pcnt;
  3446. kfree(ssqd);
  3447. if (mpno)
  3448. mpno = min(mpno - 1, QETH_MAX_PORTNO);
  3449. if (card->info.portno > mpno) {
  3450. QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
  3451. "\n.", CARD_BUS_ID(card), card->info.portno);
  3452. rc = -ENODEV;
  3453. goto out;
  3454. }
  3455. qeth_init_tokens(card);
  3456. qeth_init_func_level(card);
  3457. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3458. if (rc == -ERESTARTSYS) {
  3459. QETH_DBF_TEXT(SETUP, 2, "break2");
  3460. return rc;
  3461. } else if (rc) {
  3462. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3463. if (--retries < 0)
  3464. goto out;
  3465. else
  3466. goto retry;
  3467. }
  3468. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3469. if (rc == -ERESTARTSYS) {
  3470. QETH_DBF_TEXT(SETUP, 2, "break3");
  3471. return rc;
  3472. } else if (rc) {
  3473. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3474. if (--retries < 0)
  3475. goto out;
  3476. else
  3477. goto retry;
  3478. }
  3479. rc = qeth_mpc_initialize(card);
  3480. if (rc) {
  3481. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3482. goto out;
  3483. }
  3484. return 0;
  3485. out:
  3486. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3487. "an error on the device\n");
  3488. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3489. dev_name(&card->gdev->dev), rc);
  3490. return rc;
  3491. }
  3492. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3493. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3494. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3495. {
  3496. struct page *page = virt_to_page(element->addr);
  3497. if (*pskb == NULL) {
  3498. /* the upper protocol layers assume that there is data in the
  3499. * skb itself. Copy a small amount (64 bytes) to make them
  3500. * happy. */
  3501. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3502. if (!(*pskb))
  3503. return -ENOMEM;
  3504. skb_reserve(*pskb, ETH_HLEN);
  3505. if (data_len <= 64) {
  3506. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3507. data_len);
  3508. } else {
  3509. get_page(page);
  3510. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3511. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3512. data_len - 64);
  3513. (*pskb)->data_len += data_len - 64;
  3514. (*pskb)->len += data_len - 64;
  3515. (*pskb)->truesize += data_len - 64;
  3516. (*pfrag)++;
  3517. }
  3518. } else {
  3519. get_page(page);
  3520. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3521. (*pskb)->data_len += data_len;
  3522. (*pskb)->len += data_len;
  3523. (*pskb)->truesize += data_len;
  3524. (*pfrag)++;
  3525. }
  3526. return 0;
  3527. }
  3528. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3529. struct qdio_buffer *buffer,
  3530. struct qdio_buffer_element **__element, int *__offset,
  3531. struct qeth_hdr **hdr)
  3532. {
  3533. struct qdio_buffer_element *element = *__element;
  3534. int offset = *__offset;
  3535. struct sk_buff *skb = NULL;
  3536. int skb_len;
  3537. void *data_ptr;
  3538. int data_len;
  3539. int headroom = 0;
  3540. int use_rx_sg = 0;
  3541. int frag = 0;
  3542. /* qeth_hdr must not cross element boundaries */
  3543. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3544. if (qeth_is_last_sbale(element))
  3545. return NULL;
  3546. element++;
  3547. offset = 0;
  3548. if (element->length < sizeof(struct qeth_hdr))
  3549. return NULL;
  3550. }
  3551. *hdr = element->addr + offset;
  3552. offset += sizeof(struct qeth_hdr);
  3553. if (card->options.layer2) {
  3554. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3555. skb_len = (*hdr)->hdr.osn.pdu_length;
  3556. headroom = sizeof(struct qeth_hdr);
  3557. } else {
  3558. skb_len = (*hdr)->hdr.l2.pkt_length;
  3559. }
  3560. } else {
  3561. skb_len = (*hdr)->hdr.l3.length;
  3562. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3563. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3564. headroom = TR_HLEN;
  3565. else
  3566. headroom = ETH_HLEN;
  3567. }
  3568. if (!skb_len)
  3569. return NULL;
  3570. if ((skb_len >= card->options.rx_sg_cb) &&
  3571. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3572. (!atomic_read(&card->force_alloc_skb))) {
  3573. use_rx_sg = 1;
  3574. } else {
  3575. skb = dev_alloc_skb(skb_len + headroom);
  3576. if (!skb)
  3577. goto no_mem;
  3578. if (headroom)
  3579. skb_reserve(skb, headroom);
  3580. }
  3581. data_ptr = element->addr + offset;
  3582. while (skb_len) {
  3583. data_len = min(skb_len, (int)(element->length - offset));
  3584. if (data_len) {
  3585. if (use_rx_sg) {
  3586. if (qeth_create_skb_frag(element, &skb, offset,
  3587. &frag, data_len))
  3588. goto no_mem;
  3589. } else {
  3590. memcpy(skb_put(skb, data_len), data_ptr,
  3591. data_len);
  3592. }
  3593. }
  3594. skb_len -= data_len;
  3595. if (skb_len) {
  3596. if (qeth_is_last_sbale(element)) {
  3597. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3598. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3599. CARD_BUS_ID(card));
  3600. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3601. QETH_DBF_TEXT_(QERR, 2, "%s",
  3602. CARD_BUS_ID(card));
  3603. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3604. dev_kfree_skb_any(skb);
  3605. card->stats.rx_errors++;
  3606. return NULL;
  3607. }
  3608. element++;
  3609. offset = 0;
  3610. data_ptr = element->addr;
  3611. } else {
  3612. offset += data_len;
  3613. }
  3614. }
  3615. *__element = element;
  3616. *__offset = offset;
  3617. if (use_rx_sg && card->options.performance_stats) {
  3618. card->perf_stats.sg_skbs_rx++;
  3619. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3620. }
  3621. return skb;
  3622. no_mem:
  3623. if (net_ratelimit()) {
  3624. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3625. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3626. }
  3627. card->stats.rx_dropped++;
  3628. return NULL;
  3629. }
  3630. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3631. static void qeth_unregister_dbf_views(void)
  3632. {
  3633. int x;
  3634. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3635. debug_unregister(qeth_dbf[x].id);
  3636. qeth_dbf[x].id = NULL;
  3637. }
  3638. }
  3639. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3640. {
  3641. char dbf_txt_buf[32];
  3642. va_list args;
  3643. if (level > (qeth_dbf[dbf_nix].id)->level)
  3644. return;
  3645. va_start(args, fmt);
  3646. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3647. va_end(args);
  3648. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3649. }
  3650. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3651. static int qeth_register_dbf_views(void)
  3652. {
  3653. int ret;
  3654. int x;
  3655. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3656. /* register the areas */
  3657. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3658. qeth_dbf[x].pages,
  3659. qeth_dbf[x].areas,
  3660. qeth_dbf[x].len);
  3661. if (qeth_dbf[x].id == NULL) {
  3662. qeth_unregister_dbf_views();
  3663. return -ENOMEM;
  3664. }
  3665. /* register a view */
  3666. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3667. if (ret) {
  3668. qeth_unregister_dbf_views();
  3669. return ret;
  3670. }
  3671. /* set a passing level */
  3672. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3673. }
  3674. return 0;
  3675. }
  3676. int qeth_core_load_discipline(struct qeth_card *card,
  3677. enum qeth_discipline_id discipline)
  3678. {
  3679. int rc = 0;
  3680. switch (discipline) {
  3681. case QETH_DISCIPLINE_LAYER3:
  3682. card->discipline.ccwgdriver = try_then_request_module(
  3683. symbol_get(qeth_l3_ccwgroup_driver),
  3684. "qeth_l3");
  3685. break;
  3686. case QETH_DISCIPLINE_LAYER2:
  3687. card->discipline.ccwgdriver = try_then_request_module(
  3688. symbol_get(qeth_l2_ccwgroup_driver),
  3689. "qeth_l2");
  3690. break;
  3691. }
  3692. if (!card->discipline.ccwgdriver) {
  3693. dev_err(&card->gdev->dev, "There is no kernel module to "
  3694. "support discipline %d\n", discipline);
  3695. rc = -EINVAL;
  3696. }
  3697. return rc;
  3698. }
  3699. void qeth_core_free_discipline(struct qeth_card *card)
  3700. {
  3701. if (card->options.layer2)
  3702. symbol_put(qeth_l2_ccwgroup_driver);
  3703. else
  3704. symbol_put(qeth_l3_ccwgroup_driver);
  3705. card->discipline.ccwgdriver = NULL;
  3706. }
  3707. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3708. {
  3709. struct qeth_card *card;
  3710. struct device *dev;
  3711. int rc;
  3712. unsigned long flags;
  3713. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3714. dev = &gdev->dev;
  3715. if (!get_device(dev))
  3716. return -ENODEV;
  3717. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3718. card = qeth_alloc_card();
  3719. if (!card) {
  3720. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3721. rc = -ENOMEM;
  3722. goto err_dev;
  3723. }
  3724. card->read.ccwdev = gdev->cdev[0];
  3725. card->write.ccwdev = gdev->cdev[1];
  3726. card->data.ccwdev = gdev->cdev[2];
  3727. dev_set_drvdata(&gdev->dev, card);
  3728. card->gdev = gdev;
  3729. gdev->cdev[0]->handler = qeth_irq;
  3730. gdev->cdev[1]->handler = qeth_irq;
  3731. gdev->cdev[2]->handler = qeth_irq;
  3732. rc = qeth_determine_card_type(card);
  3733. if (rc) {
  3734. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3735. goto err_card;
  3736. }
  3737. rc = qeth_setup_card(card);
  3738. if (rc) {
  3739. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3740. goto err_card;
  3741. }
  3742. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3743. rc = qeth_core_create_osn_attributes(dev);
  3744. if (rc)
  3745. goto err_card;
  3746. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3747. if (rc) {
  3748. qeth_core_remove_osn_attributes(dev);
  3749. goto err_card;
  3750. }
  3751. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3752. if (rc) {
  3753. qeth_core_free_discipline(card);
  3754. qeth_core_remove_osn_attributes(dev);
  3755. goto err_card;
  3756. }
  3757. } else {
  3758. rc = qeth_core_create_device_attributes(dev);
  3759. if (rc)
  3760. goto err_card;
  3761. }
  3762. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3763. list_add_tail(&card->list, &qeth_core_card_list.list);
  3764. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3765. return 0;
  3766. err_card:
  3767. qeth_core_free_card(card);
  3768. err_dev:
  3769. put_device(dev);
  3770. return rc;
  3771. }
  3772. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3773. {
  3774. unsigned long flags;
  3775. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3776. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3777. if (card->discipline.ccwgdriver) {
  3778. card->discipline.ccwgdriver->remove(gdev);
  3779. qeth_core_free_discipline(card);
  3780. }
  3781. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3782. qeth_core_remove_osn_attributes(&gdev->dev);
  3783. } else {
  3784. qeth_core_remove_device_attributes(&gdev->dev);
  3785. }
  3786. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3787. list_del(&card->list);
  3788. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3789. qeth_core_free_card(card);
  3790. dev_set_drvdata(&gdev->dev, NULL);
  3791. put_device(&gdev->dev);
  3792. return;
  3793. }
  3794. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3795. {
  3796. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3797. int rc = 0;
  3798. int def_discipline;
  3799. if (!card->discipline.ccwgdriver) {
  3800. if (card->info.type == QETH_CARD_TYPE_IQD)
  3801. def_discipline = QETH_DISCIPLINE_LAYER3;
  3802. else
  3803. def_discipline = QETH_DISCIPLINE_LAYER2;
  3804. rc = qeth_core_load_discipline(card, def_discipline);
  3805. if (rc)
  3806. goto err;
  3807. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3808. if (rc)
  3809. goto err;
  3810. }
  3811. rc = card->discipline.ccwgdriver->set_online(gdev);
  3812. err:
  3813. return rc;
  3814. }
  3815. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3816. {
  3817. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3818. return card->discipline.ccwgdriver->set_offline(gdev);
  3819. }
  3820. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3821. {
  3822. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3823. if (card->discipline.ccwgdriver &&
  3824. card->discipline.ccwgdriver->shutdown)
  3825. card->discipline.ccwgdriver->shutdown(gdev);
  3826. }
  3827. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3828. .owner = THIS_MODULE,
  3829. .name = "qeth",
  3830. .driver_id = 0xD8C5E3C8,
  3831. .probe = qeth_core_probe_device,
  3832. .remove = qeth_core_remove_device,
  3833. .set_online = qeth_core_set_online,
  3834. .set_offline = qeth_core_set_offline,
  3835. .shutdown = qeth_core_shutdown,
  3836. };
  3837. static ssize_t
  3838. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3839. size_t count)
  3840. {
  3841. int err;
  3842. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3843. qeth_core_ccwgroup_driver.driver_id);
  3844. if (err)
  3845. return err;
  3846. else
  3847. return count;
  3848. }
  3849. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3850. static struct {
  3851. const char str[ETH_GSTRING_LEN];
  3852. } qeth_ethtool_stats_keys[] = {
  3853. /* 0 */{"rx skbs"},
  3854. {"rx buffers"},
  3855. {"tx skbs"},
  3856. {"tx buffers"},
  3857. {"tx skbs no packing"},
  3858. {"tx buffers no packing"},
  3859. {"tx skbs packing"},
  3860. {"tx buffers packing"},
  3861. {"tx sg skbs"},
  3862. {"tx sg frags"},
  3863. /* 10 */{"rx sg skbs"},
  3864. {"rx sg frags"},
  3865. {"rx sg page allocs"},
  3866. {"tx large kbytes"},
  3867. {"tx large count"},
  3868. {"tx pk state ch n->p"},
  3869. {"tx pk state ch p->n"},
  3870. {"tx pk watermark low"},
  3871. {"tx pk watermark high"},
  3872. {"queue 0 buffer usage"},
  3873. /* 20 */{"queue 1 buffer usage"},
  3874. {"queue 2 buffer usage"},
  3875. {"queue 3 buffer usage"},
  3876. {"rx handler time"},
  3877. {"rx handler count"},
  3878. {"rx do_QDIO time"},
  3879. {"rx do_QDIO count"},
  3880. {"tx handler time"},
  3881. {"tx handler count"},
  3882. {"tx time"},
  3883. /* 30 */{"tx count"},
  3884. {"tx do_QDIO time"},
  3885. {"tx do_QDIO count"},
  3886. };
  3887. int qeth_core_get_stats_count(struct net_device *dev)
  3888. {
  3889. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3890. }
  3891. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3892. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3893. struct ethtool_stats *stats, u64 *data)
  3894. {
  3895. struct qeth_card *card = dev->ml_priv;
  3896. data[0] = card->stats.rx_packets -
  3897. card->perf_stats.initial_rx_packets;
  3898. data[1] = card->perf_stats.bufs_rec;
  3899. data[2] = card->stats.tx_packets -
  3900. card->perf_stats.initial_tx_packets;
  3901. data[3] = card->perf_stats.bufs_sent;
  3902. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3903. - card->perf_stats.skbs_sent_pack;
  3904. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3905. data[6] = card->perf_stats.skbs_sent_pack;
  3906. data[7] = card->perf_stats.bufs_sent_pack;
  3907. data[8] = card->perf_stats.sg_skbs_sent;
  3908. data[9] = card->perf_stats.sg_frags_sent;
  3909. data[10] = card->perf_stats.sg_skbs_rx;
  3910. data[11] = card->perf_stats.sg_frags_rx;
  3911. data[12] = card->perf_stats.sg_alloc_page_rx;
  3912. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3913. data[14] = card->perf_stats.large_send_cnt;
  3914. data[15] = card->perf_stats.sc_dp_p;
  3915. data[16] = card->perf_stats.sc_p_dp;
  3916. data[17] = QETH_LOW_WATERMARK_PACK;
  3917. data[18] = QETH_HIGH_WATERMARK_PACK;
  3918. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3919. data[20] = (card->qdio.no_out_queues > 1) ?
  3920. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  3921. data[21] = (card->qdio.no_out_queues > 2) ?
  3922. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  3923. data[22] = (card->qdio.no_out_queues > 3) ?
  3924. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  3925. data[23] = card->perf_stats.inbound_time;
  3926. data[24] = card->perf_stats.inbound_cnt;
  3927. data[25] = card->perf_stats.inbound_do_qdio_time;
  3928. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  3929. data[27] = card->perf_stats.outbound_handler_time;
  3930. data[28] = card->perf_stats.outbound_handler_cnt;
  3931. data[29] = card->perf_stats.outbound_time;
  3932. data[30] = card->perf_stats.outbound_cnt;
  3933. data[31] = card->perf_stats.outbound_do_qdio_time;
  3934. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  3935. }
  3936. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  3937. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3938. {
  3939. switch (stringset) {
  3940. case ETH_SS_STATS:
  3941. memcpy(data, &qeth_ethtool_stats_keys,
  3942. sizeof(qeth_ethtool_stats_keys));
  3943. break;
  3944. default:
  3945. WARN_ON(1);
  3946. break;
  3947. }
  3948. }
  3949. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  3950. void qeth_core_get_drvinfo(struct net_device *dev,
  3951. struct ethtool_drvinfo *info)
  3952. {
  3953. struct qeth_card *card = dev->ml_priv;
  3954. if (card->options.layer2)
  3955. strcpy(info->driver, "qeth_l2");
  3956. else
  3957. strcpy(info->driver, "qeth_l3");
  3958. strcpy(info->version, "1.0");
  3959. strcpy(info->fw_version, card->info.mcl_level);
  3960. sprintf(info->bus_info, "%s/%s/%s",
  3961. CARD_RDEV_ID(card),
  3962. CARD_WDEV_ID(card),
  3963. CARD_DDEV_ID(card));
  3964. }
  3965. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  3966. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  3967. struct ethtool_cmd *ecmd)
  3968. {
  3969. struct qeth_card *card = netdev->ml_priv;
  3970. enum qeth_link_types link_type;
  3971. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  3972. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  3973. else
  3974. link_type = card->info.link_type;
  3975. ecmd->transceiver = XCVR_INTERNAL;
  3976. ecmd->supported = SUPPORTED_Autoneg;
  3977. ecmd->advertising = ADVERTISED_Autoneg;
  3978. ecmd->duplex = DUPLEX_FULL;
  3979. ecmd->autoneg = AUTONEG_ENABLE;
  3980. switch (link_type) {
  3981. case QETH_LINK_TYPE_FAST_ETH:
  3982. case QETH_LINK_TYPE_LANE_ETH100:
  3983. ecmd->supported |= SUPPORTED_10baseT_Half |
  3984. SUPPORTED_10baseT_Full |
  3985. SUPPORTED_100baseT_Half |
  3986. SUPPORTED_100baseT_Full |
  3987. SUPPORTED_TP;
  3988. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3989. ADVERTISED_10baseT_Full |
  3990. ADVERTISED_100baseT_Half |
  3991. ADVERTISED_100baseT_Full |
  3992. ADVERTISED_TP;
  3993. ecmd->speed = SPEED_100;
  3994. ecmd->port = PORT_TP;
  3995. break;
  3996. case QETH_LINK_TYPE_GBIT_ETH:
  3997. case QETH_LINK_TYPE_LANE_ETH1000:
  3998. ecmd->supported |= SUPPORTED_10baseT_Half |
  3999. SUPPORTED_10baseT_Full |
  4000. SUPPORTED_100baseT_Half |
  4001. SUPPORTED_100baseT_Full |
  4002. SUPPORTED_1000baseT_Half |
  4003. SUPPORTED_1000baseT_Full |
  4004. SUPPORTED_FIBRE;
  4005. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4006. ADVERTISED_10baseT_Full |
  4007. ADVERTISED_100baseT_Half |
  4008. ADVERTISED_100baseT_Full |
  4009. ADVERTISED_1000baseT_Half |
  4010. ADVERTISED_1000baseT_Full |
  4011. ADVERTISED_FIBRE;
  4012. ecmd->speed = SPEED_1000;
  4013. ecmd->port = PORT_FIBRE;
  4014. break;
  4015. case QETH_LINK_TYPE_10GBIT_ETH:
  4016. ecmd->supported |= SUPPORTED_10baseT_Half |
  4017. SUPPORTED_10baseT_Full |
  4018. SUPPORTED_100baseT_Half |
  4019. SUPPORTED_100baseT_Full |
  4020. SUPPORTED_1000baseT_Half |
  4021. SUPPORTED_1000baseT_Full |
  4022. SUPPORTED_10000baseT_Full |
  4023. SUPPORTED_FIBRE;
  4024. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4025. ADVERTISED_10baseT_Full |
  4026. ADVERTISED_100baseT_Half |
  4027. ADVERTISED_100baseT_Full |
  4028. ADVERTISED_1000baseT_Half |
  4029. ADVERTISED_1000baseT_Full |
  4030. ADVERTISED_10000baseT_Full |
  4031. ADVERTISED_FIBRE;
  4032. ecmd->speed = SPEED_10000;
  4033. ecmd->port = PORT_FIBRE;
  4034. break;
  4035. default:
  4036. ecmd->supported |= SUPPORTED_10baseT_Half |
  4037. SUPPORTED_10baseT_Full |
  4038. SUPPORTED_TP;
  4039. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4040. ADVERTISED_10baseT_Full |
  4041. ADVERTISED_TP;
  4042. ecmd->speed = SPEED_10;
  4043. ecmd->port = PORT_TP;
  4044. }
  4045. return 0;
  4046. }
  4047. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4048. static int __init qeth_core_init(void)
  4049. {
  4050. int rc;
  4051. pr_info("loading core functions\n");
  4052. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4053. rwlock_init(&qeth_core_card_list.rwlock);
  4054. rc = qeth_register_dbf_views();
  4055. if (rc)
  4056. goto out_err;
  4057. rc = ccw_driver_register(&qeth_ccw_driver);
  4058. if (rc)
  4059. goto ccw_err;
  4060. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4061. if (rc)
  4062. goto ccwgroup_err;
  4063. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4064. &driver_attr_group);
  4065. if (rc)
  4066. goto driver_err;
  4067. qeth_core_root_dev = s390_root_dev_register("qeth");
  4068. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4069. if (rc)
  4070. goto register_err;
  4071. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4072. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4073. if (!qeth_core_header_cache) {
  4074. rc = -ENOMEM;
  4075. goto slab_err;
  4076. }
  4077. return 0;
  4078. slab_err:
  4079. s390_root_dev_unregister(qeth_core_root_dev);
  4080. register_err:
  4081. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4082. &driver_attr_group);
  4083. driver_err:
  4084. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4085. ccwgroup_err:
  4086. ccw_driver_unregister(&qeth_ccw_driver);
  4087. ccw_err:
  4088. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4089. qeth_unregister_dbf_views();
  4090. out_err:
  4091. pr_err("Initializing the qeth device driver failed\n");
  4092. return rc;
  4093. }
  4094. static void __exit qeth_core_exit(void)
  4095. {
  4096. s390_root_dev_unregister(qeth_core_root_dev);
  4097. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4098. &driver_attr_group);
  4099. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4100. ccw_driver_unregister(&qeth_ccw_driver);
  4101. kmem_cache_destroy(qeth_core_header_cache);
  4102. qeth_unregister_dbf_views();
  4103. pr_info("core functions removed\n");
  4104. }
  4105. module_init(qeth_core_init);
  4106. module_exit(qeth_core_exit);
  4107. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4108. MODULE_DESCRIPTION("qeth core functions");
  4109. MODULE_LICENSE("GPL");