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asm-arm
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hardware
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iop3xx.h

iop3xx.h 15 KB
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  1. /*
    2. 

  2.  * include/asm-arm/hardware/iop3xx.h
    3. 

  3.  *
    4. 

  4.  * Intel IOP32X and IOP33X register definitions
    5. 

  5.  *
    6. 

  6.  * Author: Rory Bolt <rorybolt@pacbell.net>
    7. 

  7.  * Copyright (C) 2002 Rory Bolt
    8. 

  8.  * Copyright (C) 2004 Intel Corp.
    9. 

  9.  *
    10. 

  10.  * This program is free software; you can redistribute it and/or modify
    11. 

  11.  * it under the terms of the GNU General Public License version 2 as
    12. 

  12.  * published by the Free Software Foundation.
    13. 

  13.  */
    14. 

  14. 

  15. #ifndef __IOP3XX_H
    16. 

  16. #define __IOP3XX_H
    17. 

  17. 

  18. /*
    19. 

  19.  * IOP3XX GPIO handling
    20. 

  20.  */
    21. 

  21. #define GPIO_IN			0
    22. 

  22. #define GPIO_OUT		1
    23. 

  23. #define GPIO_LOW		0
    24. 

  24. #define GPIO_HIGH		1
    25. 

  25. #define IOP3XX_GPIO_LINE(x)	(x)
    26. 

  26. 

  27. #ifndef __ASSEMBLY__
    28. 

  28. extern void gpio_line_config(int line, int direction);
    29. 

  29. extern int  gpio_line_get(int line);
    30. 

  30. extern void gpio_line_set(int line, int value);
    31. 

  31. extern int init_atu;
    32. 

  32. #endif
    33. 

  33. 

  34. 

  35. /*
    36. 

  36.  * IOP3XX processor registers
    37. 

  37.  */
    38. 

  38. #define IOP3XX_PERIPHERAL_PHYS_BASE	0xffffe000
    39. 

  39. #define IOP3XX_PERIPHERAL_VIRT_BASE	0xfeffe000
    40. 

  40. #define IOP3XX_PERIPHERAL_SIZE		0x00002000
    41. 

  41. #define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
    42. 

  42. 					IOP3XX_PERIPHERAL_SIZE - 1)
    43. 

  43. #define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
    44. 

  44. 					IOP3XX_PERIPHERAL_SIZE - 1)
    45. 

  45. #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
    46. 

  46. 					(IOP3XX_PERIPHERAL_PHYS_BASE\
    47. 

  47. 					- IOP3XX_PERIPHERAL_VIRT_BASE))
    48. 

  48. #define IOP3XX_REG_ADDR(reg)		(IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
    49. 

  49. 

  50. /* Address Translation Unit  */
    51. 

  51. #define IOP3XX_ATUVID		(volatile u16 *)IOP3XX_REG_ADDR(0x0100)
    52. 

  52. #define IOP3XX_ATUDID		(volatile u16 *)IOP3XX_REG_ADDR(0x0102)
    53. 

  53. #define IOP3XX_ATUCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x0104)
    54. 

  54. #define IOP3XX_ATUSR		(volatile u16 *)IOP3XX_REG_ADDR(0x0106)
    55. 

  55. #define IOP3XX_ATURID		(volatile u8  *)IOP3XX_REG_ADDR(0x0108)
    56. 

  56. #define IOP3XX_ATUCCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0109)
    57. 

  57. #define IOP3XX_ATUCLSR		(volatile u8  *)IOP3XX_REG_ADDR(0x010c)
    58. 

  58. #define IOP3XX_ATULT		(volatile u8  *)IOP3XX_REG_ADDR(0x010d)
    59. 

  59. #define IOP3XX_ATUHTR		(volatile u8  *)IOP3XX_REG_ADDR(0x010e)
    60. 

  60. #define IOP3XX_ATUBIST		(volatile u8  *)IOP3XX_REG_ADDR(0x010f)
    61. 

  61. #define IOP3XX_IABAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0110)
    62. 

  62. #define IOP3XX_IAUBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0114)
    63. 

  63. #define IOP3XX_IABAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0118)
    64. 

  64. #define IOP3XX_IAUBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x011c)
    65. 

  65. #define IOP3XX_IABAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0120)
    66. 

  66. #define IOP3XX_IAUBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0124)
    67. 

  67. #define IOP3XX_ASVIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012c)
    68. 

  68. #define IOP3XX_ASIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012e)
    69. 

  69. #define IOP3XX_ERBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0130)
    70. 

  70. #define IOP3XX_ATUILR		(volatile u8  *)IOP3XX_REG_ADDR(0x013c)
    71. 

  71. #define IOP3XX_ATUIPR		(volatile u8  *)IOP3XX_REG_ADDR(0x013d)
    72. 

  72. #define IOP3XX_ATUMGNT		(volatile u8  *)IOP3XX_REG_ADDR(0x013e)
    73. 

  73. #define IOP3XX_ATUMLAT		(volatile u8  *)IOP3XX_REG_ADDR(0x013f)
    74. 

  74. #define IOP3XX_IALR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0140)
    75. 

  75. #define IOP3XX_IATVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0144)
    76. 

  76. #define IOP3XX_ERLR		(volatile u32 *)IOP3XX_REG_ADDR(0x0148)
    77. 

  77. #define IOP3XX_ERTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x014c)
    78. 

  78. #define IOP3XX_IALR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0150)
    79. 

  79. #define IOP3XX_IALR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0154)
    80. 

  80. #define IOP3XX_IATVR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0158)
    81. 

  81. #define IOP3XX_OIOWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x015c)
    82. 

  82. #define IOP3XX_OMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0160)
    83. 

  83. #define IOP3XX_OUMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0164)
    84. 

  84. #define IOP3XX_OMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0168)
    85. 

  85. #define IOP3XX_OUMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x016c)
    86. 

  86. #define IOP3XX_OUDWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x0178)
    87. 

  87. #define IOP3XX_ATUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0180)
    88. 

  88. #define IOP3XX_PCSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0184)
    89. 

  89. #define IOP3XX_ATUISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0188)
    90. 

  90. #define IOP3XX_ATUIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x018c)
    91. 

  91. #define IOP3XX_IABAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0190)
    92. 

  92. #define IOP3XX_IAUBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0194)
    93. 

  93. #define IOP3XX_IALR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0198)
    94. 

  94. #define IOP3XX_IATVR3		(volatile u32 *)IOP3XX_REG_ADDR(0x019c)
    95. 

  95. #define IOP3XX_OCCAR		(volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
    96. 

  96. #define IOP3XX_OCCDR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
    97. 

  97. #define IOP3XX_PDSCR		(volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
    98. 

  98. #define IOP3XX_PMCAPID		(volatile u8  *)IOP3XX_REG_ADDR(0x01c0)
    99. 

  99. #define IOP3XX_PMNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01c1)
    100. 

  100. #define IOP3XX_APMCR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
    101. 

  101. #define IOP3XX_APMCSR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
    102. 

  102. #define IOP3XX_PCIXCAPID	(volatile u8  *)IOP3XX_REG_ADDR(0x01e0)
    103. 

  103. #define IOP3XX_PCIXNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01e1)
    104. 

  104. #define IOP3XX_PCIXCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
    105. 

  105. #define IOP3XX_PCIXSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
    106. 

  106. #define IOP3XX_PCIIRSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
    107. 

  107. #define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
    108. 

  108. #define IOP3XX_PCSR_IN_Q_BUSY	(1 << 14)
    109. 

  109. #define IOP3XX_ATUCR_OUT_EN	(1 << 1)
    110. 

  110. 

  111. #define IOP3XX_INIT_ATU_DEFAULT 0
    112. 

  112. #define IOP3XX_INIT_ATU_DISABLE -1
    113. 

  113. #define IOP3XX_INIT_ATU_ENABLE	 1
    114. 

  114. 

  115. #ifdef CONFIG_IOP3XX_ATU
    116. 

  116. #define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
    117. 

  117. 				IOP3XX_INIT_ATU_ENABLE : init_atu)
    118. 

  118. #else
    119. 

  119. #define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
    120. 

  120. 				IOP3XX_INIT_ATU_DISABLE : init_atu)
    121. 

  121. #endif
    122. 

  122. 

  123. /* Messaging Unit  */
    124. 

  124. #define IOP3XX_IMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0310)
    125. 

  125. #define IOP3XX_IMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0314)
    126. 

  126. #define IOP3XX_OMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0318)
    127. 

  127. #define IOP3XX_OMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x031c)
    128. 

  128. #define IOP3XX_IDR		(volatile u32 *)IOP3XX_REG_ADDR(0x0320)
    129. 

  129. #define IOP3XX_IISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0324)
    130. 

  130. #define IOP3XX_IIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0328)
    131. 

  131. #define IOP3XX_ODR		(volatile u32 *)IOP3XX_REG_ADDR(0x032c)
    132. 

  132. #define IOP3XX_OISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0330)
    133. 

  133. #define IOP3XX_OIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0334)
    134. 

  134. #define IOP3XX_MUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0350)
    135. 

  135. #define IOP3XX_QBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0354)
    136. 

  136. #define IOP3XX_IFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0360)
    137. 

  137. #define IOP3XX_IFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0364)
    138. 

  138. #define IOP3XX_IPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0368)
    139. 

  139. #define IOP3XX_IPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x036c)
    140. 

  140. #define IOP3XX_OFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0370)
    141. 

  141. #define IOP3XX_OFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0374)
    142. 

  142. #define IOP3XX_OPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0378)
    143. 

  143. #define IOP3XX_OPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x037c)
    144. 

  144. #define IOP3XX_IAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0380)
    145. 

  145. 

  146. /* DMA Controller  */
    147. 

  147. #define IOP3XX_DMA0_CCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0400)
    148. 

  148. #define IOP3XX_DMA0_CSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0404)
    149. 

  149. #define IOP3XX_DMA0_DAR		(volatile u32 *)IOP3XX_REG_ADDR(0x040c)
    150. 

  150. #define IOP3XX_DMA0_NDAR	(volatile u32 *)IOP3XX_REG_ADDR(0x0410)
    151. 

  151. #define IOP3XX_DMA0_PADR	(volatile u32 *)IOP3XX_REG_ADDR(0x0414)
    152. 

  152. #define IOP3XX_DMA0_PUADR	(volatile u32 *)IOP3XX_REG_ADDR(0x0418)
    153. 

  153. #define IOP3XX_DMA0_LADR	(volatile u32 *)IOP3XX_REG_ADDR(0x041c)
    154. 

  154. #define IOP3XX_DMA0_BCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0420)
    155. 

  155. #define IOP3XX_DMA0_DCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0424)
    156. 

  156. #define IOP3XX_DMA1_CCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0440)
    157. 

  157. #define IOP3XX_DMA1_CSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0444)
    158. 

  158. #define IOP3XX_DMA1_DAR		(volatile u32 *)IOP3XX_REG_ADDR(0x044c)
    159. 

  159. #define IOP3XX_DMA1_NDAR	(volatile u32 *)IOP3XX_REG_ADDR(0x0450)
    160. 

  160. #define IOP3XX_DMA1_PADR	(volatile u32 *)IOP3XX_REG_ADDR(0x0454)
    161. 

  161. #define IOP3XX_DMA1_PUADR	(volatile u32 *)IOP3XX_REG_ADDR(0x0458)
    162. 

  162. #define IOP3XX_DMA1_LADR	(volatile u32 *)IOP3XX_REG_ADDR(0x045c)
    163. 

  163. #define IOP3XX_DMA1_BCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0460)
    164. 

  164. #define IOP3XX_DMA1_DCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0464)
    165. 

  165. 

  166. /* Peripheral bus interface  */
    167. 

  167. #define IOP3XX_PBCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0680)
    168. 

  168. #define IOP3XX_PBISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0684)
    169. 

  169. #define IOP3XX_PBBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0688)
    170. 

  170. #define IOP3XX_PBLR0		(volatile u32 *)IOP3XX_REG_ADDR(0x068c)
    171. 

  171. #define IOP3XX_PBBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0690)
    172. 

  172. #define IOP3XX_PBLR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0694)
    173. 

  173. #define IOP3XX_PBBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0698)
    174. 

  174. #define IOP3XX_PBLR2		(volatile u32 *)IOP3XX_REG_ADDR(0x069c)
    175. 

  175. #define IOP3XX_PBBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
    176. 

  176. #define IOP3XX_PBLR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
    177. 

  177. #define IOP3XX_PBBAR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
    178. 

  178. #define IOP3XX_PBLR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
    179. 

  179. #define IOP3XX_PBBAR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
    180. 

  180. #define IOP3XX_PBLR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
    181. 

  181. #define IOP3XX_PMBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
    182. 

  182. #define IOP3XX_PMBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
    183. 

  183. #define IOP3XX_PMBR2		(volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
    184. 

  184. 

  185. /* Peripheral performance monitoring unit  */
    186. 

  186. #define IOP3XX_GTMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0700)
    187. 

  187. #define IOP3XX_ESR		(volatile u32 *)IOP3XX_REG_ADDR(0x0704)
    188. 

  188. #define IOP3XX_EMISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0708)
    189. 

  189. #define IOP3XX_GTSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)
    190. 

  190. /* PERCR0 DOESN'T EXIST - index from 1! */
    191. 

  191. #define IOP3XX_PERCR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)
    192. 

  192. 

  193. /* General Purpose I/O  */
    194. 

  194. #define IOP3XX_GPOE		(volatile u32 *)IOP3XX_GPIO_REG(0x0000)
    195. 

  195. #define IOP3XX_GPID		(volatile u32 *)IOP3XX_GPIO_REG(0x0004)
    196. 

  196. #define IOP3XX_GPOD		(volatile u32 *)IOP3XX_GPIO_REG(0x0008)
    197. 

  197. 

  198. /* Timers  */
    199. 

  199. #define IOP3XX_TU_TMR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0000)
    200. 

  200. #define IOP3XX_TU_TMR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0004)
    201. 

  201. #define IOP3XX_TU_TCR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0008)
    202. 

  202. #define IOP3XX_TU_TCR1		(volatile u32 *)IOP3XX_TIMER_REG(0x000c)
    203. 

  203. #define IOP3XX_TU_TRR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0010)
    204. 

  204. #define IOP3XX_TU_TRR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0014)
    205. 

  205. #define IOP3XX_TU_TISR		(volatile u32 *)IOP3XX_TIMER_REG(0x0018)
    206. 

  206. #define IOP3XX_TU_WDTCR		(volatile u32 *)IOP3XX_TIMER_REG(0x001c)
    207. 

  207. #define IOP_TMR_EN	    0x02
    208. 

  208. #define IOP_TMR_RELOAD	    0x04
    209. 

  209. #define IOP_TMR_PRIVILEGED 0x08
    210. 

  210. #define IOP_TMR_RATIO_1_1  0x00
    211. 

  211. 

  212. /* Application accelerator unit  */
    213. 

  213. #define IOP3XX_AAU_ACR		(volatile u32 *)IOP3XX_REG_ADDR(0x0800)
    214. 

  214. #define IOP3XX_AAU_ASR		(volatile u32 *)IOP3XX_REG_ADDR(0x0804)
    215. 

  215. #define IOP3XX_AAU_ADAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0808)
    216. 

  216. #define IOP3XX_AAU_ANDAR	(volatile u32 *)IOP3XX_REG_ADDR(0x080c)
    217. 

  217. #define IOP3XX_AAU_SAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0810)
    218. 

  218. #define IOP3XX_AAU_SAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0814)
    219. 

  219. #define IOP3XX_AAU_SAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0818)
    220. 

  220. #define IOP3XX_AAU_SAR4		(volatile u32 *)IOP3XX_REG_ADDR(0x081c)
    221. 

  221. #define IOP3XX_AAU_DAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0820)
    222. 

  222. #define IOP3XX_AAU_ABCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0824)
    223. 

  223. #define IOP3XX_AAU_ADCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0828)
    224. 

  224. #define IOP3XX_AAU_SAR5		(volatile u32 *)IOP3XX_REG_ADDR(0x082c)
    225. 

  225. #define IOP3XX_AAU_SAR6		(volatile u32 *)IOP3XX_REG_ADDR(0x0830)
    226. 

  226. #define IOP3XX_AAU_SAR7		(volatile u32 *)IOP3XX_REG_ADDR(0x0834)
    227. 

  227. #define IOP3XX_AAU_SAR8		(volatile u32 *)IOP3XX_REG_ADDR(0x0838)
    228. 

  228. #define IOP3XX_AAU_EDCR0	(volatile u32 *)IOP3XX_REG_ADDR(0x083c)
    229. 

  229. #define IOP3XX_AAU_SAR9		(volatile u32 *)IOP3XX_REG_ADDR(0x0840)
    230. 

  230. #define IOP3XX_AAU_SAR10	(volatile u32 *)IOP3XX_REG_ADDR(0x0844)
    231. 

  231. #define IOP3XX_AAU_SAR11	(volatile u32 *)IOP3XX_REG_ADDR(0x0848)
    232. 

  232. #define IOP3XX_AAU_SAR12	(volatile u32 *)IOP3XX_REG_ADDR(0x084c)
    233. 

  233. #define IOP3XX_AAU_SAR13	(volatile u32 *)IOP3XX_REG_ADDR(0x0850)
    234. 

  234. #define IOP3XX_AAU_SAR14	(volatile u32 *)IOP3XX_REG_ADDR(0x0854)
    235. 

  235. #define IOP3XX_AAU_SAR15	(volatile u32 *)IOP3XX_REG_ADDR(0x0858)
    236. 

  236. #define IOP3XX_AAU_SAR16	(volatile u32 *)IOP3XX_REG_ADDR(0x085c)
    237. 

  237. #define IOP3XX_AAU_EDCR1	(volatile u32 *)IOP3XX_REG_ADDR(0x0860)
    238. 

  238. #define IOP3XX_AAU_SAR17	(volatile u32 *)IOP3XX_REG_ADDR(0x0864)
    239. 

  239. #define IOP3XX_AAU_SAR18	(volatile u32 *)IOP3XX_REG_ADDR(0x0868)
    240. 

  240. #define IOP3XX_AAU_SAR19	(volatile u32 *)IOP3XX_REG_ADDR(0x086c)
    241. 

  241. #define IOP3XX_AAU_SAR20	(volatile u32 *)IOP3XX_REG_ADDR(0x0870)
    242. 

  242. #define IOP3XX_AAU_SAR21	(volatile u32 *)IOP3XX_REG_ADDR(0x0874)
    243. 

  243. #define IOP3XX_AAU_SAR22	(volatile u32 *)IOP3XX_REG_ADDR(0x0878)
    244. 

  244. #define IOP3XX_AAU_SAR23	(volatile u32 *)IOP3XX_REG_ADDR(0x087c)
    245. 

  245. #define IOP3XX_AAU_SAR24	(volatile u32 *)IOP3XX_REG_ADDR(0x0880)
    246. 

  246. #define IOP3XX_AAU_EDCR2	(volatile u32 *)IOP3XX_REG_ADDR(0x0884)
    247. 

  247. #define IOP3XX_AAU_SAR25	(volatile u32 *)IOP3XX_REG_ADDR(0x0888)
    248. 

  248. #define IOP3XX_AAU_SAR26	(volatile u32 *)IOP3XX_REG_ADDR(0x088c)
    249. 

  249. #define IOP3XX_AAU_SAR27	(volatile u32 *)IOP3XX_REG_ADDR(0x0890)
    250. 

  250. #define IOP3XX_AAU_SAR28	(volatile u32 *)IOP3XX_REG_ADDR(0x0894)
    251. 

  251. #define IOP3XX_AAU_SAR29	(volatile u32 *)IOP3XX_REG_ADDR(0x0898)
    252. 

  252. #define IOP3XX_AAU_SAR30	(volatile u32 *)IOP3XX_REG_ADDR(0x089c)
    253. 

  253. #define IOP3XX_AAU_SAR31	(volatile u32 *)IOP3XX_REG_ADDR(0x08a0)
    254. 

  254. #define IOP3XX_AAU_SAR32	(volatile u32 *)IOP3XX_REG_ADDR(0x08a4)
    255. 

  255. 

  256. /* I2C bus interface unit  */
    257. 

  257. #define IOP3XX_ICR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1680)
    258. 

  258. #define IOP3XX_ISR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1684)
    259. 

  259. #define IOP3XX_ISAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1688)
    260. 

  260. #define IOP3XX_IDBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x168c)
    261. 

  261. #define IOP3XX_IBMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1694)
    262. 

  262. #define IOP3XX_ICR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
    263. 

  263. #define IOP3XX_ISR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
    264. 

  264. #define IOP3XX_ISAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
    265. 

  265. #define IOP3XX_IDBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
    266. 

  266. #define IOP3XX_IBMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
    267. 

  267. 

  268. 

  269. /*
    270. 

  270.  * IOP3XX I/O and Mem space regions for PCI autoconfiguration
    271. 

  271.  */
    272. 

  272. #define IOP3XX_PCI_LOWER_MEM_PA	0x80000000
    273. 

  273. 

  274. #define IOP3XX_PCI_IO_WINDOW_SIZE	0x00010000
    275. 

  275. #define IOP3XX_PCI_LOWER_IO_PA		0x90000000
    276. 

  276. #define IOP3XX_PCI_LOWER_IO_VA		0xfe000000
    277. 

  277. #define IOP3XX_PCI_LOWER_IO_BA		0x90000000
    278. 

  278. #define IOP3XX_PCI_UPPER_IO_PA		(IOP3XX_PCI_LOWER_IO_PA +\
    279. 

  279. 					IOP3XX_PCI_IO_WINDOW_SIZE - 1)
    280. 

  280. #define IOP3XX_PCI_UPPER_IO_VA		(IOP3XX_PCI_LOWER_IO_VA +\
    281. 

  281. 					IOP3XX_PCI_IO_WINDOW_SIZE - 1)
    282. 

  282. #define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) addr -\
    283. 

  283. 					IOP3XX_PCI_LOWER_IO_PA) +\
    284. 

  284. 					IOP3XX_PCI_LOWER_IO_VA)
    285. 

  285. 

  286. 

  287. #ifndef __ASSEMBLY__
    288. 

  288. void iop3xx_map_io(void);
    289. 

  289. void iop_init_cp6_handler(void);
    290. 

  290. void iop_init_time(unsigned long tickrate);
    291. 

  291. unsigned long iop_gettimeoffset(void);
    292. 

  292. 

  293. static inline void write_tmr0(u32 val)
    294. 

  294. {
    295. 

  295. 	asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
    296. 

  296. }
    297. 

  297. 

  298. static inline void write_tmr1(u32 val)
    299. 

  299. {
    300. 

  300. 	asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
    301. 

  301. }
    302. 

  302. 

  303. static inline u32 read_tcr0(void)
    304. 

  304. {
    305. 

  305. 	u32 val;
    306. 

  306. 	asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
    307. 

  307. 	return val;
    308. 

  308. }
    309. 

  309. 

  310. static inline u32 read_tcr1(void)
    311. 

  311. {
    312. 

  312. 	u32 val;
    313. 

  313. 	asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
    314. 

  314. 	return val;
    315. 

  315. }
    316. 

  316. 

  317. static inline void write_trr0(u32 val)
    318. 

  318. {
    319. 

  319. 	asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
    320. 

  320. }
    321. 

  321. 

  322. static inline void write_trr1(u32 val)
    323. 

  323. {
    324. 

  324. 	asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
    325. 

  325. }
    326. 

  326. 

  327. static inline void write_tisr(u32 val)
    328. 

  328. {
    329. 

  329. 	asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
    330. 

  330. }
    331. 

  331. 

  332. extern struct platform_device iop3xx_i2c0_device;
    333. 

  333. extern struct platform_device iop3xx_i2c1_device;
    334. 

  334. 

  335. #endif
    336. 

  336. 

  337. 

  338. #endif
    339.