uhci-q.c 45 KB

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  1. /*
  2. * Universal Host Controller Interface driver for USB.
  3. *
  4. * Maintainer: Alan Stern <stern@rowland.harvard.edu>
  5. *
  6. * (C) Copyright 1999 Linus Torvalds
  7. * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
  8. * (C) Copyright 1999 Randy Dunlap
  9. * (C) Copyright 1999 Georg Acher, acher@in.tum.de
  10. * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
  11. * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
  12. * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
  13. * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
  14. * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
  15. * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
  16. * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
  17. */
  18. /*
  19. * Technically, updating td->status here is a race, but it's not really a
  20. * problem. The worst that can happen is that we set the IOC bit again
  21. * generating a spurious interrupt. We could fix this by creating another
  22. * QH and leaving the IOC bit always set, but then we would have to play
  23. * games with the FSBR code to make sure we get the correct order in all
  24. * the cases. I don't think it's worth the effort
  25. */
  26. static void uhci_set_next_interrupt(struct uhci_hcd *uhci)
  27. {
  28. if (uhci->is_stopped)
  29. mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
  30. uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC);
  31. }
  32. static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
  33. {
  34. uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
  35. }
  36. /*
  37. * Full-Speed Bandwidth Reclamation (FSBR).
  38. * We turn on FSBR whenever a queue that wants it is advancing,
  39. * and leave it on for a short time thereafter.
  40. */
  41. static void uhci_fsbr_on(struct uhci_hcd *uhci)
  42. {
  43. struct uhci_qh *lqh;
  44. /* The terminating skeleton QH always points back to the first
  45. * FSBR QH. Make the last async QH point to the terminating
  46. * skeleton QH. */
  47. uhci->fsbr_is_on = 1;
  48. lqh = list_entry(uhci->skel_async_qh->node.prev,
  49. struct uhci_qh, node);
  50. lqh->link = LINK_TO_QH(uhci->skel_term_qh);
  51. }
  52. static void uhci_fsbr_off(struct uhci_hcd *uhci)
  53. {
  54. struct uhci_qh *lqh;
  55. /* Remove the link from the last async QH to the terminating
  56. * skeleton QH. */
  57. uhci->fsbr_is_on = 0;
  58. lqh = list_entry(uhci->skel_async_qh->node.prev,
  59. struct uhci_qh, node);
  60. lqh->link = UHCI_PTR_TERM;
  61. }
  62. static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  63. {
  64. struct urb_priv *urbp = urb->hcpriv;
  65. if (!(urb->transfer_flags & URB_NO_FSBR))
  66. urbp->fsbr = 1;
  67. }
  68. static void uhci_urbp_wants_fsbr(struct uhci_hcd *uhci, struct urb_priv *urbp)
  69. {
  70. if (urbp->fsbr) {
  71. uhci->fsbr_is_wanted = 1;
  72. if (!uhci->fsbr_is_on)
  73. uhci_fsbr_on(uhci);
  74. else if (uhci->fsbr_expiring) {
  75. uhci->fsbr_expiring = 0;
  76. del_timer(&uhci->fsbr_timer);
  77. }
  78. }
  79. }
  80. static void uhci_fsbr_timeout(unsigned long _uhci)
  81. {
  82. struct uhci_hcd *uhci = (struct uhci_hcd *) _uhci;
  83. unsigned long flags;
  84. spin_lock_irqsave(&uhci->lock, flags);
  85. if (uhci->fsbr_expiring) {
  86. uhci->fsbr_expiring = 0;
  87. uhci_fsbr_off(uhci);
  88. }
  89. spin_unlock_irqrestore(&uhci->lock, flags);
  90. }
  91. static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci)
  92. {
  93. dma_addr_t dma_handle;
  94. struct uhci_td *td;
  95. td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
  96. if (!td)
  97. return NULL;
  98. td->dma_handle = dma_handle;
  99. td->frame = -1;
  100. INIT_LIST_HEAD(&td->list);
  101. INIT_LIST_HEAD(&td->fl_list);
  102. return td;
  103. }
  104. static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
  105. {
  106. if (!list_empty(&td->list)) {
  107. dev_warn(uhci_dev(uhci), "td %p still in list!\n", td);
  108. WARN_ON(1);
  109. }
  110. if (!list_empty(&td->fl_list)) {
  111. dev_warn(uhci_dev(uhci), "td %p still in fl_list!\n", td);
  112. WARN_ON(1);
  113. }
  114. dma_pool_free(uhci->td_pool, td, td->dma_handle);
  115. }
  116. static inline void uhci_fill_td(struct uhci_td *td, u32 status,
  117. u32 token, u32 buffer)
  118. {
  119. td->status = cpu_to_le32(status);
  120. td->token = cpu_to_le32(token);
  121. td->buffer = cpu_to_le32(buffer);
  122. }
  123. static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp)
  124. {
  125. list_add_tail(&td->list, &urbp->td_list);
  126. }
  127. static void uhci_remove_td_from_urbp(struct uhci_td *td)
  128. {
  129. list_del_init(&td->list);
  130. }
  131. /*
  132. * We insert Isochronous URBs directly into the frame list at the beginning
  133. */
  134. static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci,
  135. struct uhci_td *td, unsigned framenum)
  136. {
  137. framenum &= (UHCI_NUMFRAMES - 1);
  138. td->frame = framenum;
  139. /* Is there a TD already mapped there? */
  140. if (uhci->frame_cpu[framenum]) {
  141. struct uhci_td *ftd, *ltd;
  142. ftd = uhci->frame_cpu[framenum];
  143. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  144. list_add_tail(&td->fl_list, &ftd->fl_list);
  145. td->link = ltd->link;
  146. wmb();
  147. ltd->link = LINK_TO_TD(td);
  148. } else {
  149. td->link = uhci->frame[framenum];
  150. wmb();
  151. uhci->frame[framenum] = LINK_TO_TD(td);
  152. uhci->frame_cpu[framenum] = td;
  153. }
  154. }
  155. static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci,
  156. struct uhci_td *td)
  157. {
  158. /* If it's not inserted, don't remove it */
  159. if (td->frame == -1) {
  160. WARN_ON(!list_empty(&td->fl_list));
  161. return;
  162. }
  163. if (uhci->frame_cpu[td->frame] == td) {
  164. if (list_empty(&td->fl_list)) {
  165. uhci->frame[td->frame] = td->link;
  166. uhci->frame_cpu[td->frame] = NULL;
  167. } else {
  168. struct uhci_td *ntd;
  169. ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list);
  170. uhci->frame[td->frame] = LINK_TO_TD(ntd);
  171. uhci->frame_cpu[td->frame] = ntd;
  172. }
  173. } else {
  174. struct uhci_td *ptd;
  175. ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
  176. ptd->link = td->link;
  177. }
  178. list_del_init(&td->fl_list);
  179. td->frame = -1;
  180. }
  181. static inline void uhci_remove_tds_from_frame(struct uhci_hcd *uhci,
  182. unsigned int framenum)
  183. {
  184. struct uhci_td *ftd, *ltd;
  185. framenum &= (UHCI_NUMFRAMES - 1);
  186. ftd = uhci->frame_cpu[framenum];
  187. if (ftd) {
  188. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  189. uhci->frame[framenum] = ltd->link;
  190. uhci->frame_cpu[framenum] = NULL;
  191. while (!list_empty(&ftd->fl_list))
  192. list_del_init(ftd->fl_list.prev);
  193. }
  194. }
  195. /*
  196. * Remove all the TDs for an Isochronous URB from the frame list
  197. */
  198. static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb)
  199. {
  200. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  201. struct uhci_td *td;
  202. list_for_each_entry(td, &urbp->td_list, list)
  203. uhci_remove_td_from_frame_list(uhci, td);
  204. }
  205. static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci,
  206. struct usb_device *udev, struct usb_host_endpoint *hep)
  207. {
  208. dma_addr_t dma_handle;
  209. struct uhci_qh *qh;
  210. qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
  211. if (!qh)
  212. return NULL;
  213. memset(qh, 0, sizeof(*qh));
  214. qh->dma_handle = dma_handle;
  215. qh->element = UHCI_PTR_TERM;
  216. qh->link = UHCI_PTR_TERM;
  217. INIT_LIST_HEAD(&qh->queue);
  218. INIT_LIST_HEAD(&qh->node);
  219. if (udev) { /* Normal QH */
  220. qh->type = hep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  221. if (qh->type != USB_ENDPOINT_XFER_ISOC) {
  222. qh->dummy_td = uhci_alloc_td(uhci);
  223. if (!qh->dummy_td) {
  224. dma_pool_free(uhci->qh_pool, qh, dma_handle);
  225. return NULL;
  226. }
  227. }
  228. qh->state = QH_STATE_IDLE;
  229. qh->hep = hep;
  230. qh->udev = udev;
  231. hep->hcpriv = qh;
  232. if (qh->type == USB_ENDPOINT_XFER_INT ||
  233. qh->type == USB_ENDPOINT_XFER_ISOC)
  234. qh->load = usb_calc_bus_time(udev->speed,
  235. usb_endpoint_dir_in(&hep->desc),
  236. qh->type == USB_ENDPOINT_XFER_ISOC,
  237. le16_to_cpu(hep->desc.wMaxPacketSize))
  238. / 1000 + 1;
  239. } else { /* Skeleton QH */
  240. qh->state = QH_STATE_ACTIVE;
  241. qh->type = -1;
  242. }
  243. return qh;
  244. }
  245. static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  246. {
  247. WARN_ON(qh->state != QH_STATE_IDLE && qh->udev);
  248. if (!list_empty(&qh->queue)) {
  249. dev_warn(uhci_dev(uhci), "qh %p list not empty!\n", qh);
  250. WARN_ON(1);
  251. }
  252. list_del(&qh->node);
  253. if (qh->udev) {
  254. qh->hep->hcpriv = NULL;
  255. if (qh->dummy_td)
  256. uhci_free_td(uhci, qh->dummy_td);
  257. }
  258. dma_pool_free(uhci->qh_pool, qh, qh->dma_handle);
  259. }
  260. /*
  261. * When a queue is stopped and a dequeued URB is given back, adjust
  262. * the previous TD link (if the URB isn't first on the queue) or
  263. * save its toggle value (if it is first and is currently executing).
  264. *
  265. * Returns 0 if the URB should not yet be given back, 1 otherwise.
  266. */
  267. static int uhci_cleanup_queue(struct uhci_hcd *uhci, struct uhci_qh *qh,
  268. struct urb *urb)
  269. {
  270. struct urb_priv *urbp = urb->hcpriv;
  271. struct uhci_td *td;
  272. int ret = 1;
  273. /* Isochronous pipes don't use toggles and their TD link pointers
  274. * get adjusted during uhci_urb_dequeue(). But since their queues
  275. * cannot truly be stopped, we have to watch out for dequeues
  276. * occurring after the nominal unlink frame. */
  277. if (qh->type == USB_ENDPOINT_XFER_ISOC) {
  278. ret = (uhci->frame_number + uhci->is_stopped !=
  279. qh->unlink_frame);
  280. goto done;
  281. }
  282. /* If the URB isn't first on its queue, adjust the link pointer
  283. * of the last TD in the previous URB. The toggle doesn't need
  284. * to be saved since this URB can't be executing yet. */
  285. if (qh->queue.next != &urbp->node) {
  286. struct urb_priv *purbp;
  287. struct uhci_td *ptd;
  288. purbp = list_entry(urbp->node.prev, struct urb_priv, node);
  289. WARN_ON(list_empty(&purbp->td_list));
  290. ptd = list_entry(purbp->td_list.prev, struct uhci_td,
  291. list);
  292. td = list_entry(urbp->td_list.prev, struct uhci_td,
  293. list);
  294. ptd->link = td->link;
  295. goto done;
  296. }
  297. /* If the QH element pointer is UHCI_PTR_TERM then then currently
  298. * executing URB has already been unlinked, so this one isn't it. */
  299. if (qh_element(qh) == UHCI_PTR_TERM)
  300. goto done;
  301. qh->element = UHCI_PTR_TERM;
  302. /* Control pipes don't have to worry about toggles */
  303. if (qh->type == USB_ENDPOINT_XFER_CONTROL)
  304. goto done;
  305. /* Save the next toggle value */
  306. WARN_ON(list_empty(&urbp->td_list));
  307. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  308. qh->needs_fixup = 1;
  309. qh->initial_toggle = uhci_toggle(td_token(td));
  310. done:
  311. return ret;
  312. }
  313. /*
  314. * Fix up the data toggles for URBs in a queue, when one of them
  315. * terminates early (short transfer, error, or dequeued).
  316. */
  317. static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first)
  318. {
  319. struct urb_priv *urbp = NULL;
  320. struct uhci_td *td;
  321. unsigned int toggle = qh->initial_toggle;
  322. unsigned int pipe;
  323. /* Fixups for a short transfer start with the second URB in the
  324. * queue (the short URB is the first). */
  325. if (skip_first)
  326. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  327. /* When starting with the first URB, if the QH element pointer is
  328. * still valid then we know the URB's toggles are okay. */
  329. else if (qh_element(qh) != UHCI_PTR_TERM)
  330. toggle = 2;
  331. /* Fix up the toggle for the URBs in the queue. Normally this
  332. * loop won't run more than once: When an error or short transfer
  333. * occurs, the queue usually gets emptied. */
  334. urbp = list_prepare_entry(urbp, &qh->queue, node);
  335. list_for_each_entry_continue(urbp, &qh->queue, node) {
  336. /* If the first TD has the right toggle value, we don't
  337. * need to change any toggles in this URB */
  338. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  339. if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) {
  340. td = list_entry(urbp->td_list.prev, struct uhci_td,
  341. list);
  342. toggle = uhci_toggle(td_token(td)) ^ 1;
  343. /* Otherwise all the toggles in the URB have to be switched */
  344. } else {
  345. list_for_each_entry(td, &urbp->td_list, list) {
  346. td->token ^= __constant_cpu_to_le32(
  347. TD_TOKEN_TOGGLE);
  348. toggle ^= 1;
  349. }
  350. }
  351. }
  352. wmb();
  353. pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe;
  354. usb_settoggle(qh->udev, usb_pipeendpoint(pipe),
  355. usb_pipeout(pipe), toggle);
  356. qh->needs_fixup = 0;
  357. }
  358. /*
  359. * Link an Isochronous QH into its skeleton's list
  360. */
  361. static inline void link_iso(struct uhci_hcd *uhci, struct uhci_qh *qh)
  362. {
  363. list_add_tail(&qh->node, &uhci->skel_iso_qh->node);
  364. /* Isochronous QHs aren't linked by the hardware */
  365. }
  366. /*
  367. * Link a high-period interrupt QH into the schedule at the end of its
  368. * skeleton's list
  369. */
  370. static void link_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh)
  371. {
  372. struct uhci_qh *pqh;
  373. list_add_tail(&qh->node, &uhci->skelqh[qh->skel]->node);
  374. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  375. qh->link = pqh->link;
  376. wmb();
  377. pqh->link = LINK_TO_QH(qh);
  378. }
  379. /*
  380. * Link a period-1 interrupt or async QH into the schedule at the
  381. * correct spot in the async skeleton's list, and update the FSBR link
  382. */
  383. static void link_async(struct uhci_hcd *uhci, struct uhci_qh *qh)
  384. {
  385. struct uhci_qh *pqh;
  386. __le32 link_to_new_qh;
  387. /* Find the predecessor QH for our new one and insert it in the list.
  388. * The list of QHs is expected to be short, so linear search won't
  389. * take too long. */
  390. list_for_each_entry_reverse(pqh, &uhci->skel_async_qh->node, node) {
  391. if (pqh->skel <= qh->skel)
  392. break;
  393. }
  394. list_add(&qh->node, &pqh->node);
  395. /* Link it into the schedule */
  396. qh->link = pqh->link;
  397. wmb();
  398. link_to_new_qh = LINK_TO_QH(qh);
  399. pqh->link = link_to_new_qh;
  400. /* If this is now the first FSBR QH, link the terminating skeleton
  401. * QH to it. */
  402. if (pqh->skel < SKEL_FSBR && qh->skel >= SKEL_FSBR)
  403. uhci->skel_term_qh->link = link_to_new_qh;
  404. }
  405. /*
  406. * Put a QH on the schedule in both hardware and software
  407. */
  408. static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  409. {
  410. WARN_ON(list_empty(&qh->queue));
  411. /* Set the element pointer if it isn't set already.
  412. * This isn't needed for Isochronous queues, but it doesn't hurt. */
  413. if (qh_element(qh) == UHCI_PTR_TERM) {
  414. struct urb_priv *urbp = list_entry(qh->queue.next,
  415. struct urb_priv, node);
  416. struct uhci_td *td = list_entry(urbp->td_list.next,
  417. struct uhci_td, list);
  418. qh->element = LINK_TO_TD(td);
  419. }
  420. /* Treat the queue as if it has just advanced */
  421. qh->wait_expired = 0;
  422. qh->advance_jiffies = jiffies;
  423. if (qh->state == QH_STATE_ACTIVE)
  424. return;
  425. qh->state = QH_STATE_ACTIVE;
  426. /* Move the QH from its old list to the correct spot in the appropriate
  427. * skeleton's list */
  428. if (qh == uhci->next_qh)
  429. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  430. node);
  431. list_del(&qh->node);
  432. if (qh->skel == SKEL_ISO)
  433. link_iso(uhci, qh);
  434. else if (qh->skel < SKEL_ASYNC)
  435. link_interrupt(uhci, qh);
  436. else
  437. link_async(uhci, qh);
  438. }
  439. /*
  440. * Unlink a high-period interrupt QH from the schedule
  441. */
  442. static void unlink_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh)
  443. {
  444. struct uhci_qh *pqh;
  445. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  446. pqh->link = qh->link;
  447. mb();
  448. }
  449. /*
  450. * Unlink a period-1 interrupt or async QH from the schedule
  451. */
  452. static void unlink_async(struct uhci_hcd *uhci, struct uhci_qh *qh)
  453. {
  454. struct uhci_qh *pqh;
  455. __le32 link_to_next_qh = qh->link;
  456. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  457. pqh->link = link_to_next_qh;
  458. /* If this was the old first FSBR QH, link the terminating skeleton
  459. * QH to the next (new first FSBR) QH. */
  460. if (pqh->skel < SKEL_FSBR && qh->skel >= SKEL_FSBR)
  461. uhci->skel_term_qh->link = link_to_next_qh;
  462. mb();
  463. }
  464. /*
  465. * Take a QH off the hardware schedule
  466. */
  467. static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  468. {
  469. if (qh->state == QH_STATE_UNLINKING)
  470. return;
  471. WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev);
  472. qh->state = QH_STATE_UNLINKING;
  473. /* Unlink the QH from the schedule and record when we did it */
  474. if (qh->skel == SKEL_ISO)
  475. ;
  476. else if (qh->skel < SKEL_ASYNC)
  477. unlink_interrupt(uhci, qh);
  478. else
  479. unlink_async(uhci, qh);
  480. uhci_get_current_frame_number(uhci);
  481. qh->unlink_frame = uhci->frame_number;
  482. /* Force an interrupt so we know when the QH is fully unlinked */
  483. if (list_empty(&uhci->skel_unlink_qh->node))
  484. uhci_set_next_interrupt(uhci);
  485. /* Move the QH from its old list to the end of the unlinking list */
  486. if (qh == uhci->next_qh)
  487. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  488. node);
  489. list_move_tail(&qh->node, &uhci->skel_unlink_qh->node);
  490. }
  491. /*
  492. * When we and the controller are through with a QH, it becomes IDLE.
  493. * This happens when a QH has been off the schedule (on the unlinking
  494. * list) for more than one frame, or when an error occurs while adding
  495. * the first URB onto a new QH.
  496. */
  497. static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh)
  498. {
  499. WARN_ON(qh->state == QH_STATE_ACTIVE);
  500. if (qh == uhci->next_qh)
  501. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  502. node);
  503. list_move(&qh->node, &uhci->idle_qh_list);
  504. qh->state = QH_STATE_IDLE;
  505. /* Now that the QH is idle, its post_td isn't being used */
  506. if (qh->post_td) {
  507. uhci_free_td(uhci, qh->post_td);
  508. qh->post_td = NULL;
  509. }
  510. /* If anyone is waiting for a QH to become idle, wake them up */
  511. if (uhci->num_waiting)
  512. wake_up_all(&uhci->waitqh);
  513. }
  514. /*
  515. * Find the highest existing bandwidth load for a given phase and period.
  516. */
  517. static int uhci_highest_load(struct uhci_hcd *uhci, int phase, int period)
  518. {
  519. int highest_load = uhci->load[phase];
  520. for (phase += period; phase < MAX_PHASE; phase += period)
  521. highest_load = max_t(int, highest_load, uhci->load[phase]);
  522. return highest_load;
  523. }
  524. /*
  525. * Set qh->phase to the optimal phase for a periodic transfer and
  526. * check whether the bandwidth requirement is acceptable.
  527. */
  528. static int uhci_check_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  529. {
  530. int minimax_load;
  531. /* Find the optimal phase (unless it is already set) and get
  532. * its load value. */
  533. if (qh->phase >= 0)
  534. minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
  535. else {
  536. int phase, load;
  537. int max_phase = min_t(int, MAX_PHASE, qh->period);
  538. qh->phase = 0;
  539. minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
  540. for (phase = 1; phase < max_phase; ++phase) {
  541. load = uhci_highest_load(uhci, phase, qh->period);
  542. if (load < minimax_load) {
  543. minimax_load = load;
  544. qh->phase = phase;
  545. }
  546. }
  547. }
  548. /* Maximum allowable periodic bandwidth is 90%, or 900 us per frame */
  549. if (minimax_load + qh->load > 900) {
  550. dev_dbg(uhci_dev(uhci), "bandwidth allocation failed: "
  551. "period %d, phase %d, %d + %d us\n",
  552. qh->period, qh->phase, minimax_load, qh->load);
  553. return -ENOSPC;
  554. }
  555. return 0;
  556. }
  557. /*
  558. * Reserve a periodic QH's bandwidth in the schedule
  559. */
  560. static void uhci_reserve_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  561. {
  562. int i;
  563. int load = qh->load;
  564. char *p = "??";
  565. for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
  566. uhci->load[i] += load;
  567. uhci->total_load += load;
  568. }
  569. uhci_to_hcd(uhci)->self.bandwidth_allocated =
  570. uhci->total_load / MAX_PHASE;
  571. switch (qh->type) {
  572. case USB_ENDPOINT_XFER_INT:
  573. ++uhci_to_hcd(uhci)->self.bandwidth_int_reqs;
  574. p = "INT";
  575. break;
  576. case USB_ENDPOINT_XFER_ISOC:
  577. ++uhci_to_hcd(uhci)->self.bandwidth_isoc_reqs;
  578. p = "ISO";
  579. break;
  580. }
  581. qh->bandwidth_reserved = 1;
  582. dev_dbg(uhci_dev(uhci),
  583. "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
  584. "reserve", qh->udev->devnum,
  585. qh->hep->desc.bEndpointAddress, p,
  586. qh->period, qh->phase, load);
  587. }
  588. /*
  589. * Release a periodic QH's bandwidth reservation
  590. */
  591. static void uhci_release_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  592. {
  593. int i;
  594. int load = qh->load;
  595. char *p = "??";
  596. for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
  597. uhci->load[i] -= load;
  598. uhci->total_load -= load;
  599. }
  600. uhci_to_hcd(uhci)->self.bandwidth_allocated =
  601. uhci->total_load / MAX_PHASE;
  602. switch (qh->type) {
  603. case USB_ENDPOINT_XFER_INT:
  604. --uhci_to_hcd(uhci)->self.bandwidth_int_reqs;
  605. p = "INT";
  606. break;
  607. case USB_ENDPOINT_XFER_ISOC:
  608. --uhci_to_hcd(uhci)->self.bandwidth_isoc_reqs;
  609. p = "ISO";
  610. break;
  611. }
  612. qh->bandwidth_reserved = 0;
  613. dev_dbg(uhci_dev(uhci),
  614. "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
  615. "release", qh->udev->devnum,
  616. qh->hep->desc.bEndpointAddress, p,
  617. qh->period, qh->phase, load);
  618. }
  619. static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci,
  620. struct urb *urb)
  621. {
  622. struct urb_priv *urbp;
  623. urbp = kmem_cache_zalloc(uhci_up_cachep, GFP_ATOMIC);
  624. if (!urbp)
  625. return NULL;
  626. urbp->urb = urb;
  627. urb->hcpriv = urbp;
  628. INIT_LIST_HEAD(&urbp->node);
  629. INIT_LIST_HEAD(&urbp->td_list);
  630. return urbp;
  631. }
  632. static void uhci_free_urb_priv(struct uhci_hcd *uhci,
  633. struct urb_priv *urbp)
  634. {
  635. struct uhci_td *td, *tmp;
  636. if (!list_empty(&urbp->node)) {
  637. dev_warn(uhci_dev(uhci), "urb %p still on QH's list!\n",
  638. urbp->urb);
  639. WARN_ON(1);
  640. }
  641. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  642. uhci_remove_td_from_urbp(td);
  643. uhci_free_td(uhci, td);
  644. }
  645. urbp->urb->hcpriv = NULL;
  646. kmem_cache_free(uhci_up_cachep, urbp);
  647. }
  648. /*
  649. * Map status to standard result codes
  650. *
  651. * <status> is (td_status(td) & 0xF60000), a.k.a.
  652. * uhci_status_bits(td_status(td)).
  653. * Note: <status> does not include the TD_CTRL_NAK bit.
  654. * <dir_out> is True for output TDs and False for input TDs.
  655. */
  656. static int uhci_map_status(int status, int dir_out)
  657. {
  658. if (!status)
  659. return 0;
  660. if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */
  661. return -EPROTO;
  662. if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */
  663. if (dir_out)
  664. return -EPROTO;
  665. else
  666. return -EILSEQ;
  667. }
  668. if (status & TD_CTRL_BABBLE) /* Babble */
  669. return -EOVERFLOW;
  670. if (status & TD_CTRL_DBUFERR) /* Buffer error */
  671. return -ENOSR;
  672. if (status & TD_CTRL_STALLED) /* Stalled */
  673. return -EPIPE;
  674. return 0;
  675. }
  676. /*
  677. * Control transfers
  678. */
  679. static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb,
  680. struct uhci_qh *qh)
  681. {
  682. struct uhci_td *td;
  683. unsigned long destination, status;
  684. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  685. int len = urb->transfer_buffer_length;
  686. dma_addr_t data = urb->transfer_dma;
  687. __le32 *plink;
  688. struct urb_priv *urbp = urb->hcpriv;
  689. int skel;
  690. /* The "pipe" thing contains the destination in bits 8--18 */
  691. destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;
  692. /* 3 errors, dummy TD remains inactive */
  693. status = uhci_maxerr(3);
  694. if (urb->dev->speed == USB_SPEED_LOW)
  695. status |= TD_CTRL_LS;
  696. /*
  697. * Build the TD for the control request setup packet
  698. */
  699. td = qh->dummy_td;
  700. uhci_add_td_to_urbp(td, urbp);
  701. uhci_fill_td(td, status, destination | uhci_explen(8),
  702. urb->setup_dma);
  703. plink = &td->link;
  704. status |= TD_CTRL_ACTIVE;
  705. /*
  706. * If direction is "send", change the packet ID from SETUP (0x2D)
  707. * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
  708. * set Short Packet Detect (SPD) for all data packets.
  709. */
  710. if (usb_pipeout(urb->pipe))
  711. destination ^= (USB_PID_SETUP ^ USB_PID_OUT);
  712. else {
  713. destination ^= (USB_PID_SETUP ^ USB_PID_IN);
  714. status |= TD_CTRL_SPD;
  715. }
  716. /*
  717. * Build the DATA TDs
  718. */
  719. while (len > 0) {
  720. int pktsze = min(len, maxsze);
  721. td = uhci_alloc_td(uhci);
  722. if (!td)
  723. goto nomem;
  724. *plink = LINK_TO_TD(td);
  725. /* Alternate Data0/1 (start with Data1) */
  726. destination ^= TD_TOKEN_TOGGLE;
  727. uhci_add_td_to_urbp(td, urbp);
  728. uhci_fill_td(td, status, destination | uhci_explen(pktsze),
  729. data);
  730. plink = &td->link;
  731. data += pktsze;
  732. len -= pktsze;
  733. }
  734. /*
  735. * Build the final TD for control status
  736. */
  737. td = uhci_alloc_td(uhci);
  738. if (!td)
  739. goto nomem;
  740. *plink = LINK_TO_TD(td);
  741. /*
  742. * It's IN if the pipe is an output pipe or we're not expecting
  743. * data back.
  744. */
  745. destination &= ~TD_TOKEN_PID_MASK;
  746. if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length)
  747. destination |= USB_PID_IN;
  748. else
  749. destination |= USB_PID_OUT;
  750. destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
  751. status &= ~TD_CTRL_SPD;
  752. uhci_add_td_to_urbp(td, urbp);
  753. uhci_fill_td(td, status | TD_CTRL_IOC,
  754. destination | uhci_explen(0), 0);
  755. plink = &td->link;
  756. /*
  757. * Build the new dummy TD and activate the old one
  758. */
  759. td = uhci_alloc_td(uhci);
  760. if (!td)
  761. goto nomem;
  762. *plink = LINK_TO_TD(td);
  763. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  764. wmb();
  765. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  766. qh->dummy_td = td;
  767. /* Low-speed transfers get a different queue, and won't hog the bus.
  768. * Also, some devices enumerate better without FSBR; the easiest way
  769. * to do that is to put URBs on the low-speed queue while the device
  770. * isn't in the CONFIGURED state. */
  771. if (urb->dev->speed == USB_SPEED_LOW ||
  772. urb->dev->state != USB_STATE_CONFIGURED)
  773. skel = SKEL_LS_CONTROL;
  774. else {
  775. skel = SKEL_FS_CONTROL;
  776. uhci_add_fsbr(uhci, urb);
  777. }
  778. if (qh->state != QH_STATE_ACTIVE)
  779. qh->skel = skel;
  780. urb->actual_length = -8; /* Account for the SETUP packet */
  781. return 0;
  782. nomem:
  783. /* Remove the dummy TD from the td_list so it doesn't get freed */
  784. uhci_remove_td_from_urbp(qh->dummy_td);
  785. return -ENOMEM;
  786. }
  787. /*
  788. * Common submit for bulk and interrupt
  789. */
  790. static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb,
  791. struct uhci_qh *qh)
  792. {
  793. struct uhci_td *td;
  794. unsigned long destination, status;
  795. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  796. int len = urb->transfer_buffer_length;
  797. dma_addr_t data = urb->transfer_dma;
  798. __le32 *plink;
  799. struct urb_priv *urbp = urb->hcpriv;
  800. unsigned int toggle;
  801. if (len < 0)
  802. return -EINVAL;
  803. /* The "pipe" thing contains the destination in bits 8--18 */
  804. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  805. toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  806. usb_pipeout(urb->pipe));
  807. /* 3 errors, dummy TD remains inactive */
  808. status = uhci_maxerr(3);
  809. if (urb->dev->speed == USB_SPEED_LOW)
  810. status |= TD_CTRL_LS;
  811. if (usb_pipein(urb->pipe))
  812. status |= TD_CTRL_SPD;
  813. /*
  814. * Build the DATA TDs
  815. */
  816. plink = NULL;
  817. td = qh->dummy_td;
  818. do { /* Allow zero length packets */
  819. int pktsze = maxsze;
  820. if (len <= pktsze) { /* The last packet */
  821. pktsze = len;
  822. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  823. status &= ~TD_CTRL_SPD;
  824. }
  825. if (plink) {
  826. td = uhci_alloc_td(uhci);
  827. if (!td)
  828. goto nomem;
  829. *plink = LINK_TO_TD(td);
  830. }
  831. uhci_add_td_to_urbp(td, urbp);
  832. uhci_fill_td(td, status,
  833. destination | uhci_explen(pktsze) |
  834. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  835. data);
  836. plink = &td->link;
  837. status |= TD_CTRL_ACTIVE;
  838. data += pktsze;
  839. len -= maxsze;
  840. toggle ^= 1;
  841. } while (len > 0);
  842. /*
  843. * URB_ZERO_PACKET means adding a 0-length packet, if direction
  844. * is OUT and the transfer_length was an exact multiple of maxsze,
  845. * hence (len = transfer_length - N * maxsze) == 0
  846. * however, if transfer_length == 0, the zero packet was already
  847. * prepared above.
  848. */
  849. if ((urb->transfer_flags & URB_ZERO_PACKET) &&
  850. usb_pipeout(urb->pipe) && len == 0 &&
  851. urb->transfer_buffer_length > 0) {
  852. td = uhci_alloc_td(uhci);
  853. if (!td)
  854. goto nomem;
  855. *plink = LINK_TO_TD(td);
  856. uhci_add_td_to_urbp(td, urbp);
  857. uhci_fill_td(td, status,
  858. destination | uhci_explen(0) |
  859. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  860. data);
  861. plink = &td->link;
  862. toggle ^= 1;
  863. }
  864. /* Set the interrupt-on-completion flag on the last packet.
  865. * A more-or-less typical 4 KB URB (= size of one memory page)
  866. * will require about 3 ms to transfer; that's a little on the
  867. * fast side but not enough to justify delaying an interrupt
  868. * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
  869. * flag setting. */
  870. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  871. /*
  872. * Build the new dummy TD and activate the old one
  873. */
  874. td = uhci_alloc_td(uhci);
  875. if (!td)
  876. goto nomem;
  877. *plink = LINK_TO_TD(td);
  878. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  879. wmb();
  880. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  881. qh->dummy_td = td;
  882. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  883. usb_pipeout(urb->pipe), toggle);
  884. return 0;
  885. nomem:
  886. /* Remove the dummy TD from the td_list so it doesn't get freed */
  887. uhci_remove_td_from_urbp(qh->dummy_td);
  888. return -ENOMEM;
  889. }
  890. static int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb,
  891. struct uhci_qh *qh)
  892. {
  893. int ret;
  894. /* Can't have low-speed bulk transfers */
  895. if (urb->dev->speed == USB_SPEED_LOW)
  896. return -EINVAL;
  897. if (qh->state != QH_STATE_ACTIVE)
  898. qh->skel = SKEL_BULK;
  899. ret = uhci_submit_common(uhci, urb, qh);
  900. if (ret == 0)
  901. uhci_add_fsbr(uhci, urb);
  902. return ret;
  903. }
  904. static int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb,
  905. struct uhci_qh *qh)
  906. {
  907. int ret;
  908. /* USB 1.1 interrupt transfers only involve one packet per interval.
  909. * Drivers can submit URBs of any length, but longer ones will need
  910. * multiple intervals to complete.
  911. */
  912. if (!qh->bandwidth_reserved) {
  913. int exponent;
  914. /* Figure out which power-of-two queue to use */
  915. for (exponent = 7; exponent >= 0; --exponent) {
  916. if ((1 << exponent) <= urb->interval)
  917. break;
  918. }
  919. if (exponent < 0)
  920. return -EINVAL;
  921. qh->period = 1 << exponent;
  922. qh->skel = SKEL_INDEX(exponent);
  923. /* For now, interrupt phase is fixed by the layout
  924. * of the QH lists. */
  925. qh->phase = (qh->period / 2) & (MAX_PHASE - 1);
  926. ret = uhci_check_bandwidth(uhci, qh);
  927. if (ret)
  928. return ret;
  929. } else if (qh->period > urb->interval)
  930. return -EINVAL; /* Can't decrease the period */
  931. ret = uhci_submit_common(uhci, urb, qh);
  932. if (ret == 0) {
  933. urb->interval = qh->period;
  934. if (!qh->bandwidth_reserved)
  935. uhci_reserve_bandwidth(uhci, qh);
  936. }
  937. return ret;
  938. }
  939. /*
  940. * Fix up the data structures following a short transfer
  941. */
  942. static int uhci_fixup_short_transfer(struct uhci_hcd *uhci,
  943. struct uhci_qh *qh, struct urb_priv *urbp)
  944. {
  945. struct uhci_td *td;
  946. struct list_head *tmp;
  947. int ret;
  948. td = list_entry(urbp->td_list.prev, struct uhci_td, list);
  949. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  950. /* When a control transfer is short, we have to restart
  951. * the queue at the status stage transaction, which is
  952. * the last TD. */
  953. WARN_ON(list_empty(&urbp->td_list));
  954. qh->element = LINK_TO_TD(td);
  955. tmp = td->list.prev;
  956. ret = -EINPROGRESS;
  957. } else {
  958. /* When a bulk/interrupt transfer is short, we have to
  959. * fix up the toggles of the following URBs on the queue
  960. * before restarting the queue at the next URB. */
  961. qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1;
  962. uhci_fixup_toggles(qh, 1);
  963. if (list_empty(&urbp->td_list))
  964. td = qh->post_td;
  965. qh->element = td->link;
  966. tmp = urbp->td_list.prev;
  967. ret = 0;
  968. }
  969. /* Remove all the TDs we skipped over, from tmp back to the start */
  970. while (tmp != &urbp->td_list) {
  971. td = list_entry(tmp, struct uhci_td, list);
  972. tmp = tmp->prev;
  973. uhci_remove_td_from_urbp(td);
  974. uhci_free_td(uhci, td);
  975. }
  976. return ret;
  977. }
  978. /*
  979. * Common result for control, bulk, and interrupt
  980. */
  981. static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
  982. {
  983. struct urb_priv *urbp = urb->hcpriv;
  984. struct uhci_qh *qh = urbp->qh;
  985. struct uhci_td *td, *tmp;
  986. unsigned status;
  987. int ret = 0;
  988. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  989. unsigned int ctrlstat;
  990. int len;
  991. ctrlstat = td_status(td);
  992. status = uhci_status_bits(ctrlstat);
  993. if (status & TD_CTRL_ACTIVE)
  994. return -EINPROGRESS;
  995. len = uhci_actual_length(ctrlstat);
  996. urb->actual_length += len;
  997. if (status) {
  998. ret = uhci_map_status(status,
  999. uhci_packetout(td_token(td)));
  1000. if ((debug == 1 && ret != -EPIPE) || debug > 1) {
  1001. /* Some debugging code */
  1002. dev_dbg(&urb->dev->dev,
  1003. "%s: failed with status %x\n",
  1004. __FUNCTION__, status);
  1005. if (debug > 1 && errbuf) {
  1006. /* Print the chain for debugging */
  1007. uhci_show_qh(uhci, urbp->qh, errbuf,
  1008. ERRBUF_LEN, 0);
  1009. lprintk(errbuf);
  1010. }
  1011. }
  1012. } else if (len < uhci_expected_length(td_token(td))) {
  1013. /* We received a short packet */
  1014. if (urb->transfer_flags & URB_SHORT_NOT_OK)
  1015. ret = -EREMOTEIO;
  1016. /* Fixup needed only if this isn't the URB's last TD */
  1017. else if (&td->list != urbp->td_list.prev)
  1018. ret = 1;
  1019. }
  1020. uhci_remove_td_from_urbp(td);
  1021. if (qh->post_td)
  1022. uhci_free_td(uhci, qh->post_td);
  1023. qh->post_td = td;
  1024. if (ret != 0)
  1025. goto err;
  1026. }
  1027. return ret;
  1028. err:
  1029. if (ret < 0) {
  1030. /* In case a control transfer gets an error
  1031. * during the setup stage */
  1032. urb->actual_length = max(urb->actual_length, 0);
  1033. /* Note that the queue has stopped and save
  1034. * the next toggle value */
  1035. qh->element = UHCI_PTR_TERM;
  1036. qh->is_stopped = 1;
  1037. qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL);
  1038. qh->initial_toggle = uhci_toggle(td_token(td)) ^
  1039. (ret == -EREMOTEIO);
  1040. } else /* Short packet received */
  1041. ret = uhci_fixup_short_transfer(uhci, qh, urbp);
  1042. return ret;
  1043. }
  1044. /*
  1045. * Isochronous transfers
  1046. */
  1047. static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb,
  1048. struct uhci_qh *qh)
  1049. {
  1050. struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */
  1051. int i, frame;
  1052. unsigned long destination, status;
  1053. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  1054. /* Values must not be too big (could overflow below) */
  1055. if (urb->interval >= UHCI_NUMFRAMES ||
  1056. urb->number_of_packets >= UHCI_NUMFRAMES)
  1057. return -EFBIG;
  1058. /* Check the period and figure out the starting frame number */
  1059. if (!qh->bandwidth_reserved) {
  1060. qh->period = urb->interval;
  1061. if (urb->transfer_flags & URB_ISO_ASAP) {
  1062. qh->phase = -1; /* Find the best phase */
  1063. i = uhci_check_bandwidth(uhci, qh);
  1064. if (i)
  1065. return i;
  1066. /* Allow a little time to allocate the TDs */
  1067. uhci_get_current_frame_number(uhci);
  1068. frame = uhci->frame_number + 10;
  1069. /* Move forward to the first frame having the
  1070. * correct phase */
  1071. urb->start_frame = frame + ((qh->phase - frame) &
  1072. (qh->period - 1));
  1073. } else {
  1074. i = urb->start_frame - uhci->last_iso_frame;
  1075. if (i <= 0 || i >= UHCI_NUMFRAMES)
  1076. return -EINVAL;
  1077. qh->phase = urb->start_frame & (qh->period - 1);
  1078. i = uhci_check_bandwidth(uhci, qh);
  1079. if (i)
  1080. return i;
  1081. }
  1082. } else if (qh->period != urb->interval) {
  1083. return -EINVAL; /* Can't change the period */
  1084. } else { /* Pick up where the last URB leaves off */
  1085. if (list_empty(&qh->queue)) {
  1086. frame = qh->iso_frame;
  1087. } else {
  1088. struct urb *lurb;
  1089. lurb = list_entry(qh->queue.prev,
  1090. struct urb_priv, node)->urb;
  1091. frame = lurb->start_frame +
  1092. lurb->number_of_packets *
  1093. lurb->interval;
  1094. }
  1095. if (urb->transfer_flags & URB_ISO_ASAP)
  1096. urb->start_frame = frame;
  1097. else if (urb->start_frame != frame)
  1098. return -EINVAL;
  1099. }
  1100. /* Make sure we won't have to go too far into the future */
  1101. if (uhci_frame_before_eq(uhci->last_iso_frame + UHCI_NUMFRAMES,
  1102. urb->start_frame + urb->number_of_packets *
  1103. urb->interval))
  1104. return -EFBIG;
  1105. status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
  1106. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  1107. for (i = 0; i < urb->number_of_packets; i++) {
  1108. td = uhci_alloc_td(uhci);
  1109. if (!td)
  1110. return -ENOMEM;
  1111. uhci_add_td_to_urbp(td, urbp);
  1112. uhci_fill_td(td, status, destination |
  1113. uhci_explen(urb->iso_frame_desc[i].length),
  1114. urb->transfer_dma +
  1115. urb->iso_frame_desc[i].offset);
  1116. }
  1117. /* Set the interrupt-on-completion flag on the last packet. */
  1118. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  1119. /* Add the TDs to the frame list */
  1120. frame = urb->start_frame;
  1121. list_for_each_entry(td, &urbp->td_list, list) {
  1122. uhci_insert_td_in_frame_list(uhci, td, frame);
  1123. frame += qh->period;
  1124. }
  1125. if (list_empty(&qh->queue)) {
  1126. qh->iso_packet_desc = &urb->iso_frame_desc[0];
  1127. qh->iso_frame = urb->start_frame;
  1128. qh->iso_status = 0;
  1129. }
  1130. qh->skel = SKEL_ISO;
  1131. if (!qh->bandwidth_reserved)
  1132. uhci_reserve_bandwidth(uhci, qh);
  1133. return 0;
  1134. }
  1135. static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
  1136. {
  1137. struct uhci_td *td, *tmp;
  1138. struct urb_priv *urbp = urb->hcpriv;
  1139. struct uhci_qh *qh = urbp->qh;
  1140. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  1141. unsigned int ctrlstat;
  1142. int status;
  1143. int actlength;
  1144. if (uhci_frame_before_eq(uhci->cur_iso_frame, qh->iso_frame))
  1145. return -EINPROGRESS;
  1146. uhci_remove_tds_from_frame(uhci, qh->iso_frame);
  1147. ctrlstat = td_status(td);
  1148. if (ctrlstat & TD_CTRL_ACTIVE) {
  1149. status = -EXDEV; /* TD was added too late? */
  1150. } else {
  1151. status = uhci_map_status(uhci_status_bits(ctrlstat),
  1152. usb_pipeout(urb->pipe));
  1153. actlength = uhci_actual_length(ctrlstat);
  1154. urb->actual_length += actlength;
  1155. qh->iso_packet_desc->actual_length = actlength;
  1156. qh->iso_packet_desc->status = status;
  1157. }
  1158. if (status) {
  1159. urb->error_count++;
  1160. qh->iso_status = status;
  1161. }
  1162. uhci_remove_td_from_urbp(td);
  1163. uhci_free_td(uhci, td);
  1164. qh->iso_frame += qh->period;
  1165. ++qh->iso_packet_desc;
  1166. }
  1167. return qh->iso_status;
  1168. }
  1169. static int uhci_urb_enqueue(struct usb_hcd *hcd,
  1170. struct usb_host_endpoint *hep,
  1171. struct urb *urb, gfp_t mem_flags)
  1172. {
  1173. int ret;
  1174. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1175. unsigned long flags;
  1176. struct urb_priv *urbp;
  1177. struct uhci_qh *qh;
  1178. spin_lock_irqsave(&uhci->lock, flags);
  1179. ret = urb->status;
  1180. if (ret != -EINPROGRESS) /* URB already unlinked! */
  1181. goto done;
  1182. ret = -ENOMEM;
  1183. urbp = uhci_alloc_urb_priv(uhci, urb);
  1184. if (!urbp)
  1185. goto done;
  1186. if (hep->hcpriv)
  1187. qh = (struct uhci_qh *) hep->hcpriv;
  1188. else {
  1189. qh = uhci_alloc_qh(uhci, urb->dev, hep);
  1190. if (!qh)
  1191. goto err_no_qh;
  1192. }
  1193. urbp->qh = qh;
  1194. switch (qh->type) {
  1195. case USB_ENDPOINT_XFER_CONTROL:
  1196. ret = uhci_submit_control(uhci, urb, qh);
  1197. break;
  1198. case USB_ENDPOINT_XFER_BULK:
  1199. ret = uhci_submit_bulk(uhci, urb, qh);
  1200. break;
  1201. case USB_ENDPOINT_XFER_INT:
  1202. ret = uhci_submit_interrupt(uhci, urb, qh);
  1203. break;
  1204. case USB_ENDPOINT_XFER_ISOC:
  1205. urb->error_count = 0;
  1206. ret = uhci_submit_isochronous(uhci, urb, qh);
  1207. break;
  1208. }
  1209. if (ret != 0)
  1210. goto err_submit_failed;
  1211. /* Add this URB to the QH */
  1212. urbp->qh = qh;
  1213. list_add_tail(&urbp->node, &qh->queue);
  1214. /* If the new URB is the first and only one on this QH then either
  1215. * the QH is new and idle or else it's unlinked and waiting to
  1216. * become idle, so we can activate it right away. But only if the
  1217. * queue isn't stopped. */
  1218. if (qh->queue.next == &urbp->node && !qh->is_stopped) {
  1219. uhci_activate_qh(uhci, qh);
  1220. uhci_urbp_wants_fsbr(uhci, urbp);
  1221. }
  1222. goto done;
  1223. err_submit_failed:
  1224. if (qh->state == QH_STATE_IDLE)
  1225. uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */
  1226. err_no_qh:
  1227. uhci_free_urb_priv(uhci, urbp);
  1228. done:
  1229. spin_unlock_irqrestore(&uhci->lock, flags);
  1230. return ret;
  1231. }
  1232. static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
  1233. {
  1234. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1235. unsigned long flags;
  1236. struct urb_priv *urbp;
  1237. struct uhci_qh *qh;
  1238. spin_lock_irqsave(&uhci->lock, flags);
  1239. urbp = urb->hcpriv;
  1240. if (!urbp) /* URB was never linked! */
  1241. goto done;
  1242. qh = urbp->qh;
  1243. /* Remove Isochronous TDs from the frame list ASAP */
  1244. if (qh->type == USB_ENDPOINT_XFER_ISOC) {
  1245. uhci_unlink_isochronous_tds(uhci, urb);
  1246. mb();
  1247. /* If the URB has already started, update the QH unlink time */
  1248. uhci_get_current_frame_number(uhci);
  1249. if (uhci_frame_before_eq(urb->start_frame, uhci->frame_number))
  1250. qh->unlink_frame = uhci->frame_number;
  1251. }
  1252. uhci_unlink_qh(uhci, qh);
  1253. done:
  1254. spin_unlock_irqrestore(&uhci->lock, flags);
  1255. return 0;
  1256. }
  1257. /*
  1258. * Finish unlinking an URB and give it back
  1259. */
  1260. static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh,
  1261. struct urb *urb)
  1262. __releases(uhci->lock)
  1263. __acquires(uhci->lock)
  1264. {
  1265. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  1266. /* When giving back the first URB in an Isochronous queue,
  1267. * reinitialize the QH's iso-related members for the next URB. */
  1268. if (qh->type == USB_ENDPOINT_XFER_ISOC &&
  1269. urbp->node.prev == &qh->queue &&
  1270. urbp->node.next != &qh->queue) {
  1271. struct urb *nurb = list_entry(urbp->node.next,
  1272. struct urb_priv, node)->urb;
  1273. qh->iso_packet_desc = &nurb->iso_frame_desc[0];
  1274. qh->iso_frame = nurb->start_frame;
  1275. qh->iso_status = 0;
  1276. }
  1277. /* Take the URB off the QH's queue. If the queue is now empty,
  1278. * this is a perfect time for a toggle fixup. */
  1279. list_del_init(&urbp->node);
  1280. if (list_empty(&qh->queue) && qh->needs_fixup) {
  1281. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  1282. usb_pipeout(urb->pipe), qh->initial_toggle);
  1283. qh->needs_fixup = 0;
  1284. }
  1285. uhci_free_urb_priv(uhci, urbp);
  1286. spin_unlock(&uhci->lock);
  1287. usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb);
  1288. spin_lock(&uhci->lock);
  1289. /* If the queue is now empty, we can unlink the QH and give up its
  1290. * reserved bandwidth. */
  1291. if (list_empty(&qh->queue)) {
  1292. uhci_unlink_qh(uhci, qh);
  1293. if (qh->bandwidth_reserved)
  1294. uhci_release_bandwidth(uhci, qh);
  1295. }
  1296. }
  1297. /*
  1298. * Scan the URBs in a QH's queue
  1299. */
  1300. #define QH_FINISHED_UNLINKING(qh) \
  1301. (qh->state == QH_STATE_UNLINKING && \
  1302. uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
  1303. static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1304. {
  1305. struct urb_priv *urbp;
  1306. struct urb *urb;
  1307. int status;
  1308. while (!list_empty(&qh->queue)) {
  1309. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1310. urb = urbp->urb;
  1311. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1312. status = uhci_result_isochronous(uhci, urb);
  1313. else
  1314. status = uhci_result_common(uhci, urb);
  1315. if (status == -EINPROGRESS)
  1316. break;
  1317. spin_lock(&urb->lock);
  1318. if (urb->status == -EINPROGRESS) /* Not dequeued */
  1319. urb->status = status;
  1320. else
  1321. status = ECONNRESET; /* Not -ECONNRESET */
  1322. spin_unlock(&urb->lock);
  1323. /* Dequeued but completed URBs can't be given back unless
  1324. * the QH is stopped or has finished unlinking. */
  1325. if (status == ECONNRESET) {
  1326. if (QH_FINISHED_UNLINKING(qh))
  1327. qh->is_stopped = 1;
  1328. else if (!qh->is_stopped)
  1329. return;
  1330. }
  1331. uhci_giveback_urb(uhci, qh, urb);
  1332. if (status < 0 && qh->type != USB_ENDPOINT_XFER_ISOC)
  1333. break;
  1334. }
  1335. /* If the QH is neither stopped nor finished unlinking (normal case),
  1336. * our work here is done. */
  1337. if (QH_FINISHED_UNLINKING(qh))
  1338. qh->is_stopped = 1;
  1339. else if (!qh->is_stopped)
  1340. return;
  1341. /* Otherwise give back each of the dequeued URBs */
  1342. restart:
  1343. list_for_each_entry(urbp, &qh->queue, node) {
  1344. urb = urbp->urb;
  1345. if (urb->status != -EINPROGRESS) {
  1346. /* Fix up the TD links and save the toggles for
  1347. * non-Isochronous queues. For Isochronous queues,
  1348. * test for too-recent dequeues. */
  1349. if (!uhci_cleanup_queue(uhci, qh, urb)) {
  1350. qh->is_stopped = 0;
  1351. return;
  1352. }
  1353. uhci_giveback_urb(uhci, qh, urb);
  1354. goto restart;
  1355. }
  1356. }
  1357. qh->is_stopped = 0;
  1358. /* There are no more dequeued URBs. If there are still URBs on the
  1359. * queue, the QH can now be re-activated. */
  1360. if (!list_empty(&qh->queue)) {
  1361. if (qh->needs_fixup)
  1362. uhci_fixup_toggles(qh, 0);
  1363. /* If the first URB on the queue wants FSBR but its time
  1364. * limit has expired, set the next TD to interrupt on
  1365. * completion before reactivating the QH. */
  1366. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1367. if (urbp->fsbr && qh->wait_expired) {
  1368. struct uhci_td *td = list_entry(urbp->td_list.next,
  1369. struct uhci_td, list);
  1370. td->status |= __cpu_to_le32(TD_CTRL_IOC);
  1371. }
  1372. uhci_activate_qh(uhci, qh);
  1373. }
  1374. /* The queue is empty. The QH can become idle if it is fully
  1375. * unlinked. */
  1376. else if (QH_FINISHED_UNLINKING(qh))
  1377. uhci_make_qh_idle(uhci, qh);
  1378. }
  1379. /*
  1380. * Check for queues that have made some forward progress.
  1381. * Returns 0 if the queue is not Isochronous, is ACTIVE, and
  1382. * has not advanced since last examined; 1 otherwise.
  1383. *
  1384. * Early Intel controllers have a bug which causes qh->element sometimes
  1385. * not to advance when a TD completes successfully. The queue remains
  1386. * stuck on the inactive completed TD. We detect such cases and advance
  1387. * the element pointer by hand.
  1388. */
  1389. static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1390. {
  1391. struct urb_priv *urbp = NULL;
  1392. struct uhci_td *td;
  1393. int ret = 1;
  1394. unsigned status;
  1395. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1396. goto done;
  1397. /* Treat an UNLINKING queue as though it hasn't advanced.
  1398. * This is okay because reactivation will treat it as though
  1399. * it has advanced, and if it is going to become IDLE then
  1400. * this doesn't matter anyway. Furthermore it's possible
  1401. * for an UNLINKING queue not to have any URBs at all, or
  1402. * for its first URB not to have any TDs (if it was dequeued
  1403. * just as it completed). So it's not easy in any case to
  1404. * test whether such queues have advanced. */
  1405. if (qh->state != QH_STATE_ACTIVE) {
  1406. urbp = NULL;
  1407. status = 0;
  1408. } else {
  1409. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1410. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  1411. status = td_status(td);
  1412. if (!(status & TD_CTRL_ACTIVE)) {
  1413. /* We're okay, the queue has advanced */
  1414. qh->wait_expired = 0;
  1415. qh->advance_jiffies = jiffies;
  1416. goto done;
  1417. }
  1418. ret = 0;
  1419. }
  1420. /* The queue hasn't advanced; check for timeout */
  1421. if (qh->wait_expired)
  1422. goto done;
  1423. if (time_after(jiffies, qh->advance_jiffies + QH_WAIT_TIMEOUT)) {
  1424. /* Detect the Intel bug and work around it */
  1425. if (qh->post_td && qh_element(qh) == LINK_TO_TD(qh->post_td)) {
  1426. qh->element = qh->post_td->link;
  1427. qh->advance_jiffies = jiffies;
  1428. ret = 1;
  1429. goto done;
  1430. }
  1431. qh->wait_expired = 1;
  1432. /* If the current URB wants FSBR, unlink it temporarily
  1433. * so that we can safely set the next TD to interrupt on
  1434. * completion. That way we'll know as soon as the queue
  1435. * starts moving again. */
  1436. if (urbp && urbp->fsbr && !(status & TD_CTRL_IOC))
  1437. uhci_unlink_qh(uhci, qh);
  1438. } else {
  1439. /* Unmoving but not-yet-expired queues keep FSBR alive */
  1440. if (urbp)
  1441. uhci_urbp_wants_fsbr(uhci, urbp);
  1442. }
  1443. done:
  1444. return ret;
  1445. }
  1446. /*
  1447. * Process events in the schedule, but only in one thread at a time
  1448. */
  1449. static void uhci_scan_schedule(struct uhci_hcd *uhci)
  1450. {
  1451. int i;
  1452. struct uhci_qh *qh;
  1453. /* Don't allow re-entrant calls */
  1454. if (uhci->scan_in_progress) {
  1455. uhci->need_rescan = 1;
  1456. return;
  1457. }
  1458. uhci->scan_in_progress = 1;
  1459. rescan:
  1460. uhci->need_rescan = 0;
  1461. uhci->fsbr_is_wanted = 0;
  1462. uhci_clear_next_interrupt(uhci);
  1463. uhci_get_current_frame_number(uhci);
  1464. uhci->cur_iso_frame = uhci->frame_number;
  1465. /* Go through all the QH queues and process the URBs in each one */
  1466. for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) {
  1467. uhci->next_qh = list_entry(uhci->skelqh[i]->node.next,
  1468. struct uhci_qh, node);
  1469. while ((qh = uhci->next_qh) != uhci->skelqh[i]) {
  1470. uhci->next_qh = list_entry(qh->node.next,
  1471. struct uhci_qh, node);
  1472. if (uhci_advance_check(uhci, qh)) {
  1473. uhci_scan_qh(uhci, qh);
  1474. if (qh->state == QH_STATE_ACTIVE) {
  1475. uhci_urbp_wants_fsbr(uhci,
  1476. list_entry(qh->queue.next, struct urb_priv, node));
  1477. }
  1478. }
  1479. }
  1480. }
  1481. uhci->last_iso_frame = uhci->cur_iso_frame;
  1482. if (uhci->need_rescan)
  1483. goto rescan;
  1484. uhci->scan_in_progress = 0;
  1485. if (uhci->fsbr_is_on && !uhci->fsbr_is_wanted &&
  1486. !uhci->fsbr_expiring) {
  1487. uhci->fsbr_expiring = 1;
  1488. mod_timer(&uhci->fsbr_timer, jiffies + FSBR_OFF_DELAY);
  1489. }
  1490. if (list_empty(&uhci->skel_unlink_qh->node))
  1491. uhci_clear_next_interrupt(uhci);
  1492. else
  1493. uhci_set_next_interrupt(uhci);
  1494. }