ohci-pci.c 8.0 KB

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  1. /*
  2. * OHCI HCD (Host Controller Driver) for USB.
  3. *
  4. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  5. * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
  6. *
  7. * [ Initialisation is based on Linus' ]
  8. * [ uhci code and gregs ohci fragments ]
  9. * [ (C) Copyright 1999 Linus Torvalds ]
  10. * [ (C) Copyright 1999 Gregory P. Smith]
  11. *
  12. * PCI Bus Glue
  13. *
  14. * This file is licenced under the GPL.
  15. */
  16. #ifndef CONFIG_PCI
  17. #error "This file is PCI bus glue. CONFIG_PCI must be defined."
  18. #endif
  19. /*-------------------------------------------------------------------------*/
  20. static int broken_suspend(struct usb_hcd *hcd)
  21. {
  22. device_init_wakeup(&hcd->self.root_hub->dev, 0);
  23. return 0;
  24. }
  25. /* AMD 756, for most chips (early revs), corrupts register
  26. * values on read ... so enable the vendor workaround.
  27. */
  28. static int ohci_quirk_amd756(struct usb_hcd *hcd)
  29. {
  30. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  31. ohci->flags = OHCI_QUIRK_AMD756;
  32. ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
  33. /* also erratum 10 (suspend/resume issues) */
  34. return broken_suspend(hcd);
  35. }
  36. /* Apple's OHCI driver has a lot of bizarre workarounds
  37. * for this chip. Evidently control and bulk lists
  38. * can get confused. (B&W G3 models, and ...)
  39. */
  40. static int ohci_quirk_opti(struct usb_hcd *hcd)
  41. {
  42. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  43. ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");
  44. return 0;
  45. }
  46. /* Check for NSC87560. We have to look at the bridge (fn1) to
  47. * identify the USB (fn2). This quirk might apply to more or
  48. * even all NSC stuff.
  49. */
  50. static int ohci_quirk_ns(struct usb_hcd *hcd)
  51. {
  52. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  53. struct pci_dev *b;
  54. b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
  55. if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
  56. && b->vendor == PCI_VENDOR_ID_NS) {
  57. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  58. ohci->flags |= OHCI_QUIRK_SUPERIO;
  59. ohci_dbg (ohci, "Using NSC SuperIO setup\n");
  60. }
  61. pci_dev_put(b);
  62. return 0;
  63. }
  64. /* Check for Compaq's ZFMicro chipset, which needs short
  65. * delays before control or bulk queues get re-activated
  66. * in finish_unlinks()
  67. */
  68. static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
  69. {
  70. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  71. ohci->flags |= OHCI_QUIRK_ZFMICRO;
  72. ohci_dbg (ohci, "enabled Compaq ZFMicro chipset quirk\n");
  73. return 0;
  74. }
  75. /* Check for Toshiba SCC OHCI which has big endian registers
  76. * and little endian in memory data structures
  77. */
  78. static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
  79. {
  80. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  81. /* That chip is only present in the southbridge of some
  82. * cell based platforms which are supposed to select
  83. * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
  84. * that was the case though.
  85. */
  86. #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
  87. ohci->flags |= OHCI_QUIRK_BE_MMIO;
  88. ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
  89. return 0;
  90. #else
  91. ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
  92. return -ENXIO;
  93. #endif
  94. }
  95. /* List of quirks for OHCI */
  96. static const struct pci_device_id ohci_pci_quirks[] = {
  97. {
  98. PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
  99. .driver_data = (unsigned long)ohci_quirk_amd756,
  100. },
  101. {
  102. PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
  103. .driver_data = (unsigned long)ohci_quirk_opti,
  104. },
  105. {
  106. PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
  107. .driver_data = (unsigned long)ohci_quirk_ns,
  108. },
  109. {
  110. PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
  111. .driver_data = (unsigned long)ohci_quirk_zfmicro,
  112. },
  113. {
  114. PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
  115. .driver_data = (unsigned long)ohci_quirk_toshiba_scc,
  116. },
  117. {
  118. /* Toshiba portege 4000 */
  119. .vendor = PCI_VENDOR_ID_AL,
  120. .device = 0x5237,
  121. .subvendor = PCI_VENDOR_ID_TOSHIBA_2,
  122. .subdevice = 0x0004,
  123. .driver_data = (unsigned long) broken_suspend,
  124. },
  125. {
  126. PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
  127. .driver_data = (unsigned long) broken_suspend,
  128. },
  129. /* FIXME for some of the early AMD 760 southbridges, OHCI
  130. * won't work at all. blacklist them.
  131. */
  132. {},
  133. };
  134. static int ohci_pci_reset (struct usb_hcd *hcd)
  135. {
  136. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  137. int ret = 0;
  138. if (hcd->self.controller) {
  139. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  140. const struct pci_device_id *quirk_id;
  141. quirk_id = pci_match_id(ohci_pci_quirks, pdev);
  142. if (quirk_id != NULL) {
  143. int (*quirk)(struct usb_hcd *ohci);
  144. quirk = (void *)quirk_id->driver_data;
  145. ret = quirk(hcd);
  146. }
  147. }
  148. if (ret == 0) {
  149. ohci_hcd_init (ohci);
  150. return ohci_init (ohci);
  151. }
  152. return ret;
  153. }
  154. static int __devinit ohci_pci_start (struct usb_hcd *hcd)
  155. {
  156. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  157. int ret;
  158. #ifdef CONFIG_PM /* avoid warnings about unused pdev */
  159. if (hcd->self.controller) {
  160. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  161. /* RWC may not be set for add-in PCI cards, since boot
  162. * firmware probably ignored them. This transfers PCI
  163. * PM wakeup capabilities (once the PCI layer is fixed).
  164. */
  165. if (device_may_wakeup(&pdev->dev))
  166. ohci->hc_control |= OHCI_CTRL_RWC;
  167. }
  168. #endif /* CONFIG_PM */
  169. ret = ohci_run (ohci);
  170. if (ret < 0) {
  171. ohci_err (ohci, "can't start\n");
  172. ohci_stop (hcd);
  173. }
  174. return ret;
  175. }
  176. #ifdef CONFIG_PM
  177. static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
  178. {
  179. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  180. unsigned long flags;
  181. int rc = 0;
  182. /* Root hub was already suspended. Disable irq emission and
  183. * mark HW unaccessible, bail out if RH has been resumed. Use
  184. * the spinlock to properly synchronize with possible pending
  185. * RH suspend or resume activity.
  186. *
  187. * This is still racy as hcd->state is manipulated outside of
  188. * any locks =P But that will be a different fix.
  189. */
  190. spin_lock_irqsave (&ohci->lock, flags);
  191. if (hcd->state != HC_STATE_SUSPENDED) {
  192. rc = -EINVAL;
  193. goto bail;
  194. }
  195. ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
  196. (void)ohci_readl(ohci, &ohci->regs->intrdisable);
  197. /* make sure snapshot being resumed re-enumerates everything */
  198. if (message.event == PM_EVENT_PRETHAW)
  199. ohci_usb_reset(ohci);
  200. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  201. bail:
  202. spin_unlock_irqrestore (&ohci->lock, flags);
  203. return rc;
  204. }
  205. static int ohci_pci_resume (struct usb_hcd *hcd)
  206. {
  207. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  208. usb_hcd_resume_root_hub(hcd);
  209. return 0;
  210. }
  211. #endif /* CONFIG_PM */
  212. /*-------------------------------------------------------------------------*/
  213. static const struct hc_driver ohci_pci_hc_driver = {
  214. .description = hcd_name,
  215. .product_desc = "OHCI Host Controller",
  216. .hcd_priv_size = sizeof(struct ohci_hcd),
  217. /*
  218. * generic hardware linkage
  219. */
  220. .irq = ohci_irq,
  221. .flags = HCD_MEMORY | HCD_USB11,
  222. /*
  223. * basic lifecycle operations
  224. */
  225. .reset = ohci_pci_reset,
  226. .start = ohci_pci_start,
  227. .stop = ohci_stop,
  228. .shutdown = ohci_shutdown,
  229. #ifdef CONFIG_PM
  230. /* these suspend/resume entries are for upstream PCI glue ONLY */
  231. .suspend = ohci_pci_suspend,
  232. .resume = ohci_pci_resume,
  233. #endif
  234. /*
  235. * managing i/o requests and associated device resources
  236. */
  237. .urb_enqueue = ohci_urb_enqueue,
  238. .urb_dequeue = ohci_urb_dequeue,
  239. .endpoint_disable = ohci_endpoint_disable,
  240. /*
  241. * scheduling support
  242. */
  243. .get_frame_number = ohci_get_frame,
  244. /*
  245. * root hub support
  246. */
  247. .hub_status_data = ohci_hub_status_data,
  248. .hub_control = ohci_hub_control,
  249. .hub_irq_enable = ohci_rhsc_enable,
  250. #ifdef CONFIG_PM
  251. .bus_suspend = ohci_bus_suspend,
  252. .bus_resume = ohci_bus_resume,
  253. #endif
  254. .start_port_reset = ohci_start_port_reset,
  255. };
  256. /*-------------------------------------------------------------------------*/
  257. static const struct pci_device_id pci_ids [] = { {
  258. /* handle any USB OHCI controller */
  259. PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
  260. .driver_data = (unsigned long) &ohci_pci_hc_driver,
  261. }, { /* end: all zeroes */ }
  262. };
  263. MODULE_DEVICE_TABLE (pci, pci_ids);
  264. /* pci driver glue; this is a "new style" PCI driver module */
  265. static struct pci_driver ohci_pci_driver = {
  266. .name = (char *) hcd_name,
  267. .id_table = pci_ids,
  268. .probe = usb_hcd_pci_probe,
  269. .remove = usb_hcd_pci_remove,
  270. #ifdef CONFIG_PM
  271. .suspend = usb_hcd_pci_suspend,
  272. .resume = usb_hcd_pci_resume,
  273. #endif
  274. .shutdown = usb_hcd_pci_shutdown,
  275. };