spi_s3c24xx.c 9.4 KB

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  1. /* linux/drivers/spi/spi_s3c24xx.c
  2. *
  3. * Copyright (c) 2006 Ben Dooks
  4. * Copyright (c) 2006 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. */
  12. #include <linux/init.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/workqueue.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/delay.h>
  17. #include <linux/errno.h>
  18. #include <linux/err.h>
  19. #include <linux/clk.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/spi/spi_bitbang.h>
  23. #include <asm/io.h>
  24. #include <asm/dma.h>
  25. #include <asm/hardware.h>
  26. #include <asm/arch/regs-gpio.h>
  27. #include <asm/arch/regs-spi.h>
  28. #include <asm/arch/spi.h>
  29. struct s3c24xx_spi {
  30. /* bitbang has to be first */
  31. struct spi_bitbang bitbang;
  32. struct completion done;
  33. void __iomem *regs;
  34. int irq;
  35. int len;
  36. int count;
  37. void (*set_cs)(struct s3c2410_spi_info *spi,
  38. int cs, int pol);
  39. /* data buffers */
  40. const unsigned char *tx;
  41. unsigned char *rx;
  42. struct clk *clk;
  43. struct resource *ioarea;
  44. struct spi_master *master;
  45. struct spi_device *curdev;
  46. struct device *dev;
  47. struct s3c2410_spi_info *pdata;
  48. };
  49. #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
  50. #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
  51. static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
  52. {
  53. return spi_master_get_devdata(sdev->master);
  54. }
  55. static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
  56. {
  57. s3c2410_gpio_setpin(spi->pin_cs, pol);
  58. }
  59. static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
  60. {
  61. struct s3c24xx_spi *hw = to_hw(spi);
  62. unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
  63. unsigned int spcon;
  64. switch (value) {
  65. case BITBANG_CS_INACTIVE:
  66. hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
  67. break;
  68. case BITBANG_CS_ACTIVE:
  69. spcon = readb(hw->regs + S3C2410_SPCON);
  70. if (spi->mode & SPI_CPHA)
  71. spcon |= S3C2410_SPCON_CPHA_FMTB;
  72. else
  73. spcon &= ~S3C2410_SPCON_CPHA_FMTB;
  74. if (spi->mode & SPI_CPOL)
  75. spcon |= S3C2410_SPCON_CPOL_HIGH;
  76. else
  77. spcon &= ~S3C2410_SPCON_CPOL_HIGH;
  78. spcon |= S3C2410_SPCON_ENSCK;
  79. /* write new configration */
  80. writeb(spcon, hw->regs + S3C2410_SPCON);
  81. hw->set_cs(hw->pdata, spi->chip_select, cspol);
  82. break;
  83. }
  84. }
  85. static int s3c24xx_spi_setupxfer(struct spi_device *spi,
  86. struct spi_transfer *t)
  87. {
  88. struct s3c24xx_spi *hw = to_hw(spi);
  89. unsigned int bpw;
  90. unsigned int hz;
  91. unsigned int div;
  92. bpw = t ? t->bits_per_word : spi->bits_per_word;
  93. hz = t ? t->speed_hz : spi->max_speed_hz;
  94. if (bpw != 8) {
  95. dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
  96. return -EINVAL;
  97. }
  98. div = clk_get_rate(hw->clk) / hz;
  99. /* is clk = pclk / (2 * (pre+1)), or is it
  100. * clk = (pclk * 2) / ( pre + 1) */
  101. div = (div / 2) - 1;
  102. if (div < 0)
  103. div = 1;
  104. if (div > 255)
  105. div = 255;
  106. dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
  107. writeb(div, hw->regs + S3C2410_SPPRE);
  108. spin_lock(&hw->bitbang.lock);
  109. if (!hw->bitbang.busy) {
  110. hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
  111. /* need to ndelay for 0.5 clocktick ? */
  112. }
  113. spin_unlock(&hw->bitbang.lock);
  114. return 0;
  115. }
  116. static int s3c24xx_spi_setup(struct spi_device *spi)
  117. {
  118. int ret;
  119. if (!spi->bits_per_word)
  120. spi->bits_per_word = 8;
  121. if ((spi->mode & SPI_LSB_FIRST) != 0)
  122. return -EINVAL;
  123. ret = s3c24xx_spi_setupxfer(spi, NULL);
  124. if (ret < 0) {
  125. dev_err(&spi->dev, "setupxfer returned %d\n", ret);
  126. return ret;
  127. }
  128. dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n",
  129. __FUNCTION__, spi->mode, spi->bits_per_word,
  130. spi->max_speed_hz);
  131. return 0;
  132. }
  133. static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
  134. {
  135. return hw->tx ? hw->tx[count] : 0;
  136. }
  137. static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
  138. {
  139. struct s3c24xx_spi *hw = to_hw(spi);
  140. dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
  141. t->tx_buf, t->rx_buf, t->len);
  142. hw->tx = t->tx_buf;
  143. hw->rx = t->rx_buf;
  144. hw->len = t->len;
  145. hw->count = 0;
  146. /* send the first byte */
  147. writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
  148. wait_for_completion(&hw->done);
  149. return hw->count;
  150. }
  151. static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
  152. {
  153. struct s3c24xx_spi *hw = dev;
  154. unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
  155. unsigned int count = hw->count;
  156. if (spsta & S3C2410_SPSTA_DCOL) {
  157. dev_dbg(hw->dev, "data-collision\n");
  158. complete(&hw->done);
  159. goto irq_done;
  160. }
  161. if (!(spsta & S3C2410_SPSTA_READY)) {
  162. dev_dbg(hw->dev, "spi not ready for tx?\n");
  163. complete(&hw->done);
  164. goto irq_done;
  165. }
  166. hw->count++;
  167. if (hw->rx)
  168. hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
  169. count++;
  170. if (count < hw->len)
  171. writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
  172. else
  173. complete(&hw->done);
  174. irq_done:
  175. return IRQ_HANDLED;
  176. }
  177. static int s3c24xx_spi_probe(struct platform_device *pdev)
  178. {
  179. struct s3c24xx_spi *hw;
  180. struct spi_master *master;
  181. struct spi_board_info *bi;
  182. struct resource *res;
  183. int err = 0;
  184. int i;
  185. master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
  186. if (master == NULL) {
  187. dev_err(&pdev->dev, "No memory for spi_master\n");
  188. err = -ENOMEM;
  189. goto err_nomem;
  190. }
  191. hw = spi_master_get_devdata(master);
  192. memset(hw, 0, sizeof(struct s3c24xx_spi));
  193. hw->master = spi_master_get(master);
  194. hw->pdata = pdev->dev.platform_data;
  195. hw->dev = &pdev->dev;
  196. if (hw->pdata == NULL) {
  197. dev_err(&pdev->dev, "No platform data supplied\n");
  198. err = -ENOENT;
  199. goto err_no_pdata;
  200. }
  201. platform_set_drvdata(pdev, hw);
  202. init_completion(&hw->done);
  203. /* setup the state for the bitbang driver */
  204. hw->bitbang.master = hw->master;
  205. hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
  206. hw->bitbang.chipselect = s3c24xx_spi_chipsel;
  207. hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
  208. hw->bitbang.master->setup = s3c24xx_spi_setup;
  209. dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
  210. /* find and map our resources */
  211. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  212. if (res == NULL) {
  213. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  214. err = -ENOENT;
  215. goto err_no_iores;
  216. }
  217. hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
  218. pdev->name);
  219. if (hw->ioarea == NULL) {
  220. dev_err(&pdev->dev, "Cannot reserve region\n");
  221. err = -ENXIO;
  222. goto err_no_iores;
  223. }
  224. hw->regs = ioremap(res->start, (res->end - res->start)+1);
  225. if (hw->regs == NULL) {
  226. dev_err(&pdev->dev, "Cannot map IO\n");
  227. err = -ENXIO;
  228. goto err_no_iomap;
  229. }
  230. hw->irq = platform_get_irq(pdev, 0);
  231. if (hw->irq < 0) {
  232. dev_err(&pdev->dev, "No IRQ specified\n");
  233. err = -ENOENT;
  234. goto err_no_irq;
  235. }
  236. err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
  237. if (err) {
  238. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  239. goto err_no_irq;
  240. }
  241. hw->clk = clk_get(&pdev->dev, "spi");
  242. if (IS_ERR(hw->clk)) {
  243. dev_err(&pdev->dev, "No clock for device\n");
  244. err = PTR_ERR(hw->clk);
  245. goto err_no_clk;
  246. }
  247. /* for the moment, permanently enable the clock */
  248. clk_enable(hw->clk);
  249. /* program defaults into the registers */
  250. writeb(0xff, hw->regs + S3C2410_SPPRE);
  251. writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
  252. writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
  253. /* setup any gpio we can */
  254. if (!hw->pdata->set_cs) {
  255. hw->set_cs = s3c24xx_spi_gpiocs;
  256. s3c2410_gpio_setpin(hw->pdata->pin_cs, 1);
  257. s3c2410_gpio_cfgpin(hw->pdata->pin_cs, S3C2410_GPIO_OUTPUT);
  258. } else
  259. hw->set_cs = hw->pdata->set_cs;
  260. /* register our spi controller */
  261. err = spi_bitbang_start(&hw->bitbang);
  262. if (err) {
  263. dev_err(&pdev->dev, "Failed to register SPI master\n");
  264. goto err_register;
  265. }
  266. /* register all the devices associated */
  267. bi = &hw->pdata->board_info[0];
  268. for (i = 0; i < hw->pdata->board_size; i++, bi++) {
  269. dev_info(hw->dev, "registering %s\n", bi->modalias);
  270. bi->controller_data = hw;
  271. spi_new_device(master, bi);
  272. }
  273. return 0;
  274. err_register:
  275. clk_disable(hw->clk);
  276. clk_put(hw->clk);
  277. err_no_clk:
  278. free_irq(hw->irq, hw);
  279. err_no_irq:
  280. iounmap(hw->regs);
  281. err_no_iomap:
  282. release_resource(hw->ioarea);
  283. kfree(hw->ioarea);
  284. err_no_iores:
  285. err_no_pdata:
  286. spi_master_put(hw->master);;
  287. err_nomem:
  288. return err;
  289. }
  290. static int s3c24xx_spi_remove(struct platform_device *dev)
  291. {
  292. struct s3c24xx_spi *hw = platform_get_drvdata(dev);
  293. platform_set_drvdata(dev, NULL);
  294. spi_unregister_master(hw->master);
  295. clk_disable(hw->clk);
  296. clk_put(hw->clk);
  297. free_irq(hw->irq, hw);
  298. iounmap(hw->regs);
  299. release_resource(hw->ioarea);
  300. kfree(hw->ioarea);
  301. spi_master_put(hw->master);
  302. return 0;
  303. }
  304. #ifdef CONFIG_PM
  305. static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
  306. {
  307. struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
  308. clk_disable(hw->clk);
  309. return 0;
  310. }
  311. static int s3c24xx_spi_resume(struct platform_device *pdev)
  312. {
  313. struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
  314. clk_enable(hw->clk);
  315. return 0;
  316. }
  317. #else
  318. #define s3c24xx_spi_suspend NULL
  319. #define s3c24xx_spi_resume NULL
  320. #endif
  321. static struct platform_driver s3c24xx_spidrv = {
  322. .probe = s3c24xx_spi_probe,
  323. .remove = s3c24xx_spi_remove,
  324. .suspend = s3c24xx_spi_suspend,
  325. .resume = s3c24xx_spi_resume,
  326. .driver = {
  327. .name = "s3c2410-spi",
  328. .owner = THIS_MODULE,
  329. },
  330. };
  331. static int __init s3c24xx_spi_init(void)
  332. {
  333. return platform_driver_register(&s3c24xx_spidrv);
  334. }
  335. static void __exit s3c24xx_spi_exit(void)
  336. {
  337. platform_driver_unregister(&s3c24xx_spidrv);
  338. }
  339. module_init(s3c24xx_spi_init);
  340. module_exit(s3c24xx_spi_exit);
  341. MODULE_DESCRIPTION("S3C24XX SPI Driver");
  342. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  343. MODULE_LICENSE("GPL");