stex.c 34 KB

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  1. /*
  2. * SuperTrak EX Series Storage Controller driver for Linux
  3. *
  4. * Copyright (C) 2005, 2006 Promise Technology Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. * Written By:
  12. * Ed Lin <promise_linux@promise.com>
  13. *
  14. */
  15. #include <linux/init.h>
  16. #include <linux/errno.h>
  17. #include <linux/kernel.h>
  18. #include <linux/delay.h>
  19. #include <linux/time.h>
  20. #include <linux/pci.h>
  21. #include <linux/blkdev.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/types.h>
  24. #include <linux/module.h>
  25. #include <linux/spinlock.h>
  26. #include <asm/io.h>
  27. #include <asm/irq.h>
  28. #include <asm/byteorder.h>
  29. #include <scsi/scsi.h>
  30. #include <scsi/scsi_device.h>
  31. #include <scsi/scsi_cmnd.h>
  32. #include <scsi/scsi_host.h>
  33. #include <scsi/scsi_tcq.h>
  34. #define DRV_NAME "stex"
  35. #define ST_DRIVER_VERSION "3.1.0.1"
  36. #define ST_VER_MAJOR 3
  37. #define ST_VER_MINOR 1
  38. #define ST_OEM 0
  39. #define ST_BUILD_VER 1
  40. enum {
  41. /* MU register offset */
  42. IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  43. IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  44. OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  45. OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  46. IDBL = 0x20, /* MU_INBOUND_DOORBELL */
  47. IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  48. IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  49. ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
  50. OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  51. OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  52. /* MU register value */
  53. MU_INBOUND_DOORBELL_HANDSHAKE = 1,
  54. MU_INBOUND_DOORBELL_REQHEADCHANGED = 2,
  55. MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4,
  56. MU_INBOUND_DOORBELL_HMUSTOPPED = 8,
  57. MU_INBOUND_DOORBELL_RESET = 16,
  58. MU_OUTBOUND_DOORBELL_HANDSHAKE = 1,
  59. MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
  60. MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4,
  61. MU_OUTBOUND_DOORBELL_BUSCHANGE = 8,
  62. MU_OUTBOUND_DOORBELL_HASEVENT = 16,
  63. /* MU status code */
  64. MU_STATE_STARTING = 1,
  65. MU_STATE_FMU_READY_FOR_HANDSHAKE = 2,
  66. MU_STATE_SEND_HANDSHAKE_FRAME = 3,
  67. MU_STATE_STARTED = 4,
  68. MU_STATE_RESETTING = 5,
  69. MU_MAX_DELAY = 120,
  70. MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
  71. MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
  72. MU_HARD_RESET_WAIT = 30000,
  73. HMU_PARTNER_TYPE = 2,
  74. /* firmware returned values */
  75. SRB_STATUS_SUCCESS = 0x01,
  76. SRB_STATUS_ERROR = 0x04,
  77. SRB_STATUS_BUSY = 0x05,
  78. SRB_STATUS_INVALID_REQUEST = 0x06,
  79. SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
  80. SRB_SEE_SENSE = 0x80,
  81. /* task attribute */
  82. TASK_ATTRIBUTE_SIMPLE = 0x0,
  83. TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
  84. TASK_ATTRIBUTE_ORDERED = 0x2,
  85. TASK_ATTRIBUTE_ACA = 0x4,
  86. /* request count, etc. */
  87. MU_MAX_REQUEST = 32,
  88. /* one message wasted, use MU_MAX_REQUEST+1
  89. to handle MU_MAX_REQUEST messages */
  90. MU_REQ_COUNT = (MU_MAX_REQUEST + 1),
  91. MU_STATUS_COUNT = (MU_MAX_REQUEST + 1),
  92. STEX_CDB_LENGTH = MAX_COMMAND_SIZE,
  93. REQ_VARIABLE_LEN = 1024,
  94. STATUS_VAR_LEN = 128,
  95. ST_CAN_QUEUE = MU_MAX_REQUEST,
  96. ST_CMD_PER_LUN = MU_MAX_REQUEST,
  97. ST_MAX_SG = 32,
  98. /* sg flags */
  99. SG_CF_EOT = 0x80, /* end of table */
  100. SG_CF_64B = 0x40, /* 64 bit item */
  101. SG_CF_HOST = 0x20, /* sg in host memory */
  102. ST_MAX_ARRAY_SUPPORTED = 16,
  103. ST_MAX_TARGET_NUM = (ST_MAX_ARRAY_SUPPORTED+1),
  104. ST_MAX_LUN_PER_TARGET = 16,
  105. st_shasta = 0,
  106. st_vsc = 1,
  107. st_vsc1 = 2,
  108. st_yosemite = 3,
  109. PASSTHRU_REQ_TYPE = 0x00000001,
  110. PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
  111. ST_INTERNAL_TIMEOUT = 30,
  112. ST_TO_CMD = 0,
  113. ST_FROM_CMD = 1,
  114. /* vendor specific commands of Promise */
  115. MGT_CMD = 0xd8,
  116. SINBAND_MGT_CMD = 0xd9,
  117. ARRAY_CMD = 0xe0,
  118. CONTROLLER_CMD = 0xe1,
  119. DEBUGGING_CMD = 0xe2,
  120. PASSTHRU_CMD = 0xe3,
  121. PASSTHRU_GET_ADAPTER = 0x05,
  122. PASSTHRU_GET_DRVVER = 0x10,
  123. CTLR_CONFIG_CMD = 0x03,
  124. CTLR_SHUTDOWN = 0x0d,
  125. CTLR_POWER_STATE_CHANGE = 0x0e,
  126. CTLR_POWER_SAVING = 0x01,
  127. PASSTHRU_SIGNATURE = 0x4e415041,
  128. MGT_CMD_SIGNATURE = 0xba,
  129. INQUIRY_EVPD = 0x01,
  130. ST_ADDITIONAL_MEM = 0x200000,
  131. };
  132. /* SCSI inquiry data */
  133. typedef struct st_inq {
  134. u8 DeviceType :5;
  135. u8 DeviceTypeQualifier :3;
  136. u8 DeviceTypeModifier :7;
  137. u8 RemovableMedia :1;
  138. u8 Versions;
  139. u8 ResponseDataFormat :4;
  140. u8 HiSupport :1;
  141. u8 NormACA :1;
  142. u8 ReservedBit :1;
  143. u8 AERC :1;
  144. u8 AdditionalLength;
  145. u8 Reserved[2];
  146. u8 SoftReset :1;
  147. u8 CommandQueue :1;
  148. u8 Reserved2 :1;
  149. u8 LinkedCommands :1;
  150. u8 Synchronous :1;
  151. u8 Wide16Bit :1;
  152. u8 Wide32Bit :1;
  153. u8 RelativeAddressing :1;
  154. u8 VendorId[8];
  155. u8 ProductId[16];
  156. u8 ProductRevisionLevel[4];
  157. u8 VendorSpecific[20];
  158. u8 Reserved3[40];
  159. } ST_INQ;
  160. struct st_sgitem {
  161. u8 ctrl; /* SG_CF_xxx */
  162. u8 reserved[3];
  163. __le32 count;
  164. __le32 addr;
  165. __le32 addr_hi;
  166. };
  167. struct st_sgtable {
  168. __le16 sg_count;
  169. __le16 max_sg_count;
  170. __le32 sz_in_byte;
  171. struct st_sgitem table[ST_MAX_SG];
  172. };
  173. struct handshake_frame {
  174. __le32 rb_phy; /* request payload queue physical address */
  175. __le32 rb_phy_hi;
  176. __le16 req_sz; /* size of each request payload */
  177. __le16 req_cnt; /* count of reqs the buffer can hold */
  178. __le16 status_sz; /* size of each status payload */
  179. __le16 status_cnt; /* count of status the buffer can hold */
  180. __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */
  181. __le32 hosttime_hi;
  182. u8 partner_type; /* who sends this frame */
  183. u8 reserved0[7];
  184. __le32 partner_ver_major;
  185. __le32 partner_ver_minor;
  186. __le32 partner_ver_oem;
  187. __le32 partner_ver_build;
  188. __le32 extra_offset; /* NEW */
  189. __le32 extra_size; /* NEW */
  190. u32 reserved1[2];
  191. };
  192. struct req_msg {
  193. __le16 tag;
  194. u8 lun;
  195. u8 target;
  196. u8 task_attr;
  197. u8 task_manage;
  198. u8 prd_entry;
  199. u8 payload_sz; /* payload size in 4-byte, not used */
  200. u8 cdb[STEX_CDB_LENGTH];
  201. u8 variable[REQ_VARIABLE_LEN];
  202. };
  203. struct status_msg {
  204. __le16 tag;
  205. u8 lun;
  206. u8 target;
  207. u8 srb_status;
  208. u8 scsi_status;
  209. u8 reserved;
  210. u8 payload_sz; /* payload size in 4-byte */
  211. u8 variable[STATUS_VAR_LEN];
  212. };
  213. struct ver_info {
  214. u32 major;
  215. u32 minor;
  216. u32 oem;
  217. u32 build;
  218. u32 reserved[2];
  219. };
  220. struct st_frame {
  221. u32 base[6];
  222. u32 rom_addr;
  223. struct ver_info drv_ver;
  224. struct ver_info bios_ver;
  225. u32 bus;
  226. u32 slot;
  227. u32 irq_level;
  228. u32 irq_vec;
  229. u32 id;
  230. u32 subid;
  231. u32 dimm_size;
  232. u8 dimm_type;
  233. u8 reserved[3];
  234. u32 channel;
  235. u32 reserved1;
  236. };
  237. struct st_drvver {
  238. u32 major;
  239. u32 minor;
  240. u32 oem;
  241. u32 build;
  242. u32 signature[2];
  243. u8 console_id;
  244. u8 host_no;
  245. u8 reserved0[2];
  246. u32 reserved[3];
  247. };
  248. #define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg))
  249. #define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg))
  250. #define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
  251. #define STEX_EXTRA_SIZE max(sizeof(struct st_frame), sizeof(ST_INQ))
  252. #define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
  253. struct st_ccb {
  254. struct req_msg *req;
  255. struct scsi_cmnd *cmd;
  256. void *sense_buffer;
  257. unsigned int sense_bufflen;
  258. int sg_count;
  259. u32 req_type;
  260. u8 srb_status;
  261. u8 scsi_status;
  262. };
  263. struct st_hba {
  264. void __iomem *mmio_base; /* iomapped PCI memory space */
  265. void *dma_mem;
  266. dma_addr_t dma_handle;
  267. size_t dma_size;
  268. struct Scsi_Host *host;
  269. struct pci_dev *pdev;
  270. u32 req_head;
  271. u32 req_tail;
  272. u32 status_head;
  273. u32 status_tail;
  274. struct status_msg *status_buffer;
  275. void *copy_buffer; /* temp buffer for driver-handled commands */
  276. struct st_ccb ccb[MU_MAX_REQUEST];
  277. struct st_ccb *wait_ccb;
  278. wait_queue_head_t waitq;
  279. unsigned int mu_status;
  280. int out_req_cnt;
  281. unsigned int cardtype;
  282. };
  283. static const char console_inq_page[] =
  284. {
  285. 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
  286. 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
  287. 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
  288. 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
  289. 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
  290. 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
  291. 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
  292. 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
  293. };
  294. MODULE_AUTHOR("Ed Lin");
  295. MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
  296. MODULE_LICENSE("GPL");
  297. MODULE_VERSION(ST_DRIVER_VERSION);
  298. static void stex_gettime(__le32 *time)
  299. {
  300. struct timeval tv;
  301. do_gettimeofday(&tv);
  302. *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
  303. *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
  304. }
  305. static struct status_msg *stex_get_status(struct st_hba *hba)
  306. {
  307. struct status_msg *status =
  308. hba->status_buffer + hba->status_tail;
  309. ++hba->status_tail;
  310. hba->status_tail %= MU_STATUS_COUNT;
  311. return status;
  312. }
  313. static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
  314. {
  315. cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
  316. cmd->sense_buffer[0] = 0x70; /* fixed format, current */
  317. cmd->sense_buffer[2] = sk;
  318. cmd->sense_buffer[7] = 18 - 8; /* additional sense length */
  319. cmd->sense_buffer[12] = asc;
  320. cmd->sense_buffer[13] = ascq;
  321. }
  322. static void stex_invalid_field(struct scsi_cmnd *cmd,
  323. void (*done)(struct scsi_cmnd *))
  324. {
  325. /* "Invalid field in cbd" */
  326. stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
  327. done(cmd);
  328. }
  329. static struct req_msg *stex_alloc_req(struct st_hba *hba)
  330. {
  331. struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
  332. hba->req_head;
  333. ++hba->req_head;
  334. hba->req_head %= MU_REQ_COUNT;
  335. return req;
  336. }
  337. static int stex_map_sg(struct st_hba *hba,
  338. struct req_msg *req, struct st_ccb *ccb)
  339. {
  340. struct pci_dev *pdev = hba->pdev;
  341. struct scsi_cmnd *cmd;
  342. dma_addr_t dma_handle;
  343. struct scatterlist *src;
  344. struct st_sgtable *dst;
  345. int i;
  346. cmd = ccb->cmd;
  347. dst = (struct st_sgtable *)req->variable;
  348. dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
  349. dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
  350. if (cmd->use_sg) {
  351. int n_elem;
  352. src = (struct scatterlist *) cmd->request_buffer;
  353. n_elem = pci_map_sg(pdev, src,
  354. cmd->use_sg, cmd->sc_data_direction);
  355. if (n_elem <= 0)
  356. return -EIO;
  357. ccb->sg_count = n_elem;
  358. dst->sg_count = cpu_to_le16((u16)n_elem);
  359. for (i = 0; i < n_elem; i++, src++) {
  360. dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
  361. dst->table[i].addr =
  362. cpu_to_le32(sg_dma_address(src) & 0xffffffff);
  363. dst->table[i].addr_hi =
  364. cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
  365. dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
  366. }
  367. dst->table[--i].ctrl |= SG_CF_EOT;
  368. return 0;
  369. }
  370. dma_handle = pci_map_single(pdev, cmd->request_buffer,
  371. cmd->request_bufflen, cmd->sc_data_direction);
  372. cmd->SCp.dma_handle = dma_handle;
  373. ccb->sg_count = 1;
  374. dst->sg_count = cpu_to_le16(1);
  375. dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
  376. dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
  377. dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
  378. dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
  379. return 0;
  380. }
  381. static void stex_internal_copy(struct scsi_cmnd *cmd,
  382. const void *src, size_t *count, int sg_count, int direction)
  383. {
  384. size_t lcount;
  385. size_t len;
  386. void *s, *d, *base = NULL;
  387. if (*count > cmd->request_bufflen)
  388. *count = cmd->request_bufflen;
  389. lcount = *count;
  390. while (lcount) {
  391. len = lcount;
  392. s = (void *)src;
  393. if (cmd->use_sg) {
  394. size_t offset = *count - lcount;
  395. s += offset;
  396. base = scsi_kmap_atomic_sg(cmd->request_buffer,
  397. sg_count, &offset, &len);
  398. if (base == NULL) {
  399. *count -= lcount;
  400. return;
  401. }
  402. d = base + offset;
  403. } else
  404. d = cmd->request_buffer;
  405. if (direction == ST_TO_CMD)
  406. memcpy(d, s, len);
  407. else
  408. memcpy(s, d, len);
  409. lcount -= len;
  410. if (cmd->use_sg)
  411. scsi_kunmap_atomic_sg(base);
  412. }
  413. }
  414. static int stex_direct_copy(struct scsi_cmnd *cmd,
  415. const void *src, size_t count)
  416. {
  417. struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
  418. size_t cp_len = count;
  419. int n_elem = 0;
  420. if (cmd->use_sg) {
  421. n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
  422. cmd->use_sg, cmd->sc_data_direction);
  423. if (n_elem <= 0)
  424. return 0;
  425. }
  426. stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD);
  427. if (cmd->use_sg)
  428. pci_unmap_sg(hba->pdev, cmd->request_buffer,
  429. cmd->use_sg, cmd->sc_data_direction);
  430. return cp_len == count;
  431. }
  432. static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
  433. {
  434. struct st_frame *p;
  435. size_t count = sizeof(struct st_frame);
  436. p = hba->copy_buffer;
  437. stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD);
  438. memset(p->base, 0, sizeof(u32)*6);
  439. *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
  440. p->rom_addr = 0;
  441. p->drv_ver.major = ST_VER_MAJOR;
  442. p->drv_ver.minor = ST_VER_MINOR;
  443. p->drv_ver.oem = ST_OEM;
  444. p->drv_ver.build = ST_BUILD_VER;
  445. p->bus = hba->pdev->bus->number;
  446. p->slot = hba->pdev->devfn;
  447. p->irq_level = 0;
  448. p->irq_vec = hba->pdev->irq;
  449. p->id = hba->pdev->vendor << 16 | hba->pdev->device;
  450. p->subid =
  451. hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
  452. stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD);
  453. }
  454. static void
  455. stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
  456. {
  457. req->tag = cpu_to_le16(tag);
  458. req->task_attr = TASK_ATTRIBUTE_SIMPLE;
  459. req->task_manage = 0; /* not supported yet */
  460. hba->ccb[tag].req = req;
  461. hba->out_req_cnt++;
  462. writel(hba->req_head, hba->mmio_base + IMR0);
  463. writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
  464. readl(hba->mmio_base + IDBL); /* flush */
  465. }
  466. static int
  467. stex_slave_alloc(struct scsi_device *sdev)
  468. {
  469. /* Cheat: usually extracted from Inquiry data */
  470. sdev->tagged_supported = 1;
  471. scsi_activate_tcq(sdev, sdev->host->can_queue);
  472. return 0;
  473. }
  474. static int
  475. stex_slave_config(struct scsi_device *sdev)
  476. {
  477. sdev->use_10_for_rw = 1;
  478. sdev->use_10_for_ms = 1;
  479. sdev->timeout = 60 * HZ;
  480. sdev->tagged_supported = 1;
  481. return 0;
  482. }
  483. static void
  484. stex_slave_destroy(struct scsi_device *sdev)
  485. {
  486. scsi_deactivate_tcq(sdev, 1);
  487. }
  488. static int
  489. stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
  490. {
  491. struct st_hba *hba;
  492. struct Scsi_Host *host;
  493. unsigned int id,lun;
  494. struct req_msg *req;
  495. u16 tag;
  496. host = cmd->device->host;
  497. id = cmd->device->id;
  498. lun = cmd->device->channel; /* firmware lun issue work around */
  499. hba = (struct st_hba *) &host->hostdata[0];
  500. switch (cmd->cmnd[0]) {
  501. case MODE_SENSE_10:
  502. {
  503. static char ms10_caching_page[12] =
  504. { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
  505. unsigned char page;
  506. page = cmd->cmnd[2] & 0x3f;
  507. if (page == 0x8 || page == 0x3f) {
  508. stex_direct_copy(cmd, ms10_caching_page,
  509. sizeof(ms10_caching_page));
  510. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  511. done(cmd);
  512. } else
  513. stex_invalid_field(cmd, done);
  514. return 0;
  515. }
  516. case INQUIRY:
  517. if (id != ST_MAX_ARRAY_SUPPORTED)
  518. break;
  519. if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
  520. stex_direct_copy(cmd, console_inq_page,
  521. sizeof(console_inq_page));
  522. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  523. done(cmd);
  524. } else
  525. stex_invalid_field(cmd, done);
  526. return 0;
  527. case PASSTHRU_CMD:
  528. if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
  529. struct st_drvver ver;
  530. ver.major = ST_VER_MAJOR;
  531. ver.minor = ST_VER_MINOR;
  532. ver.oem = ST_OEM;
  533. ver.build = ST_BUILD_VER;
  534. ver.signature[0] = PASSTHRU_SIGNATURE;
  535. ver.console_id = ST_MAX_ARRAY_SUPPORTED;
  536. ver.host_no = hba->host->host_no;
  537. cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
  538. DID_OK << 16 | COMMAND_COMPLETE << 8 :
  539. DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  540. done(cmd);
  541. return 0;
  542. }
  543. default:
  544. break;
  545. }
  546. cmd->scsi_done = done;
  547. tag = cmd->request->tag;
  548. if (unlikely(tag >= host->can_queue))
  549. return SCSI_MLQUEUE_HOST_BUSY;
  550. req = stex_alloc_req(hba);
  551. if (hba->cardtype == st_yosemite) {
  552. req->lun = lun * (ST_MAX_TARGET_NUM - 1) + id;
  553. req->target = 0;
  554. } else {
  555. req->lun = lun;
  556. req->target = id;
  557. }
  558. /* cdb */
  559. memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
  560. hba->ccb[tag].cmd = cmd;
  561. hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
  562. hba->ccb[tag].sense_buffer = cmd->sense_buffer;
  563. hba->ccb[tag].req_type = 0;
  564. if (cmd->sc_data_direction != DMA_NONE)
  565. stex_map_sg(hba, req, &hba->ccb[tag]);
  566. stex_send_cmd(hba, req, tag);
  567. return 0;
  568. }
  569. static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
  570. {
  571. if (cmd->sc_data_direction != DMA_NONE) {
  572. if (cmd->use_sg)
  573. pci_unmap_sg(hba->pdev, cmd->request_buffer,
  574. cmd->use_sg, cmd->sc_data_direction);
  575. else
  576. pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
  577. cmd->request_bufflen, cmd->sc_data_direction);
  578. }
  579. }
  580. static void stex_scsi_done(struct st_ccb *ccb)
  581. {
  582. struct scsi_cmnd *cmd = ccb->cmd;
  583. int result;
  584. if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
  585. result = ccb->scsi_status;
  586. switch (ccb->scsi_status) {
  587. case SAM_STAT_GOOD:
  588. result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
  589. break;
  590. case SAM_STAT_CHECK_CONDITION:
  591. result |= DRIVER_SENSE << 24;
  592. break;
  593. case SAM_STAT_BUSY:
  594. result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
  595. break;
  596. default:
  597. result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  598. break;
  599. }
  600. }
  601. else if (ccb->srb_status & SRB_SEE_SENSE)
  602. result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
  603. else switch (ccb->srb_status) {
  604. case SRB_STATUS_SELECTION_TIMEOUT:
  605. result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
  606. break;
  607. case SRB_STATUS_BUSY:
  608. result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
  609. break;
  610. case SRB_STATUS_INVALID_REQUEST:
  611. case SRB_STATUS_ERROR:
  612. default:
  613. result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  614. break;
  615. }
  616. cmd->result = result;
  617. cmd->scsi_done(cmd);
  618. }
  619. static void stex_copy_data(struct st_ccb *ccb,
  620. struct status_msg *resp, unsigned int variable)
  621. {
  622. size_t count = variable;
  623. if (resp->scsi_status != SAM_STAT_GOOD) {
  624. if (ccb->sense_buffer != NULL)
  625. memcpy(ccb->sense_buffer, resp->variable,
  626. min(variable, ccb->sense_bufflen));
  627. return;
  628. }
  629. if (ccb->cmd == NULL)
  630. return;
  631. stex_internal_copy(ccb->cmd,
  632. resp->variable, &count, ccb->sg_count, ST_TO_CMD);
  633. }
  634. static void stex_ys_commands(struct st_hba *hba,
  635. struct st_ccb *ccb, struct status_msg *resp)
  636. {
  637. size_t count;
  638. if (ccb->cmd->cmnd[0] == MGT_CMD &&
  639. resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
  640. ccb->cmd->request_bufflen =
  641. le32_to_cpu(*(__le32 *)&resp->variable[0]);
  642. return;
  643. }
  644. if (resp->srb_status != 0)
  645. return;
  646. /* determine inquiry command status by DeviceTypeQualifier */
  647. if (ccb->cmd->cmnd[0] == INQUIRY &&
  648. resp->scsi_status == SAM_STAT_GOOD) {
  649. ST_INQ *inq_data;
  650. count = STEX_EXTRA_SIZE;
  651. stex_internal_copy(ccb->cmd, hba->copy_buffer,
  652. &count, ccb->sg_count, ST_FROM_CMD);
  653. inq_data = (ST_INQ *)hba->copy_buffer;
  654. if (inq_data->DeviceTypeQualifier != 0)
  655. ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
  656. else
  657. ccb->srb_status = SRB_STATUS_SUCCESS;
  658. } else if (ccb->cmd->cmnd[0] == REPORT_LUNS) {
  659. u8 *report_lun_data = (u8 *)hba->copy_buffer;
  660. count = STEX_EXTRA_SIZE;
  661. stex_internal_copy(ccb->cmd, report_lun_data,
  662. &count, ccb->sg_count, ST_FROM_CMD);
  663. if (report_lun_data[2] || report_lun_data[3]) {
  664. report_lun_data[2] = 0x00;
  665. report_lun_data[3] = 0x08;
  666. stex_internal_copy(ccb->cmd, report_lun_data,
  667. &count, ccb->sg_count, ST_TO_CMD);
  668. }
  669. }
  670. }
  671. static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
  672. {
  673. void __iomem *base = hba->mmio_base;
  674. struct status_msg *resp;
  675. struct st_ccb *ccb;
  676. unsigned int size;
  677. u16 tag;
  678. if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
  679. return;
  680. /* status payloads */
  681. hba->status_head = readl(base + OMR1);
  682. if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
  683. printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
  684. pci_name(hba->pdev));
  685. return;
  686. }
  687. /*
  688. * it's not a valid status payload if:
  689. * 1. there are no pending requests(e.g. during init stage)
  690. * 2. there are some pending requests, but the controller is in
  691. * reset status, and its type is not st_yosemite
  692. * firmware of st_yosemite in reset status will return pending requests
  693. * to driver, so we allow it to pass
  694. */
  695. if (unlikely(hba->out_req_cnt <= 0 ||
  696. (hba->mu_status == MU_STATE_RESETTING &&
  697. hba->cardtype != st_yosemite))) {
  698. hba->status_tail = hba->status_head;
  699. goto update_status;
  700. }
  701. while (hba->status_tail != hba->status_head) {
  702. resp = stex_get_status(hba);
  703. tag = le16_to_cpu(resp->tag);
  704. if (unlikely(tag >= hba->host->can_queue)) {
  705. printk(KERN_WARNING DRV_NAME
  706. "(%s): invalid tag\n", pci_name(hba->pdev));
  707. continue;
  708. }
  709. ccb = &hba->ccb[tag];
  710. if (hba->wait_ccb == ccb)
  711. hba->wait_ccb = NULL;
  712. if (unlikely(ccb->req == NULL)) {
  713. printk(KERN_WARNING DRV_NAME
  714. "(%s): lagging req\n", pci_name(hba->pdev));
  715. hba->out_req_cnt--;
  716. continue;
  717. }
  718. size = resp->payload_sz * sizeof(u32); /* payload size */
  719. if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
  720. size > sizeof(*resp))) {
  721. printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
  722. pci_name(hba->pdev));
  723. } else {
  724. size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
  725. if (size)
  726. stex_copy_data(ccb, resp, size);
  727. }
  728. ccb->srb_status = resp->srb_status;
  729. ccb->scsi_status = resp->scsi_status;
  730. if (likely(ccb->cmd != NULL)) {
  731. if (hba->cardtype == st_yosemite)
  732. stex_ys_commands(hba, ccb, resp);
  733. if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
  734. ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
  735. stex_controller_info(hba, ccb);
  736. stex_unmap_sg(hba, ccb->cmd);
  737. stex_scsi_done(ccb);
  738. hba->out_req_cnt--;
  739. } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
  740. hba->out_req_cnt--;
  741. if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
  742. ccb->req_type = 0;
  743. continue;
  744. }
  745. ccb->req_type = 0;
  746. if (waitqueue_active(&hba->waitq))
  747. wake_up(&hba->waitq);
  748. }
  749. }
  750. update_status:
  751. writel(hba->status_head, base + IMR1);
  752. readl(base + IMR1); /* flush */
  753. }
  754. static irqreturn_t stex_intr(int irq, void *__hba)
  755. {
  756. struct st_hba *hba = __hba;
  757. void __iomem *base = hba->mmio_base;
  758. u32 data;
  759. unsigned long flags;
  760. int handled = 0;
  761. spin_lock_irqsave(hba->host->host_lock, flags);
  762. data = readl(base + ODBL);
  763. if (data && data != 0xffffffff) {
  764. /* clear the interrupt */
  765. writel(data, base + ODBL);
  766. readl(base + ODBL); /* flush */
  767. stex_mu_intr(hba, data);
  768. handled = 1;
  769. }
  770. spin_unlock_irqrestore(hba->host->host_lock, flags);
  771. return IRQ_RETVAL(handled);
  772. }
  773. static int stex_handshake(struct st_hba *hba)
  774. {
  775. void __iomem *base = hba->mmio_base;
  776. struct handshake_frame *h;
  777. dma_addr_t status_phys;
  778. u32 data;
  779. unsigned long before;
  780. if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  781. writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
  782. readl(base + IDBL);
  783. before = jiffies;
  784. while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  785. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  786. printk(KERN_ERR DRV_NAME
  787. "(%s): no handshake signature\n",
  788. pci_name(hba->pdev));
  789. return -1;
  790. }
  791. rmb();
  792. msleep(1);
  793. }
  794. }
  795. udelay(10);
  796. data = readl(base + OMR1);
  797. if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
  798. data &= 0x0000ffff;
  799. if (hba->host->can_queue > data)
  800. hba->host->can_queue = data;
  801. }
  802. h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
  803. h->rb_phy = cpu_to_le32(hba->dma_handle);
  804. h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
  805. h->req_sz = cpu_to_le16(sizeof(struct req_msg));
  806. h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
  807. h->status_sz = cpu_to_le16(sizeof(struct status_msg));
  808. h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
  809. stex_gettime(&h->hosttime);
  810. h->partner_type = HMU_PARTNER_TYPE;
  811. if (hba->dma_size > STEX_BUFFER_SIZE) {
  812. h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
  813. h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
  814. } else
  815. h->extra_offset = h->extra_size = 0;
  816. status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
  817. writel(status_phys, base + IMR0);
  818. readl(base + IMR0);
  819. writel((status_phys >> 16) >> 16, base + IMR1);
  820. readl(base + IMR1);
  821. writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
  822. readl(base + OMR0);
  823. writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
  824. readl(base + IDBL); /* flush */
  825. udelay(10);
  826. before = jiffies;
  827. while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  828. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  829. printk(KERN_ERR DRV_NAME
  830. "(%s): no signature after handshake frame\n",
  831. pci_name(hba->pdev));
  832. return -1;
  833. }
  834. rmb();
  835. msleep(1);
  836. }
  837. writel(0, base + IMR0);
  838. readl(base + IMR0);
  839. writel(0, base + OMR0);
  840. readl(base + OMR0);
  841. writel(0, base + IMR1);
  842. readl(base + IMR1);
  843. writel(0, base + OMR1);
  844. readl(base + OMR1); /* flush */
  845. hba->mu_status = MU_STATE_STARTED;
  846. return 0;
  847. }
  848. static int stex_abort(struct scsi_cmnd *cmd)
  849. {
  850. struct Scsi_Host *host = cmd->device->host;
  851. struct st_hba *hba = (struct st_hba *)host->hostdata;
  852. u16 tag = cmd->request->tag;
  853. void __iomem *base;
  854. u32 data;
  855. int result = SUCCESS;
  856. unsigned long flags;
  857. base = hba->mmio_base;
  858. spin_lock_irqsave(host->host_lock, flags);
  859. if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
  860. hba->wait_ccb = &hba->ccb[tag];
  861. else {
  862. for (tag = 0; tag < host->can_queue; tag++)
  863. if (hba->ccb[tag].cmd == cmd) {
  864. hba->wait_ccb = &hba->ccb[tag];
  865. break;
  866. }
  867. if (tag >= host->can_queue)
  868. goto out;
  869. }
  870. data = readl(base + ODBL);
  871. if (data == 0 || data == 0xffffffff)
  872. goto fail_out;
  873. writel(data, base + ODBL);
  874. readl(base + ODBL); /* flush */
  875. stex_mu_intr(hba, data);
  876. if (hba->wait_ccb == NULL) {
  877. printk(KERN_WARNING DRV_NAME
  878. "(%s): lost interrupt\n", pci_name(hba->pdev));
  879. goto out;
  880. }
  881. fail_out:
  882. stex_unmap_sg(hba, cmd);
  883. hba->wait_ccb->req = NULL; /* nullify the req's future return */
  884. hba->wait_ccb = NULL;
  885. result = FAILED;
  886. out:
  887. spin_unlock_irqrestore(host->host_lock, flags);
  888. return result;
  889. }
  890. static void stex_hard_reset(struct st_hba *hba)
  891. {
  892. struct pci_bus *bus;
  893. int i;
  894. u16 pci_cmd;
  895. u8 pci_bctl;
  896. for (i = 0; i < 16; i++)
  897. pci_read_config_dword(hba->pdev, i * 4,
  898. &hba->pdev->saved_config_space[i]);
  899. /* Reset secondary bus. Our controller(MU/ATU) is the only device on
  900. secondary bus. Consult Intel 80331/3 developer's manual for detail */
  901. bus = hba->pdev->bus;
  902. pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
  903. pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
  904. pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
  905. msleep(1);
  906. pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
  907. pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
  908. for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
  909. pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
  910. if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
  911. break;
  912. msleep(1);
  913. }
  914. ssleep(5);
  915. for (i = 0; i < 16; i++)
  916. pci_write_config_dword(hba->pdev, i * 4,
  917. hba->pdev->saved_config_space[i]);
  918. }
  919. static int stex_reset(struct scsi_cmnd *cmd)
  920. {
  921. struct st_hba *hba;
  922. unsigned long flags;
  923. unsigned long before;
  924. hba = (struct st_hba *) &cmd->device->host->hostdata[0];
  925. hba->mu_status = MU_STATE_RESETTING;
  926. if (hba->cardtype == st_shasta)
  927. stex_hard_reset(hba);
  928. if (hba->cardtype != st_yosemite) {
  929. if (stex_handshake(hba)) {
  930. printk(KERN_WARNING DRV_NAME
  931. "(%s): resetting: handshake failed\n",
  932. pci_name(hba->pdev));
  933. return FAILED;
  934. }
  935. spin_lock_irqsave(hba->host->host_lock, flags);
  936. hba->req_head = 0;
  937. hba->req_tail = 0;
  938. hba->status_head = 0;
  939. hba->status_tail = 0;
  940. hba->out_req_cnt = 0;
  941. spin_unlock_irqrestore(hba->host->host_lock, flags);
  942. return SUCCESS;
  943. }
  944. /* st_yosemite */
  945. writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
  946. readl(hba->mmio_base + IDBL); /* flush */
  947. before = jiffies;
  948. while (hba->out_req_cnt > 0) {
  949. if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
  950. printk(KERN_WARNING DRV_NAME
  951. "(%s): reset timeout\n", pci_name(hba->pdev));
  952. return FAILED;
  953. }
  954. msleep(1);
  955. }
  956. hba->mu_status = MU_STATE_STARTED;
  957. return SUCCESS;
  958. }
  959. static int stex_biosparam(struct scsi_device *sdev,
  960. struct block_device *bdev, sector_t capacity, int geom[])
  961. {
  962. int heads = 255, sectors = 63;
  963. if (capacity < 0x200000) {
  964. heads = 64;
  965. sectors = 32;
  966. }
  967. sector_div(capacity, heads * sectors);
  968. geom[0] = heads;
  969. geom[1] = sectors;
  970. geom[2] = capacity;
  971. return 0;
  972. }
  973. static struct scsi_host_template driver_template = {
  974. .module = THIS_MODULE,
  975. .name = DRV_NAME,
  976. .proc_name = DRV_NAME,
  977. .bios_param = stex_biosparam,
  978. .queuecommand = stex_queuecommand,
  979. .slave_alloc = stex_slave_alloc,
  980. .slave_configure = stex_slave_config,
  981. .slave_destroy = stex_slave_destroy,
  982. .eh_abort_handler = stex_abort,
  983. .eh_host_reset_handler = stex_reset,
  984. .can_queue = ST_CAN_QUEUE,
  985. .this_id = -1,
  986. .sg_tablesize = ST_MAX_SG,
  987. .cmd_per_lun = ST_CMD_PER_LUN,
  988. };
  989. static int stex_set_dma_mask(struct pci_dev * pdev)
  990. {
  991. int ret;
  992. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
  993. && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
  994. return 0;
  995. ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  996. if (!ret)
  997. ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  998. return ret;
  999. }
  1000. static int __devinit
  1001. stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1002. {
  1003. struct st_hba *hba;
  1004. struct Scsi_Host *host;
  1005. int err;
  1006. err = pci_enable_device(pdev);
  1007. if (err)
  1008. return err;
  1009. pci_set_master(pdev);
  1010. host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
  1011. if (!host) {
  1012. printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
  1013. pci_name(pdev));
  1014. err = -ENOMEM;
  1015. goto out_disable;
  1016. }
  1017. hba = (struct st_hba *)host->hostdata;
  1018. memset(hba, 0, sizeof(struct st_hba));
  1019. err = pci_request_regions(pdev, DRV_NAME);
  1020. if (err < 0) {
  1021. printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
  1022. pci_name(pdev));
  1023. goto out_scsi_host_put;
  1024. }
  1025. hba->mmio_base = ioremap(pci_resource_start(pdev, 0),
  1026. pci_resource_len(pdev, 0));
  1027. if ( !hba->mmio_base) {
  1028. printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
  1029. pci_name(pdev));
  1030. err = -ENOMEM;
  1031. goto out_release_regions;
  1032. }
  1033. err = stex_set_dma_mask(pdev);
  1034. if (err) {
  1035. printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
  1036. pci_name(pdev));
  1037. goto out_iounmap;
  1038. }
  1039. hba->cardtype = (unsigned int) id->driver_data;
  1040. if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
  1041. hba->cardtype = st_vsc1;
  1042. hba->dma_size = (hba->cardtype == st_vsc1) ?
  1043. (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
  1044. hba->dma_mem = dma_alloc_coherent(&pdev->dev,
  1045. hba->dma_size, &hba->dma_handle, GFP_KERNEL);
  1046. if (!hba->dma_mem) {
  1047. err = -ENOMEM;
  1048. printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
  1049. pci_name(pdev));
  1050. goto out_iounmap;
  1051. }
  1052. hba->status_buffer =
  1053. (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
  1054. hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
  1055. hba->mu_status = MU_STATE_STARTING;
  1056. /* firmware uses id/lun pair for a logical drive, but lun would be
  1057. always 0 if CONFIG_SCSI_MULTI_LUN not configured, so we use
  1058. channel to map lun here */
  1059. host->max_channel = ST_MAX_LUN_PER_TARGET - 1;
  1060. host->max_id = ST_MAX_TARGET_NUM;
  1061. host->max_lun = 1;
  1062. host->unique_id = host->host_no;
  1063. host->max_cmd_len = STEX_CDB_LENGTH;
  1064. hba->host = host;
  1065. hba->pdev = pdev;
  1066. init_waitqueue_head(&hba->waitq);
  1067. err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
  1068. if (err) {
  1069. printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
  1070. pci_name(pdev));
  1071. goto out_pci_free;
  1072. }
  1073. err = stex_handshake(hba);
  1074. if (err)
  1075. goto out_free_irq;
  1076. err = scsi_init_shared_tag_map(host, host->can_queue);
  1077. if (err) {
  1078. printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
  1079. pci_name(pdev));
  1080. goto out_free_irq;
  1081. }
  1082. pci_set_drvdata(pdev, hba);
  1083. err = scsi_add_host(host, &pdev->dev);
  1084. if (err) {
  1085. printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
  1086. pci_name(pdev));
  1087. goto out_free_irq;
  1088. }
  1089. scsi_scan_host(host);
  1090. return 0;
  1091. out_free_irq:
  1092. free_irq(pdev->irq, hba);
  1093. out_pci_free:
  1094. dma_free_coherent(&pdev->dev, hba->dma_size,
  1095. hba->dma_mem, hba->dma_handle);
  1096. out_iounmap:
  1097. iounmap(hba->mmio_base);
  1098. out_release_regions:
  1099. pci_release_regions(pdev);
  1100. out_scsi_host_put:
  1101. scsi_host_put(host);
  1102. out_disable:
  1103. pci_disable_device(pdev);
  1104. return err;
  1105. }
  1106. static void stex_hba_stop(struct st_hba *hba)
  1107. {
  1108. struct req_msg *req;
  1109. unsigned long flags;
  1110. unsigned long before;
  1111. u16 tag = 0;
  1112. spin_lock_irqsave(hba->host->host_lock, flags);
  1113. req = stex_alloc_req(hba);
  1114. memset(req->cdb, 0, STEX_CDB_LENGTH);
  1115. if (hba->cardtype == st_yosemite) {
  1116. req->cdb[0] = MGT_CMD;
  1117. req->cdb[1] = MGT_CMD_SIGNATURE;
  1118. req->cdb[2] = CTLR_CONFIG_CMD;
  1119. req->cdb[3] = CTLR_SHUTDOWN;
  1120. } else {
  1121. req->cdb[0] = CONTROLLER_CMD;
  1122. req->cdb[1] = CTLR_POWER_STATE_CHANGE;
  1123. req->cdb[2] = CTLR_POWER_SAVING;
  1124. }
  1125. hba->ccb[tag].cmd = NULL;
  1126. hba->ccb[tag].sg_count = 0;
  1127. hba->ccb[tag].sense_bufflen = 0;
  1128. hba->ccb[tag].sense_buffer = NULL;
  1129. hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
  1130. stex_send_cmd(hba, req, tag);
  1131. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1132. before = jiffies;
  1133. while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
  1134. if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
  1135. return;
  1136. msleep(10);
  1137. }
  1138. }
  1139. static void stex_hba_free(struct st_hba *hba)
  1140. {
  1141. free_irq(hba->pdev->irq, hba);
  1142. iounmap(hba->mmio_base);
  1143. pci_release_regions(hba->pdev);
  1144. dma_free_coherent(&hba->pdev->dev, hba->dma_size,
  1145. hba->dma_mem, hba->dma_handle);
  1146. }
  1147. static void stex_remove(struct pci_dev *pdev)
  1148. {
  1149. struct st_hba *hba = pci_get_drvdata(pdev);
  1150. scsi_remove_host(hba->host);
  1151. pci_set_drvdata(pdev, NULL);
  1152. stex_hba_stop(hba);
  1153. stex_hba_free(hba);
  1154. scsi_host_put(hba->host);
  1155. pci_disable_device(pdev);
  1156. }
  1157. static void stex_shutdown(struct pci_dev *pdev)
  1158. {
  1159. struct st_hba *hba = pci_get_drvdata(pdev);
  1160. stex_hba_stop(hba);
  1161. }
  1162. static struct pci_device_id stex_pci_tbl[] = {
  1163. /* st_shasta */
  1164. { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1165. st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
  1166. { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1167. st_shasta }, /* SuperTrak EX12350 */
  1168. { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1169. st_shasta }, /* SuperTrak EX4350 */
  1170. { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1171. st_shasta }, /* SuperTrak EX24350 */
  1172. /* st_vsc */
  1173. { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
  1174. /* st_yosemite */
  1175. { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
  1176. st_yosemite }, /* SuperTrak EX4650 */
  1177. { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
  1178. st_yosemite }, /* SuperTrak EX4650o */
  1179. { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
  1180. st_yosemite }, /* SuperTrak EX8650EL */
  1181. { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
  1182. st_yosemite }, /* SuperTrak EX8650 */
  1183. { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
  1184. st_yosemite }, /* SuperTrak EX8654 */
  1185. { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1186. st_yosemite }, /* generic st_yosemite */
  1187. { } /* terminate list */
  1188. };
  1189. MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
  1190. static struct pci_driver stex_pci_driver = {
  1191. .name = DRV_NAME,
  1192. .id_table = stex_pci_tbl,
  1193. .probe = stex_probe,
  1194. .remove = __devexit_p(stex_remove),
  1195. .shutdown = stex_shutdown,
  1196. };
  1197. static int __init stex_init(void)
  1198. {
  1199. printk(KERN_INFO DRV_NAME
  1200. ": Promise SuperTrak EX Driver version: %s\n",
  1201. ST_DRIVER_VERSION);
  1202. return pci_register_driver(&stex_pci_driver);
  1203. }
  1204. static void __exit stex_exit(void)
  1205. {
  1206. pci_unregister_driver(&stex_pci_driver);
  1207. }
  1208. module_init(stex_init);
  1209. module_exit(stex_exit);