ql4_def.h 15 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2006 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #ifndef __QL4_DEF_H
  8. #define __QL4_DEF_H
  9. #include <linux/kernel.h>
  10. #include <linux/init.h>
  11. #include <linux/types.h>
  12. #include <linux/module.h>
  13. #include <linux/list.h>
  14. #include <linux/pci.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/sched.h>
  17. #include <linux/slab.h>
  18. #include <linux/dmapool.h>
  19. #include <linux/mempool.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/workqueue.h>
  22. #include <linux/delay.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/mutex.h>
  25. #include <net/tcp.h>
  26. #include <scsi/scsi.h>
  27. #include <scsi/scsi_host.h>
  28. #include <scsi/scsi_device.h>
  29. #include <scsi/scsi_cmnd.h>
  30. #include <scsi/scsi_transport.h>
  31. #include <scsi/scsi_transport_iscsi.h>
  32. #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
  33. #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
  34. #endif
  35. #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
  36. #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
  37. #endif
  38. #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
  39. #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
  40. #endif
  41. #define QLA_SUCCESS 0
  42. #define QLA_ERROR 1
  43. /*
  44. * Data bit definitions
  45. */
  46. #define BIT_0 0x1
  47. #define BIT_1 0x2
  48. #define BIT_2 0x4
  49. #define BIT_3 0x8
  50. #define BIT_4 0x10
  51. #define BIT_5 0x20
  52. #define BIT_6 0x40
  53. #define BIT_7 0x80
  54. #define BIT_8 0x100
  55. #define BIT_9 0x200
  56. #define BIT_10 0x400
  57. #define BIT_11 0x800
  58. #define BIT_12 0x1000
  59. #define BIT_13 0x2000
  60. #define BIT_14 0x4000
  61. #define BIT_15 0x8000
  62. #define BIT_16 0x10000
  63. #define BIT_17 0x20000
  64. #define BIT_18 0x40000
  65. #define BIT_19 0x80000
  66. #define BIT_20 0x100000
  67. #define BIT_21 0x200000
  68. #define BIT_22 0x400000
  69. #define BIT_23 0x800000
  70. #define BIT_24 0x1000000
  71. #define BIT_25 0x2000000
  72. #define BIT_26 0x4000000
  73. #define BIT_27 0x8000000
  74. #define BIT_28 0x10000000
  75. #define BIT_29 0x20000000
  76. #define BIT_30 0x40000000
  77. #define BIT_31 0x80000000
  78. /*
  79. * Host adapter default definitions
  80. ***********************************/
  81. #define MAX_HBAS 16
  82. #define MAX_BUSES 1
  83. #define MAX_TARGETS (MAX_PRST_DEV_DB_ENTRIES + MAX_DEV_DB_ENTRIES)
  84. #define MAX_LUNS 0xffff
  85. #define MAX_AEN_ENTRIES 256 /* should be > EXT_DEF_MAX_AEN_QUEUE */
  86. #define MAX_DDB_ENTRIES (MAX_PRST_DEV_DB_ENTRIES + MAX_DEV_DB_ENTRIES)
  87. #define MAX_PDU_ENTRIES 32
  88. #define INVALID_ENTRY 0xFFFF
  89. #define MAX_CMDS_TO_RISC 1024
  90. #define MAX_SRBS MAX_CMDS_TO_RISC
  91. #define MBOX_AEN_REG_COUNT 5
  92. #define MAX_INIT_RETRIES 5
  93. #define IOCB_HIWAT_CUSHION 16
  94. /*
  95. * Buffer sizes
  96. */
  97. #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
  98. #define RESPONSE_QUEUE_DEPTH 64
  99. #define QUEUE_SIZE 64
  100. #define DMA_BUFFER_SIZE 512
  101. /*
  102. * Misc
  103. */
  104. #define MAC_ADDR_LEN 6 /* in bytes */
  105. #define IP_ADDR_LEN 4 /* in bytes */
  106. #define DRIVER_NAME "qla4xxx"
  107. #define MAX_LINKED_CMDS_PER_LUN 3
  108. #define MAX_REQS_SERVICED_PER_INTR 16
  109. #define ISCSI_IPADDR_SIZE 4 /* IP address size */
  110. #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alais name size */
  111. #define ISCSI_NAME_SIZE 255 /* ISCSI Name size -
  112. * usually a string */
  113. #define LSDW(x) ((u32)((u64)(x)))
  114. #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
  115. /*
  116. * Retry & Timeout Values
  117. */
  118. #define MBOX_TOV 60
  119. #define SOFT_RESET_TOV 30
  120. #define RESET_INTR_TOV 3
  121. #define SEMAPHORE_TOV 10
  122. #define ADAPTER_INIT_TOV 120
  123. #define ADAPTER_RESET_TOV 180
  124. #define EXTEND_CMD_TOV 60
  125. #define WAIT_CMD_TOV 30
  126. #define EH_WAIT_CMD_TOV 120
  127. #define FIRMWARE_UP_TOV 60
  128. #define RESET_FIRMWARE_TOV 30
  129. #define LOGOUT_TOV 10
  130. #define IOCB_TOV_MARGIN 10
  131. #define RELOGIN_TOV 18
  132. #define ISNS_DEREG_TOV 5
  133. #define MAX_RESET_HA_RETRIES 2
  134. /*
  135. * SCSI Request Block structure (srb) that is placed
  136. * on cmd->SCp location of every I/O [We have 22 bytes available]
  137. */
  138. struct srb {
  139. struct list_head list; /* (8) */
  140. struct scsi_qla_host *ha; /* HA the SP is queued on */
  141. struct ddb_entry *ddb;
  142. uint16_t flags; /* (1) Status flags. */
  143. #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
  144. #define SRB_GOT_SENSE BIT_4 /* sense data recieved. */
  145. uint8_t state; /* (1) Status flags. */
  146. #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
  147. #define SRB_FREE_STATE 1
  148. #define SRB_ACTIVE_STATE 3
  149. #define SRB_ACTIVE_TIMEOUT_STATE 4
  150. #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
  151. struct scsi_cmnd *cmd; /* (4) SCSI command block */
  152. dma_addr_t dma_handle; /* (4) for unmap of single transfers */
  153. atomic_t ref_count; /* reference count for this srb */
  154. uint32_t fw_ddb_index;
  155. uint8_t err_id; /* error id */
  156. #define SRB_ERR_PORT 1 /* Request failed because "port down" */
  157. #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
  158. #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
  159. #define SRB_ERR_OTHER 4
  160. uint16_t reserved;
  161. uint16_t iocb_tov;
  162. uint16_t iocb_cnt; /* Number of used iocbs */
  163. uint16_t cc_stat;
  164. u_long r_start; /* Time we recieve a cmd from OS */
  165. u_long u_start; /* Time when we handed the cmd to F/W */
  166. };
  167. /*
  168. * Device Database (DDB) structure
  169. */
  170. struct ddb_entry {
  171. struct list_head list; /* ddb list */
  172. struct scsi_qla_host *ha;
  173. struct iscsi_cls_session *sess;
  174. struct iscsi_cls_conn *conn;
  175. atomic_t state; /* DDB State */
  176. unsigned long flags; /* DDB Flags */
  177. unsigned long dev_scan_wait_to_start_relogin;
  178. unsigned long dev_scan_wait_to_complete_relogin;
  179. uint16_t os_target_id; /* Target ID */
  180. uint16_t fw_ddb_index; /* DDB firmware index */
  181. uint8_t reserved[2];
  182. uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
  183. uint32_t CmdSn;
  184. uint16_t target_session_id;
  185. uint16_t connection_id;
  186. uint16_t exe_throttle; /* Max mumber of cmds outstanding
  187. * simultaneously */
  188. uint16_t task_mgmt_timeout; /* Min time for task mgmt cmds to
  189. * complete */
  190. uint16_t default_relogin_timeout; /* Max time to wait for
  191. * relogin to complete */
  192. uint16_t tcp_source_port_num;
  193. uint32_t default_time2wait; /* Default Min time between
  194. * relogins (+aens) */
  195. atomic_t port_down_timer; /* Device connection timer */
  196. atomic_t retry_relogin_timer; /* Min Time between relogins
  197. * (4000 only) */
  198. atomic_t relogin_timer; /* Max Time to wait for relogin to complete */
  199. atomic_t relogin_retry_count; /* Num of times relogin has been
  200. * retried */
  201. uint16_t port;
  202. uint32_t tpgt;
  203. uint8_t ip_addr[ISCSI_IPADDR_SIZE];
  204. uint8_t iscsi_name[ISCSI_NAME_SIZE]; /* 72 x48 */
  205. uint8_t iscsi_alias[0x20];
  206. };
  207. /*
  208. * DDB states.
  209. */
  210. #define DDB_STATE_DEAD 0 /* We can no longer talk to
  211. * this device */
  212. #define DDB_STATE_ONLINE 1 /* Device ready to accept
  213. * commands */
  214. #define DDB_STATE_MISSING 2 /* Device logged off, trying
  215. * to re-login */
  216. /*
  217. * DDB flags.
  218. */
  219. #define DF_RELOGIN 0 /* Relogin to device */
  220. #define DF_NO_RELOGIN 1 /* Do not relogin if IOCTL
  221. * logged it out */
  222. #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
  223. #define DF_FO_MASKED 3
  224. /*
  225. * Asynchronous Event Queue structure
  226. */
  227. struct aen {
  228. uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
  229. };
  230. #include "ql4_fw.h"
  231. #include "ql4_nvram.h"
  232. /*
  233. * Linux Host Adapter structure
  234. */
  235. struct scsi_qla_host {
  236. /* Linux adapter configuration data */
  237. struct Scsi_Host *host; /* pointer to host data */
  238. uint32_t tot_ddbs;
  239. unsigned long flags;
  240. #define AF_ONLINE 0 /* 0x00000001 */
  241. #define AF_INIT_DONE 1 /* 0x00000002 */
  242. #define AF_MBOX_COMMAND 2 /* 0x00000004 */
  243. #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
  244. #define AF_INTERRUPTS_ON 6 /* 0x00000040 Not Used */
  245. #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
  246. #define AF_LINK_UP 8 /* 0x00000100 */
  247. #define AF_IRQ_ATTACHED 10 /* 0x00000400 */
  248. #define AF_ISNS_CMD_IN_PROCESS 12 /* 0x00001000 */
  249. #define AF_ISNS_CMD_DONE 13 /* 0x00002000 */
  250. unsigned long dpc_flags;
  251. #define DPC_RESET_HA 1 /* 0x00000002 */
  252. #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
  253. #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
  254. #define DPC_RESET_HA_DESTROY_DDB_LIST 4 /* 0x00000010 */
  255. #define DPC_RESET_HA_INTR 5 /* 0x00000020 */
  256. #define DPC_ISNS_RESTART 7 /* 0x00000080 */
  257. #define DPC_AEN 9 /* 0x00000200 */
  258. #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
  259. uint16_t iocb_cnt;
  260. uint16_t iocb_hiwat;
  261. /* SRB cache. */
  262. #define SRB_MIN_REQ 128
  263. mempool_t *srb_mempool;
  264. /* pci information */
  265. struct pci_dev *pdev;
  266. struct isp_reg __iomem *reg; /* Base I/O address */
  267. unsigned long pio_address;
  268. unsigned long pio_length;
  269. #define MIN_IOBASE_LEN 0x100
  270. uint16_t req_q_count;
  271. uint8_t marker_needed;
  272. uint8_t rsvd1;
  273. unsigned long host_no;
  274. /* NVRAM registers */
  275. struct eeprom_data *nvram;
  276. spinlock_t hardware_lock ____cacheline_aligned;
  277. uint32_t eeprom_cmd_data;
  278. /* Counters for general statistics */
  279. uint64_t isr_count;
  280. uint64_t adapter_error_count;
  281. uint64_t device_error_count;
  282. uint64_t total_io_count;
  283. uint64_t total_mbytes_xferred;
  284. uint64_t link_failure_count;
  285. uint64_t invalid_crc_count;
  286. uint32_t bytes_xfered;
  287. uint32_t spurious_int_count;
  288. uint32_t aborted_io_count;
  289. uint32_t io_timeout_count;
  290. uint32_t mailbox_timeout_count;
  291. uint32_t seconds_since_last_intr;
  292. uint32_t seconds_since_last_heartbeat;
  293. uint32_t mac_index;
  294. /* Info Needed for Management App */
  295. /* --- From GetFwVersion --- */
  296. uint32_t firmware_version[2];
  297. uint32_t patch_number;
  298. uint32_t build_number;
  299. /* --- From Init_FW --- */
  300. /* init_cb_t *init_cb; */
  301. uint16_t firmware_options;
  302. uint16_t tcp_options;
  303. uint8_t ip_address[IP_ADDR_LEN];
  304. uint8_t subnet_mask[IP_ADDR_LEN];
  305. uint8_t gateway[IP_ADDR_LEN];
  306. uint8_t alias[32];
  307. uint8_t name_string[256];
  308. uint8_t heartbeat_interval;
  309. uint8_t rsvd;
  310. /* --- From FlashSysInfo --- */
  311. uint8_t my_mac[MAC_ADDR_LEN];
  312. uint8_t serial_number[16];
  313. /* --- From GetFwState --- */
  314. uint32_t firmware_state;
  315. uint32_t board_id;
  316. uint32_t addl_fw_state;
  317. /* Linux kernel thread */
  318. struct workqueue_struct *dpc_thread;
  319. struct work_struct dpc_work;
  320. /* Linux timer thread */
  321. struct timer_list timer;
  322. uint32_t timer_active;
  323. /* Recovery Timers */
  324. uint32_t port_down_retry_count;
  325. uint32_t discovery_wait;
  326. atomic_t check_relogin_timeouts;
  327. uint32_t retry_reset_ha_cnt;
  328. uint32_t isp_reset_timer; /* reset test timer */
  329. uint32_t nic_reset_timer; /* simulated nic reset test timer */
  330. int eh_start;
  331. struct list_head free_srb_q;
  332. uint16_t free_srb_q_count;
  333. uint16_t num_srbs_allocated;
  334. /* DMA Memory Block */
  335. void *queues;
  336. dma_addr_t queues_dma;
  337. unsigned long queues_len;
  338. #define MEM_ALIGN_VALUE \
  339. ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
  340. sizeof(struct queue_entry))
  341. /* request and response queue variables */
  342. dma_addr_t request_dma;
  343. struct queue_entry *request_ring;
  344. struct queue_entry *request_ptr;
  345. dma_addr_t response_dma;
  346. struct queue_entry *response_ring;
  347. struct queue_entry *response_ptr;
  348. dma_addr_t shadow_regs_dma;
  349. struct shadow_regs *shadow_regs;
  350. uint16_t request_in; /* Current indexes. */
  351. uint16_t request_out;
  352. uint16_t response_in;
  353. uint16_t response_out;
  354. /* aen queue variables */
  355. uint16_t aen_q_count; /* Number of available aen_q entries */
  356. uint16_t aen_in; /* Current indexes */
  357. uint16_t aen_out;
  358. struct aen aen_q[MAX_AEN_ENTRIES];
  359. /* This mutex protects several threads to do mailbox commands
  360. * concurrently.
  361. */
  362. struct mutex mbox_sem;
  363. /* temporary mailbox status registers */
  364. volatile uint8_t mbox_status_count;
  365. volatile uint32_t mbox_status[MBOX_REG_COUNT];
  366. /* local device database list (contains internal ddb entries) */
  367. struct list_head ddb_list;
  368. /* Map ddb_list entry by FW ddb index */
  369. struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
  370. };
  371. static inline int is_qla4010(struct scsi_qla_host *ha)
  372. {
  373. return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
  374. }
  375. static inline int is_qla4022(struct scsi_qla_host *ha)
  376. {
  377. return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
  378. }
  379. static inline int is_qla4032(struct scsi_qla_host *ha)
  380. {
  381. return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
  382. }
  383. static inline int adapter_up(struct scsi_qla_host *ha)
  384. {
  385. return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
  386. (test_bit(AF_LINK_UP, &ha->flags) != 0);
  387. }
  388. static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
  389. {
  390. return (struct scsi_qla_host *)shost->hostdata;
  391. }
  392. static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
  393. {
  394. return (is_qla4010(ha) ?
  395. &ha->reg->u1.isp4010.nvram :
  396. &ha->reg->u1.isp4022.semaphore);
  397. }
  398. static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
  399. {
  400. return (is_qla4010(ha) ?
  401. &ha->reg->u1.isp4010.nvram :
  402. &ha->reg->u1.isp4022.nvram);
  403. }
  404. static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
  405. {
  406. return (is_qla4010(ha) ?
  407. &ha->reg->u2.isp4010.ext_hw_conf :
  408. &ha->reg->u2.isp4022.p0.ext_hw_conf);
  409. }
  410. static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
  411. {
  412. return (is_qla4010(ha) ?
  413. &ha->reg->u2.isp4010.port_status :
  414. &ha->reg->u2.isp4022.p0.port_status);
  415. }
  416. static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
  417. {
  418. return (is_qla4010(ha) ?
  419. &ha->reg->u2.isp4010.port_ctrl :
  420. &ha->reg->u2.isp4022.p0.port_ctrl);
  421. }
  422. static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
  423. {
  424. return (is_qla4010(ha) ?
  425. &ha->reg->u2.isp4010.port_err_status :
  426. &ha->reg->u2.isp4022.p0.port_err_status);
  427. }
  428. static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
  429. {
  430. return (is_qla4010(ha) ?
  431. &ha->reg->u2.isp4010.gp_out :
  432. &ha->reg->u2.isp4022.p0.gp_out);
  433. }
  434. static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
  435. {
  436. return (is_qla4010(ha) ?
  437. offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
  438. offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
  439. }
  440. int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
  441. void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
  442. int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
  443. static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
  444. {
  445. if (is_qla4010(a))
  446. return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
  447. QL4010_FLASH_SEM_BITS);
  448. else
  449. return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
  450. (QL4022_RESOURCE_BITS_BASE_CODE |
  451. (a->mac_index)) << 13);
  452. }
  453. static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
  454. {
  455. if (is_qla4010(a))
  456. ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
  457. else
  458. ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
  459. }
  460. static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
  461. {
  462. if (is_qla4010(a))
  463. return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
  464. QL4010_NVRAM_SEM_BITS);
  465. else
  466. return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
  467. (QL4022_RESOURCE_BITS_BASE_CODE |
  468. (a->mac_index)) << 10);
  469. }
  470. static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
  471. {
  472. if (is_qla4010(a))
  473. ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
  474. else
  475. ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
  476. }
  477. static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
  478. {
  479. if (is_qla4010(a))
  480. return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
  481. QL4010_DRVR_SEM_BITS);
  482. else
  483. return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
  484. (QL4022_RESOURCE_BITS_BASE_CODE |
  485. (a->mac_index)) << 1);
  486. }
  487. static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
  488. {
  489. if (is_qla4010(a))
  490. ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
  491. else
  492. ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
  493. }
  494. /*---------------------------------------------------------------------------*/
  495. /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
  496. #define PRESERVE_DDB_LIST 0
  497. #define REBUILD_DDB_LIST 1
  498. /* Defines for process_aen() */
  499. #define PROCESS_ALL_AENS 0
  500. #define FLUSH_DDB_CHANGED_AENS 1
  501. #define RELOGIN_DDB_CHANGED_AENS 2
  502. #include "ql4_version.h"
  503. #include "ql4_glbl.h"
  504. #include "ql4_dbg.h"
  505. #include "ql4_inline.h"
  506. #endif /*_QLA4XXX_H */