gdth.c 201 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.4.x, 2.6.x supported *
  31. * *
  32. * $Log: gdth.c,v $
  33. * Revision 1.74 2006/04/10 13:44:47 achim
  34. * Community changes for 2.6.x
  35. * Kernel 2.2.x no longer supported
  36. * scsi_request interface removed, thanks to Christoph Hellwig
  37. *
  38. * Revision 1.73 2004/03/31 13:33:03 achim
  39. * Special command 0xfd implemented to detect 64-bit DMA support
  40. *
  41. * Revision 1.72 2004/03/17 08:56:04 achim
  42. * 64-bit DMA only enabled if FW >= x.43
  43. *
  44. * Revision 1.71 2004/03/05 15:51:29 achim
  45. * Screen service: separate message buffer, bugfixes
  46. *
  47. * Revision 1.70 2004/02/27 12:19:07 achim
  48. * Bugfix: Reset bit in config (0xfe) call removed
  49. *
  50. * Revision 1.69 2004/02/20 09:50:24 achim
  51. * Compatibility changes for kernels < 2.4.20
  52. * Bugfix screen service command size
  53. * pci_set_dma_mask() error handling added
  54. *
  55. * Revision 1.68 2004/02/19 15:46:54 achim
  56. * 64-bit DMA bugfixes
  57. * Drive size bugfix for drives > 1TB
  58. *
  59. * Revision 1.67 2004/01/14 13:11:57 achim
  60. * Tool access over /proc no longer supported
  61. * Bugfixes IOCTLs
  62. *
  63. * Revision 1.66 2003/12/19 15:04:06 achim
  64. * Bugfixes support for drives > 2TB
  65. *
  66. * Revision 1.65 2003/12/15 11:21:56 achim
  67. * 64-bit DMA support added
  68. * Support for drives > 2 TB implemented
  69. * Kernels 2.2.x, 2.4.x, 2.6.x supported
  70. *
  71. * Revision 1.64 2003/09/17 08:30:26 achim
  72. * EISA/ISA controller scan disabled
  73. * Command line switch probe_eisa_isa added
  74. *
  75. * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
  76. * Minor cleanups in gdth_ioctl.
  77. *
  78. * Revision 1.62 2003/02/27 15:01:59 achim
  79. * Dynamic DMA mapping implemented
  80. * New (character device) IOCTL interface added
  81. * Other controller related changes made
  82. *
  83. * Revision 1.61 2002/11/08 13:09:52 boji
  84. * Added support for XSCALE based RAID Controllers
  85. * Fixed SCREENSERVICE initialization in SMP cases
  86. * Added checks for gdth_polling before GDTH_HA_LOCK
  87. *
  88. * Revision 1.60 2002/02/05 09:35:22 achim
  89. * MODULE_LICENSE only if kernel >= 2.4.11
  90. *
  91. * Revision 1.59 2002/01/30 09:46:33 achim
  92. * Small changes
  93. *
  94. * Revision 1.58 2002/01/29 15:30:02 achim
  95. * Set default value of shared_access to Y
  96. * New status S_CACHE_RESERV for clustering added
  97. *
  98. * Revision 1.57 2001/08/21 11:16:35 achim
  99. * Bugfix free_irq()
  100. *
  101. * Revision 1.56 2001/08/09 11:19:39 achim
  102. * Scsi_Host_Template changes
  103. *
  104. * Revision 1.55 2001/08/09 10:11:28 achim
  105. * Command HOST_UNFREEZE_IO before cache service init.
  106. *
  107. * Revision 1.54 2001/07/20 13:48:12 achim
  108. * Expand: gdth_analyse_hdrive() removed
  109. *
  110. * Revision 1.53 2001/07/17 09:52:49 achim
  111. * Small OEM related change
  112. *
  113. * Revision 1.52 2001/06/19 15:06:20 achim
  114. * New host command GDT_UNFREEZE_IO added
  115. *
  116. * Revision 1.51 2001/05/22 06:42:37 achim
  117. * PCI: Subdevice ID added
  118. *
  119. * Revision 1.50 2001/05/17 13:42:16 achim
  120. * Support for Intel Storage RAID Controllers added
  121. *
  122. * Revision 1.50 2001/05/17 12:12:34 achim
  123. * Support for Intel Storage RAID Controllers added
  124. *
  125. * Revision 1.49 2001/03/15 15:07:17 achim
  126. * New __setup interface for boot command line options added
  127. *
  128. * Revision 1.48 2001/02/06 12:36:28 achim
  129. * Bugfix Cluster protocol
  130. *
  131. * Revision 1.47 2001/01/10 14:42:06 achim
  132. * New switch shared_access added
  133. *
  134. * Revision 1.46 2001/01/09 08:11:35 achim
  135. * gdth_command() removed
  136. * meaning of Scsi_Pointer members changed
  137. *
  138. * Revision 1.45 2000/11/16 12:02:24 achim
  139. * Changes for kernel 2.4
  140. *
  141. * Revision 1.44 2000/10/11 08:44:10 achim
  142. * Clustering changes: New flag media_changed added
  143. *
  144. * Revision 1.43 2000/09/20 12:59:01 achim
  145. * DPMEM remap functions for all PCI controller types implemented
  146. * Small changes for ia64 platform
  147. *
  148. * Revision 1.42 2000/07/20 09:04:50 achim
  149. * Small changes for kernel 2.4
  150. *
  151. * Revision 1.41 2000/07/04 14:11:11 achim
  152. * gdth_analyse_hdrive() added to rescan drives after online expansion
  153. *
  154. * Revision 1.40 2000/06/27 11:24:16 achim
  155. * Changes Clustering, Screenservice
  156. *
  157. * Revision 1.39 2000/06/15 13:09:04 achim
  158. * Changes for gdth_do_cmd()
  159. *
  160. * Revision 1.38 2000/06/15 12:08:43 achim
  161. * Bugfix gdth_sync_event(), service SCREENSERVICE
  162. * Data direction for command 0xc2 changed to DOU
  163. *
  164. * Revision 1.37 2000/05/25 13:50:10 achim
  165. * New driver parameter virt_ctr added
  166. *
  167. * Revision 1.36 2000/05/04 08:50:46 achim
  168. * Event buffer now in gdth_ha_str
  169. *
  170. * Revision 1.35 2000/03/03 10:44:08 achim
  171. * New event_string only valid for the RP controller family
  172. *
  173. * Revision 1.34 2000/03/02 14:55:29 achim
  174. * New mechanism for async. event handling implemented
  175. *
  176. * Revision 1.33 2000/02/21 15:37:37 achim
  177. * Bugfix Alpha platform + DPMEM above 4GB
  178. *
  179. * Revision 1.32 2000/02/14 16:17:37 achim
  180. * Bugfix sense_buffer[] + raw devices
  181. *
  182. * Revision 1.31 2000/02/10 10:29:00 achim
  183. * Delete sense_buffer[0], if command OK
  184. *
  185. * Revision 1.30 1999/11/02 13:42:39 achim
  186. * ARRAY_DRV_LIST2 implemented
  187. * Now 255 log. and 100 host drives supported
  188. *
  189. * Revision 1.29 1999/10/05 13:28:47 achim
  190. * GDT_CLUST_RESET added
  191. *
  192. * Revision 1.28 1999/08/12 13:44:54 achim
  193. * MOUNTALL removed
  194. * Cluster drives -> removeable drives
  195. *
  196. * Revision 1.27 1999/06/22 07:22:38 achim
  197. * Small changes
  198. *
  199. * Revision 1.26 1999/06/10 16:09:12 achim
  200. * Cluster Host Drive support: Bugfixes
  201. *
  202. * Revision 1.25 1999/06/01 16:03:56 achim
  203. * gdth_init_pci(): Manipulate config. space to start RP controller
  204. *
  205. * Revision 1.24 1999/05/26 11:53:06 achim
  206. * Cluster Host Drive support added
  207. *
  208. * Revision 1.23 1999/03/26 09:12:31 achim
  209. * Default value for hdr_channel set to 0
  210. *
  211. * Revision 1.22 1999/03/22 16:27:16 achim
  212. * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
  213. *
  214. * Revision 1.21 1999/03/16 13:40:34 achim
  215. * Problems with reserved drives solved
  216. * gdth_eh_bus_reset() implemented
  217. *
  218. * Revision 1.20 1999/03/10 09:08:13 achim
  219. * Bugfix: Corrections in gdth_direction_tab[] made
  220. * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
  221. *
  222. * Revision 1.19 1999/03/05 14:38:16 achim
  223. * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
  224. * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
  225. * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
  226. * with BIOS disabled and memory test set to Intensive
  227. * Enhanced /proc support
  228. *
  229. * Revision 1.18 1999/02/24 09:54:33 achim
  230. * Command line parameter hdr_channel implemented
  231. * Bugfix for EISA controllers + Linux 2.2.x
  232. *
  233. * Revision 1.17 1998/12/17 15:58:11 achim
  234. * Command line parameters implemented
  235. * Changes for Alpha platforms
  236. * PCI controller scan changed
  237. * SMP support improved (spin_lock_irqsave(),...)
  238. * New async. events, new scan/reserve commands included
  239. *
  240. * Revision 1.16 1998/09/28 16:08:46 achim
  241. * GDT_PCIMPR: DPMEM remapping, if required
  242. * mdelay() added
  243. *
  244. * Revision 1.15 1998/06/03 14:54:06 achim
  245. * gdth_delay(), gdth_flush() implemented
  246. * Bugfix: gdth_release() changed
  247. *
  248. * Revision 1.14 1998/05/22 10:01:17 achim
  249. * mj: pcibios_strerror() removed
  250. * Improved SMP support (if version >= 2.1.95)
  251. * gdth_halt(): halt_called flag added (if version < 2.1)
  252. *
  253. * Revision 1.13 1998/04/16 09:14:57 achim
  254. * Reserve drives (for raw service) implemented
  255. * New error handling code enabled
  256. * Get controller name from board_info() IOCTL
  257. * Final round of PCI device driver patches by Martin Mares
  258. *
  259. * Revision 1.12 1998/03/03 09:32:37 achim
  260. * Fibre channel controller support added
  261. *
  262. * Revision 1.11 1998/01/27 16:19:14 achim
  263. * SA_SHIRQ added
  264. * add_timer()/del_timer() instead of GDTH_TIMER
  265. * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
  266. * New error handling included
  267. *
  268. * Revision 1.10 1997/10/31 12:29:57 achim
  269. * Read heads/sectors from host drive
  270. *
  271. * Revision 1.9 1997/09/04 10:07:25 achim
  272. * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
  273. * register_reboot_notifier() to get a notify on shutown used
  274. *
  275. * Revision 1.8 1997/04/02 12:14:30 achim
  276. * Version 1.00 (see gdth.h), tested with kernel 2.0.29
  277. *
  278. * Revision 1.7 1997/03/12 13:33:37 achim
  279. * gdth_reset() changed, new async. events
  280. *
  281. * Revision 1.6 1997/03/04 14:01:11 achim
  282. * Shutdown routine gdth_halt() implemented
  283. *
  284. * Revision 1.5 1997/02/21 09:08:36 achim
  285. * New controller included (RP, RP1, RP2 series)
  286. * IOCTL interface implemented
  287. *
  288. * Revision 1.4 1996/07/05 12:48:55 achim
  289. * Function gdth_bios_param() implemented
  290. * New constant GDTH_MAXC_P_L inserted
  291. * GDT_WRITE_THR, GDT_EXT_INFO implemented
  292. * Function gdth_reset() changed
  293. *
  294. * Revision 1.3 1996/05/10 09:04:41 achim
  295. * Small changes for Linux 1.2.13
  296. *
  297. * Revision 1.2 1996/05/09 12:45:27 achim
  298. * Loadable module support implemented
  299. * /proc support corrections made
  300. *
  301. * Revision 1.1 1996/04/11 07:35:57 achim
  302. * Initial revision
  303. *
  304. ************************************************************************/
  305. /* All GDT Disk Array Controllers are fully supported by this driver.
  306. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  307. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  308. * list of all controller types.
  309. *
  310. * If you have one or more GDT3000/3020 EISA controllers with
  311. * controller BIOS disabled, you have to set the IRQ values with the
  312. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  313. * the IRQ values for the EISA controllers.
  314. *
  315. * After the optional list of IRQ values, other possible
  316. * command line options are:
  317. * disable:Y disable driver
  318. * disable:N enable driver
  319. * reserve_mode:0 reserve no drives for the raw service
  320. * reserve_mode:1 reserve all not init., removable drives
  321. * reserve_mode:2 reserve all not init. drives
  322. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  323. * h- controller no., b- channel no.,
  324. * t- target ID, l- LUN
  325. * reverse_scan:Y reverse scan order for PCI controllers
  326. * reverse_scan:N scan PCI controllers like BIOS
  327. * max_ids:x x - target ID count per channel (1..MAXID)
  328. * rescan:Y rescan all channels/IDs
  329. * rescan:N use all devices found until now
  330. * virt_ctr:Y map every channel to a virtual controller
  331. * virt_ctr:N use multi channel support
  332. * hdr_channel:x x - number of virtual bus for host drives
  333. * shared_access:Y disable driver reserve/release protocol to
  334. * access a shared resource from several nodes,
  335. * appropriate controller firmware required
  336. * shared_access:N enable driver reserve/release protocol
  337. * probe_eisa_isa:Y scan for EISA/ISA controllers
  338. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  339. * force_dma32:Y use only 32 bit DMA mode
  340. * force_dma32:N use 64 bit DMA mode, if supported
  341. *
  342. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  343. * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
  344. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  345. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  346. *
  347. * When loading the gdth driver as a module, the same options are available.
  348. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  349. * options changes slightly. You must replace all ',' between options
  350. * with ' ' and all ':' with '=' and you must use
  351. * '1' in place of 'Y' and '0' in place of 'N'.
  352. *
  353. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  354. * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
  355. * probe_eisa_isa=0 force_dma32=0"
  356. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  357. */
  358. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  359. * ptr: Chaining
  360. * this_residual: Command priority
  361. * buffer: phys. DMA sense buffer
  362. * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
  363. * buffers_residual: Timeout value
  364. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  365. * Message: Additional info (gdth_do_cmd()), DMA direction
  366. * have_data_in: Flag for gdth_wait_completion()
  367. * sent_command: Opcode special command
  368. * phase: Service/parameter/return code special command
  369. */
  370. /* interrupt coalescing */
  371. /* #define INT_COAL */
  372. /* statistics */
  373. #define GDTH_STATISTICS
  374. #include <linux/module.h>
  375. #include <linux/version.h>
  376. #include <linux/kernel.h>
  377. #include <linux/types.h>
  378. #include <linux/pci.h>
  379. #include <linux/string.h>
  380. #include <linux/ctype.h>
  381. #include <linux/ioport.h>
  382. #include <linux/delay.h>
  383. #include <linux/interrupt.h>
  384. #include <linux/in.h>
  385. #include <linux/proc_fs.h>
  386. #include <linux/time.h>
  387. #include <linux/timer.h>
  388. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,6)
  389. #include <linux/dma-mapping.h>
  390. #else
  391. #define DMA_32BIT_MASK 0x00000000ffffffffULL
  392. #define DMA_64BIT_MASK 0xffffffffffffffffULL
  393. #endif
  394. #ifdef GDTH_RTC
  395. #include <linux/mc146818rtc.h>
  396. #endif
  397. #include <linux/reboot.h>
  398. #include <asm/dma.h>
  399. #include <asm/system.h>
  400. #include <asm/io.h>
  401. #include <asm/uaccess.h>
  402. #include <linux/spinlock.h>
  403. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  404. #include <linux/blkdev.h>
  405. #else
  406. #include <linux/blk.h>
  407. #include "sd.h"
  408. #endif
  409. #include "scsi.h"
  410. #include <scsi/scsi_host.h>
  411. #include "gdth_kcompat.h"
  412. #include "gdth.h"
  413. static void gdth_delay(int milliseconds);
  414. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  415. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  416. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
  417. static int gdth_async_event(int hanum);
  418. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  419. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
  420. static void gdth_next(int hanum);
  421. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
  422. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
  423. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  424. ushort idx, gdth_evt_data *evt);
  425. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  426. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  427. gdth_evt_str *estr);
  428. static void gdth_clear_events(void);
  429. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  430. char *buffer,ushort count);
  431. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
  432. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
  433. static int gdth_search_eisa(ushort eisa_adr);
  434. static int gdth_search_isa(ulong32 bios_adr);
  435. static int gdth_search_pci(gdth_pci_str *pcistr);
  436. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  437. ushort vendor, ushort dev);
  438. static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
  439. static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
  440. static int gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha);
  441. static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
  442. static void gdth_enable_int(int hanum);
  443. static int gdth_get_status(unchar *pIStatus,int irq);
  444. static int gdth_test_busy(int hanum);
  445. static int gdth_get_cmd_index(int hanum);
  446. static void gdth_release_event(int hanum);
  447. static int gdth_wait(int hanum,int index,ulong32 time);
  448. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  449. ulong64 p2,ulong64 p3);
  450. static int gdth_search_drives(int hanum);
  451. static int gdth_analyse_hdrive(int hanum, ushort hdrive);
  452. static const char *gdth_ctr_name(int hanum);
  453. static int gdth_open(struct inode *inode, struct file *filep);
  454. static int gdth_close(struct inode *inode, struct file *filep);
  455. static int gdth_ioctl(struct inode *inode, struct file *filep,
  456. unsigned int cmd, unsigned long arg);
  457. static void gdth_flush(int hanum);
  458. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  459. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  460. static void gdth_scsi_done(struct scsi_cmnd *scp);
  461. #ifdef DEBUG_GDTH
  462. static unchar DebugState = DEBUG_GDTH;
  463. #ifdef __SERIAL__
  464. #define MAX_SERBUF 160
  465. static void ser_init(void);
  466. static void ser_puts(char *str);
  467. static void ser_putc(char c);
  468. static int ser_printk(const char *fmt, ...);
  469. static char strbuf[MAX_SERBUF+1];
  470. #ifdef __COM2__
  471. #define COM_BASE 0x2f8
  472. #else
  473. #define COM_BASE 0x3f8
  474. #endif
  475. static void ser_init()
  476. {
  477. unsigned port=COM_BASE;
  478. outb(0x80,port+3);
  479. outb(0,port+1);
  480. /* 19200 Baud, if 9600: outb(12,port) */
  481. outb(6, port);
  482. outb(3,port+3);
  483. outb(0,port+1);
  484. /*
  485. ser_putc('I');
  486. ser_putc(' ');
  487. */
  488. }
  489. static void ser_puts(char *str)
  490. {
  491. char *ptr;
  492. ser_init();
  493. for (ptr=str;*ptr;++ptr)
  494. ser_putc(*ptr);
  495. }
  496. static void ser_putc(char c)
  497. {
  498. unsigned port=COM_BASE;
  499. while ((inb(port+5) & 0x20)==0);
  500. outb(c,port);
  501. if (c==0x0a)
  502. {
  503. while ((inb(port+5) & 0x20)==0);
  504. outb(0x0d,port);
  505. }
  506. }
  507. static int ser_printk(const char *fmt, ...)
  508. {
  509. va_list args;
  510. int i;
  511. va_start(args,fmt);
  512. i = vsprintf(strbuf,fmt,args);
  513. ser_puts(strbuf);
  514. va_end(args);
  515. return i;
  516. }
  517. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  518. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  519. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  520. #else /* !__SERIAL__ */
  521. #define TRACE(a) {if (DebugState==1) {printk a;}}
  522. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  523. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  524. #endif
  525. #else /* !DEBUG */
  526. #define TRACE(a)
  527. #define TRACE2(a)
  528. #define TRACE3(a)
  529. #endif
  530. #ifdef GDTH_STATISTICS
  531. static ulong32 max_rq=0, max_index=0, max_sg=0;
  532. #ifdef INT_COAL
  533. static ulong32 max_int_coal=0;
  534. #endif
  535. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  536. static struct timer_list gdth_timer;
  537. #endif
  538. #define PTR2USHORT(a) (ushort)(ulong)(a)
  539. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  540. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  541. #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
  542. #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
  543. #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
  544. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  545. #define gdth_readb(addr) readb(addr)
  546. #define gdth_readw(addr) readw(addr)
  547. #define gdth_readl(addr) readl(addr)
  548. #define gdth_writeb(b,addr) writeb((b),(addr))
  549. #define gdth_writew(b,addr) writew((b),(addr))
  550. #define gdth_writel(b,addr) writel((b),(addr))
  551. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  552. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  553. static unchar gdth_polling; /* polling if TRUE */
  554. static unchar gdth_from_wait = FALSE; /* gdth_wait() */
  555. static int wait_index,wait_hanum; /* gdth_wait() */
  556. static int gdth_ctr_count = 0; /* controller count */
  557. static int gdth_ctr_vcount = 0; /* virt. ctr. count */
  558. static int gdth_ctr_released = 0; /* gdth_release() */
  559. static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
  560. static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
  561. static unchar gdth_write_through = FALSE; /* write through */
  562. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  563. static int elastidx;
  564. static int eoldidx;
  565. static int major;
  566. #define DIN 1 /* IN data direction */
  567. #define DOU 2 /* OUT data direction */
  568. #define DNO DIN /* no data transfer */
  569. #define DUN DIN /* unknown data direction */
  570. static unchar gdth_direction_tab[0x100] = {
  571. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  572. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  573. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  574. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  575. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  576. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  577. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  578. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  579. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  580. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  581. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  582. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  583. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  584. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  585. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  586. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  587. };
  588. /* LILO and modprobe/insmod parameters */
  589. /* IRQ list for GDT3000/3020 EISA controllers */
  590. static int irq[MAXHA] __initdata =
  591. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  592. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  593. /* disable driver flag */
  594. static int disable __initdata = 0;
  595. /* reserve flag */
  596. static int reserve_mode = 1;
  597. /* reserve list */
  598. static int reserve_list[MAX_RES_ARGS] =
  599. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  600. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  601. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  602. /* scan order for PCI controllers */
  603. static int reverse_scan = 0;
  604. /* virtual channel for the host drives */
  605. static int hdr_channel = 0;
  606. /* max. IDs per channel */
  607. static int max_ids = MAXID;
  608. /* rescan all IDs */
  609. static int rescan = 0;
  610. /* map channels to virtual controllers */
  611. static int virt_ctr = 0;
  612. /* shared access */
  613. static int shared_access = 1;
  614. /* enable support for EISA and ISA controllers */
  615. static int probe_eisa_isa = 0;
  616. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  617. static int force_dma32 = 0;
  618. /* parameters for modprobe/insmod */
  619. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
  620. module_param_array(irq, int, NULL, 0);
  621. module_param(disable, int, 0);
  622. module_param(reserve_mode, int, 0);
  623. module_param_array(reserve_list, int, NULL, 0);
  624. module_param(reverse_scan, int, 0);
  625. module_param(hdr_channel, int, 0);
  626. module_param(max_ids, int, 0);
  627. module_param(rescan, int, 0);
  628. module_param(virt_ctr, int, 0);
  629. module_param(shared_access, int, 0);
  630. module_param(probe_eisa_isa, int, 0);
  631. module_param(force_dma32, int, 0);
  632. #else
  633. MODULE_PARM(irq, "i");
  634. MODULE_PARM(disable, "i");
  635. MODULE_PARM(reserve_mode, "i");
  636. MODULE_PARM(reserve_list, "4-" __MODULE_STRING(MAX_RES_ARGS) "i");
  637. MODULE_PARM(reverse_scan, "i");
  638. MODULE_PARM(hdr_channel, "i");
  639. MODULE_PARM(max_ids, "i");
  640. MODULE_PARM(rescan, "i");
  641. MODULE_PARM(virt_ctr, "i");
  642. MODULE_PARM(shared_access, "i");
  643. MODULE_PARM(probe_eisa_isa, "i");
  644. MODULE_PARM(force_dma32, "i");
  645. #endif
  646. MODULE_AUTHOR("Achim Leubner");
  647. MODULE_LICENSE("GPL");
  648. /* ioctl interface */
  649. static const struct file_operations gdth_fops = {
  650. .ioctl = gdth_ioctl,
  651. .open = gdth_open,
  652. .release = gdth_close,
  653. };
  654. #include "gdth_proc.h"
  655. #include "gdth_proc.c"
  656. /* notifier block to get a notify on system shutdown/halt/reboot */
  657. static struct notifier_block gdth_notifier = {
  658. gdth_halt, NULL, 0
  659. };
  660. static int notifier_disabled = 0;
  661. static void gdth_delay(int milliseconds)
  662. {
  663. if (milliseconds == 0) {
  664. udelay(1);
  665. } else {
  666. mdelay(milliseconds);
  667. }
  668. }
  669. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  670. static void gdth_scsi_done(struct scsi_cmnd *scp)
  671. {
  672. TRACE2(("gdth_scsi_done()\n"));
  673. if (scp->request)
  674. complete((struct completion *)scp->request);
  675. }
  676. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  677. int timeout, u32 *info)
  678. {
  679. Scsi_Cmnd *scp;
  680. DECLARE_COMPLETION_ONSTACK(wait);
  681. int rval;
  682. scp = kmalloc(sizeof(*scp), GFP_KERNEL);
  683. if (!scp)
  684. return -ENOMEM;
  685. memset(scp, 0, sizeof(*scp));
  686. scp->device = sdev;
  687. /* use request field to save the ptr. to completion struct. */
  688. scp->request = (struct request *)&wait;
  689. scp->timeout_per_command = timeout*HZ;
  690. scp->request_buffer = gdtcmd;
  691. scp->cmd_len = 12;
  692. memcpy(scp->cmnd, cmnd, 12);
  693. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  694. scp->done = gdth_scsi_done; /* some fn. test this */
  695. gdth_queuecommand(scp, gdth_scsi_done);
  696. wait_for_completion(&wait);
  697. rval = scp->SCp.Status;
  698. if (info)
  699. *info = scp->SCp.Message;
  700. kfree(scp);
  701. return rval;
  702. }
  703. #else
  704. static void gdth_scsi_done(Scsi_Cmnd *scp)
  705. {
  706. TRACE2(("gdth_scsi_done()\n"));
  707. scp->request.rq_status = RQ_SCSI_DONE;
  708. if (scp->request.waiting)
  709. complete(scp->request.waiting);
  710. }
  711. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  712. int timeout, u32 *info)
  713. {
  714. Scsi_Cmnd *scp = scsi_allocate_device(sdev, 1, FALSE);
  715. unsigned bufflen = gdtcmd ? sizeof(gdth_cmd_str) : 0;
  716. DECLARE_COMPLETION_ONSTACK(wait);
  717. int rval;
  718. if (!scp)
  719. return -ENOMEM;
  720. scp->cmd_len = 12;
  721. scp->use_sg = 0;
  722. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  723. scp->request.rq_status = RQ_SCSI_BUSY;
  724. scp->request.waiting = &wait;
  725. scsi_do_cmd(scp, cmnd, gdtcmd, bufflen, gdth_scsi_done, timeout*HZ, 1);
  726. wait_for_completion(&wait);
  727. rval = scp->SCp.Status;
  728. if (info)
  729. *info = scp->SCp.Message;
  730. scsi_release_command(scp);
  731. return rval;
  732. }
  733. #endif
  734. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  735. int timeout, u32 *info)
  736. {
  737. struct scsi_device *sdev = scsi_get_host_dev(shost);
  738. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  739. scsi_free_host_dev(sdev);
  740. return rval;
  741. }
  742. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  743. {
  744. *cyls = size /HEADS/SECS;
  745. if (*cyls <= MAXCYLS) {
  746. *heads = HEADS;
  747. *secs = SECS;
  748. } else { /* too high for 64*32 */
  749. *cyls = size /MEDHEADS/MEDSECS;
  750. if (*cyls <= MAXCYLS) {
  751. *heads = MEDHEADS;
  752. *secs = MEDSECS;
  753. } else { /* too high for 127*63 */
  754. *cyls = size /BIGHEADS/BIGSECS;
  755. *heads = BIGHEADS;
  756. *secs = BIGSECS;
  757. }
  758. }
  759. }
  760. /* controller search and initialization functions */
  761. static int __init gdth_search_eisa(ushort eisa_adr)
  762. {
  763. ulong32 id;
  764. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  765. id = inl(eisa_adr+ID0REG);
  766. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  767. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  768. return 0; /* not EISA configured */
  769. return 1;
  770. }
  771. if (id == GDT3_ID) /* GDT3000 */
  772. return 1;
  773. return 0;
  774. }
  775. static int __init gdth_search_isa(ulong32 bios_adr)
  776. {
  777. void __iomem *addr;
  778. ulong32 id;
  779. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  780. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  781. id = gdth_readl(addr);
  782. iounmap(addr);
  783. if (id == GDT2_ID) /* GDT2000 */
  784. return 1;
  785. }
  786. return 0;
  787. }
  788. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  789. {
  790. ushort device, cnt;
  791. TRACE(("gdth_search_pci()\n"));
  792. cnt = 0;
  793. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  794. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  795. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  796. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  797. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  798. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  799. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  800. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  801. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  802. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  803. PCI_DEVICE_ID_INTEL_SRC);
  804. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  805. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  806. return cnt;
  807. }
  808. /* Vortex only makes RAID controllers.
  809. * We do not really want to specify all 550 ids here, so wildcard match.
  810. */
  811. static struct pci_device_id gdthtable[] __attribute_used__ = {
  812. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  813. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  814. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  815. {0}
  816. };
  817. MODULE_DEVICE_TABLE(pci,gdthtable);
  818. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  819. ushort vendor, ushort device)
  820. {
  821. ulong base0, base1, base2;
  822. struct pci_dev *pdev;
  823. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  824. *cnt, vendor, device));
  825. pdev = NULL;
  826. while ((pdev = pci_find_device(vendor, device, pdev))
  827. != NULL) {
  828. if (pci_enable_device(pdev))
  829. continue;
  830. if (*cnt >= MAXHA)
  831. return;
  832. /* GDT PCI controller found, resources are already in pdev */
  833. pcistr[*cnt].pdev = pdev;
  834. pcistr[*cnt].vendor_id = vendor;
  835. pcistr[*cnt].device_id = device;
  836. pcistr[*cnt].subdevice_id = pdev->subsystem_device;
  837. pcistr[*cnt].bus = pdev->bus->number;
  838. pcistr[*cnt].device_fn = pdev->devfn;
  839. pcistr[*cnt].irq = pdev->irq;
  840. base0 = pci_resource_flags(pdev, 0);
  841. base1 = pci_resource_flags(pdev, 1);
  842. base2 = pci_resource_flags(pdev, 2);
  843. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  844. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  845. if (!(base0 & IORESOURCE_MEM))
  846. continue;
  847. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  848. } else { /* GDT6110, GDT6120, .. */
  849. if (!(base0 & IORESOURCE_MEM) ||
  850. !(base2 & IORESOURCE_MEM) ||
  851. !(base1 & IORESOURCE_IO))
  852. continue;
  853. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  854. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  855. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  856. }
  857. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  858. pcistr[*cnt].bus, PCI_SLOT(pcistr[*cnt].device_fn),
  859. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  860. (*cnt)++;
  861. }
  862. }
  863. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  864. {
  865. gdth_pci_str temp;
  866. int i, changed;
  867. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  868. if (cnt == 0)
  869. return;
  870. do {
  871. changed = FALSE;
  872. for (i = 0; i < cnt-1; ++i) {
  873. if (!reverse_scan) {
  874. if ((pcistr[i].bus > pcistr[i+1].bus) ||
  875. (pcistr[i].bus == pcistr[i+1].bus &&
  876. PCI_SLOT(pcistr[i].device_fn) >
  877. PCI_SLOT(pcistr[i+1].device_fn))) {
  878. temp = pcistr[i];
  879. pcistr[i] = pcistr[i+1];
  880. pcistr[i+1] = temp;
  881. changed = TRUE;
  882. }
  883. } else {
  884. if ((pcistr[i].bus < pcistr[i+1].bus) ||
  885. (pcistr[i].bus == pcistr[i+1].bus &&
  886. PCI_SLOT(pcistr[i].device_fn) <
  887. PCI_SLOT(pcistr[i+1].device_fn))) {
  888. temp = pcistr[i];
  889. pcistr[i] = pcistr[i+1];
  890. pcistr[i+1] = temp;
  891. changed = TRUE;
  892. }
  893. }
  894. }
  895. } while (changed);
  896. }
  897. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  898. {
  899. ulong32 retries,id;
  900. unchar prot_ver,eisacf,i,irq_found;
  901. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  902. /* disable board interrupts, deinitialize services */
  903. outb(0xff,eisa_adr+EDOORREG);
  904. outb(0x00,eisa_adr+EDENABREG);
  905. outb(0x00,eisa_adr+EINTENABREG);
  906. outb(0xff,eisa_adr+LDOORREG);
  907. retries = INIT_RETRIES;
  908. gdth_delay(20);
  909. while (inb(eisa_adr+EDOORREG) != 0xff) {
  910. if (--retries == 0) {
  911. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  912. return 0;
  913. }
  914. gdth_delay(1);
  915. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  916. }
  917. prot_ver = inb(eisa_adr+MAILBOXREG);
  918. outb(0xff,eisa_adr+EDOORREG);
  919. if (prot_ver != PROTOCOL_VERSION) {
  920. printk("GDT-EISA: Illegal protocol version\n");
  921. return 0;
  922. }
  923. ha->bmic = eisa_adr;
  924. ha->brd_phys = (ulong32)eisa_adr >> 12;
  925. outl(0,eisa_adr+MAILBOXREG);
  926. outl(0,eisa_adr+MAILBOXREG+4);
  927. outl(0,eisa_adr+MAILBOXREG+8);
  928. outl(0,eisa_adr+MAILBOXREG+12);
  929. /* detect IRQ */
  930. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  931. ha->oem_id = OEM_ID_ICP;
  932. ha->type = GDT_EISA;
  933. ha->stype = id;
  934. outl(1,eisa_adr+MAILBOXREG+8);
  935. outb(0xfe,eisa_adr+LDOORREG);
  936. retries = INIT_RETRIES;
  937. gdth_delay(20);
  938. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  939. if (--retries == 0) {
  940. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  941. return 0;
  942. }
  943. gdth_delay(1);
  944. }
  945. ha->irq = inb(eisa_adr+MAILBOXREG);
  946. outb(0xff,eisa_adr+EDOORREG);
  947. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  948. /* check the result */
  949. if (ha->irq == 0) {
  950. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  951. for (i = 0, irq_found = FALSE;
  952. i < MAXHA && irq[i] != 0xff; ++i) {
  953. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  954. irq_found = TRUE;
  955. break;
  956. }
  957. }
  958. if (irq_found) {
  959. ha->irq = irq[i];
  960. irq[i] = 0;
  961. printk("GDT-EISA: Can not detect controller IRQ,\n");
  962. printk("Use IRQ setting from command line (IRQ = %d)\n",
  963. ha->irq);
  964. } else {
  965. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  966. printk("the controller BIOS or use command line parameters\n");
  967. return 0;
  968. }
  969. }
  970. } else {
  971. eisacf = inb(eisa_adr+EISAREG) & 7;
  972. if (eisacf > 4) /* level triggered */
  973. eisacf -= 4;
  974. ha->irq = gdth_irq_tab[eisacf];
  975. ha->oem_id = OEM_ID_ICP;
  976. ha->type = GDT_EISA;
  977. ha->stype = id;
  978. }
  979. ha->dma64_support = 0;
  980. return 1;
  981. }
  982. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  983. {
  984. register gdt2_dpram_str __iomem *dp2_ptr;
  985. int i;
  986. unchar irq_drq,prot_ver;
  987. ulong32 retries;
  988. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  989. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  990. if (ha->brd == NULL) {
  991. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  992. return 0;
  993. }
  994. dp2_ptr = ha->brd;
  995. gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  996. /* reset interface area */
  997. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  998. if (gdth_readl(&dp2_ptr->u) != 0) {
  999. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  1000. iounmap(ha->brd);
  1001. return 0;
  1002. }
  1003. /* disable board interrupts, read DRQ and IRQ */
  1004. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1005. gdth_writeb(0x00, &dp2_ptr->io.irqen);
  1006. gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
  1007. gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  1008. irq_drq = gdth_readb(&dp2_ptr->io.rq);
  1009. for (i=0; i<3; ++i) {
  1010. if ((irq_drq & 1)==0)
  1011. break;
  1012. irq_drq >>= 1;
  1013. }
  1014. ha->drq = gdth_drq_tab[i];
  1015. irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
  1016. for (i=1; i<5; ++i) {
  1017. if ((irq_drq & 1)==0)
  1018. break;
  1019. irq_drq >>= 1;
  1020. }
  1021. ha->irq = gdth_irq_tab[i];
  1022. /* deinitialize services */
  1023. gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  1024. gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  1025. gdth_writeb(0, &dp2_ptr->io.event);
  1026. retries = INIT_RETRIES;
  1027. gdth_delay(20);
  1028. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  1029. if (--retries == 0) {
  1030. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  1031. iounmap(ha->brd);
  1032. return 0;
  1033. }
  1034. gdth_delay(1);
  1035. }
  1036. prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
  1037. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  1038. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1039. if (prot_ver != PROTOCOL_VERSION) {
  1040. printk("GDT-ISA: Illegal protocol version\n");
  1041. iounmap(ha->brd);
  1042. return 0;
  1043. }
  1044. ha->oem_id = OEM_ID_ICP;
  1045. ha->type = GDT_ISA;
  1046. ha->ic_all_size = sizeof(dp2_ptr->u);
  1047. ha->stype= GDT2_ID;
  1048. ha->brd_phys = bios_adr >> 4;
  1049. /* special request to controller BIOS */
  1050. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  1051. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  1052. gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  1053. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  1054. gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  1055. gdth_writeb(0, &dp2_ptr->io.event);
  1056. retries = INIT_RETRIES;
  1057. gdth_delay(20);
  1058. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  1059. if (--retries == 0) {
  1060. printk("GDT-ISA: Initialization error\n");
  1061. iounmap(ha->brd);
  1062. return 0;
  1063. }
  1064. gdth_delay(1);
  1065. }
  1066. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  1067. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1068. ha->dma64_support = 0;
  1069. return 1;
  1070. }
  1071. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  1072. {
  1073. register gdt6_dpram_str __iomem *dp6_ptr;
  1074. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1075. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1076. ulong32 retries;
  1077. unchar prot_ver;
  1078. ushort command;
  1079. int i, found = FALSE;
  1080. TRACE(("gdth_init_pci()\n"));
  1081. if (pcistr->vendor_id == PCI_VENDOR_ID_INTEL)
  1082. ha->oem_id = OEM_ID_INTEL;
  1083. else
  1084. ha->oem_id = OEM_ID_ICP;
  1085. ha->brd_phys = (pcistr->bus << 8) | (pcistr->device_fn & 0xf8);
  1086. ha->stype = (ulong32)pcistr->device_id;
  1087. ha->subdevice_id = pcistr->subdevice_id;
  1088. ha->irq = pcistr->irq;
  1089. ha->pdev = pcistr->pdev;
  1090. if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  1091. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1092. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  1093. if (ha->brd == NULL) {
  1094. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1095. return 0;
  1096. }
  1097. /* check and reset interface area */
  1098. dp6_ptr = ha->brd;
  1099. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1100. if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  1101. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1102. pcistr->dpmem);
  1103. found = FALSE;
  1104. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1105. iounmap(ha->brd);
  1106. ha->brd = ioremap(i, sizeof(ushort));
  1107. if (ha->brd == NULL) {
  1108. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1109. return 0;
  1110. }
  1111. if (gdth_readw(ha->brd) != 0xffff) {
  1112. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  1113. continue;
  1114. }
  1115. iounmap(ha->brd);
  1116. pci_write_config_dword(pcistr->pdev,
  1117. PCI_BASE_ADDRESS_0, i);
  1118. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  1119. if (ha->brd == NULL) {
  1120. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1121. return 0;
  1122. }
  1123. dp6_ptr = ha->brd;
  1124. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1125. if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  1126. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1127. found = TRUE;
  1128. break;
  1129. }
  1130. }
  1131. if (!found) {
  1132. printk("GDT-PCI: No free address found!\n");
  1133. iounmap(ha->brd);
  1134. return 0;
  1135. }
  1136. }
  1137. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  1138. if (gdth_readl(&dp6_ptr->u) != 0) {
  1139. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1140. iounmap(ha->brd);
  1141. return 0;
  1142. }
  1143. /* disable board interrupts, deinit services */
  1144. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1145. gdth_writeb(0x00, &dp6_ptr->io.irqen);
  1146. gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
  1147. gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  1148. gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  1149. gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  1150. gdth_writeb(0, &dp6_ptr->io.event);
  1151. retries = INIT_RETRIES;
  1152. gdth_delay(20);
  1153. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  1154. if (--retries == 0) {
  1155. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1156. iounmap(ha->brd);
  1157. return 0;
  1158. }
  1159. gdth_delay(1);
  1160. }
  1161. prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
  1162. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1163. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1164. if (prot_ver != PROTOCOL_VERSION) {
  1165. printk("GDT-PCI: Illegal protocol version\n");
  1166. iounmap(ha->brd);
  1167. return 0;
  1168. }
  1169. ha->type = GDT_PCI;
  1170. ha->ic_all_size = sizeof(dp6_ptr->u);
  1171. /* special command to controller BIOS */
  1172. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  1173. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  1174. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  1175. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  1176. gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  1177. gdth_writeb(0, &dp6_ptr->io.event);
  1178. retries = INIT_RETRIES;
  1179. gdth_delay(20);
  1180. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  1181. if (--retries == 0) {
  1182. printk("GDT-PCI: Initialization error\n");
  1183. iounmap(ha->brd);
  1184. return 0;
  1185. }
  1186. gdth_delay(1);
  1187. }
  1188. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1189. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1190. ha->dma64_support = 0;
  1191. } else if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  1192. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  1193. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  1194. pcistr->dpmem,ha->irq));
  1195. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  1196. if (ha->brd == NULL) {
  1197. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1198. iounmap(ha->brd);
  1199. return 0;
  1200. }
  1201. /* check and reset interface area */
  1202. dp6c_ptr = ha->brd;
  1203. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1204. if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  1205. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1206. pcistr->dpmem);
  1207. found = FALSE;
  1208. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1209. iounmap(ha->brd);
  1210. ha->brd = ioremap(i, sizeof(ushort));
  1211. if (ha->brd == NULL) {
  1212. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1213. return 0;
  1214. }
  1215. if (gdth_readw(ha->brd) != 0xffff) {
  1216. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  1217. continue;
  1218. }
  1219. iounmap(ha->brd);
  1220. pci_write_config_dword(pcistr->pdev,
  1221. PCI_BASE_ADDRESS_2, i);
  1222. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  1223. if (ha->brd == NULL) {
  1224. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1225. return 0;
  1226. }
  1227. dp6c_ptr = ha->brd;
  1228. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1229. if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  1230. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1231. found = TRUE;
  1232. break;
  1233. }
  1234. }
  1235. if (!found) {
  1236. printk("GDT-PCI: No free address found!\n");
  1237. iounmap(ha->brd);
  1238. return 0;
  1239. }
  1240. }
  1241. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  1242. if (gdth_readl(&dp6c_ptr->u) != 0) {
  1243. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1244. iounmap(ha->brd);
  1245. return 0;
  1246. }
  1247. /* disable board interrupts, deinit services */
  1248. outb(0x00,PTR2USHORT(&ha->plx->control1));
  1249. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  1250. gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  1251. gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  1252. gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  1253. gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1254. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1255. retries = INIT_RETRIES;
  1256. gdth_delay(20);
  1257. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  1258. if (--retries == 0) {
  1259. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1260. iounmap(ha->brd);
  1261. return 0;
  1262. }
  1263. gdth_delay(1);
  1264. }
  1265. prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
  1266. gdth_writeb(0, &dp6c_ptr->u.ic.Status);
  1267. if (prot_ver != PROTOCOL_VERSION) {
  1268. printk("GDT-PCI: Illegal protocol version\n");
  1269. iounmap(ha->brd);
  1270. return 0;
  1271. }
  1272. ha->type = GDT_PCINEW;
  1273. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1274. /* special command to controller BIOS */
  1275. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1276. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1277. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1278. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1279. gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1280. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1281. retries = INIT_RETRIES;
  1282. gdth_delay(20);
  1283. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1284. if (--retries == 0) {
  1285. printk("GDT-PCI: Initialization error\n");
  1286. iounmap(ha->brd);
  1287. return 0;
  1288. }
  1289. gdth_delay(1);
  1290. }
  1291. gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
  1292. ha->dma64_support = 0;
  1293. } else { /* MPR */
  1294. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1295. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1296. if (ha->brd == NULL) {
  1297. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1298. return 0;
  1299. }
  1300. /* manipulate config. space to enable DPMEM, start RP controller */
  1301. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1302. command |= 6;
  1303. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1304. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1305. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1306. i = 0xFEFF0001UL;
  1307. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1308. gdth_delay(1);
  1309. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1310. pci_resource_start(pcistr->pdev, 8));
  1311. dp6m_ptr = ha->brd;
  1312. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1313. * Aditional check needed for Xscale based RAID controllers */
  1314. while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1315. gdth_delay(1);
  1316. /* check and reset interface area */
  1317. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1318. if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1319. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1320. pcistr->dpmem);
  1321. found = FALSE;
  1322. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1323. iounmap(ha->brd);
  1324. ha->brd = ioremap(i, sizeof(ushort));
  1325. if (ha->brd == NULL) {
  1326. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1327. return 0;
  1328. }
  1329. if (gdth_readw(ha->brd) != 0xffff) {
  1330. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1331. continue;
  1332. }
  1333. iounmap(ha->brd);
  1334. pci_write_config_dword(pcistr->pdev,
  1335. PCI_BASE_ADDRESS_0, i);
  1336. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1337. if (ha->brd == NULL) {
  1338. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1339. return 0;
  1340. }
  1341. dp6m_ptr = ha->brd;
  1342. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1343. if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1344. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1345. found = TRUE;
  1346. break;
  1347. }
  1348. }
  1349. if (!found) {
  1350. printk("GDT-PCI: No free address found!\n");
  1351. iounmap(ha->brd);
  1352. return 0;
  1353. }
  1354. }
  1355. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1356. /* disable board interrupts, deinit services */
  1357. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1358. &dp6m_ptr->i960r.edoor_en_reg);
  1359. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1360. gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1361. gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1362. gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1363. gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1364. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1365. retries = INIT_RETRIES;
  1366. gdth_delay(20);
  1367. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1368. if (--retries == 0) {
  1369. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1370. iounmap(ha->brd);
  1371. return 0;
  1372. }
  1373. gdth_delay(1);
  1374. }
  1375. prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
  1376. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1377. if (prot_ver != PROTOCOL_VERSION) {
  1378. printk("GDT-PCI: Illegal protocol version\n");
  1379. iounmap(ha->brd);
  1380. return 0;
  1381. }
  1382. ha->type = GDT_PCIMPR;
  1383. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1384. /* special command to controller BIOS */
  1385. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1386. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1387. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1388. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1389. gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1390. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1391. retries = INIT_RETRIES;
  1392. gdth_delay(20);
  1393. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1394. if (--retries == 0) {
  1395. printk("GDT-PCI: Initialization error\n");
  1396. iounmap(ha->brd);
  1397. return 0;
  1398. }
  1399. gdth_delay(1);
  1400. }
  1401. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1402. /* read FW version to detect 64-bit DMA support */
  1403. gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1404. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1405. retries = INIT_RETRIES;
  1406. gdth_delay(20);
  1407. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1408. if (--retries == 0) {
  1409. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1410. iounmap(ha->brd);
  1411. return 0;
  1412. }
  1413. gdth_delay(1);
  1414. }
  1415. prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1416. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1417. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1418. ha->dma64_support = 0;
  1419. else
  1420. ha->dma64_support = 1;
  1421. }
  1422. return 1;
  1423. }
  1424. /* controller protocol functions */
  1425. static void __init gdth_enable_int(int hanum)
  1426. {
  1427. gdth_ha_str *ha;
  1428. ulong flags;
  1429. gdt2_dpram_str __iomem *dp2_ptr;
  1430. gdt6_dpram_str __iomem *dp6_ptr;
  1431. gdt6m_dpram_str __iomem *dp6m_ptr;
  1432. TRACE(("gdth_enable_int() hanum %d\n",hanum));
  1433. ha = HADATA(gdth_ctr_tab[hanum]);
  1434. spin_lock_irqsave(&ha->smp_lock, flags);
  1435. if (ha->type == GDT_EISA) {
  1436. outb(0xff, ha->bmic + EDOORREG);
  1437. outb(0xff, ha->bmic + EDENABREG);
  1438. outb(0x01, ha->bmic + EINTENABREG);
  1439. } else if (ha->type == GDT_ISA) {
  1440. dp2_ptr = ha->brd;
  1441. gdth_writeb(1, &dp2_ptr->io.irqdel);
  1442. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1443. gdth_writeb(1, &dp2_ptr->io.irqen);
  1444. } else if (ha->type == GDT_PCI) {
  1445. dp6_ptr = ha->brd;
  1446. gdth_writeb(1, &dp6_ptr->io.irqdel);
  1447. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1448. gdth_writeb(1, &dp6_ptr->io.irqen);
  1449. } else if (ha->type == GDT_PCINEW) {
  1450. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1451. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1452. } else if (ha->type == GDT_PCIMPR) {
  1453. dp6m_ptr = ha->brd;
  1454. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1455. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1456. &dp6m_ptr->i960r.edoor_en_reg);
  1457. }
  1458. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1459. }
  1460. static int gdth_get_status(unchar *pIStatus,int irq)
  1461. {
  1462. register gdth_ha_str *ha;
  1463. int i;
  1464. TRACE(("gdth_get_status() irq %d ctr_count %d\n",
  1465. irq,gdth_ctr_count));
  1466. *pIStatus = 0;
  1467. for (i=0; i<gdth_ctr_count; ++i) {
  1468. ha = HADATA(gdth_ctr_tab[i]);
  1469. if (ha->irq != (unchar)irq) /* check IRQ */
  1470. continue;
  1471. if (ha->type == GDT_EISA)
  1472. *pIStatus = inb((ushort)ha->bmic + EDOORREG);
  1473. else if (ha->type == GDT_ISA)
  1474. *pIStatus =
  1475. gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1476. else if (ha->type == GDT_PCI)
  1477. *pIStatus =
  1478. gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1479. else if (ha->type == GDT_PCINEW)
  1480. *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1481. else if (ha->type == GDT_PCIMPR)
  1482. *pIStatus =
  1483. gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1484. if (*pIStatus)
  1485. return i; /* board found */
  1486. }
  1487. return -1;
  1488. }
  1489. static int gdth_test_busy(int hanum)
  1490. {
  1491. register gdth_ha_str *ha;
  1492. register int gdtsema0 = 0;
  1493. TRACE(("gdth_test_busy() hanum %d\n",hanum));
  1494. ha = HADATA(gdth_ctr_tab[hanum]);
  1495. if (ha->type == GDT_EISA)
  1496. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1497. else if (ha->type == GDT_ISA)
  1498. gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1499. else if (ha->type == GDT_PCI)
  1500. gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1501. else if (ha->type == GDT_PCINEW)
  1502. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1503. else if (ha->type == GDT_PCIMPR)
  1504. gdtsema0 =
  1505. (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1506. return (gdtsema0 & 1);
  1507. }
  1508. static int gdth_get_cmd_index(int hanum)
  1509. {
  1510. register gdth_ha_str *ha;
  1511. int i;
  1512. TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
  1513. ha = HADATA(gdth_ctr_tab[hanum]);
  1514. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1515. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1516. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1517. ha->cmd_tab[i].service = ha->pccb->Service;
  1518. ha->pccb->CommandIndex = (ulong32)i+2;
  1519. return (i+2);
  1520. }
  1521. }
  1522. return 0;
  1523. }
  1524. static void gdth_set_sema0(int hanum)
  1525. {
  1526. register gdth_ha_str *ha;
  1527. TRACE(("gdth_set_sema0() hanum %d\n",hanum));
  1528. ha = HADATA(gdth_ctr_tab[hanum]);
  1529. if (ha->type == GDT_EISA) {
  1530. outb(1, ha->bmic + SEMA0REG);
  1531. } else if (ha->type == GDT_ISA) {
  1532. gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1533. } else if (ha->type == GDT_PCI) {
  1534. gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1535. } else if (ha->type == GDT_PCINEW) {
  1536. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1537. } else if (ha->type == GDT_PCIMPR) {
  1538. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1539. }
  1540. }
  1541. static void gdth_copy_command(int hanum)
  1542. {
  1543. register gdth_ha_str *ha;
  1544. register gdth_cmd_str *cmd_ptr;
  1545. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1546. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1547. gdt6_dpram_str __iomem *dp6_ptr;
  1548. gdt2_dpram_str __iomem *dp2_ptr;
  1549. ushort cp_count,dp_offset,cmd_no;
  1550. TRACE(("gdth_copy_command() hanum %d\n",hanum));
  1551. ha = HADATA(gdth_ctr_tab[hanum]);
  1552. cp_count = ha->cmd_len;
  1553. dp_offset= ha->cmd_offs_dpmem;
  1554. cmd_no = ha->cmd_cnt;
  1555. cmd_ptr = ha->pccb;
  1556. ++ha->cmd_cnt;
  1557. if (ha->type == GDT_EISA)
  1558. return; /* no DPMEM, no copy */
  1559. /* set cpcount dword aligned */
  1560. if (cp_count & 3)
  1561. cp_count += (4 - (cp_count & 3));
  1562. ha->cmd_offs_dpmem += cp_count;
  1563. /* set offset and service, copy command to DPMEM */
  1564. if (ha->type == GDT_ISA) {
  1565. dp2_ptr = ha->brd;
  1566. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1567. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1568. gdth_writew((ushort)cmd_ptr->Service,
  1569. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1570. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1571. } else if (ha->type == GDT_PCI) {
  1572. dp6_ptr = ha->brd;
  1573. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1574. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1575. gdth_writew((ushort)cmd_ptr->Service,
  1576. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1577. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1578. } else if (ha->type == GDT_PCINEW) {
  1579. dp6c_ptr = ha->brd;
  1580. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1581. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1582. gdth_writew((ushort)cmd_ptr->Service,
  1583. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1584. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1585. } else if (ha->type == GDT_PCIMPR) {
  1586. dp6m_ptr = ha->brd;
  1587. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1588. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1589. gdth_writew((ushort)cmd_ptr->Service,
  1590. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1591. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1592. }
  1593. }
  1594. static void gdth_release_event(int hanum)
  1595. {
  1596. register gdth_ha_str *ha;
  1597. TRACE(("gdth_release_event() hanum %d\n",hanum));
  1598. ha = HADATA(gdth_ctr_tab[hanum]);
  1599. #ifdef GDTH_STATISTICS
  1600. {
  1601. ulong32 i,j;
  1602. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1603. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1604. ++i;
  1605. }
  1606. if (max_index < i) {
  1607. max_index = i;
  1608. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1609. }
  1610. }
  1611. #endif
  1612. if (ha->pccb->OpCode == GDT_INIT)
  1613. ha->pccb->Service |= 0x80;
  1614. if (ha->type == GDT_EISA) {
  1615. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1616. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1617. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1618. } else if (ha->type == GDT_ISA) {
  1619. gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1620. } else if (ha->type == GDT_PCI) {
  1621. gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1622. } else if (ha->type == GDT_PCINEW) {
  1623. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1624. } else if (ha->type == GDT_PCIMPR) {
  1625. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1626. }
  1627. }
  1628. static int gdth_wait(int hanum,int index,ulong32 time)
  1629. {
  1630. gdth_ha_str *ha;
  1631. int answer_found = FALSE;
  1632. TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
  1633. ha = HADATA(gdth_ctr_tab[hanum]);
  1634. if (index == 0)
  1635. return 1; /* no wait required */
  1636. gdth_from_wait = TRUE;
  1637. do {
  1638. gdth_interrupt((int)ha->irq,ha);
  1639. if (wait_hanum==hanum && wait_index==index) {
  1640. answer_found = TRUE;
  1641. break;
  1642. }
  1643. gdth_delay(1);
  1644. } while (--time);
  1645. gdth_from_wait = FALSE;
  1646. while (gdth_test_busy(hanum))
  1647. gdth_delay(0);
  1648. return (answer_found);
  1649. }
  1650. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  1651. ulong64 p2,ulong64 p3)
  1652. {
  1653. register gdth_ha_str *ha;
  1654. register gdth_cmd_str *cmd_ptr;
  1655. int retries,index;
  1656. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1657. ha = HADATA(gdth_ctr_tab[hanum]);
  1658. cmd_ptr = ha->pccb;
  1659. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1660. /* make command */
  1661. for (retries = INIT_RETRIES;;) {
  1662. cmd_ptr->Service = service;
  1663. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1664. if (!(index=gdth_get_cmd_index(hanum))) {
  1665. TRACE(("GDT: No free command index found\n"));
  1666. return 0;
  1667. }
  1668. gdth_set_sema0(hanum);
  1669. cmd_ptr->OpCode = opcode;
  1670. cmd_ptr->BoardNode = LOCALBOARD;
  1671. if (service == CACHESERVICE) {
  1672. if (opcode == GDT_IOCTL) {
  1673. cmd_ptr->u.ioctl.subfunc = p1;
  1674. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1675. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1676. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1677. } else {
  1678. if (ha->cache_feat & GDT_64BIT) {
  1679. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1680. cmd_ptr->u.cache64.BlockNo = p2;
  1681. } else {
  1682. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1683. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1684. }
  1685. }
  1686. } else if (service == SCSIRAWSERVICE) {
  1687. if (ha->raw_feat & GDT_64BIT) {
  1688. cmd_ptr->u.raw64.direction = p1;
  1689. cmd_ptr->u.raw64.bus = (unchar)p2;
  1690. cmd_ptr->u.raw64.target = (unchar)p3;
  1691. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1692. } else {
  1693. cmd_ptr->u.raw.direction = p1;
  1694. cmd_ptr->u.raw.bus = (unchar)p2;
  1695. cmd_ptr->u.raw.target = (unchar)p3;
  1696. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1697. }
  1698. } else if (service == SCREENSERVICE) {
  1699. if (opcode == GDT_REALTIME) {
  1700. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1701. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1702. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1703. }
  1704. }
  1705. ha->cmd_len = sizeof(gdth_cmd_str);
  1706. ha->cmd_offs_dpmem = 0;
  1707. ha->cmd_cnt = 0;
  1708. gdth_copy_command(hanum);
  1709. gdth_release_event(hanum);
  1710. gdth_delay(20);
  1711. if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
  1712. printk("GDT: Initialization error (timeout service %d)\n",service);
  1713. return 0;
  1714. }
  1715. if (ha->status != S_BSY || --retries == 0)
  1716. break;
  1717. gdth_delay(1);
  1718. }
  1719. return (ha->status != S_OK ? 0:1);
  1720. }
  1721. /* search for devices */
  1722. static int __init gdth_search_drives(int hanum)
  1723. {
  1724. register gdth_ha_str *ha;
  1725. ushort cdev_cnt, i;
  1726. int ok;
  1727. ulong32 bus_no, drv_cnt, drv_no, j;
  1728. gdth_getch_str *chn;
  1729. gdth_drlist_str *drl;
  1730. gdth_iochan_str *ioc;
  1731. gdth_raw_iochan_str *iocr;
  1732. gdth_arcdl_str *alst;
  1733. gdth_alist_str *alst2;
  1734. gdth_oem_str_ioctl *oemstr;
  1735. #ifdef INT_COAL
  1736. gdth_perf_modes *pmod;
  1737. #endif
  1738. #ifdef GDTH_RTC
  1739. unchar rtc[12];
  1740. ulong flags;
  1741. #endif
  1742. TRACE(("gdth_search_drives() hanum %d\n",hanum));
  1743. ha = HADATA(gdth_ctr_tab[hanum]);
  1744. ok = 0;
  1745. /* initialize controller services, at first: screen service */
  1746. ha->screen_feat = 0;
  1747. if (!force_dma32) {
  1748. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
  1749. if (ok)
  1750. ha->screen_feat = GDT_64BIT;
  1751. }
  1752. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1753. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
  1754. if (!ok) {
  1755. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1756. hanum, ha->status);
  1757. return 0;
  1758. }
  1759. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1760. #ifdef GDTH_RTC
  1761. /* read realtime clock info, send to controller */
  1762. /* 1. wait for the falling edge of update flag */
  1763. spin_lock_irqsave(&rtc_lock, flags);
  1764. for (j = 0; j < 1000000; ++j)
  1765. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1766. break;
  1767. for (j = 0; j < 1000000; ++j)
  1768. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1769. break;
  1770. /* 2. read info */
  1771. do {
  1772. for (j = 0; j < 12; ++j)
  1773. rtc[j] = CMOS_READ(j);
  1774. } while (rtc[0] != CMOS_READ(0));
  1775. spin_lock_irqrestore(&rtc_lock, flags);
  1776. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1777. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1778. /* 3. send to controller firmware */
  1779. gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
  1780. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1781. #endif
  1782. /* unfreeze all IOs */
  1783. gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
  1784. /* initialize cache service */
  1785. ha->cache_feat = 0;
  1786. if (!force_dma32) {
  1787. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
  1788. if (ok)
  1789. ha->cache_feat = GDT_64BIT;
  1790. }
  1791. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1792. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
  1793. if (!ok) {
  1794. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1795. hanum, ha->status);
  1796. return 0;
  1797. }
  1798. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1799. cdev_cnt = (ushort)ha->info;
  1800. ha->fw_vers = ha->service;
  1801. #ifdef INT_COAL
  1802. if (ha->type == GDT_PCIMPR) {
  1803. /* set perf. modes */
  1804. pmod = (gdth_perf_modes *)ha->pscratch;
  1805. pmod->version = 1;
  1806. pmod->st_mode = 1; /* enable one status buffer */
  1807. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1808. pmod->st_buff_indx1 = COALINDEX;
  1809. pmod->st_buff_addr2 = 0;
  1810. pmod->st_buff_u_addr2 = 0;
  1811. pmod->st_buff_indx2 = 0;
  1812. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1813. pmod->cmd_mode = 0; // disable all cmd buffers
  1814. pmod->cmd_buff_addr1 = 0;
  1815. pmod->cmd_buff_u_addr1 = 0;
  1816. pmod->cmd_buff_indx1 = 0;
  1817. pmod->cmd_buff_addr2 = 0;
  1818. pmod->cmd_buff_u_addr2 = 0;
  1819. pmod->cmd_buff_indx2 = 0;
  1820. pmod->cmd_buff_size = 0;
  1821. pmod->reserved1 = 0;
  1822. pmod->reserved2 = 0;
  1823. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
  1824. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1825. printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
  1826. }
  1827. }
  1828. #endif
  1829. /* detect number of buses - try new IOCTL */
  1830. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1831. iocr->hdr.version = 0xffffffff;
  1832. iocr->hdr.list_entries = MAXBUS;
  1833. iocr->hdr.first_chan = 0;
  1834. iocr->hdr.last_chan = MAXBUS-1;
  1835. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1836. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
  1837. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1838. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1839. ha->bus_cnt = iocr->hdr.chan_count;
  1840. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1841. if (iocr->list[bus_no].proc_id < MAXID)
  1842. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1843. else
  1844. ha->bus_id[bus_no] = 0xff;
  1845. }
  1846. } else {
  1847. /* old method */
  1848. chn = (gdth_getch_str *)ha->pscratch;
  1849. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1850. chn->channel_no = bus_no;
  1851. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1852. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1853. IO_CHANNEL | INVALID_CHANNEL,
  1854. sizeof(gdth_getch_str))) {
  1855. if (bus_no == 0) {
  1856. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1857. hanum, ha->status);
  1858. return 0;
  1859. }
  1860. break;
  1861. }
  1862. if (chn->siop_id < MAXID)
  1863. ha->bus_id[bus_no] = chn->siop_id;
  1864. else
  1865. ha->bus_id[bus_no] = 0xff;
  1866. }
  1867. ha->bus_cnt = (unchar)bus_no;
  1868. }
  1869. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1870. /* read cache configuration */
  1871. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
  1872. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1873. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1874. hanum, ha->status);
  1875. return 0;
  1876. }
  1877. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1878. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1879. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1880. ha->cpar.write_back,ha->cpar.block_size));
  1881. /* read board info and features */
  1882. ha->more_proc = FALSE;
  1883. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
  1884. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1885. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1886. sizeof(gdth_binfo_str));
  1887. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
  1888. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1889. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1890. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1891. ha->more_proc = TRUE;
  1892. }
  1893. } else {
  1894. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1895. strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
  1896. }
  1897. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1898. /* read more informations */
  1899. if (ha->more_proc) {
  1900. /* physical drives, channel addresses */
  1901. ioc = (gdth_iochan_str *)ha->pscratch;
  1902. ioc->hdr.version = 0xffffffff;
  1903. ioc->hdr.list_entries = MAXBUS;
  1904. ioc->hdr.first_chan = 0;
  1905. ioc->hdr.last_chan = MAXBUS-1;
  1906. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1907. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
  1908. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1909. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1910. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1911. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1912. }
  1913. } else {
  1914. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1915. ha->raw[bus_no].address = IO_CHANNEL;
  1916. ha->raw[bus_no].local_no = bus_no;
  1917. }
  1918. }
  1919. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1920. chn = (gdth_getch_str *)ha->pscratch;
  1921. chn->channel_no = ha->raw[bus_no].local_no;
  1922. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1923. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1924. ha->raw[bus_no].address | INVALID_CHANNEL,
  1925. sizeof(gdth_getch_str))) {
  1926. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1927. TRACE2(("Channel %d: %d phys. drives\n",
  1928. bus_no,chn->drive_cnt));
  1929. }
  1930. if (ha->raw[bus_no].pdev_cnt > 0) {
  1931. drl = (gdth_drlist_str *)ha->pscratch;
  1932. drl->sc_no = ha->raw[bus_no].local_no;
  1933. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1934. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1935. SCSI_DR_LIST | L_CTRL_PATTERN,
  1936. ha->raw[bus_no].address | INVALID_CHANNEL,
  1937. sizeof(gdth_drlist_str))) {
  1938. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1939. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1940. } else {
  1941. ha->raw[bus_no].pdev_cnt = 0;
  1942. }
  1943. }
  1944. }
  1945. /* logical drives */
  1946. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
  1947. INVALID_CHANNEL,sizeof(ulong32))) {
  1948. drv_cnt = *(ulong32 *)ha->pscratch;
  1949. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
  1950. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1951. for (j = 0; j < drv_cnt; ++j) {
  1952. drv_no = ((ulong32 *)ha->pscratch)[j];
  1953. if (drv_no < MAX_LDRIVES) {
  1954. ha->hdr[drv_no].is_logdrv = TRUE;
  1955. TRACE2(("Drive %d is log. drive\n",drv_no));
  1956. }
  1957. }
  1958. }
  1959. alst = (gdth_arcdl_str *)ha->pscratch;
  1960. alst->entries_avail = MAX_LDRIVES;
  1961. alst->first_entry = 0;
  1962. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1963. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1964. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1965. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1966. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1967. for (j = 0; j < alst->entries_init; ++j) {
  1968. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1969. ha->hdr[j].is_master = alst->list[j].is_master;
  1970. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1971. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1972. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1973. }
  1974. } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1975. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1976. 0, 35 * sizeof(gdth_alist_str))) {
  1977. for (j = 0; j < 35; ++j) {
  1978. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1979. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1980. ha->hdr[j].is_master = alst2->is_master;
  1981. ha->hdr[j].is_parity = alst2->is_parity;
  1982. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1983. ha->hdr[j].master_no = alst2->cd_handle;
  1984. }
  1985. }
  1986. }
  1987. }
  1988. /* initialize raw service */
  1989. ha->raw_feat = 0;
  1990. if (!force_dma32) {
  1991. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
  1992. if (ok)
  1993. ha->raw_feat = GDT_64BIT;
  1994. }
  1995. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1996. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
  1997. if (!ok) {
  1998. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1999. hanum, ha->status);
  2000. return 0;
  2001. }
  2002. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  2003. /* set/get features raw service (scatter/gather) */
  2004. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
  2005. 0,0)) {
  2006. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  2007. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
  2008. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  2009. ha->info));
  2010. ha->raw_feat |= (ushort)ha->info;
  2011. }
  2012. }
  2013. /* set/get features cache service (equal to raw service) */
  2014. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
  2015. SCATTER_GATHER,0)) {
  2016. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  2017. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
  2018. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  2019. ha->info));
  2020. ha->cache_feat |= (ushort)ha->info;
  2021. }
  2022. }
  2023. /* reserve drives for raw service */
  2024. if (reserve_mode != 0) {
  2025. gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
  2026. reserve_mode == 1 ? 1 : 3, 0, 0);
  2027. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  2028. ha->status));
  2029. }
  2030. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  2031. if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
  2032. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  2033. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  2034. reserve_list[i], reserve_list[i+1],
  2035. reserve_list[i+2], reserve_list[i+3]));
  2036. if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
  2037. reserve_list[i+1], reserve_list[i+2] |
  2038. (reserve_list[i+3] << 8))) {
  2039. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  2040. hanum, ha->status);
  2041. }
  2042. }
  2043. }
  2044. /* Determine OEM string using IOCTL */
  2045. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  2046. oemstr->params.ctl_version = 0x01;
  2047. oemstr->params.buffer_size = sizeof(oemstr->text);
  2048. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  2049. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  2050. sizeof(gdth_oem_str_ioctl))) {
  2051. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  2052. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  2053. hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
  2054. /* Save the Host Drive inquiry data */
  2055. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2056. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  2057. sizeof(ha->oem_name));
  2058. #else
  2059. strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
  2060. ha->oem_name[7] = '\0';
  2061. #endif
  2062. } else {
  2063. /* Old method, based on PCI ID */
  2064. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  2065. printk("GDT-HA %d: Name: %s\n",
  2066. hanum,ha->binfo.type_string);
  2067. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2068. if (ha->oem_id == OEM_ID_INTEL)
  2069. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  2070. else
  2071. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  2072. #else
  2073. if (ha->oem_id == OEM_ID_INTEL)
  2074. strcpy(ha->oem_name,"Intel ");
  2075. else
  2076. strcpy(ha->oem_name,"ICP ");
  2077. #endif
  2078. }
  2079. /* scanning for host drives */
  2080. for (i = 0; i < cdev_cnt; ++i)
  2081. gdth_analyse_hdrive(hanum,i);
  2082. TRACE(("gdth_search_drives() OK\n"));
  2083. return 1;
  2084. }
  2085. static int gdth_analyse_hdrive(int hanum,ushort hdrive)
  2086. {
  2087. register gdth_ha_str *ha;
  2088. ulong32 drv_cyls;
  2089. int drv_hds, drv_secs;
  2090. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
  2091. if (hdrive >= MAX_HDRIVES)
  2092. return 0;
  2093. ha = HADATA(gdth_ctr_tab[hanum]);
  2094. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
  2095. return 0;
  2096. ha->hdr[hdrive].present = TRUE;
  2097. ha->hdr[hdrive].size = ha->info;
  2098. /* evaluate mapping (sectors per head, heads per cylinder) */
  2099. ha->hdr[hdrive].size &= ~SECS32;
  2100. if (ha->info2 == 0) {
  2101. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  2102. } else {
  2103. drv_hds = ha->info2 & 0xff;
  2104. drv_secs = (ha->info2 >> 8) & 0xff;
  2105. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  2106. }
  2107. ha->hdr[hdrive].heads = (unchar)drv_hds;
  2108. ha->hdr[hdrive].secs = (unchar)drv_secs;
  2109. /* round size */
  2110. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  2111. if (ha->cache_feat & GDT_64BIT) {
  2112. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
  2113. && ha->info2 != 0) {
  2114. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  2115. }
  2116. }
  2117. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  2118. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  2119. /* get informations about device */
  2120. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
  2121. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  2122. hdrive,ha->info));
  2123. ha->hdr[hdrive].devtype = (ushort)ha->info;
  2124. }
  2125. /* cluster info */
  2126. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
  2127. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  2128. hdrive,ha->info));
  2129. if (!shared_access)
  2130. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  2131. }
  2132. /* R/W attributes */
  2133. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
  2134. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  2135. hdrive,ha->info));
  2136. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  2137. }
  2138. return 1;
  2139. }
  2140. /* command queueing/sending functions */
  2141. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
  2142. {
  2143. register gdth_ha_str *ha;
  2144. register Scsi_Cmnd *pscp;
  2145. register Scsi_Cmnd *nscp;
  2146. ulong flags;
  2147. unchar b, t;
  2148. TRACE(("gdth_putq() priority %d\n",priority));
  2149. ha = HADATA(gdth_ctr_tab[hanum]);
  2150. spin_lock_irqsave(&ha->smp_lock, flags);
  2151. if (scp->done != gdth_scsi_done) {
  2152. scp->SCp.this_residual = (int)priority;
  2153. b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
  2154. t = scp->device->id;
  2155. if (priority >= DEFAULT_PRI) {
  2156. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2157. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  2158. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  2159. scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
  2160. }
  2161. }
  2162. }
  2163. if (ha->req_first==NULL) {
  2164. ha->req_first = scp; /* queue was empty */
  2165. scp->SCp.ptr = NULL;
  2166. } else { /* queue not empty */
  2167. pscp = ha->req_first;
  2168. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2169. /* priority: 0-highest,..,0xff-lowest */
  2170. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  2171. pscp = nscp;
  2172. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2173. }
  2174. pscp->SCp.ptr = (char *)scp;
  2175. scp->SCp.ptr = (char *)nscp;
  2176. }
  2177. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2178. #ifdef GDTH_STATISTICS
  2179. flags = 0;
  2180. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  2181. ++flags;
  2182. if (max_rq < flags) {
  2183. max_rq = flags;
  2184. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  2185. }
  2186. #endif
  2187. }
  2188. static void gdth_next(int hanum)
  2189. {
  2190. register gdth_ha_str *ha;
  2191. register Scsi_Cmnd *pscp;
  2192. register Scsi_Cmnd *nscp;
  2193. unchar b, t, l, firsttime;
  2194. unchar this_cmd, next_cmd;
  2195. ulong flags = 0;
  2196. int cmd_index;
  2197. TRACE(("gdth_next() hanum %d\n",hanum));
  2198. ha = HADATA(gdth_ctr_tab[hanum]);
  2199. if (!gdth_polling)
  2200. spin_lock_irqsave(&ha->smp_lock, flags);
  2201. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  2202. this_cmd = firsttime = TRUE;
  2203. next_cmd = gdth_polling ? FALSE:TRUE;
  2204. cmd_index = 0;
  2205. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  2206. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  2207. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2208. if (nscp->done != gdth_scsi_done) {
  2209. b = virt_ctr ?
  2210. NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
  2211. t = nscp->device->id;
  2212. l = nscp->device->lun;
  2213. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  2214. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2215. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  2216. continue;
  2217. }
  2218. } else
  2219. b = t = l = 0;
  2220. if (firsttime) {
  2221. if (gdth_test_busy(hanum)) { /* controller busy ? */
  2222. TRACE(("gdth_next() controller %d busy !\n",hanum));
  2223. if (!gdth_polling) {
  2224. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2225. return;
  2226. }
  2227. while (gdth_test_busy(hanum))
  2228. gdth_delay(1);
  2229. }
  2230. firsttime = FALSE;
  2231. }
  2232. if (nscp->done != gdth_scsi_done) {
  2233. if (nscp->SCp.phase == -1) {
  2234. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  2235. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  2236. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  2237. b, t, l));
  2238. /* TEST_UNIT_READY -> set scan mode */
  2239. if ((ha->scan_mode & 0x0f) == 0) {
  2240. if (b == 0 && t == 0 && l == 0) {
  2241. ha->scan_mode |= 1;
  2242. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2243. }
  2244. } else if ((ha->scan_mode & 0x0f) == 1) {
  2245. if (b == 0 && ((t == 0 && l == 1) ||
  2246. (t == 1 && l == 0))) {
  2247. nscp->SCp.sent_command = GDT_SCAN_START;
  2248. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  2249. | SCSIRAWSERVICE;
  2250. ha->scan_mode = 0x12;
  2251. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  2252. ha->scan_mode));
  2253. } else {
  2254. ha->scan_mode &= 0x10;
  2255. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2256. }
  2257. } else if (ha->scan_mode == 0x12) {
  2258. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  2259. nscp->SCp.phase = SCSIRAWSERVICE;
  2260. nscp->SCp.sent_command = GDT_SCAN_END;
  2261. ha->scan_mode &= 0x10;
  2262. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  2263. ha->scan_mode));
  2264. }
  2265. }
  2266. }
  2267. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  2268. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  2269. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  2270. /* always GDT_CLUST_INFO! */
  2271. nscp->SCp.sent_command = GDT_CLUST_INFO;
  2272. }
  2273. }
  2274. }
  2275. if (nscp->SCp.sent_command != -1) {
  2276. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  2277. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2278. this_cmd = FALSE;
  2279. next_cmd = FALSE;
  2280. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  2281. if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2282. this_cmd = FALSE;
  2283. next_cmd = FALSE;
  2284. } else {
  2285. memset((char*)nscp->sense_buffer,0,16);
  2286. nscp->sense_buffer[0] = 0x70;
  2287. nscp->sense_buffer[2] = NOT_READY;
  2288. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2289. if (!nscp->SCp.have_data_in)
  2290. nscp->SCp.have_data_in++;
  2291. else
  2292. nscp->scsi_done(nscp);
  2293. }
  2294. } else if (nscp->done == gdth_scsi_done) {
  2295. if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
  2296. this_cmd = FALSE;
  2297. next_cmd = FALSE;
  2298. } else if (b != ha->virt_bus) {
  2299. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  2300. !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2301. this_cmd = FALSE;
  2302. else
  2303. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  2304. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  2305. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  2306. nscp->cmnd[0], b, t, l));
  2307. nscp->result = DID_BAD_TARGET << 16;
  2308. if (!nscp->SCp.have_data_in)
  2309. nscp->SCp.have_data_in++;
  2310. else
  2311. nscp->scsi_done(nscp);
  2312. } else {
  2313. switch (nscp->cmnd[0]) {
  2314. case TEST_UNIT_READY:
  2315. case INQUIRY:
  2316. case REQUEST_SENSE:
  2317. case READ_CAPACITY:
  2318. case VERIFY:
  2319. case START_STOP:
  2320. case MODE_SENSE:
  2321. case SERVICE_ACTION_IN:
  2322. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2323. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2324. nscp->cmnd[4],nscp->cmnd[5]));
  2325. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2326. /* return UNIT_ATTENTION */
  2327. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2328. nscp->cmnd[0], t));
  2329. ha->hdr[t].media_changed = FALSE;
  2330. memset((char*)nscp->sense_buffer,0,16);
  2331. nscp->sense_buffer[0] = 0x70;
  2332. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2333. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2334. if (!nscp->SCp.have_data_in)
  2335. nscp->SCp.have_data_in++;
  2336. else
  2337. nscp->scsi_done(nscp);
  2338. } else if (gdth_internal_cache_cmd(hanum,nscp))
  2339. nscp->scsi_done(nscp);
  2340. break;
  2341. case ALLOW_MEDIUM_REMOVAL:
  2342. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2343. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2344. nscp->cmnd[4],nscp->cmnd[5]));
  2345. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2346. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2347. nscp->result = DID_OK << 16;
  2348. nscp->sense_buffer[0] = 0;
  2349. if (!nscp->SCp.have_data_in)
  2350. nscp->SCp.have_data_in++;
  2351. else
  2352. nscp->scsi_done(nscp);
  2353. } else {
  2354. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2355. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2356. nscp->cmnd[4],nscp->cmnd[3]));
  2357. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2358. this_cmd = FALSE;
  2359. }
  2360. break;
  2361. case RESERVE:
  2362. case RELEASE:
  2363. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2364. "RESERVE" : "RELEASE"));
  2365. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2366. this_cmd = FALSE;
  2367. break;
  2368. case READ_6:
  2369. case WRITE_6:
  2370. case READ_10:
  2371. case WRITE_10:
  2372. case READ_16:
  2373. case WRITE_16:
  2374. if (ha->hdr[t].media_changed) {
  2375. /* return UNIT_ATTENTION */
  2376. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2377. nscp->cmnd[0], t));
  2378. ha->hdr[t].media_changed = FALSE;
  2379. memset((char*)nscp->sense_buffer,0,16);
  2380. nscp->sense_buffer[0] = 0x70;
  2381. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2382. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2383. if (!nscp->SCp.have_data_in)
  2384. nscp->SCp.have_data_in++;
  2385. else
  2386. nscp->scsi_done(nscp);
  2387. } else if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2388. this_cmd = FALSE;
  2389. break;
  2390. default:
  2391. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2392. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2393. nscp->cmnd[4],nscp->cmnd[5]));
  2394. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2395. hanum, nscp->cmnd[0]);
  2396. nscp->result = DID_ABORT << 16;
  2397. if (!nscp->SCp.have_data_in)
  2398. nscp->SCp.have_data_in++;
  2399. else
  2400. nscp->scsi_done(nscp);
  2401. break;
  2402. }
  2403. }
  2404. if (!this_cmd)
  2405. break;
  2406. if (nscp == ha->req_first)
  2407. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2408. else
  2409. pscp->SCp.ptr = nscp->SCp.ptr;
  2410. if (!next_cmd)
  2411. break;
  2412. }
  2413. if (ha->cmd_cnt > 0) {
  2414. gdth_release_event(hanum);
  2415. }
  2416. if (!gdth_polling)
  2417. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2418. if (gdth_polling && ha->cmd_cnt > 0) {
  2419. if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
  2420. printk("GDT-HA %d: Command %d timed out !\n",
  2421. hanum,cmd_index);
  2422. }
  2423. }
  2424. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  2425. char *buffer,ushort count)
  2426. {
  2427. ushort cpcount,i;
  2428. ushort cpsum,cpnow;
  2429. struct scatterlist *sl;
  2430. gdth_ha_str *ha;
  2431. char *address;
  2432. cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
  2433. ha = HADATA(gdth_ctr_tab[hanum]);
  2434. if (scp->use_sg) {
  2435. sl = (struct scatterlist *)scp->request_buffer;
  2436. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2437. unsigned long flags;
  2438. cpnow = (ushort)sl->length;
  2439. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2440. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2441. if (cpsum+cpnow > cpcount)
  2442. cpnow = cpcount - cpsum;
  2443. cpsum += cpnow;
  2444. if (!sl->page) {
  2445. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2446. hanum);
  2447. return;
  2448. }
  2449. local_irq_save(flags);
  2450. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2451. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2452. memcpy(address,buffer,cpnow);
  2453. flush_dcache_page(sl->page);
  2454. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2455. #else
  2456. address = kmap_atomic(sl->page, KM_BH_IRQ) + sl->offset;
  2457. memcpy(address,buffer,cpnow);
  2458. flush_dcache_page(sl->page);
  2459. kunmap_atomic(address, KM_BH_IRQ);
  2460. #endif
  2461. local_irq_restore(flags);
  2462. if (cpsum == cpcount)
  2463. break;
  2464. buffer += cpnow;
  2465. }
  2466. } else {
  2467. TRACE(("copy_internal() count %d\n",cpcount));
  2468. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2469. }
  2470. }
  2471. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
  2472. {
  2473. register gdth_ha_str *ha;
  2474. unchar t;
  2475. gdth_inq_data inq;
  2476. gdth_rdcap_data rdc;
  2477. gdth_sense_data sd;
  2478. gdth_modep_data mpd;
  2479. ha = HADATA(gdth_ctr_tab[hanum]);
  2480. t = scp->device->id;
  2481. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2482. scp->cmnd[0],t));
  2483. scp->result = DID_OK << 16;
  2484. scp->sense_buffer[0] = 0;
  2485. switch (scp->cmnd[0]) {
  2486. case TEST_UNIT_READY:
  2487. case VERIFY:
  2488. case START_STOP:
  2489. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2490. break;
  2491. case INQUIRY:
  2492. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2493. t,ha->hdr[t].devtype));
  2494. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2495. /* you can here set all disks to removable, if you want to do
  2496. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2497. inq.modif_rmb = 0x00;
  2498. if ((ha->hdr[t].devtype & 1) ||
  2499. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2500. inq.modif_rmb = 0x80;
  2501. inq.version = 2;
  2502. inq.resp_aenc = 2;
  2503. inq.add_length= 32;
  2504. strcpy(inq.vendor,ha->oem_name);
  2505. sprintf(inq.product,"Host Drive #%02d",t);
  2506. strcpy(inq.revision," ");
  2507. gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
  2508. break;
  2509. case REQUEST_SENSE:
  2510. TRACE2(("Request sense hdrive %d\n",t));
  2511. sd.errorcode = 0x70;
  2512. sd.segno = 0x00;
  2513. sd.key = NO_SENSE;
  2514. sd.info = 0;
  2515. sd.add_length= 0;
  2516. gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
  2517. break;
  2518. case MODE_SENSE:
  2519. TRACE2(("Mode sense hdrive %d\n",t));
  2520. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2521. mpd.hd.data_length = sizeof(gdth_modep_data);
  2522. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2523. mpd.hd.bd_length = sizeof(mpd.bd);
  2524. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2525. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2526. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2527. gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
  2528. break;
  2529. case READ_CAPACITY:
  2530. TRACE2(("Read capacity hdrive %d\n",t));
  2531. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2532. rdc.last_block_no = 0xffffffff;
  2533. else
  2534. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2535. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2536. gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
  2537. break;
  2538. case SERVICE_ACTION_IN:
  2539. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2540. (ha->cache_feat & GDT_64BIT)) {
  2541. gdth_rdcap16_data rdc16;
  2542. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2543. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2544. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2545. gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
  2546. } else {
  2547. scp->result = DID_ABORT << 16;
  2548. }
  2549. break;
  2550. default:
  2551. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2552. break;
  2553. }
  2554. if (!scp->SCp.have_data_in)
  2555. scp->SCp.have_data_in++;
  2556. else
  2557. return 1;
  2558. return 0;
  2559. }
  2560. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
  2561. {
  2562. register gdth_ha_str *ha;
  2563. register gdth_cmd_str *cmdp;
  2564. struct scatterlist *sl;
  2565. ulong32 cnt, blockcnt;
  2566. ulong64 no, blockno;
  2567. dma_addr_t phys_addr;
  2568. int i, cmd_index, read_write, sgcnt, mode64;
  2569. struct page *page;
  2570. ulong offset;
  2571. ha = HADATA(gdth_ctr_tab[hanum]);
  2572. cmdp = ha->pccb;
  2573. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2574. scp->cmnd[0],scp->cmd_len,hdrive));
  2575. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2576. return 0;
  2577. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2578. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2579. not required, should not occur due to error return on
  2580. READ_CAPACITY_16 */
  2581. cmdp->Service = CACHESERVICE;
  2582. cmdp->RequestBuffer = scp;
  2583. /* search free command index */
  2584. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2585. TRACE(("GDT: No free command index found\n"));
  2586. return 0;
  2587. }
  2588. /* if it's the first command, set command semaphore */
  2589. if (ha->cmd_cnt == 0)
  2590. gdth_set_sema0(hanum);
  2591. /* fill command */
  2592. read_write = 0;
  2593. if (scp->SCp.sent_command != -1)
  2594. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2595. else if (scp->cmnd[0] == RESERVE)
  2596. cmdp->OpCode = GDT_RESERVE_DRV;
  2597. else if (scp->cmnd[0] == RELEASE)
  2598. cmdp->OpCode = GDT_RELEASE_DRV;
  2599. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2600. if (scp->cmnd[4] & 1) /* prevent ? */
  2601. cmdp->OpCode = GDT_MOUNT;
  2602. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2603. cmdp->OpCode = GDT_UNMOUNT;
  2604. else
  2605. cmdp->OpCode = GDT_FLUSH;
  2606. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2607. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2608. ) {
  2609. read_write = 1;
  2610. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2611. (ha->cache_feat & GDT_WR_THROUGH)))
  2612. cmdp->OpCode = GDT_WRITE_THR;
  2613. else
  2614. cmdp->OpCode = GDT_WRITE;
  2615. } else {
  2616. read_write = 2;
  2617. cmdp->OpCode = GDT_READ;
  2618. }
  2619. cmdp->BoardNode = LOCALBOARD;
  2620. if (mode64) {
  2621. cmdp->u.cache64.DeviceNo = hdrive;
  2622. cmdp->u.cache64.BlockNo = 1;
  2623. cmdp->u.cache64.sg_canz = 0;
  2624. } else {
  2625. cmdp->u.cache.DeviceNo = hdrive;
  2626. cmdp->u.cache.BlockNo = 1;
  2627. cmdp->u.cache.sg_canz = 0;
  2628. }
  2629. if (read_write) {
  2630. if (scp->cmd_len == 16) {
  2631. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2632. blockno = be64_to_cpu(no);
  2633. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2634. blockcnt = be32_to_cpu(cnt);
  2635. } else if (scp->cmd_len == 10) {
  2636. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2637. blockno = be32_to_cpu(no);
  2638. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2639. blockcnt = be16_to_cpu(cnt);
  2640. } else {
  2641. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2642. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2643. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2644. }
  2645. if (mode64) {
  2646. cmdp->u.cache64.BlockNo = blockno;
  2647. cmdp->u.cache64.BlockCnt = blockcnt;
  2648. } else {
  2649. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2650. cmdp->u.cache.BlockCnt = blockcnt;
  2651. }
  2652. if (scp->use_sg) {
  2653. sl = (struct scatterlist *)scp->request_buffer;
  2654. sgcnt = scp->use_sg;
  2655. scp->SCp.Status = GDTH_MAP_SG;
  2656. scp->SCp.Message = (read_write == 1 ?
  2657. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2658. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2659. if (mode64) {
  2660. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2661. cmdp->u.cache64.sg_canz = sgcnt;
  2662. for (i=0; i<sgcnt; ++i,++sl) {
  2663. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2664. #ifdef GDTH_DMA_STATISTICS
  2665. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2666. ha->dma64_cnt++;
  2667. else
  2668. ha->dma32_cnt++;
  2669. #endif
  2670. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2671. }
  2672. } else {
  2673. cmdp->u.cache.DestAddr= 0xffffffff;
  2674. cmdp->u.cache.sg_canz = sgcnt;
  2675. for (i=0; i<sgcnt; ++i,++sl) {
  2676. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2677. #ifdef GDTH_DMA_STATISTICS
  2678. ha->dma32_cnt++;
  2679. #endif
  2680. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2681. }
  2682. }
  2683. #ifdef GDTH_STATISTICS
  2684. if (max_sg < (ulong32)sgcnt) {
  2685. max_sg = (ulong32)sgcnt;
  2686. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2687. }
  2688. #endif
  2689. } else if (scp->request_bufflen) {
  2690. scp->SCp.Status = GDTH_MAP_SINGLE;
  2691. scp->SCp.Message = (read_write == 1 ?
  2692. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2693. page = virt_to_page(scp->request_buffer);
  2694. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2695. phys_addr = pci_map_page(ha->pdev,page,offset,
  2696. scp->request_bufflen,scp->SCp.Message);
  2697. scp->SCp.dma_handle = phys_addr;
  2698. if (mode64) {
  2699. if (ha->cache_feat & SCATTER_GATHER) {
  2700. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2701. cmdp->u.cache64.sg_canz = 1;
  2702. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2703. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2704. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2705. } else {
  2706. cmdp->u.cache64.DestAddr = phys_addr;
  2707. cmdp->u.cache64.sg_canz= 0;
  2708. }
  2709. } else {
  2710. if (ha->cache_feat & SCATTER_GATHER) {
  2711. cmdp->u.cache.DestAddr = 0xffffffff;
  2712. cmdp->u.cache.sg_canz = 1;
  2713. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2714. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2715. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2716. } else {
  2717. cmdp->u.cache.DestAddr = phys_addr;
  2718. cmdp->u.cache.sg_canz= 0;
  2719. }
  2720. }
  2721. }
  2722. }
  2723. /* evaluate command size, check space */
  2724. if (mode64) {
  2725. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2726. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2727. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2728. cmdp->u.cache64.sg_lst[0].sg_len));
  2729. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2730. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2731. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2732. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2733. } else {
  2734. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2735. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2736. cmdp->u.cache.sg_lst[0].sg_ptr,
  2737. cmdp->u.cache.sg_lst[0].sg_len));
  2738. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2739. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2740. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2741. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2742. }
  2743. if (ha->cmd_len & 3)
  2744. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2745. if (ha->cmd_cnt > 0) {
  2746. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2747. ha->ic_all_size) {
  2748. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2749. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2750. return 0;
  2751. }
  2752. }
  2753. /* copy command */
  2754. gdth_copy_command(hanum);
  2755. return cmd_index;
  2756. }
  2757. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
  2758. {
  2759. register gdth_ha_str *ha;
  2760. register gdth_cmd_str *cmdp;
  2761. struct scatterlist *sl;
  2762. ushort i;
  2763. dma_addr_t phys_addr, sense_paddr;
  2764. int cmd_index, sgcnt, mode64;
  2765. unchar t,l;
  2766. struct page *page;
  2767. ulong offset;
  2768. ha = HADATA(gdth_ctr_tab[hanum]);
  2769. t = scp->device->id;
  2770. l = scp->device->lun;
  2771. cmdp = ha->pccb;
  2772. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2773. scp->cmnd[0],b,t,l));
  2774. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2775. return 0;
  2776. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2777. cmdp->Service = SCSIRAWSERVICE;
  2778. cmdp->RequestBuffer = scp;
  2779. /* search free command index */
  2780. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2781. TRACE(("GDT: No free command index found\n"));
  2782. return 0;
  2783. }
  2784. /* if it's the first command, set command semaphore */
  2785. if (ha->cmd_cnt == 0)
  2786. gdth_set_sema0(hanum);
  2787. /* fill command */
  2788. if (scp->SCp.sent_command != -1) {
  2789. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2790. cmdp->BoardNode = LOCALBOARD;
  2791. if (mode64) {
  2792. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2793. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2794. cmdp->OpCode, cmdp->u.raw64.direction));
  2795. /* evaluate command size */
  2796. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2797. } else {
  2798. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2799. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2800. cmdp->OpCode, cmdp->u.raw.direction));
  2801. /* evaluate command size */
  2802. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2803. }
  2804. } else {
  2805. page = virt_to_page(scp->sense_buffer);
  2806. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2807. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2808. 16,PCI_DMA_FROMDEVICE);
  2809. *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
  2810. /* high part, if 64bit */
  2811. *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
  2812. cmdp->OpCode = GDT_WRITE; /* always */
  2813. cmdp->BoardNode = LOCALBOARD;
  2814. if (mode64) {
  2815. cmdp->u.raw64.reserved = 0;
  2816. cmdp->u.raw64.mdisc_time = 0;
  2817. cmdp->u.raw64.mcon_time = 0;
  2818. cmdp->u.raw64.clen = scp->cmd_len;
  2819. cmdp->u.raw64.target = t;
  2820. cmdp->u.raw64.lun = l;
  2821. cmdp->u.raw64.bus = b;
  2822. cmdp->u.raw64.priority = 0;
  2823. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2824. cmdp->u.raw64.sense_len = 16;
  2825. cmdp->u.raw64.sense_data = sense_paddr;
  2826. cmdp->u.raw64.direction =
  2827. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2828. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2829. cmdp->u.raw64.sg_ranz = 0;
  2830. } else {
  2831. cmdp->u.raw.reserved = 0;
  2832. cmdp->u.raw.mdisc_time = 0;
  2833. cmdp->u.raw.mcon_time = 0;
  2834. cmdp->u.raw.clen = scp->cmd_len;
  2835. cmdp->u.raw.target = t;
  2836. cmdp->u.raw.lun = l;
  2837. cmdp->u.raw.bus = b;
  2838. cmdp->u.raw.priority = 0;
  2839. cmdp->u.raw.link_p = 0;
  2840. cmdp->u.raw.sdlen = scp->request_bufflen;
  2841. cmdp->u.raw.sense_len = 16;
  2842. cmdp->u.raw.sense_data = sense_paddr;
  2843. cmdp->u.raw.direction =
  2844. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2845. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2846. cmdp->u.raw.sg_ranz = 0;
  2847. }
  2848. if (scp->use_sg) {
  2849. sl = (struct scatterlist *)scp->request_buffer;
  2850. sgcnt = scp->use_sg;
  2851. scp->SCp.Status = GDTH_MAP_SG;
  2852. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2853. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2854. if (mode64) {
  2855. cmdp->u.raw64.sdata = (ulong64)-1;
  2856. cmdp->u.raw64.sg_ranz = sgcnt;
  2857. for (i=0; i<sgcnt; ++i,++sl) {
  2858. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2859. #ifdef GDTH_DMA_STATISTICS
  2860. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2861. ha->dma64_cnt++;
  2862. else
  2863. ha->dma32_cnt++;
  2864. #endif
  2865. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2866. }
  2867. } else {
  2868. cmdp->u.raw.sdata = 0xffffffff;
  2869. cmdp->u.raw.sg_ranz = sgcnt;
  2870. for (i=0; i<sgcnt; ++i,++sl) {
  2871. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2872. #ifdef GDTH_DMA_STATISTICS
  2873. ha->dma32_cnt++;
  2874. #endif
  2875. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2876. }
  2877. }
  2878. #ifdef GDTH_STATISTICS
  2879. if (max_sg < sgcnt) {
  2880. max_sg = sgcnt;
  2881. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2882. }
  2883. #endif
  2884. } else if (scp->request_bufflen) {
  2885. scp->SCp.Status = GDTH_MAP_SINGLE;
  2886. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2887. page = virt_to_page(scp->request_buffer);
  2888. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2889. phys_addr = pci_map_page(ha->pdev,page,offset,
  2890. scp->request_bufflen,scp->SCp.Message);
  2891. scp->SCp.dma_handle = phys_addr;
  2892. if (mode64) {
  2893. if (ha->raw_feat & SCATTER_GATHER) {
  2894. cmdp->u.raw64.sdata = (ulong64)-1;
  2895. cmdp->u.raw64.sg_ranz= 1;
  2896. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2897. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2898. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2899. } else {
  2900. cmdp->u.raw64.sdata = phys_addr;
  2901. cmdp->u.raw64.sg_ranz= 0;
  2902. }
  2903. } else {
  2904. if (ha->raw_feat & SCATTER_GATHER) {
  2905. cmdp->u.raw.sdata = 0xffffffff;
  2906. cmdp->u.raw.sg_ranz= 1;
  2907. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2908. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2909. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2910. } else {
  2911. cmdp->u.raw.sdata = phys_addr;
  2912. cmdp->u.raw.sg_ranz= 0;
  2913. }
  2914. }
  2915. }
  2916. if (mode64) {
  2917. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2918. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2919. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2920. cmdp->u.raw64.sg_lst[0].sg_len));
  2921. /* evaluate command size */
  2922. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2923. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2924. } else {
  2925. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2926. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2927. cmdp->u.raw.sg_lst[0].sg_ptr,
  2928. cmdp->u.raw.sg_lst[0].sg_len));
  2929. /* evaluate command size */
  2930. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2931. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2932. }
  2933. }
  2934. /* check space */
  2935. if (ha->cmd_len & 3)
  2936. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2937. if (ha->cmd_cnt > 0) {
  2938. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2939. ha->ic_all_size) {
  2940. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2941. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2942. return 0;
  2943. }
  2944. }
  2945. /* copy command */
  2946. gdth_copy_command(hanum);
  2947. return cmd_index;
  2948. }
  2949. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
  2950. {
  2951. register gdth_ha_str *ha;
  2952. register gdth_cmd_str *cmdp;
  2953. int cmd_index;
  2954. ha = HADATA(gdth_ctr_tab[hanum]);
  2955. cmdp= ha->pccb;
  2956. TRACE2(("gdth_special_cmd(): "));
  2957. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2958. return 0;
  2959. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2960. cmdp->RequestBuffer = scp;
  2961. /* search free command index */
  2962. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2963. TRACE(("GDT: No free command index found\n"));
  2964. return 0;
  2965. }
  2966. /* if it's the first command, set command semaphore */
  2967. if (ha->cmd_cnt == 0)
  2968. gdth_set_sema0(hanum);
  2969. /* evaluate command size, check space */
  2970. if (cmdp->OpCode == GDT_IOCTL) {
  2971. TRACE2(("IOCTL\n"));
  2972. ha->cmd_len =
  2973. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2974. } else if (cmdp->Service == CACHESERVICE) {
  2975. TRACE2(("cache command %d\n",cmdp->OpCode));
  2976. if (ha->cache_feat & GDT_64BIT)
  2977. ha->cmd_len =
  2978. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2979. else
  2980. ha->cmd_len =
  2981. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2982. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2983. TRACE2(("raw command %d\n",cmdp->OpCode));
  2984. if (ha->raw_feat & GDT_64BIT)
  2985. ha->cmd_len =
  2986. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2987. else
  2988. ha->cmd_len =
  2989. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2990. }
  2991. if (ha->cmd_len & 3)
  2992. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2993. if (ha->cmd_cnt > 0) {
  2994. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2995. ha->ic_all_size) {
  2996. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2997. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2998. return 0;
  2999. }
  3000. }
  3001. /* copy command */
  3002. gdth_copy_command(hanum);
  3003. return cmd_index;
  3004. }
  3005. /* Controller event handling functions */
  3006. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  3007. ushort idx, gdth_evt_data *evt)
  3008. {
  3009. gdth_evt_str *e;
  3010. struct timeval tv;
  3011. /* no GDTH_LOCK_HA() ! */
  3012. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  3013. if (source == 0) /* no source -> no event */
  3014. return NULL;
  3015. if (ebuffer[elastidx].event_source == source &&
  3016. ebuffer[elastidx].event_idx == idx &&
  3017. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  3018. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  3019. (char *)&evt->eu, evt->size)) ||
  3020. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  3021. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  3022. (char *)&evt->event_string)))) {
  3023. e = &ebuffer[elastidx];
  3024. do_gettimeofday(&tv);
  3025. e->last_stamp = tv.tv_sec;
  3026. ++e->same_count;
  3027. } else {
  3028. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  3029. ++elastidx;
  3030. if (elastidx == MAX_EVENTS)
  3031. elastidx = 0;
  3032. if (elastidx == eoldidx) { /* reached mark ? */
  3033. ++eoldidx;
  3034. if (eoldidx == MAX_EVENTS)
  3035. eoldidx = 0;
  3036. }
  3037. }
  3038. e = &ebuffer[elastidx];
  3039. e->event_source = source;
  3040. e->event_idx = idx;
  3041. do_gettimeofday(&tv);
  3042. e->first_stamp = e->last_stamp = tv.tv_sec;
  3043. e->same_count = 1;
  3044. e->event_data = *evt;
  3045. e->application = 0;
  3046. }
  3047. return e;
  3048. }
  3049. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  3050. {
  3051. gdth_evt_str *e;
  3052. int eindex;
  3053. ulong flags;
  3054. TRACE2(("gdth_read_event() handle %d\n", handle));
  3055. spin_lock_irqsave(&ha->smp_lock, flags);
  3056. if (handle == -1)
  3057. eindex = eoldidx;
  3058. else
  3059. eindex = handle;
  3060. estr->event_source = 0;
  3061. if (eindex >= MAX_EVENTS) {
  3062. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3063. return eindex;
  3064. }
  3065. e = &ebuffer[eindex];
  3066. if (e->event_source != 0) {
  3067. if (eindex != elastidx) {
  3068. if (++eindex == MAX_EVENTS)
  3069. eindex = 0;
  3070. } else {
  3071. eindex = -1;
  3072. }
  3073. memcpy(estr, e, sizeof(gdth_evt_str));
  3074. }
  3075. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3076. return eindex;
  3077. }
  3078. static void gdth_readapp_event(gdth_ha_str *ha,
  3079. unchar application, gdth_evt_str *estr)
  3080. {
  3081. gdth_evt_str *e;
  3082. int eindex;
  3083. ulong flags;
  3084. unchar found = FALSE;
  3085. TRACE2(("gdth_readapp_event() app. %d\n", application));
  3086. spin_lock_irqsave(&ha->smp_lock, flags);
  3087. eindex = eoldidx;
  3088. for (;;) {
  3089. e = &ebuffer[eindex];
  3090. if (e->event_source == 0)
  3091. break;
  3092. if ((e->application & application) == 0) {
  3093. e->application |= application;
  3094. found = TRUE;
  3095. break;
  3096. }
  3097. if (eindex == elastidx)
  3098. break;
  3099. if (++eindex == MAX_EVENTS)
  3100. eindex = 0;
  3101. }
  3102. if (found)
  3103. memcpy(estr, e, sizeof(gdth_evt_str));
  3104. else
  3105. estr->event_source = 0;
  3106. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3107. }
  3108. static void gdth_clear_events(void)
  3109. {
  3110. TRACE(("gdth_clear_events()"));
  3111. eoldidx = elastidx = 0;
  3112. ebuffer[0].event_source = 0;
  3113. }
  3114. /* SCSI interface functions */
  3115. static irqreturn_t gdth_interrupt(int irq,void *dev_id)
  3116. {
  3117. gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
  3118. register gdth_ha_str *ha;
  3119. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  3120. gdt6_dpram_str __iomem *dp6_ptr;
  3121. gdt2_dpram_str __iomem *dp2_ptr;
  3122. Scsi_Cmnd *scp;
  3123. int hanum, rval, i;
  3124. unchar IStatus;
  3125. ushort Service;
  3126. ulong flags = 0;
  3127. #ifdef INT_COAL
  3128. int coalesced = FALSE;
  3129. int next = FALSE;
  3130. gdth_coal_status *pcs = NULL;
  3131. int act_int_coal = 0;
  3132. #endif
  3133. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  3134. /* if polling and not from gdth_wait() -> return */
  3135. if (gdth_polling) {
  3136. if (!gdth_from_wait) {
  3137. return IRQ_HANDLED;
  3138. }
  3139. }
  3140. if (!gdth_polling)
  3141. spin_lock_irqsave(&ha2->smp_lock, flags);
  3142. wait_index = 0;
  3143. /* search controller */
  3144. if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
  3145. /* spurious interrupt */
  3146. if (!gdth_polling)
  3147. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3148. return IRQ_HANDLED;
  3149. }
  3150. ha = HADATA(gdth_ctr_tab[hanum]);
  3151. #ifdef GDTH_STATISTICS
  3152. ++act_ints;
  3153. #endif
  3154. #ifdef INT_COAL
  3155. /* See if the fw is returning coalesced status */
  3156. if (IStatus == COALINDEX) {
  3157. /* Coalesced status. Setup the initial status
  3158. buffer pointer and flags */
  3159. pcs = ha->coal_stat;
  3160. coalesced = TRUE;
  3161. next = TRUE;
  3162. }
  3163. do {
  3164. if (coalesced) {
  3165. /* For coalesced requests all status
  3166. information is found in the status buffer */
  3167. IStatus = (unchar)(pcs->status & 0xff);
  3168. }
  3169. #endif
  3170. if (ha->type == GDT_EISA) {
  3171. if (IStatus & 0x80) { /* error flag */
  3172. IStatus &= ~0x80;
  3173. ha->status = inw(ha->bmic + MAILBOXREG+8);
  3174. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3175. } else /* no error */
  3176. ha->status = S_OK;
  3177. ha->info = inl(ha->bmic + MAILBOXREG+12);
  3178. ha->service = inw(ha->bmic + MAILBOXREG+10);
  3179. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  3180. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  3181. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  3182. } else if (ha->type == GDT_ISA) {
  3183. dp2_ptr = ha->brd;
  3184. if (IStatus & 0x80) { /* error flag */
  3185. IStatus &= ~0x80;
  3186. ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
  3187. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3188. } else /* no error */
  3189. ha->status = S_OK;
  3190. ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
  3191. ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
  3192. ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
  3193. gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  3194. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  3195. gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  3196. } else if (ha->type == GDT_PCI) {
  3197. dp6_ptr = ha->brd;
  3198. if (IStatus & 0x80) { /* error flag */
  3199. IStatus &= ~0x80;
  3200. ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
  3201. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3202. } else /* no error */
  3203. ha->status = S_OK;
  3204. ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
  3205. ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
  3206. ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
  3207. gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  3208. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  3209. gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  3210. } else if (ha->type == GDT_PCINEW) {
  3211. if (IStatus & 0x80) { /* error flag */
  3212. IStatus &= ~0x80;
  3213. ha->status = inw(PTR2USHORT(&ha->plx->status));
  3214. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3215. } else
  3216. ha->status = S_OK;
  3217. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  3218. ha->service = inw(PTR2USHORT(&ha->plx->service));
  3219. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  3220. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  3221. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  3222. } else if (ha->type == GDT_PCIMPR) {
  3223. dp6m_ptr = ha->brd;
  3224. if (IStatus & 0x80) { /* error flag */
  3225. IStatus &= ~0x80;
  3226. #ifdef INT_COAL
  3227. if (coalesced)
  3228. ha->status = pcs->ext_status & 0xffff;
  3229. else
  3230. #endif
  3231. ha->status = gdth_readw(&dp6m_ptr->i960r.status);
  3232. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3233. } else /* no error */
  3234. ha->status = S_OK;
  3235. #ifdef INT_COAL
  3236. /* get information */
  3237. if (coalesced) {
  3238. ha->info = pcs->info0;
  3239. ha->info2 = pcs->info1;
  3240. ha->service = (pcs->ext_status >> 16) & 0xffff;
  3241. } else
  3242. #endif
  3243. {
  3244. ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
  3245. ha->service = gdth_readw(&dp6m_ptr->i960r.service);
  3246. ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
  3247. }
  3248. /* event string */
  3249. if (IStatus == ASYNCINDEX) {
  3250. if (ha->service != SCREENSERVICE &&
  3251. (ha->fw_vers & 0xff) >= 0x1a) {
  3252. ha->dvr.severity = gdth_readb
  3253. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  3254. for (i = 0; i < 256; ++i) {
  3255. ha->dvr.event_string[i] = gdth_readb
  3256. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  3257. if (ha->dvr.event_string[i] == 0)
  3258. break;
  3259. }
  3260. }
  3261. }
  3262. #ifdef INT_COAL
  3263. /* Make sure that non coalesced interrupts get cleared
  3264. before being handled by gdth_async_event/gdth_sync_event */
  3265. if (!coalesced)
  3266. #endif
  3267. {
  3268. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3269. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3270. }
  3271. } else {
  3272. TRACE2(("gdth_interrupt() unknown controller type\n"));
  3273. if (!gdth_polling)
  3274. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3275. return IRQ_HANDLED;
  3276. }
  3277. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  3278. IStatus,ha->status,ha->info));
  3279. if (gdth_from_wait) {
  3280. wait_hanum = hanum;
  3281. wait_index = (int)IStatus;
  3282. }
  3283. if (IStatus == ASYNCINDEX) {
  3284. TRACE2(("gdth_interrupt() async. event\n"));
  3285. gdth_async_event(hanum);
  3286. if (!gdth_polling)
  3287. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3288. gdth_next(hanum);
  3289. return IRQ_HANDLED;
  3290. }
  3291. if (IStatus == SPEZINDEX) {
  3292. TRACE2(("Service unknown or not initialized !\n"));
  3293. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3294. ha->dvr.eu.driver.ionode = hanum;
  3295. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  3296. if (!gdth_polling)
  3297. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3298. return IRQ_HANDLED;
  3299. }
  3300. scp = ha->cmd_tab[IStatus-2].cmnd;
  3301. Service = ha->cmd_tab[IStatus-2].service;
  3302. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  3303. if (scp == UNUSED_CMND) {
  3304. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  3305. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3306. ha->dvr.eu.driver.ionode = hanum;
  3307. ha->dvr.eu.driver.index = IStatus;
  3308. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  3309. if (!gdth_polling)
  3310. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3311. return IRQ_HANDLED;
  3312. }
  3313. if (scp == INTERNAL_CMND) {
  3314. TRACE(("gdth_interrupt() answer to internal command\n"));
  3315. if (!gdth_polling)
  3316. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3317. return IRQ_HANDLED;
  3318. }
  3319. TRACE(("gdth_interrupt() sync. status\n"));
  3320. rval = gdth_sync_event(hanum,Service,IStatus,scp);
  3321. if (!gdth_polling)
  3322. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3323. if (rval == 2) {
  3324. gdth_putq(hanum,scp,scp->SCp.this_residual);
  3325. } else if (rval == 1) {
  3326. scp->scsi_done(scp);
  3327. }
  3328. #ifdef INT_COAL
  3329. if (coalesced) {
  3330. /* go to the next status in the status buffer */
  3331. ++pcs;
  3332. #ifdef GDTH_STATISTICS
  3333. ++act_int_coal;
  3334. if (act_int_coal > max_int_coal) {
  3335. max_int_coal = act_int_coal;
  3336. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  3337. }
  3338. #endif
  3339. /* see if there is another status */
  3340. if (pcs->status == 0)
  3341. /* Stop the coalesce loop */
  3342. next = FALSE;
  3343. }
  3344. } while (next);
  3345. /* coalescing only for new GDT_PCIMPR controllers available */
  3346. if (ha->type == GDT_PCIMPR && coalesced) {
  3347. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3348. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3349. }
  3350. #endif
  3351. gdth_next(hanum);
  3352. return IRQ_HANDLED;
  3353. }
  3354. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
  3355. {
  3356. register gdth_ha_str *ha;
  3357. gdth_msg_str *msg;
  3358. gdth_cmd_str *cmdp;
  3359. unchar b, t;
  3360. ha = HADATA(gdth_ctr_tab[hanum]);
  3361. cmdp = ha->pccb;
  3362. TRACE(("gdth_sync_event() serv %d status %d\n",
  3363. service,ha->status));
  3364. if (service == SCREENSERVICE) {
  3365. msg = ha->pmsg;
  3366. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  3367. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  3368. if (msg->msg_len > MSGLEN+1)
  3369. msg->msg_len = MSGLEN+1;
  3370. if (msg->msg_len)
  3371. if (!(msg->msg_answer && msg->msg_ext)) {
  3372. msg->msg_text[msg->msg_len] = '\0';
  3373. printk("%s",msg->msg_text);
  3374. }
  3375. if (msg->msg_ext && !msg->msg_answer) {
  3376. while (gdth_test_busy(hanum))
  3377. gdth_delay(0);
  3378. cmdp->Service = SCREENSERVICE;
  3379. cmdp->RequestBuffer = SCREEN_CMND;
  3380. gdth_get_cmd_index(hanum);
  3381. gdth_set_sema0(hanum);
  3382. cmdp->OpCode = GDT_READ;
  3383. cmdp->BoardNode = LOCALBOARD;
  3384. cmdp->u.screen.reserved = 0;
  3385. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3386. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3387. ha->cmd_offs_dpmem = 0;
  3388. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3389. + sizeof(ulong64);
  3390. ha->cmd_cnt = 0;
  3391. gdth_copy_command(hanum);
  3392. gdth_release_event(hanum);
  3393. return 0;
  3394. }
  3395. if (msg->msg_answer && msg->msg_alen) {
  3396. /* default answers (getchar() not possible) */
  3397. if (msg->msg_alen == 1) {
  3398. msg->msg_alen = 0;
  3399. msg->msg_len = 1;
  3400. msg->msg_text[0] = 0;
  3401. } else {
  3402. msg->msg_alen -= 2;
  3403. msg->msg_len = 2;
  3404. msg->msg_text[0] = 1;
  3405. msg->msg_text[1] = 0;
  3406. }
  3407. msg->msg_ext = 0;
  3408. msg->msg_answer = 0;
  3409. while (gdth_test_busy(hanum))
  3410. gdth_delay(0);
  3411. cmdp->Service = SCREENSERVICE;
  3412. cmdp->RequestBuffer = SCREEN_CMND;
  3413. gdth_get_cmd_index(hanum);
  3414. gdth_set_sema0(hanum);
  3415. cmdp->OpCode = GDT_WRITE;
  3416. cmdp->BoardNode = LOCALBOARD;
  3417. cmdp->u.screen.reserved = 0;
  3418. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3419. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3420. ha->cmd_offs_dpmem = 0;
  3421. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3422. + sizeof(ulong64);
  3423. ha->cmd_cnt = 0;
  3424. gdth_copy_command(hanum);
  3425. gdth_release_event(hanum);
  3426. return 0;
  3427. }
  3428. printk("\n");
  3429. } else {
  3430. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  3431. t = scp->device->id;
  3432. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3433. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3434. }
  3435. /* cache or raw service */
  3436. if (ha->status == S_BSY) {
  3437. TRACE2(("Controller busy -> retry !\n"));
  3438. if (scp->SCp.sent_command == GDT_MOUNT)
  3439. scp->SCp.sent_command = GDT_CLUST_INFO;
  3440. /* retry */
  3441. return 2;
  3442. }
  3443. if (scp->SCp.Status == GDTH_MAP_SG)
  3444. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3445. scp->use_sg,scp->SCp.Message);
  3446. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3447. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3448. scp->request_bufflen,scp->SCp.Message);
  3449. if (scp->SCp.buffer) {
  3450. dma_addr_t addr;
  3451. addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
  3452. if (scp->host_scribble)
  3453. addr += (dma_addr_t)
  3454. ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
  3455. pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
  3456. }
  3457. if (ha->status == S_OK) {
  3458. scp->SCp.Status = S_OK;
  3459. scp->SCp.Message = ha->info;
  3460. if (scp->SCp.sent_command != -1) {
  3461. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3462. scp->SCp.sent_command));
  3463. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3464. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3465. ha->hdr[t].cluster_type = (unchar)ha->info;
  3466. if (!(ha->hdr[t].cluster_type &
  3467. CLUSTER_MOUNTED)) {
  3468. /* NOT MOUNTED -> MOUNT */
  3469. scp->SCp.sent_command = GDT_MOUNT;
  3470. if (ha->hdr[t].cluster_type &
  3471. CLUSTER_RESERVED) {
  3472. /* cluster drive RESERVED (on the other node) */
  3473. scp->SCp.phase = -2; /* reservation conflict */
  3474. }
  3475. } else {
  3476. scp->SCp.sent_command = -1;
  3477. }
  3478. } else {
  3479. if (scp->SCp.sent_command == GDT_MOUNT) {
  3480. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3481. ha->hdr[t].media_changed = TRUE;
  3482. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3483. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3484. ha->hdr[t].media_changed = TRUE;
  3485. }
  3486. scp->SCp.sent_command = -1;
  3487. }
  3488. /* retry */
  3489. scp->SCp.this_residual = HIGH_PRI;
  3490. return 2;
  3491. } else {
  3492. /* RESERVE/RELEASE ? */
  3493. if (scp->cmnd[0] == RESERVE) {
  3494. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3495. } else if (scp->cmnd[0] == RELEASE) {
  3496. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3497. }
  3498. scp->result = DID_OK << 16;
  3499. scp->sense_buffer[0] = 0;
  3500. }
  3501. } else {
  3502. scp->SCp.Status = ha->status;
  3503. scp->SCp.Message = ha->info;
  3504. if (scp->SCp.sent_command != -1) {
  3505. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3506. scp->SCp.sent_command, ha->status));
  3507. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3508. scp->SCp.sent_command == GDT_SCAN_END) {
  3509. scp->SCp.sent_command = -1;
  3510. /* retry */
  3511. scp->SCp.this_residual = HIGH_PRI;
  3512. return 2;
  3513. }
  3514. memset((char*)scp->sense_buffer,0,16);
  3515. scp->sense_buffer[0] = 0x70;
  3516. scp->sense_buffer[2] = NOT_READY;
  3517. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3518. } else if (service == CACHESERVICE) {
  3519. if (ha->status == S_CACHE_UNKNOWN &&
  3520. (ha->hdr[t].cluster_type &
  3521. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3522. /* bus reset -> force GDT_CLUST_INFO */
  3523. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3524. }
  3525. memset((char*)scp->sense_buffer,0,16);
  3526. if (ha->status == (ushort)S_CACHE_RESERV) {
  3527. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3528. } else {
  3529. scp->sense_buffer[0] = 0x70;
  3530. scp->sense_buffer[2] = NOT_READY;
  3531. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3532. }
  3533. if (scp->done != gdth_scsi_done) {
  3534. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3535. ha->dvr.eu.sync.ionode = hanum;
  3536. ha->dvr.eu.sync.service = service;
  3537. ha->dvr.eu.sync.status = ha->status;
  3538. ha->dvr.eu.sync.info = ha->info;
  3539. ha->dvr.eu.sync.hostdrive = t;
  3540. if (ha->status >= 0x8000)
  3541. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3542. else
  3543. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3544. }
  3545. } else {
  3546. /* sense buffer filled from controller firmware (DMA) */
  3547. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3548. scp->result = DID_BAD_TARGET << 16;
  3549. } else {
  3550. scp->result = (DID_OK << 16) | ha->info;
  3551. }
  3552. }
  3553. }
  3554. if (!scp->SCp.have_data_in)
  3555. scp->SCp.have_data_in++;
  3556. else
  3557. return 1;
  3558. }
  3559. return 0;
  3560. }
  3561. static char *async_cache_tab[] = {
  3562. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3563. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3564. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3565. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3566. /* 2*/ "\005\000\002\006\004"
  3567. "GDT HA %u, Host Drive %lu not ready",
  3568. /* 3*/ "\005\000\002\006\004"
  3569. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3570. /* 4*/ "\005\000\002\006\004"
  3571. "GDT HA %u, mirror update on Host Drive %lu failed",
  3572. /* 5*/ "\005\000\002\006\004"
  3573. "GDT HA %u, Mirror Drive %lu failed",
  3574. /* 6*/ "\005\000\002\006\004"
  3575. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3576. /* 7*/ "\005\000\002\006\004"
  3577. "GDT HA %u, Host Drive %lu write protected",
  3578. /* 8*/ "\005\000\002\006\004"
  3579. "GDT HA %u, media changed in Host Drive %lu",
  3580. /* 9*/ "\005\000\002\006\004"
  3581. "GDT HA %u, Host Drive %lu is offline",
  3582. /*10*/ "\005\000\002\006\004"
  3583. "GDT HA %u, media change of Mirror Drive %lu",
  3584. /*11*/ "\005\000\002\006\004"
  3585. "GDT HA %u, Mirror Drive %lu is write protected",
  3586. /*12*/ "\005\000\002\006\004"
  3587. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3588. /*13*/ "\007\000\002\006\002\010\002"
  3589. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3590. /*14*/ "\005\000\002\006\002"
  3591. "GDT HA %u, Array Drive %u: FAIL state entered",
  3592. /*15*/ "\005\000\002\006\002"
  3593. "GDT HA %u, Array Drive %u: error",
  3594. /*16*/ "\007\000\002\006\002\010\002"
  3595. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3596. /*17*/ "\005\000\002\006\002"
  3597. "GDT HA %u, Array Drive %u: parity build failed",
  3598. /*18*/ "\005\000\002\006\002"
  3599. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3600. /*19*/ "\005\000\002\010\002"
  3601. "GDT HA %u, Test of Hot Fix %u failed",
  3602. /*20*/ "\005\000\002\006\002"
  3603. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3604. /*21*/ "\005\000\002\006\002"
  3605. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3606. /*22*/ "\007\000\002\006\002\010\002"
  3607. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3608. /*23*/ "\005\000\002\006\002"
  3609. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3610. /*24*/ "\005\000\002\010\002"
  3611. "GDT HA %u, mirror update on Cache Drive %u completed",
  3612. /*25*/ "\005\000\002\010\002"
  3613. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3614. /*26*/ "\005\000\002\006\002"
  3615. "GDT HA %u, Array Drive %u: drive rebuild started",
  3616. /*27*/ "\005\000\002\012\001"
  3617. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3618. /*28*/ "\005\000\002\012\001"
  3619. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3620. /*29*/ "\007\000\002\012\001\013\001"
  3621. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3622. /*30*/ "\007\000\002\012\001\013\001"
  3623. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3624. /*31*/ "\007\000\002\012\001\013\001"
  3625. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3626. /*32*/ "\007\000\002\012\001\013\001"
  3627. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3628. /*33*/ "\007\000\002\012\001\013\001"
  3629. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3630. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3631. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3632. /*35*/ "\007\000\002\012\001\013\001"
  3633. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3634. /*36*/ "\007\000\002\012\001\013\001"
  3635. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3636. /*37*/ "\007\000\002\012\001\006\004"
  3637. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3638. /*38*/ "\007\000\002\012\001\013\001"
  3639. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3640. /*39*/ "\007\000\002\012\001\013\001"
  3641. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3642. /*40*/ "\007\000\002\012\001\013\001"
  3643. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3644. /*41*/ "\007\000\002\012\001\013\001"
  3645. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3646. /*42*/ "\005\000\002\006\002"
  3647. "GDT HA %u, Array Drive %u: drive build started",
  3648. /*43*/ "\003\000\002"
  3649. "GDT HA %u, DRAM parity error detected",
  3650. /*44*/ "\005\000\002\006\002"
  3651. "GDT HA %u, Mirror Drive %u: update started",
  3652. /*45*/ "\007\000\002\006\002\010\002"
  3653. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3654. /*46*/ "\005\000\002\006\002"
  3655. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3656. /*47*/ "\005\000\002\006\002"
  3657. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3658. /*48*/ "\005\000\002\006\002"
  3659. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3660. /*49*/ "\005\000\002\006\002"
  3661. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3662. /*50*/ "\007\000\002\012\001\013\001"
  3663. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3664. /*51*/ "\005\000\002\006\002"
  3665. "GDT HA %u, Array Drive %u: expand started",
  3666. /*52*/ "\005\000\002\006\002"
  3667. "GDT HA %u, Array Drive %u: expand finished successfully",
  3668. /*53*/ "\005\000\002\006\002"
  3669. "GDT HA %u, Array Drive %u: expand failed",
  3670. /*54*/ "\003\000\002"
  3671. "GDT HA %u, CPU temperature critical",
  3672. /*55*/ "\003\000\002"
  3673. "GDT HA %u, CPU temperature OK",
  3674. /*56*/ "\005\000\002\006\004"
  3675. "GDT HA %u, Host drive %lu created",
  3676. /*57*/ "\005\000\002\006\002"
  3677. "GDT HA %u, Array Drive %u: expand restarted",
  3678. /*58*/ "\005\000\002\006\002"
  3679. "GDT HA %u, Array Drive %u: expand stopped",
  3680. /*59*/ "\005\000\002\010\002"
  3681. "GDT HA %u, Mirror Drive %u: drive build quited",
  3682. /*60*/ "\005\000\002\006\002"
  3683. "GDT HA %u, Array Drive %u: parity build quited",
  3684. /*61*/ "\005\000\002\006\002"
  3685. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3686. /*62*/ "\005\000\002\006\002"
  3687. "GDT HA %u, Array Drive %u: parity verify started",
  3688. /*63*/ "\005\000\002\006\002"
  3689. "GDT HA %u, Array Drive %u: parity verify done",
  3690. /*64*/ "\005\000\002\006\002"
  3691. "GDT HA %u, Array Drive %u: parity verify failed",
  3692. /*65*/ "\005\000\002\006\002"
  3693. "GDT HA %u, Array Drive %u: parity error detected",
  3694. /*66*/ "\005\000\002\006\002"
  3695. "GDT HA %u, Array Drive %u: parity verify quited",
  3696. /*67*/ "\005\000\002\006\002"
  3697. "GDT HA %u, Host Drive %u reserved",
  3698. /*68*/ "\005\000\002\006\002"
  3699. "GDT HA %u, Host Drive %u mounted and released",
  3700. /*69*/ "\005\000\002\006\002"
  3701. "GDT HA %u, Host Drive %u released",
  3702. /*70*/ "\003\000\002"
  3703. "GDT HA %u, DRAM error detected and corrected with ECC",
  3704. /*71*/ "\003\000\002"
  3705. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3706. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3707. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3708. /*73*/ "\005\000\002\006\002"
  3709. "GDT HA %u, Host drive %u resetted locally",
  3710. /*74*/ "\005\000\002\006\002"
  3711. "GDT HA %u, Host drive %u resetted remotely",
  3712. /*75*/ "\003\000\002"
  3713. "GDT HA %u, async. status 75 unknown",
  3714. };
  3715. static int gdth_async_event(int hanum)
  3716. {
  3717. gdth_ha_str *ha;
  3718. gdth_cmd_str *cmdp;
  3719. int cmd_index;
  3720. ha = HADATA(gdth_ctr_tab[hanum]);
  3721. cmdp= ha->pccb;
  3722. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3723. hanum,ha->service));
  3724. if (ha->service == SCREENSERVICE) {
  3725. if (ha->status == MSG_REQUEST) {
  3726. while (gdth_test_busy(hanum))
  3727. gdth_delay(0);
  3728. cmdp->Service = SCREENSERVICE;
  3729. cmdp->RequestBuffer = SCREEN_CMND;
  3730. cmd_index = gdth_get_cmd_index(hanum);
  3731. gdth_set_sema0(hanum);
  3732. cmdp->OpCode = GDT_READ;
  3733. cmdp->BoardNode = LOCALBOARD;
  3734. cmdp->u.screen.reserved = 0;
  3735. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3736. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3737. ha->cmd_offs_dpmem = 0;
  3738. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3739. + sizeof(ulong64);
  3740. ha->cmd_cnt = 0;
  3741. gdth_copy_command(hanum);
  3742. if (ha->type == GDT_EISA)
  3743. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3744. else if (ha->type == GDT_ISA)
  3745. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3746. else
  3747. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3748. (ushort)((ha->brd_phys>>3)&0x1f));
  3749. gdth_release_event(hanum);
  3750. }
  3751. } else {
  3752. if (ha->type == GDT_PCIMPR &&
  3753. (ha->fw_vers & 0xff) >= 0x1a) {
  3754. ha->dvr.size = 0;
  3755. ha->dvr.eu.async.ionode = hanum;
  3756. ha->dvr.eu.async.status = ha->status;
  3757. /* severity and event_string already set! */
  3758. } else {
  3759. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3760. ha->dvr.eu.async.ionode = hanum;
  3761. ha->dvr.eu.async.service = ha->service;
  3762. ha->dvr.eu.async.status = ha->status;
  3763. ha->dvr.eu.async.info = ha->info;
  3764. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3765. }
  3766. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3767. gdth_log_event( &ha->dvr, NULL );
  3768. /* new host drive from expand? */
  3769. if (ha->service == CACHESERVICE && ha->status == 56) {
  3770. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3771. (ushort)ha->info));
  3772. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3773. }
  3774. }
  3775. return 1;
  3776. }
  3777. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3778. {
  3779. gdth_stackframe stack;
  3780. char *f = NULL;
  3781. int i,j;
  3782. TRACE2(("gdth_log_event()\n"));
  3783. if (dvr->size == 0) {
  3784. if (buffer == NULL) {
  3785. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3786. } else {
  3787. sprintf(buffer,"Adapter %d: %s\n",
  3788. dvr->eu.async.ionode,dvr->event_string);
  3789. }
  3790. } else if (dvr->eu.async.service == CACHESERVICE &&
  3791. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3792. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3793. dvr->eu.async.status));
  3794. f = async_cache_tab[dvr->eu.async.status];
  3795. /* i: parameter to push, j: stack element to fill */
  3796. for (j=0,i=1; i < f[0]; i+=2) {
  3797. switch (f[i+1]) {
  3798. case 4:
  3799. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3800. break;
  3801. case 2:
  3802. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3803. break;
  3804. case 1:
  3805. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3806. break;
  3807. default:
  3808. break;
  3809. }
  3810. }
  3811. if (buffer == NULL) {
  3812. printk(&f[(int)f[0]],stack);
  3813. printk("\n");
  3814. } else {
  3815. sprintf(buffer,&f[(int)f[0]],stack);
  3816. }
  3817. } else {
  3818. if (buffer == NULL) {
  3819. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3820. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3821. } else {
  3822. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3823. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3824. }
  3825. }
  3826. }
  3827. #ifdef GDTH_STATISTICS
  3828. static void gdth_timeout(ulong data)
  3829. {
  3830. ulong32 i;
  3831. Scsi_Cmnd *nscp;
  3832. gdth_ha_str *ha;
  3833. ulong flags;
  3834. int hanum = 0;
  3835. ha = HADATA(gdth_ctr_tab[hanum]);
  3836. spin_lock_irqsave(&ha->smp_lock, flags);
  3837. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3838. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3839. ++act_stats;
  3840. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3841. ++act_rq;
  3842. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3843. act_ints, act_ios, act_stats, act_rq));
  3844. act_ints = act_ios = 0;
  3845. gdth_timer.expires = jiffies + 30 * HZ;
  3846. add_timer(&gdth_timer);
  3847. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3848. }
  3849. #endif
  3850. static void __init internal_setup(char *str,int *ints)
  3851. {
  3852. int i, argc;
  3853. char *cur_str, *argv;
  3854. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3855. str ? str:"NULL", ints ? ints[0]:0));
  3856. /* read irq[] from ints[] */
  3857. if (ints) {
  3858. argc = ints[0];
  3859. if (argc > 0) {
  3860. if (argc > MAXHA)
  3861. argc = MAXHA;
  3862. for (i = 0; i < argc; ++i)
  3863. irq[i] = ints[i+1];
  3864. }
  3865. }
  3866. /* analyse string */
  3867. argv = str;
  3868. while (argv && (cur_str = strchr(argv, ':'))) {
  3869. int val = 0, c = *++cur_str;
  3870. if (c == 'n' || c == 'N')
  3871. val = 0;
  3872. else if (c == 'y' || c == 'Y')
  3873. val = 1;
  3874. else
  3875. val = (int)simple_strtoul(cur_str, NULL, 0);
  3876. if (!strncmp(argv, "disable:", 8))
  3877. disable = val;
  3878. else if (!strncmp(argv, "reserve_mode:", 13))
  3879. reserve_mode = val;
  3880. else if (!strncmp(argv, "reverse_scan:", 13))
  3881. reverse_scan = val;
  3882. else if (!strncmp(argv, "hdr_channel:", 12))
  3883. hdr_channel = val;
  3884. else if (!strncmp(argv, "max_ids:", 8))
  3885. max_ids = val;
  3886. else if (!strncmp(argv, "rescan:", 7))
  3887. rescan = val;
  3888. else if (!strncmp(argv, "virt_ctr:", 9))
  3889. virt_ctr = val;
  3890. else if (!strncmp(argv, "shared_access:", 14))
  3891. shared_access = val;
  3892. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3893. probe_eisa_isa = val;
  3894. else if (!strncmp(argv, "reserve_list:", 13)) {
  3895. reserve_list[0] = val;
  3896. for (i = 1; i < MAX_RES_ARGS; i++) {
  3897. cur_str = strchr(cur_str, ',');
  3898. if (!cur_str)
  3899. break;
  3900. if (!isdigit((int)*++cur_str)) {
  3901. --cur_str;
  3902. break;
  3903. }
  3904. reserve_list[i] =
  3905. (int)simple_strtoul(cur_str, NULL, 0);
  3906. }
  3907. if (!cur_str)
  3908. break;
  3909. argv = ++cur_str;
  3910. continue;
  3911. }
  3912. if ((argv = strchr(argv, ',')))
  3913. ++argv;
  3914. }
  3915. }
  3916. int __init option_setup(char *str)
  3917. {
  3918. int ints[MAXHA];
  3919. char *cur = str;
  3920. int i = 1;
  3921. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3922. while (cur && isdigit(*cur) && i <= MAXHA) {
  3923. ints[i++] = simple_strtoul(cur, NULL, 0);
  3924. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3925. }
  3926. ints[0] = i - 1;
  3927. internal_setup(cur, ints);
  3928. return 1;
  3929. }
  3930. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  3931. static int __init gdth_detect(struct scsi_host_template *shtp)
  3932. #else
  3933. static int __init gdth_detect(Scsi_Host_Template *shtp)
  3934. #endif
  3935. {
  3936. struct Scsi_Host *shp;
  3937. gdth_pci_str pcistr[MAXHA];
  3938. gdth_ha_str *ha;
  3939. ulong32 isa_bios;
  3940. ushort eisa_slot;
  3941. int i,hanum,cnt,ctr,err;
  3942. unchar b;
  3943. #ifdef DEBUG_GDTH
  3944. printk("GDT: This driver contains debugging information !! Trace level = %d\n",
  3945. DebugState);
  3946. printk(" Destination of debugging information: ");
  3947. #ifdef __SERIAL__
  3948. #ifdef __COM2__
  3949. printk("Serial port COM2\n");
  3950. #else
  3951. printk("Serial port COM1\n");
  3952. #endif
  3953. #else
  3954. printk("Console\n");
  3955. #endif
  3956. gdth_delay(3000);
  3957. #endif
  3958. TRACE(("gdth_detect()\n"));
  3959. if (disable) {
  3960. printk("GDT-HA: Controller driver disabled from command line !\n");
  3961. return 0;
  3962. }
  3963. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
  3964. /* initializations */
  3965. gdth_polling = TRUE; b = 0;
  3966. gdth_clear_events();
  3967. /* As default we do not probe for EISA or ISA controllers */
  3968. if (probe_eisa_isa) {
  3969. /* scanning for controllers, at first: ISA controller */
  3970. for (isa_bios=0xc8000UL; isa_bios<=0xd8000UL; isa_bios+=0x8000UL) {
  3971. dma_addr_t scratch_dma_handle;
  3972. scratch_dma_handle = 0;
  3973. if (gdth_ctr_count >= MAXHA)
  3974. break;
  3975. if (gdth_search_isa(isa_bios)) { /* controller found */
  3976. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  3977. if (shp == NULL)
  3978. continue;
  3979. ha = HADATA(shp);
  3980. if (!gdth_init_isa(isa_bios,ha)) {
  3981. scsi_unregister(shp);
  3982. continue;
  3983. }
  3984. #ifdef __ia64__
  3985. break;
  3986. #else
  3987. /* controller found and initialized */
  3988. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  3989. isa_bios,ha->irq,ha->drq);
  3990. if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
  3991. printk("GDT-ISA: Unable to allocate IRQ\n");
  3992. scsi_unregister(shp);
  3993. continue;
  3994. }
  3995. if (request_dma(ha->drq,"gdth")) {
  3996. printk("GDT-ISA: Unable to allocate DMA channel\n");
  3997. free_irq(ha->irq,ha);
  3998. scsi_unregister(shp);
  3999. continue;
  4000. }
  4001. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4002. enable_dma(ha->drq);
  4003. shp->unchecked_isa_dma = 1;
  4004. shp->irq = ha->irq;
  4005. shp->dma_channel = ha->drq;
  4006. hanum = gdth_ctr_count;
  4007. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4008. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4009. NUMDATA(shp)->hanum = (ushort)hanum;
  4010. NUMDATA(shp)->busnum= 0;
  4011. ha->pccb = CMDDATA(shp);
  4012. ha->ccb_phys = 0L;
  4013. ha->pdev = NULL;
  4014. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4015. &scratch_dma_handle);
  4016. ha->scratch_phys = scratch_dma_handle;
  4017. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4018. &scratch_dma_handle);
  4019. ha->msg_phys = scratch_dma_handle;
  4020. #ifdef INT_COAL
  4021. ha->coal_stat = (gdth_coal_status *)
  4022. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4023. MAXOFFSETS, &scratch_dma_handle);
  4024. ha->coal_stat_phys = scratch_dma_handle;
  4025. #endif
  4026. ha->scratch_busy = FALSE;
  4027. ha->req_first = NULL;
  4028. ha->tid_cnt = MAX_HDRIVES;
  4029. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4030. ha->tid_cnt = max_ids;
  4031. for (i=0; i<GDTH_MAXCMDS; ++i)
  4032. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4033. ha->scan_mode = rescan ? 0x10 : 0;
  4034. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4035. !gdth_search_drives(hanum)) {
  4036. printk("GDT-ISA: Error during device scan\n");
  4037. --gdth_ctr_count;
  4038. --gdth_ctr_vcount;
  4039. #ifdef INT_COAL
  4040. if (ha->coal_stat)
  4041. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4042. MAXOFFSETS, ha->coal_stat,
  4043. ha->coal_stat_phys);
  4044. #endif
  4045. if (ha->pscratch)
  4046. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4047. ha->pscratch, ha->scratch_phys);
  4048. if (ha->pmsg)
  4049. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4050. ha->pmsg, ha->msg_phys);
  4051. free_irq(ha->irq,ha);
  4052. scsi_unregister(shp);
  4053. continue;
  4054. }
  4055. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4056. hdr_channel = ha->bus_cnt;
  4057. ha->virt_bus = hdr_channel;
  4058. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  4059. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4060. shp->highmem_io = 0;
  4061. #endif
  4062. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4063. shp->max_cmd_len = 16;
  4064. shp->max_id = ha->tid_cnt;
  4065. shp->max_lun = MAXLUN;
  4066. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4067. if (virt_ctr) {
  4068. virt_ctr = 1;
  4069. /* register addit. SCSI channels as virtual controllers */
  4070. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4071. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4072. shp->unchecked_isa_dma = 1;
  4073. shp->irq = ha->irq;
  4074. shp->dma_channel = ha->drq;
  4075. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4076. NUMDATA(shp)->hanum = (ushort)hanum;
  4077. NUMDATA(shp)->busnum = b;
  4078. }
  4079. }
  4080. spin_lock_init(&ha->smp_lock);
  4081. gdth_enable_int(hanum);
  4082. #endif /* !__ia64__ */
  4083. }
  4084. }
  4085. /* scanning for EISA controllers */
  4086. for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
  4087. dma_addr_t scratch_dma_handle;
  4088. scratch_dma_handle = 0;
  4089. if (gdth_ctr_count >= MAXHA)
  4090. break;
  4091. if (gdth_search_eisa(eisa_slot)) { /* controller found */
  4092. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4093. if (shp == NULL)
  4094. continue;
  4095. ha = HADATA(shp);
  4096. if (!gdth_init_eisa(eisa_slot,ha)) {
  4097. scsi_unregister(shp);
  4098. continue;
  4099. }
  4100. /* controller found and initialized */
  4101. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4102. eisa_slot>>12,ha->irq);
  4103. if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
  4104. printk("GDT-EISA: Unable to allocate IRQ\n");
  4105. scsi_unregister(shp);
  4106. continue;
  4107. }
  4108. shp->unchecked_isa_dma = 0;
  4109. shp->irq = ha->irq;
  4110. shp->dma_channel = 0xff;
  4111. hanum = gdth_ctr_count;
  4112. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4113. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4114. NUMDATA(shp)->hanum = (ushort)hanum;
  4115. NUMDATA(shp)->busnum= 0;
  4116. TRACE2(("EISA detect Bus 0: hanum %d\n",
  4117. NUMDATA(shp)->hanum));
  4118. ha->pccb = CMDDATA(shp);
  4119. ha->ccb_phys = 0L;
  4120. ha->pdev = NULL;
  4121. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4122. &scratch_dma_handle);
  4123. ha->scratch_phys = scratch_dma_handle;
  4124. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4125. &scratch_dma_handle);
  4126. ha->msg_phys = scratch_dma_handle;
  4127. #ifdef INT_COAL
  4128. ha->coal_stat = (gdth_coal_status *)
  4129. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4130. MAXOFFSETS, &scratch_dma_handle);
  4131. ha->coal_stat_phys = scratch_dma_handle;
  4132. #endif
  4133. ha->ccb_phys =
  4134. pci_map_single(ha->pdev,ha->pccb,
  4135. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4136. ha->scratch_busy = FALSE;
  4137. ha->req_first = NULL;
  4138. ha->tid_cnt = MAX_HDRIVES;
  4139. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4140. ha->tid_cnt = max_ids;
  4141. for (i=0; i<GDTH_MAXCMDS; ++i)
  4142. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4143. ha->scan_mode = rescan ? 0x10 : 0;
  4144. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4145. !gdth_search_drives(hanum)) {
  4146. printk("GDT-EISA: Error during device scan\n");
  4147. --gdth_ctr_count;
  4148. --gdth_ctr_vcount;
  4149. #ifdef INT_COAL
  4150. if (ha->coal_stat)
  4151. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4152. MAXOFFSETS, ha->coal_stat,
  4153. ha->coal_stat_phys);
  4154. #endif
  4155. if (ha->pscratch)
  4156. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4157. ha->pscratch, ha->scratch_phys);
  4158. if (ha->pmsg)
  4159. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4160. ha->pmsg, ha->msg_phys);
  4161. if (ha->ccb_phys)
  4162. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4163. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4164. free_irq(ha->irq,ha);
  4165. scsi_unregister(shp);
  4166. continue;
  4167. }
  4168. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4169. hdr_channel = ha->bus_cnt;
  4170. ha->virt_bus = hdr_channel;
  4171. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  4172. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4173. shp->highmem_io = 0;
  4174. #endif
  4175. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4176. shp->max_cmd_len = 16;
  4177. shp->max_id = ha->tid_cnt;
  4178. shp->max_lun = MAXLUN;
  4179. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4180. if (virt_ctr) {
  4181. virt_ctr = 1;
  4182. /* register addit. SCSI channels as virtual controllers */
  4183. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4184. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4185. shp->unchecked_isa_dma = 0;
  4186. shp->irq = ha->irq;
  4187. shp->dma_channel = 0xff;
  4188. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4189. NUMDATA(shp)->hanum = (ushort)hanum;
  4190. NUMDATA(shp)->busnum = b;
  4191. }
  4192. }
  4193. spin_lock_init(&ha->smp_lock);
  4194. gdth_enable_int(hanum);
  4195. }
  4196. }
  4197. }
  4198. /* scanning for PCI controllers */
  4199. cnt = gdth_search_pci(pcistr);
  4200. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
  4201. gdth_sort_pci(pcistr,cnt);
  4202. for (ctr = 0; ctr < cnt; ++ctr) {
  4203. dma_addr_t scratch_dma_handle;
  4204. scratch_dma_handle = 0;
  4205. if (gdth_ctr_count >= MAXHA)
  4206. break;
  4207. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4208. if (shp == NULL)
  4209. continue;
  4210. ha = HADATA(shp);
  4211. if (!gdth_init_pci(&pcistr[ctr],ha)) {
  4212. scsi_unregister(shp);
  4213. continue;
  4214. }
  4215. /* controller found and initialized */
  4216. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4217. pcistr[ctr].bus,PCI_SLOT(pcistr[ctr].device_fn),ha->irq);
  4218. if (request_irq(ha->irq, gdth_interrupt,
  4219. IRQF_DISABLED|IRQF_SHARED, "gdth", ha))
  4220. {
  4221. printk("GDT-PCI: Unable to allocate IRQ\n");
  4222. scsi_unregister(shp);
  4223. continue;
  4224. }
  4225. shp->unchecked_isa_dma = 0;
  4226. shp->irq = ha->irq;
  4227. shp->dma_channel = 0xff;
  4228. hanum = gdth_ctr_count;
  4229. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4230. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4231. NUMDATA(shp)->hanum = (ushort)hanum;
  4232. NUMDATA(shp)->busnum= 0;
  4233. ha->pccb = CMDDATA(shp);
  4234. ha->ccb_phys = 0L;
  4235. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4236. &scratch_dma_handle);
  4237. ha->scratch_phys = scratch_dma_handle;
  4238. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4239. &scratch_dma_handle);
  4240. ha->msg_phys = scratch_dma_handle;
  4241. #ifdef INT_COAL
  4242. ha->coal_stat = (gdth_coal_status *)
  4243. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4244. MAXOFFSETS, &scratch_dma_handle);
  4245. ha->coal_stat_phys = scratch_dma_handle;
  4246. #endif
  4247. ha->scratch_busy = FALSE;
  4248. ha->req_first = NULL;
  4249. ha->tid_cnt = pcistr[ctr].device_id >= 0x200 ? MAXID : MAX_HDRIVES;
  4250. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4251. ha->tid_cnt = max_ids;
  4252. for (i=0; i<GDTH_MAXCMDS; ++i)
  4253. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4254. ha->scan_mode = rescan ? 0x10 : 0;
  4255. err = FALSE;
  4256. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4257. !gdth_search_drives(hanum)) {
  4258. err = TRUE;
  4259. } else {
  4260. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4261. hdr_channel = ha->bus_cnt;
  4262. ha->virt_bus = hdr_channel;
  4263. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4264. scsi_set_pci_device(shp, pcistr[ctr].pdev);
  4265. #endif
  4266. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
  4267. /* 64-bit DMA only supported from FW >= x.43 */
  4268. (!ha->dma64_support)) {
  4269. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4270. printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
  4271. err = TRUE;
  4272. }
  4273. } else {
  4274. shp->max_cmd_len = 16;
  4275. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4276. printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
  4277. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4278. printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
  4279. err = TRUE;
  4280. }
  4281. }
  4282. }
  4283. if (err) {
  4284. printk("GDT-PCI %d: Error during device scan\n", hanum);
  4285. --gdth_ctr_count;
  4286. --gdth_ctr_vcount;
  4287. #ifdef INT_COAL
  4288. if (ha->coal_stat)
  4289. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4290. MAXOFFSETS, ha->coal_stat,
  4291. ha->coal_stat_phys);
  4292. #endif
  4293. if (ha->pscratch)
  4294. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4295. ha->pscratch, ha->scratch_phys);
  4296. if (ha->pmsg)
  4297. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4298. ha->pmsg, ha->msg_phys);
  4299. free_irq(ha->irq,ha);
  4300. scsi_unregister(shp);
  4301. continue;
  4302. }
  4303. shp->max_id = ha->tid_cnt;
  4304. shp->max_lun = MAXLUN;
  4305. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4306. if (virt_ctr) {
  4307. virt_ctr = 1;
  4308. /* register addit. SCSI channels as virtual controllers */
  4309. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4310. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4311. shp->unchecked_isa_dma = 0;
  4312. shp->irq = ha->irq;
  4313. shp->dma_channel = 0xff;
  4314. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4315. NUMDATA(shp)->hanum = (ushort)hanum;
  4316. NUMDATA(shp)->busnum = b;
  4317. }
  4318. }
  4319. spin_lock_init(&ha->smp_lock);
  4320. gdth_enable_int(hanum);
  4321. }
  4322. TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
  4323. if (gdth_ctr_count > 0) {
  4324. #ifdef GDTH_STATISTICS
  4325. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4326. init_timer(&gdth_timer);
  4327. gdth_timer.expires = jiffies + HZ;
  4328. gdth_timer.data = 0L;
  4329. gdth_timer.function = gdth_timeout;
  4330. add_timer(&gdth_timer);
  4331. #endif
  4332. major = register_chrdev(0,"gdth",&gdth_fops);
  4333. notifier_disabled = 0;
  4334. register_reboot_notifier(&gdth_notifier);
  4335. }
  4336. gdth_polling = FALSE;
  4337. return gdth_ctr_vcount;
  4338. }
  4339. static int gdth_release(struct Scsi_Host *shp)
  4340. {
  4341. int hanum;
  4342. gdth_ha_str *ha;
  4343. TRACE2(("gdth_release()\n"));
  4344. if (NUMDATA(shp)->busnum == 0) {
  4345. hanum = NUMDATA(shp)->hanum;
  4346. ha = HADATA(gdth_ctr_tab[hanum]);
  4347. if (ha->sdev) {
  4348. scsi_free_host_dev(ha->sdev);
  4349. ha->sdev = NULL;
  4350. }
  4351. gdth_flush(hanum);
  4352. if (shp->irq) {
  4353. free_irq(shp->irq,ha);
  4354. }
  4355. #ifndef __ia64__
  4356. if (shp->dma_channel != 0xff) {
  4357. free_dma(shp->dma_channel);
  4358. }
  4359. #endif
  4360. #ifdef INT_COAL
  4361. if (ha->coal_stat)
  4362. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4363. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4364. #endif
  4365. if (ha->pscratch)
  4366. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4367. ha->pscratch, ha->scratch_phys);
  4368. if (ha->pmsg)
  4369. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4370. ha->pmsg, ha->msg_phys);
  4371. if (ha->ccb_phys)
  4372. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4373. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4374. gdth_ctr_released++;
  4375. TRACE2(("gdth_release(): HA %d of %d\n",
  4376. gdth_ctr_released, gdth_ctr_count));
  4377. if (gdth_ctr_released == gdth_ctr_count) {
  4378. #ifdef GDTH_STATISTICS
  4379. del_timer(&gdth_timer);
  4380. #endif
  4381. unregister_chrdev(major,"gdth");
  4382. unregister_reboot_notifier(&gdth_notifier);
  4383. }
  4384. }
  4385. scsi_unregister(shp);
  4386. return 0;
  4387. }
  4388. static const char *gdth_ctr_name(int hanum)
  4389. {
  4390. gdth_ha_str *ha;
  4391. TRACE2(("gdth_ctr_name()\n"));
  4392. ha = HADATA(gdth_ctr_tab[hanum]);
  4393. if (ha->type == GDT_EISA) {
  4394. switch (ha->stype) {
  4395. case GDT3_ID:
  4396. return("GDT3000/3020");
  4397. case GDT3A_ID:
  4398. return("GDT3000A/3020A/3050A");
  4399. case GDT3B_ID:
  4400. return("GDT3000B/3010A");
  4401. }
  4402. } else if (ha->type == GDT_ISA) {
  4403. return("GDT2000/2020");
  4404. } else if (ha->type == GDT_PCI) {
  4405. switch (ha->stype) {
  4406. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  4407. return("GDT6000/6020/6050");
  4408. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  4409. return("GDT6000B/6010");
  4410. }
  4411. }
  4412. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  4413. return("");
  4414. }
  4415. static const char *gdth_info(struct Scsi_Host *shp)
  4416. {
  4417. int hanum;
  4418. gdth_ha_str *ha;
  4419. TRACE2(("gdth_info()\n"));
  4420. hanum = NUMDATA(shp)->hanum;
  4421. ha = HADATA(gdth_ctr_tab[hanum]);
  4422. return ((const char *)ha->binfo.type_string);
  4423. }
  4424. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  4425. {
  4426. int i, hanum;
  4427. gdth_ha_str *ha;
  4428. ulong flags;
  4429. Scsi_Cmnd *cmnd;
  4430. unchar b;
  4431. TRACE2(("gdth_eh_bus_reset()\n"));
  4432. hanum = NUMDATA(scp->device->host)->hanum;
  4433. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  4434. ha = HADATA(gdth_ctr_tab[hanum]);
  4435. /* clear command tab */
  4436. spin_lock_irqsave(&ha->smp_lock, flags);
  4437. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  4438. cmnd = ha->cmd_tab[i].cmnd;
  4439. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  4440. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4441. }
  4442. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4443. if (b == ha->virt_bus) {
  4444. /* host drives */
  4445. for (i = 0; i < MAX_HDRIVES; ++i) {
  4446. if (ha->hdr[i].present) {
  4447. spin_lock_irqsave(&ha->smp_lock, flags);
  4448. gdth_polling = TRUE;
  4449. while (gdth_test_busy(hanum))
  4450. gdth_delay(0);
  4451. if (gdth_internal_cmd(hanum, CACHESERVICE,
  4452. GDT_CLUST_RESET, i, 0, 0))
  4453. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  4454. gdth_polling = FALSE;
  4455. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4456. }
  4457. }
  4458. } else {
  4459. /* raw devices */
  4460. spin_lock_irqsave(&ha->smp_lock, flags);
  4461. for (i = 0; i < MAXID; ++i)
  4462. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  4463. gdth_polling = TRUE;
  4464. while (gdth_test_busy(hanum))
  4465. gdth_delay(0);
  4466. gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
  4467. BUS_L2P(ha,b), 0, 0);
  4468. gdth_polling = FALSE;
  4469. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4470. }
  4471. return SUCCESS;
  4472. }
  4473. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4474. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  4475. #else
  4476. static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
  4477. #endif
  4478. {
  4479. unchar b, t;
  4480. int hanum;
  4481. gdth_ha_str *ha;
  4482. struct scsi_device *sd;
  4483. unsigned capacity;
  4484. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4485. sd = sdev;
  4486. capacity = cap;
  4487. #else
  4488. sd = disk->device;
  4489. capacity = disk->capacity;
  4490. #endif
  4491. hanum = NUMDATA(sd->host)->hanum;
  4492. b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
  4493. t = sd->id;
  4494. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
  4495. ha = HADATA(gdth_ctr_tab[hanum]);
  4496. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  4497. /* raw device or host drive without mapping information */
  4498. TRACE2(("Evaluate mapping\n"));
  4499. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  4500. } else {
  4501. ip[0] = ha->hdr[t].heads;
  4502. ip[1] = ha->hdr[t].secs;
  4503. ip[2] = capacity / ip[0] / ip[1];
  4504. }
  4505. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  4506. ip[0],ip[1],ip[2]));
  4507. return 0;
  4508. }
  4509. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *))
  4510. {
  4511. int hanum;
  4512. int priority;
  4513. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  4514. scp->scsi_done = (void *)done;
  4515. scp->SCp.have_data_in = 1;
  4516. scp->SCp.phase = -1;
  4517. scp->SCp.sent_command = -1;
  4518. scp->SCp.Status = GDTH_MAP_NONE;
  4519. scp->SCp.buffer = (struct scatterlist *)NULL;
  4520. hanum = NUMDATA(scp->device->host)->hanum;
  4521. #ifdef GDTH_STATISTICS
  4522. ++act_ios;
  4523. #endif
  4524. priority = DEFAULT_PRI;
  4525. if (scp->done == gdth_scsi_done)
  4526. priority = scp->SCp.this_residual;
  4527. else
  4528. gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
  4529. gdth_putq( hanum, scp, priority );
  4530. gdth_next( hanum );
  4531. return 0;
  4532. }
  4533. static int gdth_open(struct inode *inode, struct file *filep)
  4534. {
  4535. gdth_ha_str *ha;
  4536. int i;
  4537. for (i = 0; i < gdth_ctr_count; i++) {
  4538. ha = HADATA(gdth_ctr_tab[i]);
  4539. if (!ha->sdev)
  4540. ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
  4541. }
  4542. TRACE(("gdth_open()\n"));
  4543. return 0;
  4544. }
  4545. static int gdth_close(struct inode *inode, struct file *filep)
  4546. {
  4547. TRACE(("gdth_close()\n"));
  4548. return 0;
  4549. }
  4550. static int ioc_event(void __user *arg)
  4551. {
  4552. gdth_ioctl_event evt;
  4553. gdth_ha_str *ha;
  4554. ulong flags;
  4555. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
  4556. evt.ionode >= gdth_ctr_count)
  4557. return -EFAULT;
  4558. ha = HADATA(gdth_ctr_tab[evt.ionode]);
  4559. if (evt.erase == 0xff) {
  4560. if (evt.event.event_source == ES_TEST)
  4561. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  4562. else if (evt.event.event_source == ES_DRIVER)
  4563. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  4564. else if (evt.event.event_source == ES_SYNC)
  4565. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  4566. else
  4567. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  4568. spin_lock_irqsave(&ha->smp_lock, flags);
  4569. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  4570. &evt.event.event_data);
  4571. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4572. } else if (evt.erase == 0xfe) {
  4573. gdth_clear_events();
  4574. } else if (evt.erase == 0) {
  4575. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  4576. } else {
  4577. gdth_readapp_event(ha, evt.erase, &evt.event);
  4578. }
  4579. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  4580. return -EFAULT;
  4581. return 0;
  4582. }
  4583. static int ioc_lockdrv(void __user *arg)
  4584. {
  4585. gdth_ioctl_lockdrv ldrv;
  4586. unchar i, j;
  4587. ulong flags;
  4588. gdth_ha_str *ha;
  4589. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
  4590. ldrv.ionode >= gdth_ctr_count)
  4591. return -EFAULT;
  4592. ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
  4593. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  4594. j = ldrv.drives[i];
  4595. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  4596. continue;
  4597. if (ldrv.lock) {
  4598. spin_lock_irqsave(&ha->smp_lock, flags);
  4599. ha->hdr[j].lock = 1;
  4600. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4601. gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
  4602. gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
  4603. } else {
  4604. spin_lock_irqsave(&ha->smp_lock, flags);
  4605. ha->hdr[j].lock = 0;
  4606. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4607. gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
  4608. gdth_next(ldrv.ionode);
  4609. }
  4610. }
  4611. return 0;
  4612. }
  4613. static int ioc_resetdrv(void __user *arg, char *cmnd)
  4614. {
  4615. gdth_ioctl_reset res;
  4616. gdth_cmd_str cmd;
  4617. int hanum;
  4618. gdth_ha_str *ha;
  4619. int rval;
  4620. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  4621. res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
  4622. return -EFAULT;
  4623. hanum = res.ionode;
  4624. ha = HADATA(gdth_ctr_tab[hanum]);
  4625. if (!ha->hdr[res.number].present)
  4626. return 0;
  4627. memset(&cmd, 0, sizeof(gdth_cmd_str));
  4628. cmd.Service = CACHESERVICE;
  4629. cmd.OpCode = GDT_CLUST_RESET;
  4630. if (ha->cache_feat & GDT_64BIT)
  4631. cmd.u.cache64.DeviceNo = res.number;
  4632. else
  4633. cmd.u.cache.DeviceNo = res.number;
  4634. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  4635. if (rval < 0)
  4636. return rval;
  4637. res.status = rval;
  4638. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  4639. return -EFAULT;
  4640. return 0;
  4641. }
  4642. static int ioc_general(void __user *arg, char *cmnd)
  4643. {
  4644. gdth_ioctl_general gen;
  4645. char *buf = NULL;
  4646. ulong64 paddr;
  4647. int hanum;
  4648. gdth_ha_str *ha;
  4649. int rval;
  4650. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
  4651. gen.ionode >= gdth_ctr_count)
  4652. return -EFAULT;
  4653. hanum = gen.ionode;
  4654. ha = HADATA(gdth_ctr_tab[hanum]);
  4655. if (gen.data_len + gen.sense_len != 0) {
  4656. if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
  4657. FALSE, &paddr)))
  4658. return -EFAULT;
  4659. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  4660. gen.data_len + gen.sense_len)) {
  4661. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4662. return -EFAULT;
  4663. }
  4664. if (gen.command.OpCode == GDT_IOCTL) {
  4665. gen.command.u.ioctl.p_param = paddr;
  4666. } else if (gen.command.Service == CACHESERVICE) {
  4667. if (ha->cache_feat & GDT_64BIT) {
  4668. /* copy elements from 32-bit IOCTL structure */
  4669. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  4670. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  4671. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  4672. /* addresses */
  4673. if (ha->cache_feat & SCATTER_GATHER) {
  4674. gen.command.u.cache64.DestAddr = (ulong64)-1;
  4675. gen.command.u.cache64.sg_canz = 1;
  4676. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  4677. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  4678. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  4679. } else {
  4680. gen.command.u.cache64.DestAddr = paddr;
  4681. gen.command.u.cache64.sg_canz = 0;
  4682. }
  4683. } else {
  4684. if (ha->cache_feat & SCATTER_GATHER) {
  4685. gen.command.u.cache.DestAddr = 0xffffffff;
  4686. gen.command.u.cache.sg_canz = 1;
  4687. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  4688. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  4689. gen.command.u.cache.sg_lst[1].sg_len = 0;
  4690. } else {
  4691. gen.command.u.cache.DestAddr = paddr;
  4692. gen.command.u.cache.sg_canz = 0;
  4693. }
  4694. }
  4695. } else if (gen.command.Service == SCSIRAWSERVICE) {
  4696. if (ha->raw_feat & GDT_64BIT) {
  4697. /* copy elements from 32-bit IOCTL structure */
  4698. char cmd[16];
  4699. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  4700. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  4701. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  4702. gen.command.u.raw64.target = gen.command.u.raw.target;
  4703. memcpy(cmd, gen.command.u.raw.cmd, 16);
  4704. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  4705. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  4706. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  4707. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  4708. /* addresses */
  4709. if (ha->raw_feat & SCATTER_GATHER) {
  4710. gen.command.u.raw64.sdata = (ulong64)-1;
  4711. gen.command.u.raw64.sg_ranz = 1;
  4712. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  4713. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  4714. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  4715. } else {
  4716. gen.command.u.raw64.sdata = paddr;
  4717. gen.command.u.raw64.sg_ranz = 0;
  4718. }
  4719. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  4720. } else {
  4721. if (ha->raw_feat & SCATTER_GATHER) {
  4722. gen.command.u.raw.sdata = 0xffffffff;
  4723. gen.command.u.raw.sg_ranz = 1;
  4724. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  4725. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  4726. gen.command.u.raw.sg_lst[1].sg_len = 0;
  4727. } else {
  4728. gen.command.u.raw.sdata = paddr;
  4729. gen.command.u.raw.sg_ranz = 0;
  4730. }
  4731. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  4732. }
  4733. } else {
  4734. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4735. return -EFAULT;
  4736. }
  4737. }
  4738. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  4739. if (rval < 0)
  4740. return rval;
  4741. gen.status = rval;
  4742. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  4743. gen.data_len + gen.sense_len)) {
  4744. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4745. return -EFAULT;
  4746. }
  4747. if (copy_to_user(arg, &gen,
  4748. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  4749. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4750. return -EFAULT;
  4751. }
  4752. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4753. return 0;
  4754. }
  4755. static int ioc_hdrlist(void __user *arg, char *cmnd)
  4756. {
  4757. gdth_ioctl_rescan *rsc;
  4758. gdth_cmd_str *cmd;
  4759. gdth_ha_str *ha;
  4760. unchar i;
  4761. int hanum, rc = -ENOMEM;
  4762. u32 cluster_type = 0;
  4763. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4764. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4765. if (!rsc || !cmd)
  4766. goto free_fail;
  4767. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4768. rsc->ionode >= gdth_ctr_count) {
  4769. rc = -EFAULT;
  4770. goto free_fail;
  4771. }
  4772. hanum = rsc->ionode;
  4773. ha = HADATA(gdth_ctr_tab[hanum]);
  4774. memset(cmd, 0, sizeof(gdth_cmd_str));
  4775. for (i = 0; i < MAX_HDRIVES; ++i) {
  4776. if (!ha->hdr[i].present) {
  4777. rsc->hdr_list[i].bus = 0xff;
  4778. continue;
  4779. }
  4780. rsc->hdr_list[i].bus = ha->virt_bus;
  4781. rsc->hdr_list[i].target = i;
  4782. rsc->hdr_list[i].lun = 0;
  4783. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4784. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  4785. cmd->Service = CACHESERVICE;
  4786. cmd->OpCode = GDT_CLUST_INFO;
  4787. if (ha->cache_feat & GDT_64BIT)
  4788. cmd->u.cache64.DeviceNo = i;
  4789. else
  4790. cmd->u.cache.DeviceNo = i;
  4791. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  4792. rsc->hdr_list[i].cluster_type = cluster_type;
  4793. }
  4794. }
  4795. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4796. rc = -EFAULT;
  4797. else
  4798. rc = 0;
  4799. free_fail:
  4800. kfree(rsc);
  4801. kfree(cmd);
  4802. return rc;
  4803. }
  4804. static int ioc_rescan(void __user *arg, char *cmnd)
  4805. {
  4806. gdth_ioctl_rescan *rsc;
  4807. gdth_cmd_str *cmd;
  4808. ushort i, status, hdr_cnt;
  4809. ulong32 info;
  4810. int hanum, cyls, hds, secs;
  4811. int rc = -ENOMEM;
  4812. ulong flags;
  4813. gdth_ha_str *ha;
  4814. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4815. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4816. if (!cmd || !rsc)
  4817. goto free_fail;
  4818. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4819. rsc->ionode >= gdth_ctr_count) {
  4820. rc = -EFAULT;
  4821. goto free_fail;
  4822. }
  4823. hanum = rsc->ionode;
  4824. ha = HADATA(gdth_ctr_tab[hanum]);
  4825. memset(cmd, 0, sizeof(gdth_cmd_str));
  4826. if (rsc->flag == 0) {
  4827. /* old method: re-init. cache service */
  4828. cmd->Service = CACHESERVICE;
  4829. if (ha->cache_feat & GDT_64BIT) {
  4830. cmd->OpCode = GDT_X_INIT_HOST;
  4831. cmd->u.cache64.DeviceNo = LINUX_OS;
  4832. } else {
  4833. cmd->OpCode = GDT_INIT;
  4834. cmd->u.cache.DeviceNo = LINUX_OS;
  4835. }
  4836. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4837. i = 0;
  4838. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  4839. } else {
  4840. i = rsc->hdr_no;
  4841. hdr_cnt = i + 1;
  4842. }
  4843. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  4844. cmd->Service = CACHESERVICE;
  4845. cmd->OpCode = GDT_INFO;
  4846. if (ha->cache_feat & GDT_64BIT)
  4847. cmd->u.cache64.DeviceNo = i;
  4848. else
  4849. cmd->u.cache.DeviceNo = i;
  4850. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4851. spin_lock_irqsave(&ha->smp_lock, flags);
  4852. rsc->hdr_list[i].bus = ha->virt_bus;
  4853. rsc->hdr_list[i].target = i;
  4854. rsc->hdr_list[i].lun = 0;
  4855. if (status != S_OK) {
  4856. ha->hdr[i].present = FALSE;
  4857. } else {
  4858. ha->hdr[i].present = TRUE;
  4859. ha->hdr[i].size = info;
  4860. /* evaluate mapping */
  4861. ha->hdr[i].size &= ~SECS32;
  4862. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  4863. ha->hdr[i].heads = hds;
  4864. ha->hdr[i].secs = secs;
  4865. /* round size */
  4866. ha->hdr[i].size = cyls * hds * secs;
  4867. }
  4868. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4869. if (status != S_OK)
  4870. continue;
  4871. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4872. /* but we need ha->info2, not yet stored in scp->SCp */
  4873. /* devtype, cluster info, R/W attribs */
  4874. cmd->Service = CACHESERVICE;
  4875. cmd->OpCode = GDT_DEVTYPE;
  4876. if (ha->cache_feat & GDT_64BIT)
  4877. cmd->u.cache64.DeviceNo = i;
  4878. else
  4879. cmd->u.cache.DeviceNo = i;
  4880. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4881. spin_lock_irqsave(&ha->smp_lock, flags);
  4882. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4883. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4884. cmd->Service = CACHESERVICE;
  4885. cmd->OpCode = GDT_CLUST_INFO;
  4886. if (ha->cache_feat & GDT_64BIT)
  4887. cmd->u.cache64.DeviceNo = i;
  4888. else
  4889. cmd->u.cache.DeviceNo = i;
  4890. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4891. spin_lock_irqsave(&ha->smp_lock, flags);
  4892. ha->hdr[i].cluster_type =
  4893. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4894. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4895. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4896. cmd->Service = CACHESERVICE;
  4897. cmd->OpCode = GDT_RW_ATTRIBS;
  4898. if (ha->cache_feat & GDT_64BIT)
  4899. cmd->u.cache64.DeviceNo = i;
  4900. else
  4901. cmd->u.cache.DeviceNo = i;
  4902. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4903. spin_lock_irqsave(&ha->smp_lock, flags);
  4904. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4905. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4906. }
  4907. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4908. rc = -EFAULT;
  4909. else
  4910. rc = 0;
  4911. free_fail:
  4912. kfree(rsc);
  4913. kfree(cmd);
  4914. return rc;
  4915. }
  4916. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4917. unsigned int cmd, unsigned long arg)
  4918. {
  4919. gdth_ha_str *ha;
  4920. Scsi_Cmnd *scp;
  4921. ulong flags;
  4922. char cmnd[MAX_COMMAND_SIZE];
  4923. void __user *argp = (void __user *)arg;
  4924. memset(cmnd, 0xff, 12);
  4925. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4926. switch (cmd) {
  4927. case GDTIOCTL_CTRCNT:
  4928. {
  4929. int cnt = gdth_ctr_count;
  4930. if (put_user(cnt, (int __user *)argp))
  4931. return -EFAULT;
  4932. break;
  4933. }
  4934. case GDTIOCTL_DRVERS:
  4935. {
  4936. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4937. if (put_user(ver, (int __user *)argp))
  4938. return -EFAULT;
  4939. break;
  4940. }
  4941. case GDTIOCTL_OSVERS:
  4942. {
  4943. gdth_ioctl_osvers osv;
  4944. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4945. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4946. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4947. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4948. return -EFAULT;
  4949. break;
  4950. }
  4951. case GDTIOCTL_CTRTYPE:
  4952. {
  4953. gdth_ioctl_ctrtype ctrt;
  4954. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4955. ctrt.ionode >= gdth_ctr_count)
  4956. return -EFAULT;
  4957. ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
  4958. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4959. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4960. } else {
  4961. if (ha->type != GDT_PCIMPR) {
  4962. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4963. } else {
  4964. ctrt.type =
  4965. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4966. if (ha->stype >= 0x300)
  4967. ctrt.ext_type = 0x6000 | ha->subdevice_id;
  4968. else
  4969. ctrt.ext_type = 0x6000 | ha->stype;
  4970. }
  4971. ctrt.device_id = ha->stype;
  4972. ctrt.sub_device_id = ha->subdevice_id;
  4973. }
  4974. ctrt.info = ha->brd_phys;
  4975. ctrt.oem_id = ha->oem_id;
  4976. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4977. return -EFAULT;
  4978. break;
  4979. }
  4980. case GDTIOCTL_GENERAL:
  4981. return ioc_general(argp, cmnd);
  4982. case GDTIOCTL_EVENT:
  4983. return ioc_event(argp);
  4984. case GDTIOCTL_LOCKDRV:
  4985. return ioc_lockdrv(argp);
  4986. case GDTIOCTL_LOCKCHN:
  4987. {
  4988. gdth_ioctl_lockchn lchn;
  4989. unchar i, j;
  4990. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4991. lchn.ionode >= gdth_ctr_count)
  4992. return -EFAULT;
  4993. ha = HADATA(gdth_ctr_tab[lchn.ionode]);
  4994. i = lchn.channel;
  4995. if (i < ha->bus_cnt) {
  4996. if (lchn.lock) {
  4997. spin_lock_irqsave(&ha->smp_lock, flags);
  4998. ha->raw[i].lock = 1;
  4999. spin_unlock_irqrestore(&ha->smp_lock, flags);
  5000. for (j = 0; j < ha->tid_cnt; ++j) {
  5001. gdth_wait_completion(lchn.ionode, i, j);
  5002. gdth_stop_timeout(lchn.ionode, i, j);
  5003. }
  5004. } else {
  5005. spin_lock_irqsave(&ha->smp_lock, flags);
  5006. ha->raw[i].lock = 0;
  5007. spin_unlock_irqrestore(&ha->smp_lock, flags);
  5008. for (j = 0; j < ha->tid_cnt; ++j) {
  5009. gdth_start_timeout(lchn.ionode, i, j);
  5010. gdth_next(lchn.ionode);
  5011. }
  5012. }
  5013. }
  5014. break;
  5015. }
  5016. case GDTIOCTL_RESCAN:
  5017. return ioc_rescan(argp, cmnd);
  5018. case GDTIOCTL_HDRLIST:
  5019. return ioc_hdrlist(argp, cmnd);
  5020. case GDTIOCTL_RESET_BUS:
  5021. {
  5022. gdth_ioctl_reset res;
  5023. int hanum, rval;
  5024. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  5025. res.ionode >= gdth_ctr_count)
  5026. return -EFAULT;
  5027. hanum = res.ionode;
  5028. ha = HADATA(gdth_ctr_tab[hanum]);
  5029. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5030. scp = kmalloc(sizeof(*scp), GFP_KERNEL);
  5031. if (!scp)
  5032. return -ENOMEM;
  5033. memset(scp, 0, sizeof(*scp));
  5034. scp->device = ha->sdev;
  5035. scp->cmd_len = 12;
  5036. scp->use_sg = 0;
  5037. scp->device->channel = virt_ctr ? 0 : res.number;
  5038. rval = gdth_eh_bus_reset(scp);
  5039. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  5040. kfree(scp);
  5041. #else
  5042. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  5043. if (!scp)
  5044. return -ENOMEM;
  5045. scp->cmd_len = 12;
  5046. scp->use_sg = 0;
  5047. scp->channel = virt_ctr ? 0 : res.number;
  5048. rval = gdth_eh_bus_reset(scp);
  5049. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  5050. scsi_release_command(scp);
  5051. #endif
  5052. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  5053. return -EFAULT;
  5054. break;
  5055. }
  5056. case GDTIOCTL_RESET_DRV:
  5057. return ioc_resetdrv(argp, cmnd);
  5058. default:
  5059. break;
  5060. }
  5061. return 0;
  5062. }
  5063. /* flush routine */
  5064. static void gdth_flush(int hanum)
  5065. {
  5066. int i;
  5067. gdth_ha_str *ha;
  5068. gdth_cmd_str gdtcmd;
  5069. char cmnd[MAX_COMMAND_SIZE];
  5070. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5071. TRACE2(("gdth_flush() hanum %d\n",hanum));
  5072. ha = HADATA(gdth_ctr_tab[hanum]);
  5073. for (i = 0; i < MAX_HDRIVES; ++i) {
  5074. if (ha->hdr[i].present) {
  5075. gdtcmd.BoardNode = LOCALBOARD;
  5076. gdtcmd.Service = CACHESERVICE;
  5077. gdtcmd.OpCode = GDT_FLUSH;
  5078. if (ha->cache_feat & GDT_64BIT) {
  5079. gdtcmd.u.cache64.DeviceNo = i;
  5080. gdtcmd.u.cache64.BlockNo = 1;
  5081. gdtcmd.u.cache64.sg_canz = 0;
  5082. } else {
  5083. gdtcmd.u.cache.DeviceNo = i;
  5084. gdtcmd.u.cache.BlockNo = 1;
  5085. gdtcmd.u.cache.sg_canz = 0;
  5086. }
  5087. TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
  5088. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
  5089. }
  5090. }
  5091. }
  5092. /* shutdown routine */
  5093. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  5094. {
  5095. int hanum;
  5096. #ifndef __alpha__
  5097. gdth_cmd_str gdtcmd;
  5098. char cmnd[MAX_COMMAND_SIZE];
  5099. #endif
  5100. if (notifier_disabled)
  5101. return NOTIFY_OK;
  5102. TRACE2(("gdth_halt() event %d\n",(int)event));
  5103. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  5104. return NOTIFY_DONE;
  5105. notifier_disabled = 1;
  5106. printk("GDT-HA: Flushing all host drives .. ");
  5107. for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
  5108. gdth_flush(hanum);
  5109. #ifndef __alpha__
  5110. /* controller reset */
  5111. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5112. gdtcmd.BoardNode = LOCALBOARD;
  5113. gdtcmd.Service = CACHESERVICE;
  5114. gdtcmd.OpCode = GDT_RESET;
  5115. TRACE2(("gdth_halt(): reset controller %d\n", hanum));
  5116. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
  5117. #endif
  5118. }
  5119. printk("Done.\n");
  5120. #ifdef GDTH_STATISTICS
  5121. del_timer(&gdth_timer);
  5122. #endif
  5123. return NOTIFY_OK;
  5124. }
  5125. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5126. /* configure lun */
  5127. static int gdth_slave_configure(struct scsi_device *sdev)
  5128. {
  5129. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  5130. sdev->skip_ms_page_3f = 1;
  5131. sdev->skip_ms_page_8 = 1;
  5132. return 0;
  5133. }
  5134. #endif
  5135. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5136. static struct scsi_host_template driver_template = {
  5137. #else
  5138. static Scsi_Host_Template driver_template = {
  5139. #endif
  5140. .proc_name = "gdth",
  5141. .proc_info = gdth_proc_info,
  5142. .name = "GDT SCSI Disk Array Controller",
  5143. .detect = gdth_detect,
  5144. .release = gdth_release,
  5145. .info = gdth_info,
  5146. .queuecommand = gdth_queuecommand,
  5147. .eh_bus_reset_handler = gdth_eh_bus_reset,
  5148. .bios_param = gdth_bios_param,
  5149. .can_queue = GDTH_MAXCMDS,
  5150. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5151. .slave_configure = gdth_slave_configure,
  5152. #endif
  5153. .this_id = -1,
  5154. .sg_tablesize = GDTH_MAXSG,
  5155. .cmd_per_lun = GDTH_MAXC_P_L,
  5156. .unchecked_isa_dma = 1,
  5157. .use_clustering = ENABLE_CLUSTERING,
  5158. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  5159. .use_new_eh_code = 1,
  5160. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
  5161. .highmem_io = 1,
  5162. #endif
  5163. #endif
  5164. };
  5165. #include "scsi_module.c"
  5166. #ifndef MODULE
  5167. __setup("gdth=", option_setup);
  5168. #endif