zd_rf_al2230.c 12 KB

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  1. /* zd_rf_al2230.c: Functions for the AL2230 RF controller
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License as published by
  5. * the Free Software Foundation; either version 2 of the License, or
  6. * (at your option) any later version.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. */
  17. #include <linux/kernel.h>
  18. #include "zd_rf.h"
  19. #include "zd_usb.h"
  20. #include "zd_chip.h"
  21. static const u32 zd1211_al2230_table[][3] = {
  22. RF_CHANNEL( 1) = { 0x03f790, 0x033331, 0x00000d, },
  23. RF_CHANNEL( 2) = { 0x03f790, 0x0b3331, 0x00000d, },
  24. RF_CHANNEL( 3) = { 0x03e790, 0x033331, 0x00000d, },
  25. RF_CHANNEL( 4) = { 0x03e790, 0x0b3331, 0x00000d, },
  26. RF_CHANNEL( 5) = { 0x03f7a0, 0x033331, 0x00000d, },
  27. RF_CHANNEL( 6) = { 0x03f7a0, 0x0b3331, 0x00000d, },
  28. RF_CHANNEL( 7) = { 0x03e7a0, 0x033331, 0x00000d, },
  29. RF_CHANNEL( 8) = { 0x03e7a0, 0x0b3331, 0x00000d, },
  30. RF_CHANNEL( 9) = { 0x03f7b0, 0x033331, 0x00000d, },
  31. RF_CHANNEL(10) = { 0x03f7b0, 0x0b3331, 0x00000d, },
  32. RF_CHANNEL(11) = { 0x03e7b0, 0x033331, 0x00000d, },
  33. RF_CHANNEL(12) = { 0x03e7b0, 0x0b3331, 0x00000d, },
  34. RF_CHANNEL(13) = { 0x03f7c0, 0x033331, 0x00000d, },
  35. RF_CHANNEL(14) = { 0x03e7c0, 0x066661, 0x00000d, },
  36. };
  37. static const u32 zd1211b_al2230_table[][3] = {
  38. RF_CHANNEL( 1) = { 0x09efc0, 0x8cccc0, 0xb00000, },
  39. RF_CHANNEL( 2) = { 0x09efc0, 0x8cccd0, 0xb00000, },
  40. RF_CHANNEL( 3) = { 0x09e7c0, 0x8cccc0, 0xb00000, },
  41. RF_CHANNEL( 4) = { 0x09e7c0, 0x8cccd0, 0xb00000, },
  42. RF_CHANNEL( 5) = { 0x05efc0, 0x8cccc0, 0xb00000, },
  43. RF_CHANNEL( 6) = { 0x05efc0, 0x8cccd0, 0xb00000, },
  44. RF_CHANNEL( 7) = { 0x05e7c0, 0x8cccc0, 0xb00000, },
  45. RF_CHANNEL( 8) = { 0x05e7c0, 0x8cccd0, 0xb00000, },
  46. RF_CHANNEL( 9) = { 0x0defc0, 0x8cccc0, 0xb00000, },
  47. RF_CHANNEL(10) = { 0x0defc0, 0x8cccd0, 0xb00000, },
  48. RF_CHANNEL(11) = { 0x0de7c0, 0x8cccc0, 0xb00000, },
  49. RF_CHANNEL(12) = { 0x0de7c0, 0x8cccd0, 0xb00000, },
  50. RF_CHANNEL(13) = { 0x03efc0, 0x8cccc0, 0xb00000, },
  51. RF_CHANNEL(14) = { 0x03e7c0, 0x866660, 0xb00000, },
  52. };
  53. static const struct zd_ioreq16 zd1211b_ioreqs_shared_1[] = {
  54. { CR240, 0x57 }, { CR9, 0xe0 },
  55. };
  56. static const struct zd_ioreq16 ioreqs_init_al2230s[] = {
  57. { CR47, 0x1e }, /* MARK_002 */
  58. { CR106, 0x22 },
  59. { CR107, 0x2a }, /* MARK_002 */
  60. { CR109, 0x13 }, /* MARK_002 */
  61. { CR118, 0xf8 }, /* MARK_002 */
  62. { CR119, 0x12 }, { CR122, 0xe0 },
  63. { CR128, 0x10 }, /* MARK_001 from 0xe->0x10 */
  64. { CR129, 0x0e }, /* MARK_001 from 0xd->0x0e */
  65. { CR130, 0x10 }, /* MARK_001 from 0xb->0x0d */
  66. };
  67. static int zd1211b_al2230_finalize_rf(struct zd_chip *chip)
  68. {
  69. int r;
  70. static const struct zd_ioreq16 ioreqs[] = {
  71. { CR80, 0x30 }, { CR81, 0x30 }, { CR79, 0x58 },
  72. { CR12, 0xf0 }, { CR77, 0x1b }, { CR78, 0x58 },
  73. { CR203, 0x06 },
  74. { },
  75. { CR240, 0x80 },
  76. };
  77. r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  78. if (r)
  79. return r;
  80. /* related to antenna selection? */
  81. if (chip->new_phy_layout) {
  82. r = zd_iowrite16_locked(chip, 0xe1, CR9);
  83. if (r)
  84. return r;
  85. }
  86. return zd_iowrite16_locked(chip, 0x06, CR203);
  87. }
  88. static int zd1211_al2230_init_hw(struct zd_rf *rf)
  89. {
  90. int r;
  91. struct zd_chip *chip = zd_rf_to_chip(rf);
  92. static const struct zd_ioreq16 ioreqs_init[] = {
  93. { CR15, 0x20 }, { CR23, 0x40 }, { CR24, 0x20 },
  94. { CR26, 0x11 }, { CR28, 0x3e }, { CR29, 0x00 },
  95. { CR44, 0x33 }, { CR106, 0x2a }, { CR107, 0x1a },
  96. { CR109, 0x09 }, { CR110, 0x27 }, { CR111, 0x2b },
  97. { CR112, 0x2b }, { CR119, 0x0a }, { CR10, 0x89 },
  98. /* for newest (3rd cut) AL2300 */
  99. { CR17, 0x28 },
  100. { CR26, 0x93 }, { CR34, 0x30 },
  101. /* for newest (3rd cut) AL2300 */
  102. { CR35, 0x3e },
  103. { CR41, 0x24 }, { CR44, 0x32 },
  104. /* for newest (3rd cut) AL2300 */
  105. { CR46, 0x96 },
  106. { CR47, 0x1e }, { CR79, 0x58 }, { CR80, 0x30 },
  107. { CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 },
  108. { CR92, 0x0a }, { CR99, 0x28 }, { CR100, 0x00 },
  109. { CR101, 0x13 }, { CR102, 0x27 }, { CR106, 0x24 },
  110. { CR107, 0x2a }, { CR109, 0x09 }, { CR110, 0x13 },
  111. { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
  112. { CR114, 0x27 },
  113. /* for newest (3rd cut) AL2300 */
  114. { CR115, 0x24 },
  115. { CR116, 0x24 }, { CR117, 0xf4 }, { CR118, 0xfc },
  116. { CR119, 0x10 }, { CR120, 0x4f }, { CR121, 0x77 },
  117. { CR122, 0xe0 }, { CR137, 0x88 }, { CR252, 0xff },
  118. { CR253, 0xff },
  119. };
  120. static const struct zd_ioreq16 ioreqs_pll[] = {
  121. /* shdnb(PLL_ON)=0 */
  122. { CR251, 0x2f },
  123. /* shdnb(PLL_ON)=1 */
  124. { CR251, 0x3f },
  125. { CR138, 0x28 }, { CR203, 0x06 },
  126. };
  127. static const u32 rv1[] = {
  128. /* Channel 1 */
  129. 0x03f790,
  130. 0x033331,
  131. 0x00000d,
  132. 0x0b3331,
  133. 0x03b812,
  134. 0x00fff3,
  135. };
  136. static const u32 rv2[] = {
  137. 0x000da4,
  138. 0x0f4dc5, /* fix freq shift, 0x04edc5 */
  139. 0x0805b6,
  140. 0x011687,
  141. 0x000688,
  142. 0x0403b9, /* external control TX power (CR31) */
  143. 0x00dbba,
  144. 0x00099b,
  145. 0x0bdffc,
  146. 0x00000d,
  147. 0x00500f,
  148. };
  149. static const u32 rv3[] = {
  150. 0x00d00f,
  151. 0x004c0f,
  152. 0x00540f,
  153. 0x00700f,
  154. 0x00500f,
  155. };
  156. r = zd_iowrite16a_locked(chip, ioreqs_init, ARRAY_SIZE(ioreqs_init));
  157. if (r)
  158. return r;
  159. if (chip->al2230s_bit) {
  160. r = zd_iowrite16a_locked(chip, ioreqs_init_al2230s,
  161. ARRAY_SIZE(ioreqs_init_al2230s));
  162. if (r)
  163. return r;
  164. }
  165. r = zd_rfwritev_locked(chip, rv1, ARRAY_SIZE(rv1), RF_RV_BITS);
  166. if (r)
  167. return r;
  168. /* improve band edge for AL2230S */
  169. if (chip->al2230s_bit)
  170. r = zd_rfwrite_locked(chip, 0x000824, RF_RV_BITS);
  171. else
  172. r = zd_rfwrite_locked(chip, 0x0005a4, RF_RV_BITS);
  173. if (r)
  174. return r;
  175. r = zd_rfwritev_locked(chip, rv2, ARRAY_SIZE(rv2), RF_RV_BITS);
  176. if (r)
  177. return r;
  178. r = zd_iowrite16a_locked(chip, ioreqs_pll, ARRAY_SIZE(ioreqs_pll));
  179. if (r)
  180. return r;
  181. r = zd_rfwritev_locked(chip, rv3, ARRAY_SIZE(rv3), RF_RV_BITS);
  182. if (r)
  183. return r;
  184. return 0;
  185. }
  186. static int zd1211b_al2230_init_hw(struct zd_rf *rf)
  187. {
  188. int r;
  189. struct zd_chip *chip = zd_rf_to_chip(rf);
  190. static const struct zd_ioreq16 ioreqs1[] = {
  191. { CR10, 0x89 }, { CR15, 0x20 },
  192. { CR17, 0x2B }, /* for newest(3rd cut) AL2230 */
  193. { CR23, 0x40 }, { CR24, 0x20 }, { CR26, 0x93 },
  194. { CR28, 0x3e }, { CR29, 0x00 },
  195. { CR33, 0x28 }, /* 5621 */
  196. { CR34, 0x30 },
  197. { CR35, 0x3e }, /* for newest(3rd cut) AL2230 */
  198. { CR41, 0x24 }, { CR44, 0x32 },
  199. { CR46, 0x99 }, /* for newest(3rd cut) AL2230 */
  200. { CR47, 0x1e },
  201. /* ZD1211B 05.06.10 */
  202. { CR48, 0x06 }, { CR49, 0xf9 }, { CR51, 0x01 },
  203. { CR52, 0x80 }, { CR53, 0x7e }, { CR65, 0x00 },
  204. { CR66, 0x00 }, { CR67, 0x00 }, { CR68, 0x00 },
  205. { CR69, 0x28 },
  206. { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 },
  207. { CR87, 0x0a }, { CR89, 0x04 },
  208. { CR91, 0x00 }, /* 5621 */
  209. { CR92, 0x0a },
  210. { CR98, 0x8d }, /* 4804, for 1212 new algorithm */
  211. { CR99, 0x00 }, /* 5621 */
  212. { CR101, 0x13 }, { CR102, 0x27 },
  213. { CR106, 0x24 }, /* for newest(3rd cut) AL2230 */
  214. { CR107, 0x2a },
  215. { CR109, 0x13 }, /* 4804, for 1212 new algorithm */
  216. { CR110, 0x1f }, /* 4804, for 1212 new algorithm */
  217. { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
  218. { CR114, 0x27 },
  219. { CR115, 0x26 }, /* 24->26 at 4902 for newest(3rd cut) AL2230 */
  220. { CR116, 0x24 },
  221. { CR117, 0xfa }, /* for 1211b */
  222. { CR118, 0xfa }, /* for 1211b */
  223. { CR119, 0x10 },
  224. { CR120, 0x4f },
  225. { CR121, 0x6c }, /* for 1211b */
  226. { CR122, 0xfc }, /* E0->FC at 4902 */
  227. { CR123, 0x57 }, /* 5623 */
  228. { CR125, 0xad }, /* 4804, for 1212 new algorithm */
  229. { CR126, 0x6c }, /* 5614 */
  230. { CR127, 0x03 }, /* 4804, for 1212 new algorithm */
  231. { CR137, 0x50 }, /* 5614 */
  232. { CR138, 0xa8 },
  233. { CR144, 0xac }, /* 5621 */
  234. { CR150, 0x0d }, { CR252, 0x34 }, { CR253, 0x34 },
  235. };
  236. static const u32 rv1[] = {
  237. 0x8cccd0,
  238. 0x481dc0,
  239. 0xcfff00,
  240. 0x25a000,
  241. };
  242. static const u32 rv2[] = {
  243. /* To improve AL2230 yield, improve phase noise, 4713 */
  244. 0x25a000,
  245. 0xa3b2f0,
  246. 0x6da010, /* Reg6 update for MP versio */
  247. 0xe36280, /* Modified by jxiao for Bor-Chin on 2004/08/02 */
  248. 0x116000,
  249. 0x9dc020, /* External control TX power (CR31) */
  250. 0x5ddb00, /* RegA update for MP version */
  251. 0xd99000, /* RegB update for MP version */
  252. 0x3ffbd0, /* RegC update for MP version */
  253. 0xb00000, /* RegD update for MP version */
  254. /* improve phase noise and remove phase calibration,4713 */
  255. 0xf01a00,
  256. };
  257. static const struct zd_ioreq16 ioreqs2[] = {
  258. { CR251, 0x2f }, /* shdnb(PLL_ON)=0 */
  259. { CR251, 0x7f }, /* shdnb(PLL_ON)=1 */
  260. };
  261. static const u32 rv3[] = {
  262. /* To improve AL2230 yield, 4713 */
  263. 0xf01b00,
  264. 0xf01e00,
  265. 0xf01a00,
  266. };
  267. static const struct zd_ioreq16 ioreqs3[] = {
  268. /* related to 6M band edge patching, happens unconditionally */
  269. { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
  270. };
  271. r = zd_iowrite16a_locked(chip, zd1211b_ioreqs_shared_1,
  272. ARRAY_SIZE(zd1211b_ioreqs_shared_1));
  273. if (r)
  274. return r;
  275. r = zd_iowrite16a_locked(chip, ioreqs1, ARRAY_SIZE(ioreqs1));
  276. if (r)
  277. return r;
  278. if (chip->al2230s_bit) {
  279. r = zd_iowrite16a_locked(chip, ioreqs_init_al2230s,
  280. ARRAY_SIZE(ioreqs_init_al2230s));
  281. if (r)
  282. return r;
  283. }
  284. r = zd_rfwritev_cr_locked(chip, zd1211b_al2230_table[0], 3);
  285. if (r)
  286. return r;
  287. r = zd_rfwritev_cr_locked(chip, rv1, ARRAY_SIZE(rv1));
  288. if (r)
  289. return r;
  290. if (chip->al2230s_bit)
  291. r = zd_rfwrite_locked(chip, 0x241000, RF_RV_BITS);
  292. else
  293. r = zd_rfwrite_locked(chip, 0x25a000, RF_RV_BITS);
  294. if (r)
  295. return r;
  296. r = zd_rfwritev_cr_locked(chip, rv2, ARRAY_SIZE(rv2));
  297. if (r)
  298. return r;
  299. r = zd_iowrite16a_locked(chip, ioreqs2, ARRAY_SIZE(ioreqs2));
  300. if (r)
  301. return r;
  302. r = zd_rfwritev_cr_locked(chip, rv3, ARRAY_SIZE(rv3));
  303. if (r)
  304. return r;
  305. r = zd_iowrite16a_locked(chip, ioreqs3, ARRAY_SIZE(ioreqs3));
  306. if (r)
  307. return r;
  308. return zd1211b_al2230_finalize_rf(chip);
  309. }
  310. static int zd1211_al2230_set_channel(struct zd_rf *rf, u8 channel)
  311. {
  312. int r;
  313. const u32 *rv = zd1211_al2230_table[channel-1];
  314. struct zd_chip *chip = zd_rf_to_chip(rf);
  315. static const struct zd_ioreq16 ioreqs[] = {
  316. { CR138, 0x28 },
  317. { CR203, 0x06 },
  318. };
  319. r = zd_rfwritev_locked(chip, rv, 3, RF_RV_BITS);
  320. if (r)
  321. return r;
  322. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  323. }
  324. static int zd1211b_al2230_set_channel(struct zd_rf *rf, u8 channel)
  325. {
  326. int r;
  327. const u32 *rv = zd1211b_al2230_table[channel-1];
  328. struct zd_chip *chip = zd_rf_to_chip(rf);
  329. r = zd_iowrite16a_locked(chip, zd1211b_ioreqs_shared_1,
  330. ARRAY_SIZE(zd1211b_ioreqs_shared_1));
  331. if (r)
  332. return r;
  333. r = zd_rfwritev_cr_locked(chip, rv, 3);
  334. if (r)
  335. return r;
  336. return zd1211b_al2230_finalize_rf(chip);
  337. }
  338. static int zd1211_al2230_switch_radio_on(struct zd_rf *rf)
  339. {
  340. struct zd_chip *chip = zd_rf_to_chip(rf);
  341. static const struct zd_ioreq16 ioreqs[] = {
  342. { CR11, 0x00 },
  343. { CR251, 0x3f },
  344. };
  345. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  346. }
  347. static int zd1211b_al2230_switch_radio_on(struct zd_rf *rf)
  348. {
  349. struct zd_chip *chip = zd_rf_to_chip(rf);
  350. static const struct zd_ioreq16 ioreqs[] = {
  351. { CR11, 0x00 },
  352. { CR251, 0x7f },
  353. };
  354. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  355. }
  356. static int al2230_switch_radio_off(struct zd_rf *rf)
  357. {
  358. struct zd_chip *chip = zd_rf_to_chip(rf);
  359. static const struct zd_ioreq16 ioreqs[] = {
  360. { CR11, 0x04 },
  361. { CR251, 0x2f },
  362. };
  363. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  364. }
  365. int zd_rf_init_al2230(struct zd_rf *rf)
  366. {
  367. struct zd_chip *chip = zd_rf_to_chip(rf);
  368. rf->switch_radio_off = al2230_switch_radio_off;
  369. if (chip->is_zd1211b) {
  370. rf->init_hw = zd1211b_al2230_init_hw;
  371. rf->set_channel = zd1211b_al2230_set_channel;
  372. rf->switch_radio_on = zd1211b_al2230_switch_radio_on;
  373. } else {
  374. rf->init_hw = zd1211_al2230_init_hw;
  375. rf->set_channel = zd1211_al2230_set_channel;
  376. rf->switch_radio_on = zd1211_al2230_switch_radio_on;
  377. }
  378. rf->patch_6m_band_edge = zd_rf_generic_patch_6m;
  379. return 0;
  380. }