pasemi_mac.c 30 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248
  1. /*
  2. * Copyright (C) 2006-2007 PA Semi, Inc
  3. *
  4. * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/dmaengine.h>
  24. #include <linux/delay.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <asm/dma-mapping.h>
  28. #include <linux/in.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/ip.h>
  31. #include <linux/tcp.h>
  32. #include <net/checksum.h>
  33. #include <asm/irq.h>
  34. #include "pasemi_mac.h"
  35. /* TODO list
  36. *
  37. * - Get rid of pci_{read,write}_config(), map registers with ioremap
  38. * for performance
  39. * - PHY support
  40. * - Multicast support
  41. * - Large MTU support
  42. * - Other performance improvements
  43. */
  44. /* Must be a power of two */
  45. #define RX_RING_SIZE 512
  46. #define TX_RING_SIZE 512
  47. #define DEFAULT_MSG_ENABLE \
  48. (NETIF_MSG_DRV | \
  49. NETIF_MSG_PROBE | \
  50. NETIF_MSG_LINK | \
  51. NETIF_MSG_TIMER | \
  52. NETIF_MSG_IFDOWN | \
  53. NETIF_MSG_IFUP | \
  54. NETIF_MSG_RX_ERR | \
  55. NETIF_MSG_TX_ERR)
  56. #define TX_DESC(mac, num) ((mac)->tx->desc[(num) & (TX_RING_SIZE-1)])
  57. #define TX_DESC_INFO(mac, num) ((mac)->tx->desc_info[(num) & (TX_RING_SIZE-1)])
  58. #define RX_DESC(mac, num) ((mac)->rx->desc[(num) & (RX_RING_SIZE-1)])
  59. #define RX_DESC_INFO(mac, num) ((mac)->rx->desc_info[(num) & (RX_RING_SIZE-1)])
  60. #define RX_BUFF(mac, num) ((mac)->rx->buffers[(num) & (RX_RING_SIZE-1)])
  61. #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
  62. MODULE_LICENSE("GPL");
  63. MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
  64. MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
  65. static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
  66. module_param(debug, int, 0);
  67. MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
  68. static struct pasdma_status *dma_status;
  69. static int pasemi_get_mac_addr(struct pasemi_mac *mac)
  70. {
  71. struct pci_dev *pdev = mac->pdev;
  72. struct device_node *dn = pci_device_to_OF_node(pdev);
  73. int len;
  74. const u8 *maddr;
  75. u8 addr[6];
  76. if (!dn) {
  77. dev_dbg(&pdev->dev,
  78. "No device node for mac, not configuring\n");
  79. return -ENOENT;
  80. }
  81. maddr = of_get_property(dn, "local-mac-address", &len);
  82. if (maddr && len == 6) {
  83. memcpy(mac->mac_addr, maddr, 6);
  84. return 0;
  85. }
  86. /* Some old versions of firmware mistakenly uses mac-address
  87. * (and as a string) instead of a byte array in local-mac-address.
  88. */
  89. if (maddr == NULL)
  90. maddr = of_get_property(dn, "mac-address", NULL);
  91. if (maddr == NULL) {
  92. dev_warn(&pdev->dev,
  93. "no mac address in device tree, not configuring\n");
  94. return -ENOENT;
  95. }
  96. if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
  97. &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
  98. dev_warn(&pdev->dev,
  99. "can't parse mac address, not configuring\n");
  100. return -EINVAL;
  101. }
  102. memcpy(mac->mac_addr, addr, 6);
  103. return 0;
  104. }
  105. static int pasemi_mac_setup_rx_resources(struct net_device *dev)
  106. {
  107. struct pasemi_mac_rxring *ring;
  108. struct pasemi_mac *mac = netdev_priv(dev);
  109. int chan_id = mac->dma_rxch;
  110. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  111. if (!ring)
  112. goto out_ring;
  113. spin_lock_init(&ring->lock);
  114. ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  115. RX_RING_SIZE, GFP_KERNEL);
  116. if (!ring->desc_info)
  117. goto out_desc_info;
  118. /* Allocate descriptors */
  119. ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev,
  120. RX_RING_SIZE *
  121. sizeof(struct pas_dma_xct_descr),
  122. &ring->dma, GFP_KERNEL);
  123. if (!ring->desc)
  124. goto out_desc;
  125. memset(ring->desc, 0, RX_RING_SIZE * sizeof(struct pas_dma_xct_descr));
  126. ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
  127. RX_RING_SIZE * sizeof(u64),
  128. &ring->buf_dma, GFP_KERNEL);
  129. if (!ring->buffers)
  130. goto out_buffers;
  131. memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
  132. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEL(chan_id),
  133. PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma));
  134. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEU(chan_id),
  135. PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) |
  136. PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 2));
  137. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_CFG(chan_id),
  138. PAS_DMA_RXCHAN_CFG_HBU(1));
  139. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEL(mac->dma_if),
  140. PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers)));
  141. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEU(mac->dma_if),
  142. PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) |
  143. PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
  144. ring->next_to_fill = 0;
  145. ring->next_to_clean = 0;
  146. snprintf(ring->irq_name, sizeof(ring->irq_name),
  147. "%s rx", dev->name);
  148. mac->rx = ring;
  149. return 0;
  150. out_buffers:
  151. dma_free_coherent(&mac->dma_pdev->dev,
  152. RX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
  153. mac->rx->desc, mac->rx->dma);
  154. out_desc:
  155. kfree(ring->desc_info);
  156. out_desc_info:
  157. kfree(ring);
  158. out_ring:
  159. return -ENOMEM;
  160. }
  161. static int pasemi_mac_setup_tx_resources(struct net_device *dev)
  162. {
  163. struct pasemi_mac *mac = netdev_priv(dev);
  164. u32 val;
  165. int chan_id = mac->dma_txch;
  166. struct pasemi_mac_txring *ring;
  167. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  168. if (!ring)
  169. goto out_ring;
  170. spin_lock_init(&ring->lock);
  171. ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  172. TX_RING_SIZE, GFP_KERNEL);
  173. if (!ring->desc_info)
  174. goto out_desc_info;
  175. /* Allocate descriptors */
  176. ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev,
  177. TX_RING_SIZE *
  178. sizeof(struct pas_dma_xct_descr),
  179. &ring->dma, GFP_KERNEL);
  180. if (!ring->desc)
  181. goto out_desc;
  182. memset(ring->desc, 0, TX_RING_SIZE * sizeof(struct pas_dma_xct_descr));
  183. pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEL(chan_id),
  184. PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma));
  185. val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32);
  186. val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2);
  187. pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEU(chan_id), val);
  188. pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_CFG(chan_id),
  189. PAS_DMA_TXCHAN_CFG_TY_IFACE |
  190. PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
  191. PAS_DMA_TXCHAN_CFG_UP |
  192. PAS_DMA_TXCHAN_CFG_WT(2));
  193. ring->next_to_use = 0;
  194. ring->next_to_clean = 0;
  195. snprintf(ring->irq_name, sizeof(ring->irq_name),
  196. "%s tx", dev->name);
  197. mac->tx = ring;
  198. return 0;
  199. out_desc:
  200. kfree(ring->desc_info);
  201. out_desc_info:
  202. kfree(ring);
  203. out_ring:
  204. return -ENOMEM;
  205. }
  206. static void pasemi_mac_free_tx_resources(struct net_device *dev)
  207. {
  208. struct pasemi_mac *mac = netdev_priv(dev);
  209. unsigned int i;
  210. struct pasemi_mac_buffer *info;
  211. struct pas_dma_xct_descr *dp;
  212. for (i = 0; i < TX_RING_SIZE; i++) {
  213. info = &TX_DESC_INFO(mac, i);
  214. dp = &TX_DESC(mac, i);
  215. if (info->dma) {
  216. if (info->skb) {
  217. pci_unmap_single(mac->dma_pdev,
  218. info->dma,
  219. info->skb->len,
  220. PCI_DMA_TODEVICE);
  221. dev_kfree_skb_any(info->skb);
  222. }
  223. info->dma = 0;
  224. info->skb = NULL;
  225. dp->mactx = 0;
  226. dp->ptr = 0;
  227. }
  228. }
  229. dma_free_coherent(&mac->dma_pdev->dev,
  230. TX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
  231. mac->tx->desc, mac->tx->dma);
  232. kfree(mac->tx->desc_info);
  233. kfree(mac->tx);
  234. mac->tx = NULL;
  235. }
  236. static void pasemi_mac_free_rx_resources(struct net_device *dev)
  237. {
  238. struct pasemi_mac *mac = netdev_priv(dev);
  239. unsigned int i;
  240. struct pasemi_mac_buffer *info;
  241. struct pas_dma_xct_descr *dp;
  242. for (i = 0; i < RX_RING_SIZE; i++) {
  243. info = &RX_DESC_INFO(mac, i);
  244. dp = &RX_DESC(mac, i);
  245. if (info->skb) {
  246. if (info->dma) {
  247. pci_unmap_single(mac->dma_pdev,
  248. info->dma,
  249. info->skb->len,
  250. PCI_DMA_FROMDEVICE);
  251. dev_kfree_skb_any(info->skb);
  252. }
  253. info->dma = 0;
  254. info->skb = NULL;
  255. dp->macrx = 0;
  256. dp->ptr = 0;
  257. }
  258. }
  259. dma_free_coherent(&mac->dma_pdev->dev,
  260. RX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
  261. mac->rx->desc, mac->rx->dma);
  262. dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
  263. mac->rx->buffers, mac->rx->buf_dma);
  264. kfree(mac->rx->desc_info);
  265. kfree(mac->rx);
  266. mac->rx = NULL;
  267. }
  268. static void pasemi_mac_replenish_rx_ring(struct net_device *dev)
  269. {
  270. struct pasemi_mac *mac = netdev_priv(dev);
  271. unsigned int i;
  272. int start = mac->rx->next_to_fill;
  273. unsigned int limit, count;
  274. limit = (mac->rx->next_to_clean + RX_RING_SIZE -
  275. mac->rx->next_to_fill) & (RX_RING_SIZE - 1);
  276. /* Check to see if we're doing first-time setup */
  277. if (unlikely(mac->rx->next_to_clean == 0 && mac->rx->next_to_fill == 0))
  278. limit = RX_RING_SIZE;
  279. if (limit <= 0)
  280. return;
  281. i = start;
  282. for (count = limit; count; count--) {
  283. struct pasemi_mac_buffer *info = &RX_DESC_INFO(mac, i);
  284. u64 *buff = &RX_BUFF(mac, i);
  285. struct sk_buff *skb;
  286. dma_addr_t dma;
  287. /* skb might still be in there for recycle on short receives */
  288. if (info->skb)
  289. skb = info->skb;
  290. else
  291. skb = dev_alloc_skb(BUF_SIZE);
  292. if (unlikely(!skb))
  293. break;
  294. dma = pci_map_single(mac->dma_pdev, skb->data, skb->len,
  295. PCI_DMA_FROMDEVICE);
  296. if (unlikely(dma_mapping_error(dma))) {
  297. dev_kfree_skb_irq(info->skb);
  298. break;
  299. }
  300. info->skb = skb;
  301. info->dma = dma;
  302. *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
  303. i++;
  304. }
  305. wmb();
  306. pci_write_config_dword(mac->dma_pdev,
  307. PAS_DMA_RXCHAN_INCR(mac->dma_rxch),
  308. limit - count);
  309. pci_write_config_dword(mac->dma_pdev,
  310. PAS_DMA_RXINT_INCR(mac->dma_if),
  311. limit - count);
  312. mac->rx->next_to_fill += limit - count;
  313. }
  314. static void pasemi_mac_restart_rx_intr(struct pasemi_mac *mac)
  315. {
  316. unsigned int reg, pcnt;
  317. /* Re-enable packet count interrupts: finally
  318. * ack the packet count interrupt we got in rx_intr.
  319. */
  320. pcnt = *mac->rx_status & PAS_STATUS_PCNT_M;
  321. reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
  322. pci_write_config_dword(mac->iob_pdev,
  323. PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch),
  324. reg);
  325. }
  326. static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac)
  327. {
  328. unsigned int reg, pcnt;
  329. /* Re-enable packet count interrupts */
  330. pcnt = *mac->tx_status & PAS_STATUS_PCNT_M;
  331. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  332. pci_write_config_dword(mac->iob_pdev,
  333. PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg);
  334. }
  335. static int pasemi_mac_clean_rx(struct pasemi_mac *mac, int limit)
  336. {
  337. unsigned int n;
  338. int count;
  339. struct pas_dma_xct_descr *dp;
  340. struct pasemi_mac_buffer *info;
  341. struct sk_buff *skb;
  342. unsigned int i, len;
  343. u64 macrx;
  344. dma_addr_t dma;
  345. spin_lock(&mac->rx->lock);
  346. n = mac->rx->next_to_clean;
  347. for (count = limit; count; count--) {
  348. rmb();
  349. dp = &RX_DESC(mac, n);
  350. macrx = dp->macrx;
  351. if (!(macrx & XCT_MACRX_O))
  352. break;
  353. info = NULL;
  354. /* We have to scan for our skb since there's no way
  355. * to back-map them from the descriptor, and if we
  356. * have several receive channels then they might not
  357. * show up in the same order as they were put on the
  358. * interface ring.
  359. */
  360. dma = (dp->ptr & XCT_PTR_ADDR_M);
  361. for (i = n; i < (n + RX_RING_SIZE); i++) {
  362. info = &RX_DESC_INFO(mac, i);
  363. if (info->dma == dma)
  364. break;
  365. }
  366. skb = info->skb;
  367. info->dma = 0;
  368. pci_unmap_single(mac->dma_pdev, dma, skb->len,
  369. PCI_DMA_FROMDEVICE);
  370. len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
  371. if (len < 256) {
  372. struct sk_buff *new_skb =
  373. netdev_alloc_skb(mac->netdev, len + NET_IP_ALIGN);
  374. if (new_skb) {
  375. skb_reserve(new_skb, NET_IP_ALIGN);
  376. memcpy(new_skb->data - NET_IP_ALIGN,
  377. skb->data - NET_IP_ALIGN,
  378. len + NET_IP_ALIGN);
  379. /* save the skb in buffer_info as good */
  380. skb = new_skb;
  381. }
  382. /* else just continue with the old one */
  383. } else
  384. info->skb = NULL;
  385. skb_put(skb, len);
  386. skb->protocol = eth_type_trans(skb, mac->netdev);
  387. if ((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK) {
  388. skb->ip_summed = CHECKSUM_COMPLETE;
  389. skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
  390. XCT_MACRX_CSUM_S;
  391. } else
  392. skb->ip_summed = CHECKSUM_NONE;
  393. mac->stats.rx_bytes += len;
  394. mac->stats.rx_packets++;
  395. netif_receive_skb(skb);
  396. dp->ptr = 0;
  397. dp->macrx = 0;
  398. n++;
  399. }
  400. mac->rx->next_to_clean += limit - count;
  401. pasemi_mac_replenish_rx_ring(mac->netdev);
  402. spin_unlock(&mac->rx->lock);
  403. return count;
  404. }
  405. static int pasemi_mac_clean_tx(struct pasemi_mac *mac)
  406. {
  407. int i;
  408. struct pasemi_mac_buffer *info;
  409. struct pas_dma_xct_descr *dp;
  410. int start, count;
  411. int flags;
  412. spin_lock_irqsave(&mac->tx->lock, flags);
  413. start = mac->tx->next_to_clean;
  414. count = 0;
  415. for (i = start; i < mac->tx->next_to_use; i++) {
  416. dp = &TX_DESC(mac, i);
  417. if (!dp || (dp->mactx & XCT_MACTX_O))
  418. break;
  419. count++;
  420. info = &TX_DESC_INFO(mac, i);
  421. pci_unmap_single(mac->dma_pdev, info->dma,
  422. info->skb->len, PCI_DMA_TODEVICE);
  423. dev_kfree_skb_irq(info->skb);
  424. info->skb = NULL;
  425. info->dma = 0;
  426. dp->mactx = 0;
  427. dp->ptr = 0;
  428. }
  429. mac->tx->next_to_clean += count;
  430. spin_unlock_irqrestore(&mac->tx->lock, flags);
  431. netif_wake_queue(mac->netdev);
  432. return count;
  433. }
  434. static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
  435. {
  436. struct net_device *dev = data;
  437. struct pasemi_mac *mac = netdev_priv(dev);
  438. unsigned int reg;
  439. if (!(*mac->rx_status & PAS_STATUS_CAUSE_M))
  440. return IRQ_NONE;
  441. if (*mac->rx_status & PAS_STATUS_ERROR)
  442. printk("rx_status reported error\n");
  443. /* Don't reset packet count so it won't fire again but clear
  444. * all others.
  445. */
  446. pci_read_config_dword(mac->dma_pdev, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), &reg);
  447. reg = 0;
  448. if (*mac->rx_status & PAS_STATUS_SOFT)
  449. reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
  450. if (*mac->rx_status & PAS_STATUS_ERROR)
  451. reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
  452. if (*mac->rx_status & PAS_STATUS_TIMER)
  453. reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
  454. netif_rx_schedule(dev);
  455. pci_write_config_dword(mac->iob_pdev,
  456. PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
  457. return IRQ_HANDLED;
  458. }
  459. static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
  460. {
  461. struct net_device *dev = data;
  462. struct pasemi_mac *mac = netdev_priv(dev);
  463. unsigned int reg, pcnt;
  464. if (!(*mac->tx_status & PAS_STATUS_CAUSE_M))
  465. return IRQ_NONE;
  466. pasemi_mac_clean_tx(mac);
  467. pcnt = *mac->tx_status & PAS_STATUS_PCNT_M;
  468. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  469. if (*mac->tx_status & PAS_STATUS_SOFT)
  470. reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
  471. if (*mac->tx_status & PAS_STATUS_ERROR)
  472. reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
  473. pci_write_config_dword(mac->iob_pdev,
  474. PAS_IOB_DMA_TXCH_RESET(mac->dma_txch),
  475. reg);
  476. return IRQ_HANDLED;
  477. }
  478. static void pasemi_adjust_link(struct net_device *dev)
  479. {
  480. struct pasemi_mac *mac = netdev_priv(dev);
  481. int msg;
  482. unsigned int flags;
  483. unsigned int new_flags;
  484. if (!mac->phydev->link) {
  485. /* If no link, MAC speed settings don't matter. Just report
  486. * link down and return.
  487. */
  488. if (mac->link && netif_msg_link(mac))
  489. printk(KERN_INFO "%s: Link is down.\n", dev->name);
  490. netif_carrier_off(dev);
  491. mac->link = 0;
  492. return;
  493. } else
  494. netif_carrier_on(dev);
  495. pci_read_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, &flags);
  496. new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
  497. PAS_MAC_CFG_PCFG_TSR_M);
  498. if (!mac->phydev->duplex)
  499. new_flags |= PAS_MAC_CFG_PCFG_HD;
  500. switch (mac->phydev->speed) {
  501. case 1000:
  502. new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
  503. PAS_MAC_CFG_PCFG_TSR_1G;
  504. break;
  505. case 100:
  506. new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
  507. PAS_MAC_CFG_PCFG_TSR_100M;
  508. break;
  509. case 10:
  510. new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
  511. PAS_MAC_CFG_PCFG_TSR_10M;
  512. break;
  513. default:
  514. printk("Unsupported speed %d\n", mac->phydev->speed);
  515. }
  516. /* Print on link or speed/duplex change */
  517. msg = mac->link != mac->phydev->link || flags != new_flags;
  518. mac->duplex = mac->phydev->duplex;
  519. mac->speed = mac->phydev->speed;
  520. mac->link = mac->phydev->link;
  521. if (new_flags != flags)
  522. pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, new_flags);
  523. if (msg && netif_msg_link(mac))
  524. printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
  525. dev->name, mac->speed, mac->duplex ? "full" : "half");
  526. }
  527. static int pasemi_mac_phy_init(struct net_device *dev)
  528. {
  529. struct pasemi_mac *mac = netdev_priv(dev);
  530. struct device_node *dn, *phy_dn;
  531. struct phy_device *phydev;
  532. unsigned int phy_id;
  533. const phandle *ph;
  534. const unsigned int *prop;
  535. struct resource r;
  536. int ret;
  537. dn = pci_device_to_OF_node(mac->pdev);
  538. ph = of_get_property(dn, "phy-handle", NULL);
  539. if (!ph)
  540. return -ENODEV;
  541. phy_dn = of_find_node_by_phandle(*ph);
  542. prop = of_get_property(phy_dn, "reg", NULL);
  543. ret = of_address_to_resource(phy_dn->parent, 0, &r);
  544. if (ret)
  545. goto err;
  546. phy_id = *prop;
  547. snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id);
  548. of_node_put(phy_dn);
  549. mac->link = 0;
  550. mac->speed = 0;
  551. mac->duplex = -1;
  552. phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII);
  553. if (IS_ERR(phydev)) {
  554. printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
  555. return PTR_ERR(phydev);
  556. }
  557. mac->phydev = phydev;
  558. return 0;
  559. err:
  560. of_node_put(phy_dn);
  561. return -ENODEV;
  562. }
  563. static int pasemi_mac_open(struct net_device *dev)
  564. {
  565. struct pasemi_mac *mac = netdev_priv(dev);
  566. int base_irq;
  567. unsigned int flags;
  568. int ret;
  569. /* enable rx section */
  570. pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_RXCMD,
  571. PAS_DMA_COM_RXCMD_EN);
  572. /* enable tx section */
  573. pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_TXCMD,
  574. PAS_DMA_COM_TXCMD_EN);
  575. flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
  576. PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
  577. PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
  578. pci_write_config_dword(mac->pdev, PAS_MAC_CFG_TXP, flags);
  579. flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
  580. PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
  581. flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
  582. pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch),
  583. PAS_IOB_DMA_RXCH_CFG_CNTTH(1));
  584. pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_TXCH_CFG(mac->dma_txch),
  585. PAS_IOB_DMA_TXCH_CFG_CNTTH(32));
  586. /* Clear out any residual packet count state from firmware */
  587. pasemi_mac_restart_rx_intr(mac);
  588. pasemi_mac_restart_tx_intr(mac);
  589. /* 0xffffff is max value, about 16ms */
  590. pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_COM_TIMEOUTCFG,
  591. PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff));
  592. pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags);
  593. ret = pasemi_mac_setup_rx_resources(dev);
  594. if (ret)
  595. goto out_rx_resources;
  596. ret = pasemi_mac_setup_tx_resources(dev);
  597. if (ret)
  598. goto out_tx_resources;
  599. pci_write_config_dword(mac->pdev, PAS_MAC_IPC_CHNL,
  600. PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) |
  601. PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch));
  602. /* enable rx if */
  603. pci_write_config_dword(mac->dma_pdev,
  604. PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  605. PAS_DMA_RXINT_RCMDSTA_EN);
  606. /* enable rx channel */
  607. pci_write_config_dword(mac->dma_pdev,
  608. PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
  609. PAS_DMA_RXCHAN_CCMDSTA_EN |
  610. PAS_DMA_RXCHAN_CCMDSTA_DU);
  611. /* enable tx channel */
  612. pci_write_config_dword(mac->dma_pdev,
  613. PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
  614. PAS_DMA_TXCHAN_TCMDSTA_EN);
  615. pasemi_mac_replenish_rx_ring(dev);
  616. ret = pasemi_mac_phy_init(dev);
  617. /* Some configs don't have PHYs (XAUI etc), so don't complain about
  618. * failed init due to -ENODEV.
  619. */
  620. if (ret && ret != -ENODEV)
  621. dev_warn(&mac->pdev->dev, "phy init failed: %d\n", ret);
  622. netif_start_queue(dev);
  623. netif_poll_enable(dev);
  624. /* Interrupts are a bit different for our DMA controller: While
  625. * it's got one a regular PCI device header, the interrupt there
  626. * is really the base of the range it's using. Each tx and rx
  627. * channel has it's own interrupt source.
  628. */
  629. base_irq = virq_to_hw(mac->dma_pdev->irq);
  630. mac->tx_irq = irq_create_mapping(NULL, base_irq + mac->dma_txch);
  631. mac->rx_irq = irq_create_mapping(NULL, base_irq + 20 + mac->dma_txch);
  632. ret = request_irq(mac->tx_irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
  633. mac->tx->irq_name, dev);
  634. if (ret) {
  635. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  636. base_irq + mac->dma_txch, ret);
  637. goto out_tx_int;
  638. }
  639. ret = request_irq(mac->rx_irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
  640. mac->rx->irq_name, dev);
  641. if (ret) {
  642. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  643. base_irq + 20 + mac->dma_rxch, ret);
  644. goto out_rx_int;
  645. }
  646. if (mac->phydev)
  647. phy_start(mac->phydev);
  648. return 0;
  649. out_rx_int:
  650. free_irq(mac->tx_irq, dev);
  651. out_tx_int:
  652. netif_poll_disable(dev);
  653. netif_stop_queue(dev);
  654. pasemi_mac_free_tx_resources(dev);
  655. out_tx_resources:
  656. pasemi_mac_free_rx_resources(dev);
  657. out_rx_resources:
  658. return ret;
  659. }
  660. #define MAX_RETRIES 5000
  661. static int pasemi_mac_close(struct net_device *dev)
  662. {
  663. struct pasemi_mac *mac = netdev_priv(dev);
  664. unsigned int stat;
  665. int retries;
  666. if (mac->phydev) {
  667. phy_stop(mac->phydev);
  668. phy_disconnect(mac->phydev);
  669. }
  670. netif_stop_queue(dev);
  671. /* Clean out any pending buffers */
  672. pasemi_mac_clean_tx(mac);
  673. pasemi_mac_clean_rx(mac, RX_RING_SIZE);
  674. /* Disable interface */
  675. pci_write_config_dword(mac->dma_pdev,
  676. PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
  677. PAS_DMA_TXCHAN_TCMDSTA_ST);
  678. pci_write_config_dword(mac->dma_pdev,
  679. PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  680. PAS_DMA_RXINT_RCMDSTA_ST);
  681. pci_write_config_dword(mac->dma_pdev,
  682. PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
  683. PAS_DMA_RXCHAN_CCMDSTA_ST);
  684. for (retries = 0; retries < MAX_RETRIES; retries++) {
  685. pci_read_config_dword(mac->dma_pdev,
  686. PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
  687. &stat);
  688. if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT))
  689. break;
  690. cond_resched();
  691. }
  692. if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)
  693. dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
  694. for (retries = 0; retries < MAX_RETRIES; retries++) {
  695. pci_read_config_dword(mac->dma_pdev,
  696. PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
  697. &stat);
  698. if (!(stat & PAS_DMA_RXCHAN_CCMDSTA_ACT))
  699. break;
  700. cond_resched();
  701. }
  702. if (stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)
  703. dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
  704. for (retries = 0; retries < MAX_RETRIES; retries++) {
  705. pci_read_config_dword(mac->dma_pdev,
  706. PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  707. &stat);
  708. if (!(stat & PAS_DMA_RXINT_RCMDSTA_ACT))
  709. break;
  710. cond_resched();
  711. }
  712. if (stat & PAS_DMA_RXINT_RCMDSTA_ACT)
  713. dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
  714. /* Then, disable the channel. This must be done separately from
  715. * stopping, since you can't disable when active.
  716. */
  717. pci_write_config_dword(mac->dma_pdev,
  718. PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0);
  719. pci_write_config_dword(mac->dma_pdev,
  720. PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0);
  721. pci_write_config_dword(mac->dma_pdev,
  722. PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
  723. free_irq(mac->tx_irq, dev);
  724. free_irq(mac->rx_irq, dev);
  725. /* Free resources */
  726. pasemi_mac_free_rx_resources(dev);
  727. pasemi_mac_free_tx_resources(dev);
  728. return 0;
  729. }
  730. static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
  731. {
  732. struct pasemi_mac *mac = netdev_priv(dev);
  733. struct pasemi_mac_txring *txring;
  734. struct pasemi_mac_buffer *info;
  735. struct pas_dma_xct_descr *dp;
  736. u64 dflags;
  737. dma_addr_t map;
  738. int flags;
  739. dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_SS | XCT_MACTX_CRC_PAD;
  740. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  741. const unsigned char *nh = skb_network_header(skb);
  742. switch (ip_hdr(skb)->protocol) {
  743. case IPPROTO_TCP:
  744. dflags |= XCT_MACTX_CSUM_TCP;
  745. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  746. dflags |= XCT_MACTX_IPO(nh - skb->data);
  747. break;
  748. case IPPROTO_UDP:
  749. dflags |= XCT_MACTX_CSUM_UDP;
  750. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  751. dflags |= XCT_MACTX_IPO(nh - skb->data);
  752. break;
  753. }
  754. }
  755. map = pci_map_single(mac->dma_pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
  756. if (dma_mapping_error(map))
  757. return NETDEV_TX_BUSY;
  758. txring = mac->tx;
  759. spin_lock_irqsave(&txring->lock, flags);
  760. if (txring->next_to_clean - txring->next_to_use == TX_RING_SIZE) {
  761. spin_unlock_irqrestore(&txring->lock, flags);
  762. pasemi_mac_clean_tx(mac);
  763. pasemi_mac_restart_tx_intr(mac);
  764. spin_lock_irqsave(&txring->lock, flags);
  765. if (txring->next_to_clean - txring->next_to_use ==
  766. TX_RING_SIZE) {
  767. /* Still no room -- stop the queue and wait for tx
  768. * intr when there's room.
  769. */
  770. netif_stop_queue(dev);
  771. goto out_err;
  772. }
  773. }
  774. dp = &TX_DESC(mac, txring->next_to_use);
  775. info = &TX_DESC_INFO(mac, txring->next_to_use);
  776. dp->mactx = dflags | XCT_MACTX_LLEN(skb->len);
  777. dp->ptr = XCT_PTR_LEN(skb->len) | XCT_PTR_ADDR(map);
  778. info->dma = map;
  779. info->skb = skb;
  780. txring->next_to_use++;
  781. mac->stats.tx_packets++;
  782. mac->stats.tx_bytes += skb->len;
  783. spin_unlock_irqrestore(&txring->lock, flags);
  784. pci_write_config_dword(mac->dma_pdev,
  785. PAS_DMA_TXCHAN_INCR(mac->dma_txch), 1);
  786. return NETDEV_TX_OK;
  787. out_err:
  788. spin_unlock_irqrestore(&txring->lock, flags);
  789. pci_unmap_single(mac->dma_pdev, map, skb->len, PCI_DMA_TODEVICE);
  790. return NETDEV_TX_BUSY;
  791. }
  792. static struct net_device_stats *pasemi_mac_get_stats(struct net_device *dev)
  793. {
  794. struct pasemi_mac *mac = netdev_priv(dev);
  795. return &mac->stats;
  796. }
  797. static void pasemi_mac_set_rx_mode(struct net_device *dev)
  798. {
  799. struct pasemi_mac *mac = netdev_priv(dev);
  800. unsigned int flags;
  801. pci_read_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, &flags);
  802. /* Set promiscuous */
  803. if (dev->flags & IFF_PROMISC)
  804. flags |= PAS_MAC_CFG_PCFG_PR;
  805. else
  806. flags &= ~PAS_MAC_CFG_PCFG_PR;
  807. pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags);
  808. }
  809. static int pasemi_mac_poll(struct net_device *dev, int *budget)
  810. {
  811. int pkts, limit = min(*budget, dev->quota);
  812. struct pasemi_mac *mac = netdev_priv(dev);
  813. pkts = pasemi_mac_clean_rx(mac, limit);
  814. dev->quota -= pkts;
  815. *budget -= pkts;
  816. if (pkts < limit) {
  817. /* all done, no more packets present */
  818. netif_rx_complete(dev);
  819. pasemi_mac_restart_rx_intr(mac);
  820. return 0;
  821. } else {
  822. /* used up our quantum, so reschedule */
  823. return 1;
  824. }
  825. }
  826. static int __devinit
  827. pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  828. {
  829. static int index = 0;
  830. struct net_device *dev;
  831. struct pasemi_mac *mac;
  832. int err;
  833. err = pci_enable_device(pdev);
  834. if (err)
  835. return err;
  836. dev = alloc_etherdev(sizeof(struct pasemi_mac));
  837. if (dev == NULL) {
  838. dev_err(&pdev->dev,
  839. "pasemi_mac: Could not allocate ethernet device.\n");
  840. err = -ENOMEM;
  841. goto out_disable_device;
  842. }
  843. SET_MODULE_OWNER(dev);
  844. pci_set_drvdata(pdev, dev);
  845. SET_NETDEV_DEV(dev, &pdev->dev);
  846. mac = netdev_priv(dev);
  847. mac->pdev = pdev;
  848. mac->netdev = dev;
  849. mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
  850. if (!mac->dma_pdev) {
  851. dev_err(&pdev->dev, "Can't find DMA Controller\n");
  852. err = -ENODEV;
  853. goto out_free_netdev;
  854. }
  855. mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
  856. if (!mac->iob_pdev) {
  857. dev_err(&pdev->dev, "Can't find I/O Bridge\n");
  858. err = -ENODEV;
  859. goto out_put_dma_pdev;
  860. }
  861. /* These should come out of the device tree eventually */
  862. mac->dma_txch = index;
  863. mac->dma_rxch = index;
  864. /* We probe GMAC before XAUI, but the DMA interfaces are
  865. * in XAUI, GMAC order.
  866. */
  867. if (index < 4)
  868. mac->dma_if = index + 2;
  869. else
  870. mac->dma_if = index - 4;
  871. index++;
  872. switch (pdev->device) {
  873. case 0xa005:
  874. mac->type = MAC_TYPE_GMAC;
  875. break;
  876. case 0xa006:
  877. mac->type = MAC_TYPE_XAUI;
  878. break;
  879. default:
  880. err = -ENODEV;
  881. goto out;
  882. }
  883. /* get mac addr from device tree */
  884. if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
  885. err = -ENODEV;
  886. goto out;
  887. }
  888. memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
  889. dev->open = pasemi_mac_open;
  890. dev->stop = pasemi_mac_close;
  891. dev->hard_start_xmit = pasemi_mac_start_tx;
  892. dev->get_stats = pasemi_mac_get_stats;
  893. dev->set_multicast_list = pasemi_mac_set_rx_mode;
  894. dev->weight = 64;
  895. dev->poll = pasemi_mac_poll;
  896. dev->features = NETIF_F_HW_CSUM;
  897. /* The dma status structure is located in the I/O bridge, and
  898. * is cache coherent.
  899. */
  900. if (!dma_status)
  901. /* XXXOJN This should come from the device tree */
  902. dma_status = __ioremap(0xfd800000, 0x1000, 0);
  903. mac->rx_status = &dma_status->rx_sta[mac->dma_rxch];
  904. mac->tx_status = &dma_status->tx_sta[mac->dma_txch];
  905. mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
  906. /* Enable most messages by default */
  907. mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  908. err = register_netdev(dev);
  909. if (err) {
  910. dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
  911. err);
  912. goto out;
  913. } else
  914. printk(KERN_INFO "%s: PA Semi %s: intf %d, txch %d, rxch %d, "
  915. "hw addr %02x:%02x:%02x:%02x:%02x:%02x\n",
  916. dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
  917. mac->dma_if, mac->dma_txch, mac->dma_rxch,
  918. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  919. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  920. return err;
  921. out:
  922. pci_dev_put(mac->iob_pdev);
  923. out_put_dma_pdev:
  924. pci_dev_put(mac->dma_pdev);
  925. out_free_netdev:
  926. free_netdev(dev);
  927. out_disable_device:
  928. pci_disable_device(pdev);
  929. return err;
  930. }
  931. static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
  932. {
  933. struct net_device *netdev = pci_get_drvdata(pdev);
  934. struct pasemi_mac *mac;
  935. if (!netdev)
  936. return;
  937. mac = netdev_priv(netdev);
  938. unregister_netdev(netdev);
  939. pci_disable_device(pdev);
  940. pci_dev_put(mac->dma_pdev);
  941. pci_dev_put(mac->iob_pdev);
  942. pci_set_drvdata(pdev, NULL);
  943. free_netdev(netdev);
  944. }
  945. static struct pci_device_id pasemi_mac_pci_tbl[] = {
  946. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
  947. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
  948. { },
  949. };
  950. MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
  951. static struct pci_driver pasemi_mac_driver = {
  952. .name = "pasemi_mac",
  953. .id_table = pasemi_mac_pci_tbl,
  954. .probe = pasemi_mac_probe,
  955. .remove = __devexit_p(pasemi_mac_remove),
  956. };
  957. static void __exit pasemi_mac_cleanup_module(void)
  958. {
  959. pci_unregister_driver(&pasemi_mac_driver);
  960. __iounmap(dma_status);
  961. dma_status = NULL;
  962. }
  963. int pasemi_mac_init_module(void)
  964. {
  965. return pci_register_driver(&pasemi_mac_driver);
  966. }
  967. module_init(pasemi_mac_init_module);
  968. module_exit(pasemi_mac_cleanup_module);