netxen_nic_init.c 40 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. unsigned long last_schedule_time;
  43. #define NETXEN_MAX_CRB_XFORM 60
  44. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  45. #define NETXEN_ADDR_ERROR (0xffffffff)
  46. #define crb_addr_transform(name) \
  47. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  48. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  49. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  50. static inline void
  51. netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  52. unsigned long off, int *data)
  53. {
  54. void __iomem *addr = pci_base_offset(adapter, off);
  55. writel(*data, addr);
  56. }
  57. static void crb_addr_transform_setup(void)
  58. {
  59. crb_addr_transform(XDMA);
  60. crb_addr_transform(TIMR);
  61. crb_addr_transform(SRE);
  62. crb_addr_transform(SQN3);
  63. crb_addr_transform(SQN2);
  64. crb_addr_transform(SQN1);
  65. crb_addr_transform(SQN0);
  66. crb_addr_transform(SQS3);
  67. crb_addr_transform(SQS2);
  68. crb_addr_transform(SQS1);
  69. crb_addr_transform(SQS0);
  70. crb_addr_transform(RPMX7);
  71. crb_addr_transform(RPMX6);
  72. crb_addr_transform(RPMX5);
  73. crb_addr_transform(RPMX4);
  74. crb_addr_transform(RPMX3);
  75. crb_addr_transform(RPMX2);
  76. crb_addr_transform(RPMX1);
  77. crb_addr_transform(RPMX0);
  78. crb_addr_transform(ROMUSB);
  79. crb_addr_transform(SN);
  80. crb_addr_transform(QMN);
  81. crb_addr_transform(QMS);
  82. crb_addr_transform(PGNI);
  83. crb_addr_transform(PGND);
  84. crb_addr_transform(PGN3);
  85. crb_addr_transform(PGN2);
  86. crb_addr_transform(PGN1);
  87. crb_addr_transform(PGN0);
  88. crb_addr_transform(PGSI);
  89. crb_addr_transform(PGSD);
  90. crb_addr_transform(PGS3);
  91. crb_addr_transform(PGS2);
  92. crb_addr_transform(PGS1);
  93. crb_addr_transform(PGS0);
  94. crb_addr_transform(PS);
  95. crb_addr_transform(PH);
  96. crb_addr_transform(NIU);
  97. crb_addr_transform(I2Q);
  98. crb_addr_transform(EG);
  99. crb_addr_transform(MN);
  100. crb_addr_transform(MS);
  101. crb_addr_transform(CAS2);
  102. crb_addr_transform(CAS1);
  103. crb_addr_transform(CAS0);
  104. crb_addr_transform(CAM);
  105. crb_addr_transform(C2C1);
  106. crb_addr_transform(C2C0);
  107. crb_addr_transform(SMB);
  108. }
  109. int netxen_init_firmware(struct netxen_adapter *adapter)
  110. {
  111. u32 state = 0, loops = 0, err = 0;
  112. /* Window 1 call */
  113. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  114. if (state == PHAN_INITIALIZE_ACK)
  115. return 0;
  116. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  117. udelay(100);
  118. /* Window 1 call */
  119. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  120. loops++;
  121. }
  122. if (loops >= 2000) {
  123. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  124. state);
  125. err = -EIO;
  126. return err;
  127. }
  128. /* Window 1 call */
  129. writel(MPORT_MULTI_FUNCTION_MODE,
  130. NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE));
  131. writel(PHAN_INITIALIZE_ACK,
  132. NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  133. return err;
  134. }
  135. #define NETXEN_ADDR_LIMIT 0xffffffffULL
  136. void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
  137. struct pci_dev **used_dev)
  138. {
  139. void *addr;
  140. addr = pci_alloc_consistent(pdev, sz, ptr);
  141. if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) {
  142. *used_dev = pdev;
  143. return addr;
  144. }
  145. pci_free_consistent(pdev, sz, addr, *ptr);
  146. addr = pci_alloc_consistent(NULL, sz, ptr);
  147. *used_dev = NULL;
  148. return addr;
  149. }
  150. void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
  151. {
  152. int ctxid, ring;
  153. u32 i;
  154. u32 num_rx_bufs = 0;
  155. struct netxen_rcv_desc_ctx *rcv_desc;
  156. DPRINTK(INFO, "initializing some queues: %p\n", adapter);
  157. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  158. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  159. struct netxen_rx_buffer *rx_buf;
  160. rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring];
  161. rcv_desc->rcv_free = rcv_desc->max_rx_desc_count;
  162. rcv_desc->begin_alloc = 0;
  163. rx_buf = rcv_desc->rx_buf_arr;
  164. num_rx_bufs = rcv_desc->max_rx_desc_count;
  165. /*
  166. * Now go through all of them, set reference handles
  167. * and put them in the queues.
  168. */
  169. for (i = 0; i < num_rx_bufs; i++) {
  170. rx_buf->ref_handle = i;
  171. rx_buf->state = NETXEN_BUFFER_FREE;
  172. DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:"
  173. "%p\n", ctxid, i, rx_buf);
  174. rx_buf++;
  175. }
  176. }
  177. }
  178. }
  179. void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
  180. {
  181. int ports = 0;
  182. struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
  183. if (netxen_nic_get_board_info(adapter) != 0)
  184. printk("%s: Error getting board config info.\n",
  185. netxen_nic_driver_name);
  186. get_brd_port_by_type(board_info->board_type, &ports);
  187. if (ports == 0)
  188. printk(KERN_ERR "%s: Unknown board type\n",
  189. netxen_nic_driver_name);
  190. adapter->ahw.max_ports = ports;
  191. }
  192. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  193. {
  194. switch (adapter->ahw.board_type) {
  195. case NETXEN_NIC_GBE:
  196. adapter->enable_phy_interrupts =
  197. netxen_niu_gbe_enable_phy_interrupts;
  198. adapter->disable_phy_interrupts =
  199. netxen_niu_gbe_disable_phy_interrupts;
  200. adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
  201. adapter->macaddr_set = netxen_niu_macaddr_set;
  202. adapter->set_mtu = netxen_nic_set_mtu_gb;
  203. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  204. adapter->unset_promisc = netxen_niu_set_promiscuous_mode;
  205. adapter->phy_read = netxen_niu_gbe_phy_read;
  206. adapter->phy_write = netxen_niu_gbe_phy_write;
  207. adapter->init_niu = netxen_nic_init_niu_gb;
  208. adapter->stop_port = netxen_niu_disable_gbe_port;
  209. break;
  210. case NETXEN_NIC_XGBE:
  211. adapter->enable_phy_interrupts =
  212. netxen_niu_xgbe_enable_phy_interrupts;
  213. adapter->disable_phy_interrupts =
  214. netxen_niu_xgbe_disable_phy_interrupts;
  215. adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
  216. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  217. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  218. adapter->init_port = netxen_niu_xg_init_port;
  219. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  220. adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
  221. adapter->stop_port = netxen_niu_disable_xg_port;
  222. break;
  223. default:
  224. break;
  225. }
  226. }
  227. /*
  228. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  229. * address to external PCI CRB address.
  230. */
  231. u32 netxen_decode_crb_addr(u32 addr)
  232. {
  233. int i;
  234. u32 base_addr, offset, pci_base;
  235. crb_addr_transform_setup();
  236. pci_base = NETXEN_ADDR_ERROR;
  237. base_addr = addr & 0xfff00000;
  238. offset = addr & 0x000fffff;
  239. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  240. if (crb_addr_xform[i] == base_addr) {
  241. pci_base = i << 20;
  242. break;
  243. }
  244. }
  245. if (pci_base == NETXEN_ADDR_ERROR)
  246. return pci_base;
  247. else
  248. return (pci_base + offset);
  249. }
  250. static long rom_max_timeout = 100;
  251. static long rom_lock_timeout = 10000;
  252. static long rom_write_timeout = 700;
  253. static inline int rom_lock(struct netxen_adapter *adapter)
  254. {
  255. int iter;
  256. u32 done = 0;
  257. int timeout = 0;
  258. while (!done) {
  259. /* acquire semaphore2 from PCI HW block */
  260. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  261. &done);
  262. if (done == 1)
  263. break;
  264. if (timeout >= rom_lock_timeout)
  265. return -EIO;
  266. timeout++;
  267. /*
  268. * Yield CPU
  269. */
  270. if (!in_atomic())
  271. schedule();
  272. else {
  273. for (iter = 0; iter < 20; iter++)
  274. cpu_relax(); /*This a nop instr on i386 */
  275. }
  276. }
  277. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  278. return 0;
  279. }
  280. int netxen_wait_rom_done(struct netxen_adapter *adapter)
  281. {
  282. long timeout = 0;
  283. long done = 0;
  284. while (done == 0) {
  285. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  286. done &= 2;
  287. timeout++;
  288. if (timeout >= rom_max_timeout) {
  289. printk("Timeout reached waiting for rom done");
  290. return -EIO;
  291. }
  292. }
  293. return 0;
  294. }
  295. static inline int netxen_rom_wren(struct netxen_adapter *adapter)
  296. {
  297. /* Set write enable latch in ROM status register */
  298. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  299. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  300. M25P_INSTR_WREN);
  301. if (netxen_wait_rom_done(adapter)) {
  302. return -1;
  303. }
  304. return 0;
  305. }
  306. static inline unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  307. unsigned int addr)
  308. {
  309. unsigned int data = 0xdeaddead;
  310. data = netxen_nic_reg_read(adapter, addr);
  311. return data;
  312. }
  313. static inline int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  314. {
  315. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  316. M25P_INSTR_RDSR);
  317. if (netxen_wait_rom_done(adapter)) {
  318. return -1;
  319. }
  320. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  321. }
  322. static inline void netxen_rom_unlock(struct netxen_adapter *adapter)
  323. {
  324. u32 val;
  325. /* release semaphore2 */
  326. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  327. }
  328. int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  329. {
  330. long timeout = 0;
  331. long wip = 1;
  332. int val;
  333. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  334. while (wip != 0) {
  335. val = netxen_do_rom_rdsr(adapter);
  336. wip = val & 1;
  337. timeout++;
  338. if (timeout > rom_max_timeout) {
  339. return -1;
  340. }
  341. }
  342. return 0;
  343. }
  344. static inline int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  345. int data)
  346. {
  347. if (netxen_rom_wren(adapter)) {
  348. return -1;
  349. }
  350. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  351. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  352. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  353. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  354. M25P_INSTR_PP);
  355. if (netxen_wait_rom_done(adapter)) {
  356. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  357. return -1;
  358. }
  359. return netxen_rom_wip_poll(adapter);
  360. }
  361. static inline int
  362. do_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  363. {
  364. if (jiffies > (last_schedule_time + (8 * HZ))) {
  365. last_schedule_time = jiffies;
  366. schedule();
  367. }
  368. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  369. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  370. udelay(100); /* prevent bursting on CRB */
  371. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  372. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  373. if (netxen_wait_rom_done(adapter)) {
  374. printk("Error waiting for rom done\n");
  375. return -EIO;
  376. }
  377. /* reset abyte_cnt and dummy_byte_cnt */
  378. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  379. udelay(100); /* prevent bursting on CRB */
  380. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  381. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  382. return 0;
  383. }
  384. static inline int
  385. do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  386. u8 *bytes, size_t size)
  387. {
  388. int addridx;
  389. int ret = 0;
  390. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  391. ret = do_rom_fast_read(adapter, addridx, (int *)bytes);
  392. if (ret != 0)
  393. break;
  394. *(int *)bytes = cpu_to_le32(*(int *)bytes);
  395. bytes += 4;
  396. }
  397. return ret;
  398. }
  399. int
  400. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  401. u8 *bytes, size_t size)
  402. {
  403. int ret;
  404. ret = rom_lock(adapter);
  405. if (ret < 0)
  406. return ret;
  407. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  408. netxen_rom_unlock(adapter);
  409. return ret;
  410. }
  411. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  412. {
  413. int ret;
  414. if (rom_lock(adapter) != 0)
  415. return -EIO;
  416. ret = do_rom_fast_read(adapter, addr, valp);
  417. netxen_rom_unlock(adapter);
  418. return ret;
  419. }
  420. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  421. {
  422. int ret = 0;
  423. if (rom_lock(adapter) != 0) {
  424. return -1;
  425. }
  426. ret = do_rom_fast_write(adapter, addr, data);
  427. netxen_rom_unlock(adapter);
  428. return ret;
  429. }
  430. static inline int do_rom_fast_write_words(struct netxen_adapter *adapter,
  431. int addr, u8 *bytes, size_t size)
  432. {
  433. int addridx = addr;
  434. int ret = 0;
  435. while (addridx < (addr + size)) {
  436. int last_attempt = 0;
  437. int timeout = 0;
  438. int data;
  439. data = le32_to_cpu((*(u32*)bytes));
  440. ret = do_rom_fast_write(adapter, addridx, data);
  441. if (ret < 0)
  442. return ret;
  443. while(1) {
  444. int data1;
  445. ret = do_rom_fast_read(adapter, addridx, &data1);
  446. if (ret < 0)
  447. return ret;
  448. if (data1 == data)
  449. break;
  450. if (timeout++ >= rom_write_timeout) {
  451. if (last_attempt++ < 4) {
  452. ret = do_rom_fast_write(adapter,
  453. addridx, data);
  454. if (ret < 0)
  455. return ret;
  456. }
  457. else {
  458. printk(KERN_INFO "Data write did not "
  459. "succeed at address 0x%x\n", addridx);
  460. break;
  461. }
  462. }
  463. }
  464. bytes += 4;
  465. addridx += 4;
  466. }
  467. return ret;
  468. }
  469. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  470. u8 *bytes, size_t size)
  471. {
  472. int ret = 0;
  473. ret = rom_lock(adapter);
  474. if (ret < 0)
  475. return ret;
  476. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  477. netxen_rom_unlock(adapter);
  478. return ret;
  479. }
  480. int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  481. {
  482. int ret;
  483. ret = netxen_rom_wren(adapter);
  484. if (ret < 0)
  485. return ret;
  486. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  487. netxen_crb_writelit_adapter(adapter,
  488. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  489. ret = netxen_wait_rom_done(adapter);
  490. if (ret < 0)
  491. return ret;
  492. return netxen_rom_wip_poll(adapter);
  493. }
  494. int netxen_rom_rdsr(struct netxen_adapter *adapter)
  495. {
  496. int ret;
  497. ret = rom_lock(adapter);
  498. if (ret < 0)
  499. return ret;
  500. ret = netxen_do_rom_rdsr(adapter);
  501. netxen_rom_unlock(adapter);
  502. return ret;
  503. }
  504. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  505. {
  506. int ret = FLASH_SUCCESS;
  507. int val;
  508. char *buffer = kmalloc(FLASH_SECTOR_SIZE, GFP_KERNEL);
  509. if (!buffer)
  510. return -ENOMEM;
  511. /* unlock sector 63 */
  512. val = netxen_rom_rdsr(adapter);
  513. val = val & 0xe3;
  514. ret = netxen_rom_wrsr(adapter, val);
  515. if (ret != FLASH_SUCCESS)
  516. goto out_kfree;
  517. ret = netxen_rom_wip_poll(adapter);
  518. if (ret != FLASH_SUCCESS)
  519. goto out_kfree;
  520. /* copy sector 0 to sector 63 */
  521. ret = netxen_rom_fast_read_words(adapter, CRBINIT_START,
  522. buffer, FLASH_SECTOR_SIZE);
  523. if (ret != FLASH_SUCCESS)
  524. goto out_kfree;
  525. ret = netxen_rom_fast_write_words(adapter, FIXED_START,
  526. buffer, FLASH_SECTOR_SIZE);
  527. if (ret != FLASH_SUCCESS)
  528. goto out_kfree;
  529. /* lock sector 63 */
  530. val = netxen_rom_rdsr(adapter);
  531. if (!(val & 0x8)) {
  532. val |= (0x1 << 2);
  533. /* lock sector 63 */
  534. if (netxen_rom_wrsr(adapter, val) == 0) {
  535. ret = netxen_rom_wip_poll(adapter);
  536. if (ret != FLASH_SUCCESS)
  537. goto out_kfree;
  538. /* lock SR writes */
  539. ret = netxen_rom_wip_poll(adapter);
  540. if (ret != FLASH_SUCCESS)
  541. goto out_kfree;
  542. }
  543. }
  544. out_kfree:
  545. kfree(buffer);
  546. return ret;
  547. }
  548. int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  549. {
  550. netxen_rom_wren(adapter);
  551. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  552. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  553. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  554. M25P_INSTR_SE);
  555. if (netxen_wait_rom_done(adapter)) {
  556. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  557. return -1;
  558. }
  559. return netxen_rom_wip_poll(adapter);
  560. }
  561. void check_erased_flash(struct netxen_adapter *adapter, int addr)
  562. {
  563. int i;
  564. int val;
  565. int count = 0, erased_errors = 0;
  566. int range;
  567. range = (addr == USER_START) ? FIXED_START : addr + FLASH_SECTOR_SIZE;
  568. for (i = addr; i < range; i += 4) {
  569. netxen_rom_fast_read(adapter, i, &val);
  570. if (val != 0xffffffff)
  571. erased_errors++;
  572. count++;
  573. }
  574. if (erased_errors)
  575. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  576. "for sector address: %x\n", erased_errors, count, addr);
  577. }
  578. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  579. {
  580. int ret = 0;
  581. if (rom_lock(adapter) != 0) {
  582. return -1;
  583. }
  584. ret = netxen_do_rom_se(adapter, addr);
  585. netxen_rom_unlock(adapter);
  586. msleep(30);
  587. check_erased_flash(adapter, addr);
  588. return ret;
  589. }
  590. int
  591. netxen_flash_erase_sections(struct netxen_adapter *adapter, int start, int end)
  592. {
  593. int ret = FLASH_SUCCESS;
  594. int i;
  595. for (i = start; i < end; i++) {
  596. ret = netxen_rom_se(adapter, i * FLASH_SECTOR_SIZE);
  597. if (ret)
  598. break;
  599. ret = netxen_rom_wip_poll(adapter);
  600. if (ret < 0)
  601. return ret;
  602. }
  603. return ret;
  604. }
  605. int
  606. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  607. {
  608. int ret = FLASH_SUCCESS;
  609. int start, end;
  610. start = SECONDARY_START / FLASH_SECTOR_SIZE;
  611. end = USER_START / FLASH_SECTOR_SIZE;
  612. ret = netxen_flash_erase_sections(adapter, start, end);
  613. return ret;
  614. }
  615. int
  616. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  617. {
  618. int ret = FLASH_SUCCESS;
  619. int start, end;
  620. start = PRIMARY_START / FLASH_SECTOR_SIZE;
  621. end = SECONDARY_START / FLASH_SECTOR_SIZE;
  622. ret = netxen_flash_erase_sections(adapter, start, end);
  623. return ret;
  624. }
  625. void netxen_halt_pegs(struct netxen_adapter *adapter)
  626. {
  627. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  628. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  629. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  630. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  631. }
  632. int netxen_flash_unlock(struct netxen_adapter *adapter)
  633. {
  634. int ret = 0;
  635. ret = netxen_rom_wrsr(adapter, 0);
  636. if (ret < 0)
  637. return ret;
  638. ret = netxen_rom_wren(adapter);
  639. if (ret < 0)
  640. return ret;
  641. return ret;
  642. }
  643. #define NETXEN_BOARDTYPE 0x4008
  644. #define NETXEN_BOARDNUM 0x400c
  645. #define NETXEN_CHIPNUM 0x4010
  646. #define NETXEN_ROMBUS_RESET 0xFFFFFFFF
  647. #define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL
  648. #define NETXEN_ROM_FOUND_INIT 0x400
  649. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  650. {
  651. int addr, val, status;
  652. int n, i;
  653. int init_delay = 0;
  654. struct crb_addr_pair *buf;
  655. u32 off;
  656. /* resetall */
  657. status = netxen_nic_get_board_info(adapter);
  658. if (status)
  659. printk("%s: netxen_pinit_from_rom: Error getting board info\n",
  660. netxen_nic_driver_name);
  661. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  662. NETXEN_ROMBUS_RESET);
  663. if (verbose) {
  664. int val;
  665. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  666. printk("P2 ROM board type: 0x%08x\n", val);
  667. else
  668. printk("Could not read board type\n");
  669. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  670. printk("P2 ROM board num: 0x%08x\n", val);
  671. else
  672. printk("Could not read board number\n");
  673. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  674. printk("P2 ROM chip num: 0x%08x\n", val);
  675. else
  676. printk("Could not read chip number\n");
  677. }
  678. if (netxen_rom_fast_read(adapter, 0, &n) == 0
  679. && (n & NETXEN_ROM_FIRST_BARRIER)) {
  680. n &= ~NETXEN_ROM_ROUNDUP;
  681. if (n < NETXEN_ROM_FOUND_INIT) {
  682. if (verbose)
  683. printk("%s: %d CRB init values found"
  684. " in ROM.\n", netxen_nic_driver_name, n);
  685. } else {
  686. printk("%s:n=0x%x Error! NetXen card flash not"
  687. " initialized.\n", __FUNCTION__, n);
  688. return -EIO;
  689. }
  690. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  691. if (buf == NULL) {
  692. printk("%s: netxen_pinit_from_rom: Unable to calloc "
  693. "memory.\n", netxen_nic_driver_name);
  694. return -ENOMEM;
  695. }
  696. for (i = 0; i < n; i++) {
  697. if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0
  698. || netxen_rom_fast_read(adapter, 8 * i + 8,
  699. &addr) != 0)
  700. return -EIO;
  701. buf[i].addr = addr;
  702. buf[i].data = val;
  703. if (verbose)
  704. printk("%s: PCI: 0x%08x == 0x%08x\n",
  705. netxen_nic_driver_name, (unsigned int)
  706. netxen_decode_crb_addr(addr), val);
  707. }
  708. for (i = 0; i < n; i++) {
  709. off = netxen_decode_crb_addr(buf[i].addr);
  710. if (off == NETXEN_ADDR_ERROR) {
  711. printk(KERN_ERR"CRB init value out of range %x\n",
  712. buf[i].addr);
  713. continue;
  714. }
  715. off += NETXEN_PCI_CRBSPACE;
  716. /* skipping cold reboot MAGIC */
  717. if (off == NETXEN_CAM_RAM(0x1fc))
  718. continue;
  719. /* After writing this register, HW needs time for CRB */
  720. /* to quiet down (else crb_window returns 0xffffffff) */
  721. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  722. init_delay = 1;
  723. /* hold xdma in reset also */
  724. buf[i].data = NETXEN_NIC_XDMA_RESET;
  725. }
  726. if (ADDR_IN_WINDOW1(off)) {
  727. writel(buf[i].data,
  728. NETXEN_CRB_NORMALIZE(adapter, off));
  729. } else {
  730. netxen_nic_pci_change_crbwindow(adapter, 0);
  731. writel(buf[i].data,
  732. pci_base_offset(adapter, off));
  733. netxen_nic_pci_change_crbwindow(adapter, 1);
  734. }
  735. if (init_delay == 1) {
  736. ssleep(1);
  737. init_delay = 0;
  738. }
  739. msleep(1);
  740. }
  741. kfree(buf);
  742. /* disable_peg_cache_all */
  743. /* unreset_net_cache */
  744. netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val,
  745. 4);
  746. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  747. (val & 0xffffff0f));
  748. /* p2dn replyCount */
  749. netxen_crb_writelit_adapter(adapter,
  750. NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  751. /* disable_peg_cache 0 */
  752. netxen_crb_writelit_adapter(adapter,
  753. NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  754. /* disable_peg_cache 1 */
  755. netxen_crb_writelit_adapter(adapter,
  756. NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  757. /* peg_clr_all */
  758. /* peg_clr 0 */
  759. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8,
  760. 0);
  761. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc,
  762. 0);
  763. /* peg_clr 1 */
  764. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8,
  765. 0);
  766. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc,
  767. 0);
  768. /* peg_clr 2 */
  769. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8,
  770. 0);
  771. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc,
  772. 0);
  773. /* peg_clr 3 */
  774. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8,
  775. 0);
  776. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc,
  777. 0);
  778. }
  779. return 0;
  780. }
  781. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  782. {
  783. uint64_t addr;
  784. uint32_t hi;
  785. uint32_t lo;
  786. adapter->dummy_dma.addr =
  787. pci_alloc_consistent(adapter->ahw.pdev,
  788. NETXEN_HOST_DUMMY_DMA_SIZE,
  789. &adapter->dummy_dma.phys_addr);
  790. if (adapter->dummy_dma.addr == NULL) {
  791. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  792. __FUNCTION__);
  793. return -ENOMEM;
  794. }
  795. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  796. hi = (addr >> 32) & 0xffffffff;
  797. lo = addr & 0xffffffff;
  798. writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI));
  799. writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO));
  800. return 0;
  801. }
  802. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  803. {
  804. if (adapter->dummy_dma.addr) {
  805. writel(0, NETXEN_CRB_NORMALIZE(adapter,
  806. CRB_HOST_DUMMY_BUF_ADDR_HI));
  807. writel(0, NETXEN_CRB_NORMALIZE(adapter,
  808. CRB_HOST_DUMMY_BUF_ADDR_LO));
  809. pci_free_consistent(adapter->ahw.pdev,
  810. NETXEN_HOST_DUMMY_DMA_SIZE,
  811. adapter->dummy_dma.addr,
  812. adapter->dummy_dma.phys_addr);
  813. adapter->dummy_dma.addr = NULL;
  814. }
  815. }
  816. void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  817. {
  818. u32 val = 0;
  819. int loops = 0;
  820. if (!pegtune_val) {
  821. val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  822. while (val != PHAN_INITIALIZE_COMPLETE &&
  823. val != PHAN_INITIALIZE_ACK && loops < 200000) {
  824. udelay(100);
  825. schedule();
  826. val =
  827. readl(NETXEN_CRB_NORMALIZE
  828. (adapter, CRB_CMDPEG_STATE));
  829. loops++;
  830. }
  831. if (val != PHAN_INITIALIZE_COMPLETE)
  832. printk("WARNING: Initial boot wait loop failed...\n");
  833. }
  834. }
  835. int netxen_nic_rx_has_work(struct netxen_adapter *adapter)
  836. {
  837. int ctx;
  838. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  839. struct netxen_recv_context *recv_ctx =
  840. &(adapter->recv_ctx[ctx]);
  841. u32 consumer;
  842. struct status_desc *desc_head;
  843. struct status_desc *desc;
  844. consumer = recv_ctx->status_rx_consumer;
  845. desc_head = recv_ctx->rcv_status_desc_head;
  846. desc = &desc_head[consumer];
  847. if (netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)
  848. return 1;
  849. }
  850. return 0;
  851. }
  852. static inline int netxen_nic_check_temp(struct netxen_adapter *adapter)
  853. {
  854. struct net_device *netdev = adapter->netdev;
  855. uint32_t temp, temp_state, temp_val;
  856. int rv = 0;
  857. temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE));
  858. temp_state = nx_get_temp_state(temp);
  859. temp_val = nx_get_temp_val(temp);
  860. if (temp_state == NX_TEMP_PANIC) {
  861. printk(KERN_ALERT
  862. "%s: Device temperature %d degrees C exceeds"
  863. " maximum allowed. Hardware has been shut down.\n",
  864. netxen_nic_driver_name, temp_val);
  865. netif_carrier_off(netdev);
  866. netif_stop_queue(netdev);
  867. rv = 1;
  868. } else if (temp_state == NX_TEMP_WARN) {
  869. if (adapter->temp == NX_TEMP_NORMAL) {
  870. printk(KERN_ALERT
  871. "%s: Device temperature %d degrees C "
  872. "exceeds operating range."
  873. " Immediate action needed.\n",
  874. netxen_nic_driver_name, temp_val);
  875. }
  876. } else {
  877. if (adapter->temp == NX_TEMP_WARN) {
  878. printk(KERN_INFO
  879. "%s: Device temperature is now %d degrees C"
  880. " in normal range.\n", netxen_nic_driver_name,
  881. temp_val);
  882. }
  883. }
  884. adapter->temp = temp_state;
  885. return rv;
  886. }
  887. void netxen_watchdog_task(struct work_struct *work)
  888. {
  889. struct net_device *netdev;
  890. struct netxen_adapter *adapter =
  891. container_of(work, struct netxen_adapter, watchdog_task);
  892. if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter))
  893. return;
  894. netdev = adapter->netdev;
  895. if ((netif_running(netdev)) && !netif_carrier_ok(netdev)) {
  896. printk(KERN_INFO "%s port %d, %s carrier is now ok\n",
  897. netxen_nic_driver_name, adapter->portnum, netdev->name);
  898. netif_carrier_on(netdev);
  899. }
  900. if (netif_queue_stopped(netdev))
  901. netif_wake_queue(netdev);
  902. if (adapter->handle_phy_intr)
  903. adapter->handle_phy_intr(adapter);
  904. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  905. }
  906. /*
  907. * netxen_process_rcv() send the received packet to the protocol stack.
  908. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  909. * invoke the routine to send more rx buffers to the Phantom...
  910. */
  911. void
  912. netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  913. struct status_desc *desc)
  914. {
  915. struct pci_dev *pdev = adapter->pdev;
  916. struct net_device *netdev = adapter->netdev;
  917. int index = netxen_get_sts_refhandle(desc);
  918. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  919. struct netxen_rx_buffer *buffer;
  920. struct sk_buff *skb;
  921. u32 length = netxen_get_sts_totallength(desc);
  922. u32 desc_ctx;
  923. struct netxen_rcv_desc_ctx *rcv_desc;
  924. int ret;
  925. desc_ctx = netxen_get_sts_type(desc);
  926. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  927. printk("%s: %s Bad Rcv descriptor ring\n",
  928. netxen_nic_driver_name, netdev->name);
  929. return;
  930. }
  931. rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
  932. if (unlikely(index > rcv_desc->max_rx_desc_count)) {
  933. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  934. index, rcv_desc->max_rx_desc_count);
  935. return;
  936. }
  937. buffer = &rcv_desc->rx_buf_arr[index];
  938. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  939. buffer->lro_current_frags++;
  940. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  941. buffer->lro_expected_frags =
  942. netxen_get_sts_desc_lro_cnt(desc);
  943. buffer->lro_length = length;
  944. }
  945. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  946. if (buffer->lro_expected_frags != 0) {
  947. printk("LRO: (refhandle:%x) recv frag."
  948. "wait for last. flags: %x expected:%d"
  949. "have:%d\n", index,
  950. netxen_get_sts_desc_lro_last_frag(desc),
  951. buffer->lro_expected_frags,
  952. buffer->lro_current_frags);
  953. }
  954. return;
  955. }
  956. }
  957. pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
  958. PCI_DMA_FROMDEVICE);
  959. skb = (struct sk_buff *)buffer->skb;
  960. if (likely(netxen_get_sts_status(desc) == STATUS_CKSUM_OK)) {
  961. adapter->stats.csummed++;
  962. skb->ip_summed = CHECKSUM_UNNECESSARY;
  963. }
  964. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  965. /* True length was only available on the last pkt */
  966. skb_put(skb, buffer->lro_length);
  967. } else {
  968. skb_put(skb, length);
  969. }
  970. skb->protocol = eth_type_trans(skb, netdev);
  971. ret = netif_receive_skb(skb);
  972. /*
  973. * RH: Do we need these stats on a regular basis. Can we get it from
  974. * Linux stats.
  975. */
  976. switch (ret) {
  977. case NET_RX_SUCCESS:
  978. adapter->stats.uphappy++;
  979. break;
  980. case NET_RX_CN_LOW:
  981. adapter->stats.uplcong++;
  982. break;
  983. case NET_RX_CN_MOD:
  984. adapter->stats.upmcong++;
  985. break;
  986. case NET_RX_CN_HIGH:
  987. adapter->stats.uphcong++;
  988. break;
  989. case NET_RX_DROP:
  990. adapter->stats.updropped++;
  991. break;
  992. default:
  993. adapter->stats.updunno++;
  994. break;
  995. }
  996. netdev->last_rx = jiffies;
  997. rcv_desc->rcv_free++;
  998. rcv_desc->rcv_pending--;
  999. /*
  1000. * We just consumed one buffer so post a buffer.
  1001. */
  1002. buffer->skb = NULL;
  1003. buffer->state = NETXEN_BUFFER_FREE;
  1004. buffer->lro_current_frags = 0;
  1005. buffer->lro_expected_frags = 0;
  1006. adapter->stats.no_rcv++;
  1007. adapter->stats.rxbytes += length;
  1008. }
  1009. /* Process Receive status ring */
  1010. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1011. {
  1012. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1013. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1014. struct status_desc *desc; /* used to read status desc here */
  1015. u32 consumer = recv_ctx->status_rx_consumer;
  1016. u32 producer = 0;
  1017. int count = 0, ring;
  1018. DPRINTK(INFO, "procesing receive\n");
  1019. /*
  1020. * we assume in this case that there is only one port and that is
  1021. * port #1...changes need to be done in firmware to indicate port
  1022. * number as part of the descriptor. This way we will be able to get
  1023. * the netdev which is associated with that device.
  1024. */
  1025. while (count < max) {
  1026. desc = &desc_head[consumer];
  1027. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1028. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1029. netxen_get_sts_owner(desc));
  1030. break;
  1031. }
  1032. netxen_process_rcv(adapter, ctxid, desc);
  1033. netxen_clear_sts_owner(desc);
  1034. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1035. consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
  1036. count++;
  1037. }
  1038. if (count) {
  1039. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  1040. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1041. }
  1042. }
  1043. /* update the consumer index in phantom */
  1044. if (count) {
  1045. recv_ctx->status_rx_consumer = consumer;
  1046. recv_ctx->status_rx_producer = producer;
  1047. /* Window = 1 */
  1048. writel(consumer,
  1049. NETXEN_CRB_NORMALIZE(adapter,
  1050. recv_crb_registers[ctxid].
  1051. crb_rcv_status_consumer));
  1052. }
  1053. return count;
  1054. }
  1055. /* Process Command status ring */
  1056. int netxen_process_cmd_ring(unsigned long data)
  1057. {
  1058. u32 last_consumer;
  1059. u32 consumer;
  1060. struct netxen_adapter *adapter = (struct netxen_adapter *)data;
  1061. int count1 = 0;
  1062. int count2 = 0;
  1063. struct netxen_cmd_buffer *buffer;
  1064. struct pci_dev *pdev;
  1065. struct netxen_skb_frag *frag;
  1066. u32 i;
  1067. struct sk_buff *skb = NULL;
  1068. int done;
  1069. spin_lock(&adapter->tx_lock);
  1070. last_consumer = adapter->last_cmd_consumer;
  1071. DPRINTK(INFO, "procesing xmit complete\n");
  1072. /* we assume in this case that there is only one port and that is
  1073. * port #1...changes need to be done in firmware to indicate port
  1074. * number as part of the descriptor. This way we will be able to get
  1075. * the netdev which is associated with that device.
  1076. */
  1077. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1078. if (last_consumer == consumer) { /* Ring is empty */
  1079. DPRINTK(INFO, "last_consumer %d == consumer %d\n",
  1080. last_consumer, consumer);
  1081. spin_unlock(&adapter->tx_lock);
  1082. return 1;
  1083. }
  1084. adapter->proc_cmd_buf_counter++;
  1085. /*
  1086. * Not needed - does not seem to be used anywhere.
  1087. * adapter->cmd_consumer = consumer;
  1088. */
  1089. spin_unlock(&adapter->tx_lock);
  1090. while ((last_consumer != consumer) && (count1 < MAX_STATUS_HANDLE)) {
  1091. buffer = &adapter->cmd_buf_arr[last_consumer];
  1092. pdev = adapter->pdev;
  1093. frag = &buffer->frag_array[0];
  1094. skb = buffer->skb;
  1095. if (skb && (cmpxchg(&buffer->skb, skb, 0) == skb)) {
  1096. pci_unmap_single(pdev, frag->dma, frag->length,
  1097. PCI_DMA_TODEVICE);
  1098. for (i = 1; i < buffer->frag_count; i++) {
  1099. DPRINTK(INFO, "getting fragment no %d\n", i);
  1100. frag++; /* Get the next frag */
  1101. pci_unmap_page(pdev, frag->dma, frag->length,
  1102. PCI_DMA_TODEVICE);
  1103. }
  1104. adapter->stats.skbfreed++;
  1105. dev_kfree_skb_any(skb);
  1106. skb = NULL;
  1107. } else if (adapter->proc_cmd_buf_counter == 1) {
  1108. adapter->stats.txnullskb++;
  1109. }
  1110. if (unlikely(netif_queue_stopped(adapter->netdev)
  1111. && netif_carrier_ok(adapter->netdev))
  1112. && ((jiffies - adapter->netdev->trans_start) >
  1113. adapter->netdev->watchdog_timeo)) {
  1114. SCHEDULE_WORK(&adapter->tx_timeout_task);
  1115. }
  1116. last_consumer = get_next_index(last_consumer,
  1117. adapter->max_tx_desc_count);
  1118. count1++;
  1119. }
  1120. count2 = 0;
  1121. spin_lock(&adapter->tx_lock);
  1122. if ((--adapter->proc_cmd_buf_counter) == 0) {
  1123. adapter->last_cmd_consumer = last_consumer;
  1124. while ((adapter->last_cmd_consumer != consumer)
  1125. && (count2 < MAX_STATUS_HANDLE)) {
  1126. buffer =
  1127. &adapter->cmd_buf_arr[adapter->last_cmd_consumer];
  1128. count2++;
  1129. if (buffer->skb)
  1130. break;
  1131. else
  1132. adapter->last_cmd_consumer =
  1133. get_next_index(adapter->last_cmd_consumer,
  1134. adapter->max_tx_desc_count);
  1135. }
  1136. }
  1137. if (count1 || count2) {
  1138. if (netif_queue_stopped(adapter->netdev)
  1139. && (adapter->flags & NETXEN_NETDEV_STATUS)) {
  1140. netif_wake_queue(adapter->netdev);
  1141. adapter->flags &= ~NETXEN_NETDEV_STATUS;
  1142. }
  1143. }
  1144. /*
  1145. * If everything is freed up to consumer then check if the ring is full
  1146. * If the ring is full then check if more needs to be freed and
  1147. * schedule the call back again.
  1148. *
  1149. * This happens when there are 2 CPUs. One could be freeing and the
  1150. * other filling it. If the ring is full when we get out of here and
  1151. * the card has already interrupted the host then the host can miss the
  1152. * interrupt.
  1153. *
  1154. * There is still a possible race condition and the host could miss an
  1155. * interrupt. The card has to take care of this.
  1156. */
  1157. if (adapter->last_cmd_consumer == consumer &&
  1158. (((adapter->cmd_producer + 1) %
  1159. adapter->max_tx_desc_count) == adapter->last_cmd_consumer)) {
  1160. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1161. }
  1162. done = (adapter->last_cmd_consumer == consumer);
  1163. spin_unlock(&adapter->tx_lock);
  1164. DPRINTK(INFO, "last consumer is %d in %s\n", last_consumer,
  1165. __FUNCTION__);
  1166. return (done);
  1167. }
  1168. /*
  1169. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1170. */
  1171. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1172. {
  1173. struct pci_dev *pdev = adapter->ahw.pdev;
  1174. struct sk_buff *skb;
  1175. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1176. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1177. uint producer;
  1178. struct rcv_desc *pdesc;
  1179. struct netxen_rx_buffer *buffer;
  1180. int count = 0;
  1181. int index = 0;
  1182. netxen_ctx_msg msg = 0;
  1183. dma_addr_t dma;
  1184. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1185. producer = rcv_desc->producer;
  1186. index = rcv_desc->begin_alloc;
  1187. buffer = &rcv_desc->rx_buf_arr[index];
  1188. /* We can start writing rx descriptors into the phantom memory. */
  1189. while (buffer->state == NETXEN_BUFFER_FREE) {
  1190. skb = dev_alloc_skb(rcv_desc->skb_size);
  1191. if (unlikely(!skb)) {
  1192. /*
  1193. * TODO
  1194. * We need to schedule the posting of buffers to the pegs.
  1195. */
  1196. rcv_desc->begin_alloc = index;
  1197. DPRINTK(ERR, "netxen_post_rx_buffers: "
  1198. " allocated only %d buffers\n", count);
  1199. break;
  1200. }
  1201. count++; /* now there should be no failure */
  1202. pdesc = &rcv_desc->desc_head[producer];
  1203. #if defined(XGB_DEBUG)
  1204. *(unsigned long *)(skb->head) = 0xc0debabe;
  1205. if (skb_is_nonlinear(skb)) {
  1206. printk("Allocated SKB @%p is nonlinear\n");
  1207. }
  1208. #endif
  1209. skb_reserve(skb, 2);
  1210. /* This will be setup when we receive the
  1211. * buffer after it has been filled FSL TBD TBD
  1212. * skb->dev = netdev;
  1213. */
  1214. dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size,
  1215. PCI_DMA_FROMDEVICE);
  1216. pdesc->addr_buffer = cpu_to_le64(dma);
  1217. buffer->skb = skb;
  1218. buffer->state = NETXEN_BUFFER_BUSY;
  1219. buffer->dma = dma;
  1220. /* make a rcv descriptor */
  1221. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1222. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1223. DPRINTK(INFO, "done writing descripter\n");
  1224. producer =
  1225. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1226. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1227. buffer = &rcv_desc->rx_buf_arr[index];
  1228. }
  1229. /* if we did allocate buffers, then write the count to Phantom */
  1230. if (count) {
  1231. rcv_desc->begin_alloc = index;
  1232. rcv_desc->rcv_pending += count;
  1233. rcv_desc->producer = producer;
  1234. if (rcv_desc->rcv_free >= 32) {
  1235. rcv_desc->rcv_free = 0;
  1236. /* Window = 1 */
  1237. writel((producer - 1) &
  1238. (rcv_desc->max_rx_desc_count - 1),
  1239. NETXEN_CRB_NORMALIZE(adapter,
  1240. recv_crb_registers[
  1241. adapter->portnum].
  1242. rcv_desc_crb[ringid].
  1243. crb_rcv_producer_offset));
  1244. /*
  1245. * Write a doorbell msg to tell phanmon of change in
  1246. * receive ring producer
  1247. */
  1248. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1249. netxen_set_msg_privid(msg);
  1250. netxen_set_msg_count(msg,
  1251. ((producer -
  1252. 1) & (rcv_desc->
  1253. max_rx_desc_count - 1)));
  1254. netxen_set_msg_ctxid(msg, adapter->portnum);
  1255. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1256. writel(msg,
  1257. DB_NORMALIZE(adapter,
  1258. NETXEN_RCV_PRODUCER_OFFSET));
  1259. }
  1260. }
  1261. }
  1262. void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, uint32_t ctx,
  1263. uint32_t ringid)
  1264. {
  1265. struct pci_dev *pdev = adapter->ahw.pdev;
  1266. struct sk_buff *skb;
  1267. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1268. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1269. u32 producer;
  1270. struct rcv_desc *pdesc;
  1271. struct netxen_rx_buffer *buffer;
  1272. int count = 0;
  1273. int index = 0;
  1274. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1275. producer = rcv_desc->producer;
  1276. index = rcv_desc->begin_alloc;
  1277. buffer = &rcv_desc->rx_buf_arr[index];
  1278. /* We can start writing rx descriptors into the phantom memory. */
  1279. while (buffer->state == NETXEN_BUFFER_FREE) {
  1280. skb = dev_alloc_skb(rcv_desc->skb_size);
  1281. if (unlikely(!skb)) {
  1282. /*
  1283. * We need to schedule the posting of buffers to the pegs.
  1284. */
  1285. rcv_desc->begin_alloc = index;
  1286. DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
  1287. " allocated only %d buffers\n", count);
  1288. break;
  1289. }
  1290. count++; /* now there should be no failure */
  1291. pdesc = &rcv_desc->desc_head[producer];
  1292. skb_reserve(skb, 2);
  1293. /*
  1294. * This will be setup when we receive the
  1295. * buffer after it has been filled
  1296. * skb->dev = netdev;
  1297. */
  1298. buffer->skb = skb;
  1299. buffer->state = NETXEN_BUFFER_BUSY;
  1300. buffer->dma = pci_map_single(pdev, skb->data,
  1301. rcv_desc->dma_size,
  1302. PCI_DMA_FROMDEVICE);
  1303. /* make a rcv descriptor */
  1304. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1305. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1306. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1307. DPRINTK(INFO, "done writing descripter\n");
  1308. producer =
  1309. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1310. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1311. buffer = &rcv_desc->rx_buf_arr[index];
  1312. }
  1313. /* if we did allocate buffers, then write the count to Phantom */
  1314. if (count) {
  1315. rcv_desc->begin_alloc = index;
  1316. rcv_desc->rcv_pending += count;
  1317. rcv_desc->producer = producer;
  1318. if (rcv_desc->rcv_free >= 32) {
  1319. rcv_desc->rcv_free = 0;
  1320. /* Window = 1 */
  1321. writel((producer - 1) &
  1322. (rcv_desc->max_rx_desc_count - 1),
  1323. NETXEN_CRB_NORMALIZE(adapter,
  1324. recv_crb_registers[
  1325. adapter->portnum].
  1326. rcv_desc_crb[ringid].
  1327. crb_rcv_producer_offset));
  1328. wmb();
  1329. }
  1330. }
  1331. }
  1332. int netxen_nic_tx_has_work(struct netxen_adapter *adapter)
  1333. {
  1334. if (find_diff_among(adapter->last_cmd_consumer,
  1335. adapter->cmd_producer,
  1336. adapter->max_tx_desc_count) > 0)
  1337. return 1;
  1338. return 0;
  1339. }
  1340. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1341. {
  1342. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1343. return;
  1344. }