macb.c 28 KB

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  1. /*
  2. * Atmel MACB Ethernet Controller driver
  3. *
  4. * Copyright (C) 2004-2006 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/slab.h>
  16. #include <linux/init.h>
  17. #include <linux/netdevice.h>
  18. #include <linux/etherdevice.h>
  19. #include <linux/mii.h>
  20. #include <linux/mutex.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/ethtool.h>
  23. #include <linux/platform_device.h>
  24. #include <asm/arch/board.h>
  25. #include "macb.h"
  26. #define RX_BUFFER_SIZE 128
  27. #define RX_RING_SIZE 512
  28. #define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
  29. /* Make the IP header word-aligned (the ethernet header is 14 bytes) */
  30. #define RX_OFFSET 2
  31. #define TX_RING_SIZE 128
  32. #define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
  33. #define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
  34. #define TX_RING_GAP(bp) \
  35. (TX_RING_SIZE - (bp)->tx_pending)
  36. #define TX_BUFFS_AVAIL(bp) \
  37. (((bp)->tx_tail <= (bp)->tx_head) ? \
  38. (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
  39. (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
  40. #define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
  41. #define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
  42. /* minimum number of free TX descriptors before waking up TX process */
  43. #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
  44. #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
  45. | MACB_BIT(ISR_ROVR))
  46. static void __macb_set_hwaddr(struct macb *bp)
  47. {
  48. u32 bottom;
  49. u16 top;
  50. bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
  51. macb_writel(bp, SA1B, bottom);
  52. top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
  53. macb_writel(bp, SA1T, top);
  54. }
  55. static void __init macb_get_hwaddr(struct macb *bp)
  56. {
  57. u32 bottom;
  58. u16 top;
  59. u8 addr[6];
  60. bottom = macb_readl(bp, SA1B);
  61. top = macb_readl(bp, SA1T);
  62. addr[0] = bottom & 0xff;
  63. addr[1] = (bottom >> 8) & 0xff;
  64. addr[2] = (bottom >> 16) & 0xff;
  65. addr[3] = (bottom >> 24) & 0xff;
  66. addr[4] = top & 0xff;
  67. addr[5] = (top >> 8) & 0xff;
  68. if (is_valid_ether_addr(addr))
  69. memcpy(bp->dev->dev_addr, addr, sizeof(addr));
  70. }
  71. static void macb_enable_mdio(struct macb *bp)
  72. {
  73. unsigned long flags;
  74. u32 reg;
  75. spin_lock_irqsave(&bp->lock, flags);
  76. reg = macb_readl(bp, NCR);
  77. reg |= MACB_BIT(MPE);
  78. macb_writel(bp, NCR, reg);
  79. macb_writel(bp, IER, MACB_BIT(MFD));
  80. spin_unlock_irqrestore(&bp->lock, flags);
  81. }
  82. static void macb_disable_mdio(struct macb *bp)
  83. {
  84. unsigned long flags;
  85. u32 reg;
  86. spin_lock_irqsave(&bp->lock, flags);
  87. reg = macb_readl(bp, NCR);
  88. reg &= ~MACB_BIT(MPE);
  89. macb_writel(bp, NCR, reg);
  90. macb_writel(bp, IDR, MACB_BIT(MFD));
  91. spin_unlock_irqrestore(&bp->lock, flags);
  92. }
  93. static int macb_mdio_read(struct net_device *dev, int phy_id, int location)
  94. {
  95. struct macb *bp = netdev_priv(dev);
  96. int value;
  97. mutex_lock(&bp->mdio_mutex);
  98. macb_enable_mdio(bp);
  99. macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
  100. | MACB_BF(RW, MACB_MAN_READ)
  101. | MACB_BF(PHYA, phy_id)
  102. | MACB_BF(REGA, location)
  103. | MACB_BF(CODE, MACB_MAN_CODE)));
  104. wait_for_completion(&bp->mdio_complete);
  105. value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
  106. macb_disable_mdio(bp);
  107. mutex_unlock(&bp->mdio_mutex);
  108. return value;
  109. }
  110. static void macb_mdio_write(struct net_device *dev, int phy_id,
  111. int location, int val)
  112. {
  113. struct macb *bp = netdev_priv(dev);
  114. dev_dbg(&bp->pdev->dev, "mdio_write %02x:%02x <- %04x\n",
  115. phy_id, location, val);
  116. mutex_lock(&bp->mdio_mutex);
  117. macb_enable_mdio(bp);
  118. macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
  119. | MACB_BF(RW, MACB_MAN_WRITE)
  120. | MACB_BF(PHYA, phy_id)
  121. | MACB_BF(REGA, location)
  122. | MACB_BF(CODE, MACB_MAN_CODE)
  123. | MACB_BF(DATA, val)));
  124. wait_for_completion(&bp->mdio_complete);
  125. macb_disable_mdio(bp);
  126. mutex_unlock(&bp->mdio_mutex);
  127. }
  128. static int macb_phy_probe(struct macb *bp)
  129. {
  130. int phy_address;
  131. u16 phyid1, phyid2;
  132. for (phy_address = 0; phy_address < 32; phy_address++) {
  133. phyid1 = macb_mdio_read(bp->dev, phy_address, MII_PHYSID1);
  134. phyid2 = macb_mdio_read(bp->dev, phy_address, MII_PHYSID2);
  135. if (phyid1 != 0xffff && phyid1 != 0x0000
  136. && phyid2 != 0xffff && phyid2 != 0x0000)
  137. break;
  138. }
  139. if (phy_address == 32)
  140. return -ENODEV;
  141. dev_info(&bp->pdev->dev,
  142. "detected PHY at address %d (ID %04x:%04x)\n",
  143. phy_address, phyid1, phyid2);
  144. bp->mii.phy_id = phy_address;
  145. return 0;
  146. }
  147. static void macb_set_media(struct macb *bp, int media)
  148. {
  149. u32 reg;
  150. spin_lock_irq(&bp->lock);
  151. reg = macb_readl(bp, NCFGR);
  152. reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
  153. if (media & (ADVERTISE_100HALF | ADVERTISE_100FULL))
  154. reg |= MACB_BIT(SPD);
  155. if (media & ADVERTISE_FULL)
  156. reg |= MACB_BIT(FD);
  157. macb_writel(bp, NCFGR, reg);
  158. spin_unlock_irq(&bp->lock);
  159. }
  160. static void macb_check_media(struct macb *bp, int ok_to_print, int init_media)
  161. {
  162. struct mii_if_info *mii = &bp->mii;
  163. unsigned int old_carrier, new_carrier;
  164. int advertise, lpa, media, duplex;
  165. /* if forced media, go no further */
  166. if (mii->force_media)
  167. return;
  168. /* check current and old link status */
  169. old_carrier = netif_carrier_ok(mii->dev) ? 1 : 0;
  170. new_carrier = (unsigned int) mii_link_ok(mii);
  171. /* if carrier state did not change, assume nothing else did */
  172. if (!init_media && old_carrier == new_carrier)
  173. return;
  174. /* no carrier, nothing much to do */
  175. if (!new_carrier) {
  176. netif_carrier_off(mii->dev);
  177. printk(KERN_INFO "%s: link down\n", mii->dev->name);
  178. return;
  179. }
  180. /*
  181. * we have carrier, see who's on the other end
  182. */
  183. netif_carrier_on(mii->dev);
  184. /* get MII advertise and LPA values */
  185. if (!init_media && mii->advertising) {
  186. advertise = mii->advertising;
  187. } else {
  188. advertise = mii->mdio_read(mii->dev, mii->phy_id, MII_ADVERTISE);
  189. mii->advertising = advertise;
  190. }
  191. lpa = mii->mdio_read(mii->dev, mii->phy_id, MII_LPA);
  192. /* figure out media and duplex from advertise and LPA values */
  193. media = mii_nway_result(lpa & advertise);
  194. duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  195. if (ok_to_print)
  196. printk(KERN_INFO "%s: link up, %sMbps, %s-duplex, lpa 0x%04X\n",
  197. mii->dev->name,
  198. media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? "100" : "10",
  199. duplex ? "full" : "half", lpa);
  200. mii->full_duplex = duplex;
  201. /* Let the MAC know about the new link state */
  202. macb_set_media(bp, media);
  203. }
  204. static void macb_update_stats(struct macb *bp)
  205. {
  206. u32 __iomem *reg = bp->regs + MACB_PFR;
  207. u32 *p = &bp->hw_stats.rx_pause_frames;
  208. u32 *end = &bp->hw_stats.tx_pause_frames + 1;
  209. WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
  210. for(; p < end; p++, reg++)
  211. *p += __raw_readl(reg);
  212. }
  213. static void macb_periodic_task(struct work_struct *work)
  214. {
  215. struct macb *bp = container_of(work, struct macb, periodic_task.work);
  216. macb_update_stats(bp);
  217. macb_check_media(bp, 1, 0);
  218. schedule_delayed_work(&bp->periodic_task, HZ);
  219. }
  220. static void macb_tx(struct macb *bp)
  221. {
  222. unsigned int tail;
  223. unsigned int head;
  224. u32 status;
  225. status = macb_readl(bp, TSR);
  226. macb_writel(bp, TSR, status);
  227. dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n",
  228. (unsigned long)status);
  229. if (status & MACB_BIT(UND)) {
  230. printk(KERN_ERR "%s: TX underrun, resetting buffers\n",
  231. bp->dev->name);
  232. bp->tx_head = bp->tx_tail = 0;
  233. }
  234. if (!(status & MACB_BIT(COMP)))
  235. /*
  236. * This may happen when a buffer becomes complete
  237. * between reading the ISR and scanning the
  238. * descriptors. Nothing to worry about.
  239. */
  240. return;
  241. head = bp->tx_head;
  242. for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
  243. struct ring_info *rp = &bp->tx_skb[tail];
  244. struct sk_buff *skb = rp->skb;
  245. u32 bufstat;
  246. BUG_ON(skb == NULL);
  247. rmb();
  248. bufstat = bp->tx_ring[tail].ctrl;
  249. if (!(bufstat & MACB_BIT(TX_USED)))
  250. break;
  251. dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n",
  252. tail, skb->data);
  253. dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
  254. DMA_TO_DEVICE);
  255. bp->stats.tx_packets++;
  256. bp->stats.tx_bytes += skb->len;
  257. rp->skb = NULL;
  258. dev_kfree_skb_irq(skb);
  259. }
  260. bp->tx_tail = tail;
  261. if (netif_queue_stopped(bp->dev) &&
  262. TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
  263. netif_wake_queue(bp->dev);
  264. }
  265. static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
  266. unsigned int last_frag)
  267. {
  268. unsigned int len;
  269. unsigned int frag;
  270. unsigned int offset = 0;
  271. struct sk_buff *skb;
  272. len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
  273. dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n",
  274. first_frag, last_frag, len);
  275. skb = dev_alloc_skb(len + RX_OFFSET);
  276. if (!skb) {
  277. bp->stats.rx_dropped++;
  278. for (frag = first_frag; ; frag = NEXT_RX(frag)) {
  279. bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
  280. if (frag == last_frag)
  281. break;
  282. }
  283. wmb();
  284. return 1;
  285. }
  286. skb_reserve(skb, RX_OFFSET);
  287. skb->ip_summed = CHECKSUM_NONE;
  288. skb_put(skb, len);
  289. for (frag = first_frag; ; frag = NEXT_RX(frag)) {
  290. unsigned int frag_len = RX_BUFFER_SIZE;
  291. if (offset + frag_len > len) {
  292. BUG_ON(frag != last_frag);
  293. frag_len = len - offset;
  294. }
  295. skb_copy_to_linear_data_offset(skb, offset,
  296. (bp->rx_buffers +
  297. (RX_BUFFER_SIZE * frag)),
  298. frag_len);
  299. offset += RX_BUFFER_SIZE;
  300. bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
  301. wmb();
  302. if (frag == last_frag)
  303. break;
  304. }
  305. skb->protocol = eth_type_trans(skb, bp->dev);
  306. bp->stats.rx_packets++;
  307. bp->stats.rx_bytes += len;
  308. bp->dev->last_rx = jiffies;
  309. dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
  310. skb->len, skb->csum);
  311. netif_receive_skb(skb);
  312. return 0;
  313. }
  314. /* Mark DMA descriptors from begin up to and not including end as unused */
  315. static void discard_partial_frame(struct macb *bp, unsigned int begin,
  316. unsigned int end)
  317. {
  318. unsigned int frag;
  319. for (frag = begin; frag != end; frag = NEXT_RX(frag))
  320. bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
  321. wmb();
  322. /*
  323. * When this happens, the hardware stats registers for
  324. * whatever caused this is updated, so we don't have to record
  325. * anything.
  326. */
  327. }
  328. static int macb_rx(struct macb *bp, int budget)
  329. {
  330. int received = 0;
  331. unsigned int tail = bp->rx_tail;
  332. int first_frag = -1;
  333. for (; budget > 0; tail = NEXT_RX(tail)) {
  334. u32 addr, ctrl;
  335. rmb();
  336. addr = bp->rx_ring[tail].addr;
  337. ctrl = bp->rx_ring[tail].ctrl;
  338. if (!(addr & MACB_BIT(RX_USED)))
  339. break;
  340. if (ctrl & MACB_BIT(RX_SOF)) {
  341. if (first_frag != -1)
  342. discard_partial_frame(bp, first_frag, tail);
  343. first_frag = tail;
  344. }
  345. if (ctrl & MACB_BIT(RX_EOF)) {
  346. int dropped;
  347. BUG_ON(first_frag == -1);
  348. dropped = macb_rx_frame(bp, first_frag, tail);
  349. first_frag = -1;
  350. if (!dropped) {
  351. received++;
  352. budget--;
  353. }
  354. }
  355. }
  356. if (first_frag != -1)
  357. bp->rx_tail = first_frag;
  358. else
  359. bp->rx_tail = tail;
  360. return received;
  361. }
  362. static int macb_poll(struct net_device *dev, int *budget)
  363. {
  364. struct macb *bp = netdev_priv(dev);
  365. int orig_budget, work_done, retval = 0;
  366. u32 status;
  367. status = macb_readl(bp, RSR);
  368. macb_writel(bp, RSR, status);
  369. if (!status) {
  370. /*
  371. * This may happen if an interrupt was pending before
  372. * this function was called last time, and no packets
  373. * have been received since.
  374. */
  375. netif_rx_complete(dev);
  376. goto out;
  377. }
  378. dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n",
  379. (unsigned long)status, *budget);
  380. if (!(status & MACB_BIT(REC))) {
  381. dev_warn(&bp->pdev->dev,
  382. "No RX buffers complete, status = %02lx\n",
  383. (unsigned long)status);
  384. netif_rx_complete(dev);
  385. goto out;
  386. }
  387. orig_budget = *budget;
  388. if (orig_budget > dev->quota)
  389. orig_budget = dev->quota;
  390. work_done = macb_rx(bp, orig_budget);
  391. if (work_done < orig_budget) {
  392. netif_rx_complete(dev);
  393. retval = 0;
  394. } else {
  395. retval = 1;
  396. }
  397. /*
  398. * We've done what we can to clean the buffers. Make sure we
  399. * get notified when new packets arrive.
  400. */
  401. out:
  402. macb_writel(bp, IER, MACB_RX_INT_FLAGS);
  403. /* TODO: Handle errors */
  404. return retval;
  405. }
  406. static irqreturn_t macb_interrupt(int irq, void *dev_id)
  407. {
  408. struct net_device *dev = dev_id;
  409. struct macb *bp = netdev_priv(dev);
  410. u32 status;
  411. status = macb_readl(bp, ISR);
  412. if (unlikely(!status))
  413. return IRQ_NONE;
  414. spin_lock(&bp->lock);
  415. while (status) {
  416. if (status & MACB_BIT(MFD))
  417. complete(&bp->mdio_complete);
  418. /* close possible race with dev_close */
  419. if (unlikely(!netif_running(dev))) {
  420. macb_writel(bp, IDR, ~0UL);
  421. break;
  422. }
  423. if (status & MACB_RX_INT_FLAGS) {
  424. if (netif_rx_schedule_prep(dev)) {
  425. /*
  426. * There's no point taking any more interrupts
  427. * until we have processed the buffers
  428. */
  429. macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
  430. dev_dbg(&bp->pdev->dev, "scheduling RX softirq\n");
  431. __netif_rx_schedule(dev);
  432. }
  433. }
  434. if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND)))
  435. macb_tx(bp);
  436. /*
  437. * Link change detection isn't possible with RMII, so we'll
  438. * add that if/when we get our hands on a full-blown MII PHY.
  439. */
  440. if (status & MACB_BIT(HRESP)) {
  441. /*
  442. * TODO: Reset the hardware, and maybe move the printk
  443. * to a lower-priority context as well (work queue?)
  444. */
  445. printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n",
  446. dev->name);
  447. }
  448. status = macb_readl(bp, ISR);
  449. }
  450. spin_unlock(&bp->lock);
  451. return IRQ_HANDLED;
  452. }
  453. static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
  454. {
  455. struct macb *bp = netdev_priv(dev);
  456. dma_addr_t mapping;
  457. unsigned int len, entry;
  458. u32 ctrl;
  459. #ifdef DEBUG
  460. int i;
  461. dev_dbg(&bp->pdev->dev,
  462. "start_xmit: len %u head %p data %p tail %p end %p\n",
  463. skb->len, skb->head, skb->data,
  464. skb_tail_pointer(skb), skb_end_pointer(skb));
  465. dev_dbg(&bp->pdev->dev,
  466. "data:");
  467. for (i = 0; i < 16; i++)
  468. printk(" %02x", (unsigned int)skb->data[i]);
  469. printk("\n");
  470. #endif
  471. len = skb->len;
  472. spin_lock_irq(&bp->lock);
  473. /* This is a hard error, log it. */
  474. if (TX_BUFFS_AVAIL(bp) < 1) {
  475. netif_stop_queue(dev);
  476. spin_unlock_irq(&bp->lock);
  477. dev_err(&bp->pdev->dev,
  478. "BUG! Tx Ring full when queue awake!\n");
  479. dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n",
  480. bp->tx_head, bp->tx_tail);
  481. return 1;
  482. }
  483. entry = bp->tx_head;
  484. dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry);
  485. mapping = dma_map_single(&bp->pdev->dev, skb->data,
  486. len, DMA_TO_DEVICE);
  487. bp->tx_skb[entry].skb = skb;
  488. bp->tx_skb[entry].mapping = mapping;
  489. dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n",
  490. skb->data, (unsigned long)mapping);
  491. ctrl = MACB_BF(TX_FRMLEN, len);
  492. ctrl |= MACB_BIT(TX_LAST);
  493. if (entry == (TX_RING_SIZE - 1))
  494. ctrl |= MACB_BIT(TX_WRAP);
  495. bp->tx_ring[entry].addr = mapping;
  496. bp->tx_ring[entry].ctrl = ctrl;
  497. wmb();
  498. entry = NEXT_TX(entry);
  499. bp->tx_head = entry;
  500. macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
  501. if (TX_BUFFS_AVAIL(bp) < 1)
  502. netif_stop_queue(dev);
  503. spin_unlock_irq(&bp->lock);
  504. dev->trans_start = jiffies;
  505. return 0;
  506. }
  507. static void macb_free_consistent(struct macb *bp)
  508. {
  509. if (bp->tx_skb) {
  510. kfree(bp->tx_skb);
  511. bp->tx_skb = NULL;
  512. }
  513. if (bp->rx_ring) {
  514. dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
  515. bp->rx_ring, bp->rx_ring_dma);
  516. bp->rx_ring = NULL;
  517. }
  518. if (bp->tx_ring) {
  519. dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
  520. bp->tx_ring, bp->tx_ring_dma);
  521. bp->tx_ring = NULL;
  522. }
  523. if (bp->rx_buffers) {
  524. dma_free_coherent(&bp->pdev->dev,
  525. RX_RING_SIZE * RX_BUFFER_SIZE,
  526. bp->rx_buffers, bp->rx_buffers_dma);
  527. bp->rx_buffers = NULL;
  528. }
  529. }
  530. static int macb_alloc_consistent(struct macb *bp)
  531. {
  532. int size;
  533. size = TX_RING_SIZE * sizeof(struct ring_info);
  534. bp->tx_skb = kmalloc(size, GFP_KERNEL);
  535. if (!bp->tx_skb)
  536. goto out_err;
  537. size = RX_RING_BYTES;
  538. bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
  539. &bp->rx_ring_dma, GFP_KERNEL);
  540. if (!bp->rx_ring)
  541. goto out_err;
  542. dev_dbg(&bp->pdev->dev,
  543. "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
  544. size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
  545. size = TX_RING_BYTES;
  546. bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
  547. &bp->tx_ring_dma, GFP_KERNEL);
  548. if (!bp->tx_ring)
  549. goto out_err;
  550. dev_dbg(&bp->pdev->dev,
  551. "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
  552. size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
  553. size = RX_RING_SIZE * RX_BUFFER_SIZE;
  554. bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
  555. &bp->rx_buffers_dma, GFP_KERNEL);
  556. if (!bp->rx_buffers)
  557. goto out_err;
  558. dev_dbg(&bp->pdev->dev,
  559. "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
  560. size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
  561. return 0;
  562. out_err:
  563. macb_free_consistent(bp);
  564. return -ENOMEM;
  565. }
  566. static void macb_init_rings(struct macb *bp)
  567. {
  568. int i;
  569. dma_addr_t addr;
  570. addr = bp->rx_buffers_dma;
  571. for (i = 0; i < RX_RING_SIZE; i++) {
  572. bp->rx_ring[i].addr = addr;
  573. bp->rx_ring[i].ctrl = 0;
  574. addr += RX_BUFFER_SIZE;
  575. }
  576. bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
  577. for (i = 0; i < TX_RING_SIZE; i++) {
  578. bp->tx_ring[i].addr = 0;
  579. bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
  580. }
  581. bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
  582. bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
  583. }
  584. static void macb_reset_hw(struct macb *bp)
  585. {
  586. /* Make sure we have the write buffer for ourselves */
  587. wmb();
  588. /*
  589. * Disable RX and TX (XXX: Should we halt the transmission
  590. * more gracefully?)
  591. */
  592. macb_writel(bp, NCR, 0);
  593. /* Clear the stats registers (XXX: Update stats first?) */
  594. macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
  595. /* Clear all status flags */
  596. macb_writel(bp, TSR, ~0UL);
  597. macb_writel(bp, RSR, ~0UL);
  598. /* Disable all interrupts */
  599. macb_writel(bp, IDR, ~0UL);
  600. macb_readl(bp, ISR);
  601. }
  602. static void macb_init_hw(struct macb *bp)
  603. {
  604. u32 config;
  605. macb_reset_hw(bp);
  606. __macb_set_hwaddr(bp);
  607. config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L);
  608. config |= MACB_BIT(PAE); /* PAuse Enable */
  609. config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
  610. if (bp->dev->flags & IFF_PROMISC)
  611. config |= MACB_BIT(CAF); /* Copy All Frames */
  612. if (!(bp->dev->flags & IFF_BROADCAST))
  613. config |= MACB_BIT(NBC); /* No BroadCast */
  614. macb_writel(bp, NCFGR, config);
  615. /* Initialize TX and RX buffers */
  616. macb_writel(bp, RBQP, bp->rx_ring_dma);
  617. macb_writel(bp, TBQP, bp->tx_ring_dma);
  618. /* Enable TX and RX */
  619. macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE));
  620. /* Enable interrupts */
  621. macb_writel(bp, IER, (MACB_BIT(RCOMP)
  622. | MACB_BIT(RXUBR)
  623. | MACB_BIT(ISR_TUND)
  624. | MACB_BIT(ISR_RLE)
  625. | MACB_BIT(TXERR)
  626. | MACB_BIT(TCOMP)
  627. | MACB_BIT(ISR_ROVR)
  628. | MACB_BIT(HRESP)));
  629. }
  630. static void macb_init_phy(struct net_device *dev)
  631. {
  632. struct macb *bp = netdev_priv(dev);
  633. /* Set some reasonable default settings */
  634. macb_mdio_write(dev, bp->mii.phy_id, MII_ADVERTISE,
  635. ADVERTISE_CSMA | ADVERTISE_ALL);
  636. macb_mdio_write(dev, bp->mii.phy_id, MII_BMCR,
  637. (BMCR_SPEED100 | BMCR_ANENABLE
  638. | BMCR_ANRESTART | BMCR_FULLDPLX));
  639. }
  640. static int macb_open(struct net_device *dev)
  641. {
  642. struct macb *bp = netdev_priv(dev);
  643. int err;
  644. dev_dbg(&bp->pdev->dev, "open\n");
  645. if (!is_valid_ether_addr(dev->dev_addr))
  646. return -EADDRNOTAVAIL;
  647. err = macb_alloc_consistent(bp);
  648. if (err) {
  649. printk(KERN_ERR
  650. "%s: Unable to allocate DMA memory (error %d)\n",
  651. dev->name, err);
  652. return err;
  653. }
  654. macb_init_rings(bp);
  655. macb_init_hw(bp);
  656. macb_init_phy(dev);
  657. macb_check_media(bp, 1, 1);
  658. netif_start_queue(dev);
  659. schedule_delayed_work(&bp->periodic_task, HZ);
  660. return 0;
  661. }
  662. static int macb_close(struct net_device *dev)
  663. {
  664. struct macb *bp = netdev_priv(dev);
  665. unsigned long flags;
  666. cancel_rearming_delayed_work(&bp->periodic_task);
  667. netif_stop_queue(dev);
  668. spin_lock_irqsave(&bp->lock, flags);
  669. macb_reset_hw(bp);
  670. netif_carrier_off(dev);
  671. spin_unlock_irqrestore(&bp->lock, flags);
  672. macb_free_consistent(bp);
  673. return 0;
  674. }
  675. static struct net_device_stats *macb_get_stats(struct net_device *dev)
  676. {
  677. struct macb *bp = netdev_priv(dev);
  678. struct net_device_stats *nstat = &bp->stats;
  679. struct macb_stats *hwstat = &bp->hw_stats;
  680. /* Convert HW stats into netdevice stats */
  681. nstat->rx_errors = (hwstat->rx_fcs_errors +
  682. hwstat->rx_align_errors +
  683. hwstat->rx_resource_errors +
  684. hwstat->rx_overruns +
  685. hwstat->rx_oversize_pkts +
  686. hwstat->rx_jabbers +
  687. hwstat->rx_undersize_pkts +
  688. hwstat->sqe_test_errors +
  689. hwstat->rx_length_mismatch);
  690. nstat->tx_errors = (hwstat->tx_late_cols +
  691. hwstat->tx_excessive_cols +
  692. hwstat->tx_underruns +
  693. hwstat->tx_carrier_errors);
  694. nstat->collisions = (hwstat->tx_single_cols +
  695. hwstat->tx_multiple_cols +
  696. hwstat->tx_excessive_cols);
  697. nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
  698. hwstat->rx_jabbers +
  699. hwstat->rx_undersize_pkts +
  700. hwstat->rx_length_mismatch);
  701. nstat->rx_over_errors = hwstat->rx_resource_errors;
  702. nstat->rx_crc_errors = hwstat->rx_fcs_errors;
  703. nstat->rx_frame_errors = hwstat->rx_align_errors;
  704. nstat->rx_fifo_errors = hwstat->rx_overruns;
  705. /* XXX: What does "missed" mean? */
  706. nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
  707. nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
  708. nstat->tx_fifo_errors = hwstat->tx_underruns;
  709. /* Don't know about heartbeat or window errors... */
  710. return nstat;
  711. }
  712. static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  713. {
  714. struct macb *bp = netdev_priv(dev);
  715. return mii_ethtool_gset(&bp->mii, cmd);
  716. }
  717. static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  718. {
  719. struct macb *bp = netdev_priv(dev);
  720. return mii_ethtool_sset(&bp->mii, cmd);
  721. }
  722. static void macb_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  723. {
  724. struct macb *bp = netdev_priv(dev);
  725. strcpy(info->driver, bp->pdev->dev.driver->name);
  726. strcpy(info->version, "$Revision: 1.14 $");
  727. strcpy(info->bus_info, bp->pdev->dev.bus_id);
  728. }
  729. static int macb_nway_reset(struct net_device *dev)
  730. {
  731. struct macb *bp = netdev_priv(dev);
  732. return mii_nway_restart(&bp->mii);
  733. }
  734. static struct ethtool_ops macb_ethtool_ops = {
  735. .get_settings = macb_get_settings,
  736. .set_settings = macb_set_settings,
  737. .get_drvinfo = macb_get_drvinfo,
  738. .nway_reset = macb_nway_reset,
  739. .get_link = ethtool_op_get_link,
  740. };
  741. static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  742. {
  743. struct macb *bp = netdev_priv(dev);
  744. if (!netif_running(dev))
  745. return -EINVAL;
  746. return generic_mii_ioctl(&bp->mii, if_mii(rq), cmd, NULL);
  747. }
  748. static ssize_t macb_mii_show(const struct device *_dev, char *buf,
  749. unsigned long addr)
  750. {
  751. struct net_device *dev = to_net_dev(_dev);
  752. struct macb *bp = netdev_priv(dev);
  753. ssize_t ret = -EINVAL;
  754. if (netif_running(dev)) {
  755. int value;
  756. value = macb_mdio_read(dev, bp->mii.phy_id, addr);
  757. ret = sprintf(buf, "0x%04x\n", (uint16_t)value);
  758. }
  759. return ret;
  760. }
  761. #define MII_ENTRY(name, addr) \
  762. static ssize_t show_##name(struct device *_dev, \
  763. struct device_attribute *attr, \
  764. char *buf) \
  765. { \
  766. return macb_mii_show(_dev, buf, addr); \
  767. } \
  768. static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
  769. MII_ENTRY(bmcr, MII_BMCR);
  770. MII_ENTRY(bmsr, MII_BMSR);
  771. MII_ENTRY(physid1, MII_PHYSID1);
  772. MII_ENTRY(physid2, MII_PHYSID2);
  773. MII_ENTRY(advertise, MII_ADVERTISE);
  774. MII_ENTRY(lpa, MII_LPA);
  775. MII_ENTRY(expansion, MII_EXPANSION);
  776. static struct attribute *macb_mii_attrs[] = {
  777. &dev_attr_bmcr.attr,
  778. &dev_attr_bmsr.attr,
  779. &dev_attr_physid1.attr,
  780. &dev_attr_physid2.attr,
  781. &dev_attr_advertise.attr,
  782. &dev_attr_lpa.attr,
  783. &dev_attr_expansion.attr,
  784. NULL,
  785. };
  786. static struct attribute_group macb_mii_group = {
  787. .name = "mii",
  788. .attrs = macb_mii_attrs,
  789. };
  790. static void macb_unregister_sysfs(struct net_device *net)
  791. {
  792. struct device *_dev = &net->dev;
  793. sysfs_remove_group(&_dev->kobj, &macb_mii_group);
  794. }
  795. static int macb_register_sysfs(struct net_device *net)
  796. {
  797. struct device *_dev = &net->dev;
  798. int ret;
  799. ret = sysfs_create_group(&_dev->kobj, &macb_mii_group);
  800. if (ret)
  801. printk(KERN_WARNING
  802. "%s: sysfs mii attribute registration failed: %d\n",
  803. net->name, ret);
  804. return ret;
  805. }
  806. static int __devinit macb_probe(struct platform_device *pdev)
  807. {
  808. struct eth_platform_data *pdata;
  809. struct resource *regs;
  810. struct net_device *dev;
  811. struct macb *bp;
  812. unsigned long pclk_hz;
  813. u32 config;
  814. int err = -ENXIO;
  815. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  816. if (!regs) {
  817. dev_err(&pdev->dev, "no mmio resource defined\n");
  818. goto err_out;
  819. }
  820. err = -ENOMEM;
  821. dev = alloc_etherdev(sizeof(*bp));
  822. if (!dev) {
  823. dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
  824. goto err_out;
  825. }
  826. SET_MODULE_OWNER(dev);
  827. SET_NETDEV_DEV(dev, &pdev->dev);
  828. /* TODO: Actually, we have some interesting features... */
  829. dev->features |= 0;
  830. bp = netdev_priv(dev);
  831. bp->pdev = pdev;
  832. bp->dev = dev;
  833. spin_lock_init(&bp->lock);
  834. #if defined(CONFIG_ARCH_AT91)
  835. bp->pclk = clk_get(&pdev->dev, "macb_clk");
  836. if (IS_ERR(bp->pclk)) {
  837. dev_err(&pdev->dev, "failed to get macb_clk\n");
  838. goto err_out_free_dev;
  839. }
  840. clk_enable(bp->pclk);
  841. #else
  842. bp->pclk = clk_get(&pdev->dev, "pclk");
  843. if (IS_ERR(bp->pclk)) {
  844. dev_err(&pdev->dev, "failed to get pclk\n");
  845. goto err_out_free_dev;
  846. }
  847. bp->hclk = clk_get(&pdev->dev, "hclk");
  848. if (IS_ERR(bp->hclk)) {
  849. dev_err(&pdev->dev, "failed to get hclk\n");
  850. goto err_out_put_pclk;
  851. }
  852. clk_enable(bp->pclk);
  853. clk_enable(bp->hclk);
  854. #endif
  855. bp->regs = ioremap(regs->start, regs->end - regs->start + 1);
  856. if (!bp->regs) {
  857. dev_err(&pdev->dev, "failed to map registers, aborting.\n");
  858. err = -ENOMEM;
  859. goto err_out_disable_clocks;
  860. }
  861. dev->irq = platform_get_irq(pdev, 0);
  862. err = request_irq(dev->irq, macb_interrupt, IRQF_SAMPLE_RANDOM,
  863. dev->name, dev);
  864. if (err) {
  865. printk(KERN_ERR
  866. "%s: Unable to request IRQ %d (error %d)\n",
  867. dev->name, dev->irq, err);
  868. goto err_out_iounmap;
  869. }
  870. dev->open = macb_open;
  871. dev->stop = macb_close;
  872. dev->hard_start_xmit = macb_start_xmit;
  873. dev->get_stats = macb_get_stats;
  874. dev->do_ioctl = macb_ioctl;
  875. dev->poll = macb_poll;
  876. dev->weight = 64;
  877. dev->ethtool_ops = &macb_ethtool_ops;
  878. dev->base_addr = regs->start;
  879. INIT_DELAYED_WORK(&bp->periodic_task, macb_periodic_task);
  880. mutex_init(&bp->mdio_mutex);
  881. init_completion(&bp->mdio_complete);
  882. /* Set MII management clock divider */
  883. pclk_hz = clk_get_rate(bp->pclk);
  884. if (pclk_hz <= 20000000)
  885. config = MACB_BF(CLK, MACB_CLK_DIV8);
  886. else if (pclk_hz <= 40000000)
  887. config = MACB_BF(CLK, MACB_CLK_DIV16);
  888. else if (pclk_hz <= 80000000)
  889. config = MACB_BF(CLK, MACB_CLK_DIV32);
  890. else
  891. config = MACB_BF(CLK, MACB_CLK_DIV64);
  892. macb_writel(bp, NCFGR, config);
  893. bp->mii.dev = dev;
  894. bp->mii.mdio_read = macb_mdio_read;
  895. bp->mii.mdio_write = macb_mdio_write;
  896. bp->mii.phy_id_mask = 0x1f;
  897. bp->mii.reg_num_mask = 0x1f;
  898. macb_get_hwaddr(bp);
  899. err = macb_phy_probe(bp);
  900. if (err) {
  901. dev_err(&pdev->dev, "Failed to detect PHY, aborting.\n");
  902. goto err_out_free_irq;
  903. }
  904. pdata = pdev->dev.platform_data;
  905. if (pdata && pdata->is_rmii)
  906. #if defined(CONFIG_ARCH_AT91)
  907. macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
  908. #else
  909. macb_writel(bp, USRIO, 0);
  910. #endif
  911. else
  912. #if defined(CONFIG_ARCH_AT91)
  913. macb_writel(bp, USRIO, MACB_BIT(CLKEN));
  914. #else
  915. macb_writel(bp, USRIO, MACB_BIT(MII));
  916. #endif
  917. bp->tx_pending = DEF_TX_RING_PENDING;
  918. err = register_netdev(dev);
  919. if (err) {
  920. dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
  921. goto err_out_free_irq;
  922. }
  923. platform_set_drvdata(pdev, dev);
  924. macb_register_sysfs(dev);
  925. printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d "
  926. "(%02x:%02x:%02x:%02x:%02x:%02x)\n",
  927. dev->name, dev->base_addr, dev->irq,
  928. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  929. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  930. return 0;
  931. err_out_free_irq:
  932. free_irq(dev->irq, dev);
  933. err_out_iounmap:
  934. iounmap(bp->regs);
  935. err_out_disable_clocks:
  936. #ifndef CONFIG_ARCH_AT91
  937. clk_disable(bp->hclk);
  938. clk_put(bp->hclk);
  939. #endif
  940. clk_disable(bp->pclk);
  941. err_out_put_pclk:
  942. clk_put(bp->pclk);
  943. err_out_free_dev:
  944. free_netdev(dev);
  945. err_out:
  946. platform_set_drvdata(pdev, NULL);
  947. return err;
  948. }
  949. static int __devexit macb_remove(struct platform_device *pdev)
  950. {
  951. struct net_device *dev;
  952. struct macb *bp;
  953. dev = platform_get_drvdata(pdev);
  954. if (dev) {
  955. bp = netdev_priv(dev);
  956. macb_unregister_sysfs(dev);
  957. unregister_netdev(dev);
  958. free_irq(dev->irq, dev);
  959. iounmap(bp->regs);
  960. #ifndef CONFIG_ARCH_AT91
  961. clk_disable(bp->hclk);
  962. clk_put(bp->hclk);
  963. #endif
  964. clk_disable(bp->pclk);
  965. clk_put(bp->pclk);
  966. free_netdev(dev);
  967. platform_set_drvdata(pdev, NULL);
  968. }
  969. return 0;
  970. }
  971. static struct platform_driver macb_driver = {
  972. .probe = macb_probe,
  973. .remove = __devexit_p(macb_remove),
  974. .driver = {
  975. .name = "macb",
  976. },
  977. };
  978. static int __init macb_init(void)
  979. {
  980. return platform_driver_register(&macb_driver);
  981. }
  982. static void __exit macb_exit(void)
  983. {
  984. platform_driver_unregister(&macb_driver);
  985. }
  986. module_init(macb_init);
  987. module_exit(macb_exit);
  988. MODULE_LICENSE("GPL");
  989. MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
  990. MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");