ichxrom.c 9.8 KB

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  1. /*
  2. * ichxrom.c
  3. *
  4. * Normal mappings of chips in physical memory
  5. * $Id: ichxrom.c,v 1.19 2005/11/07 11:14:27 gleixner Exp $
  6. */
  7. #include <linux/module.h>
  8. #include <linux/types.h>
  9. #include <linux/kernel.h>
  10. #include <linux/init.h>
  11. #include <asm/io.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/mtd/map.h>
  14. #include <linux/mtd/cfi.h>
  15. #include <linux/mtd/flashchip.h>
  16. #include <linux/pci.h>
  17. #include <linux/pci_ids.h>
  18. #include <linux/list.h>
  19. #define xstr(s) str(s)
  20. #define str(s) #s
  21. #define MOD_NAME xstr(KBUILD_BASENAME)
  22. #define ADDRESS_NAME_LEN 18
  23. #define ROM_PROBE_STEP_SIZE (64*1024) /* 64KiB */
  24. #define BIOS_CNTL 0x4e
  25. #define FWH_DEC_EN1 0xE3
  26. #define FWH_DEC_EN2 0xF0
  27. #define FWH_SEL1 0xE8
  28. #define FWH_SEL2 0xEE
  29. struct ichxrom_window {
  30. void __iomem* virt;
  31. unsigned long phys;
  32. unsigned long size;
  33. struct list_head maps;
  34. struct resource rsrc;
  35. struct pci_dev *pdev;
  36. };
  37. struct ichxrom_map_info {
  38. struct list_head list;
  39. struct map_info map;
  40. struct mtd_info *mtd;
  41. struct resource rsrc;
  42. char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];
  43. };
  44. static struct ichxrom_window ichxrom_window = {
  45. .maps = LIST_HEAD_INIT(ichxrom_window.maps),
  46. };
  47. static void ichxrom_cleanup(struct ichxrom_window *window)
  48. {
  49. struct ichxrom_map_info *map, *scratch;
  50. u16 word;
  51. /* Disable writes through the rom window */
  52. pci_read_config_word(window->pdev, BIOS_CNTL, &word);
  53. pci_write_config_word(window->pdev, BIOS_CNTL, word & ~1);
  54. pci_dev_put(window->pdev);
  55. /* Free all of the mtd devices */
  56. list_for_each_entry_safe(map, scratch, &window->maps, list) {
  57. if (map->rsrc.parent)
  58. release_resource(&map->rsrc);
  59. del_mtd_device(map->mtd);
  60. map_destroy(map->mtd);
  61. list_del(&map->list);
  62. kfree(map);
  63. }
  64. if (window->rsrc.parent)
  65. release_resource(&window->rsrc);
  66. if (window->virt) {
  67. iounmap(window->virt);
  68. window->virt = NULL;
  69. window->phys = 0;
  70. window->size = 0;
  71. window->pdev = NULL;
  72. }
  73. }
  74. static int __devinit ichxrom_init_one (struct pci_dev *pdev,
  75. const struct pci_device_id *ent)
  76. {
  77. static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };
  78. struct ichxrom_window *window = &ichxrom_window;
  79. struct ichxrom_map_info *map = NULL;
  80. unsigned long map_top;
  81. u8 byte;
  82. u16 word;
  83. /* For now I just handle the ichx and I assume there
  84. * are not a lot of resources up at the top of the address
  85. * space. It is possible to handle other devices in the
  86. * top 16MB but it is very painful. Also since
  87. * you can only really attach a FWH to an ICHX there
  88. * a number of simplifications you can make.
  89. *
  90. * Also you can page firmware hubs if an 8MB window isn't enough
  91. * but don't currently handle that case either.
  92. */
  93. window->pdev = pdev;
  94. /* Find a region continuous to the end of the ROM window */
  95. window->phys = 0;
  96. pci_read_config_byte(pdev, FWH_DEC_EN1, &byte);
  97. if (byte == 0xff) {
  98. window->phys = 0xffc00000;
  99. pci_read_config_byte(pdev, FWH_DEC_EN2, &byte);
  100. if ((byte & 0x0f) == 0x0f) {
  101. window->phys = 0xff400000;
  102. }
  103. else if ((byte & 0x0e) == 0x0e) {
  104. window->phys = 0xff500000;
  105. }
  106. else if ((byte & 0x0c) == 0x0c) {
  107. window->phys = 0xff600000;
  108. }
  109. else if ((byte & 0x08) == 0x08) {
  110. window->phys = 0xff700000;
  111. }
  112. }
  113. else if ((byte & 0xfe) == 0xfe) {
  114. window->phys = 0xffc80000;
  115. }
  116. else if ((byte & 0xfc) == 0xfc) {
  117. window->phys = 0xffd00000;
  118. }
  119. else if ((byte & 0xf8) == 0xf8) {
  120. window->phys = 0xffd80000;
  121. }
  122. else if ((byte & 0xf0) == 0xf0) {
  123. window->phys = 0xffe00000;
  124. }
  125. else if ((byte & 0xe0) == 0xe0) {
  126. window->phys = 0xffe80000;
  127. }
  128. else if ((byte & 0xc0) == 0xc0) {
  129. window->phys = 0xfff00000;
  130. }
  131. else if ((byte & 0x80) == 0x80) {
  132. window->phys = 0xfff80000;
  133. }
  134. if (window->phys == 0) {
  135. printk(KERN_ERR MOD_NAME ": Rom window is closed\n");
  136. goto out;
  137. }
  138. window->phys -= 0x400000UL;
  139. window->size = (0xffffffffUL - window->phys) + 1UL;
  140. /* Enable writes through the rom window */
  141. pci_read_config_word(pdev, BIOS_CNTL, &word);
  142. if (!(word & 1) && (word & (1<<1))) {
  143. /* The BIOS will generate an error if I enable
  144. * this device, so don't even try.
  145. */
  146. printk(KERN_ERR MOD_NAME ": firmware access control, I can't enable writes\n");
  147. goto out;
  148. }
  149. pci_write_config_word(pdev, BIOS_CNTL, word | 1);
  150. /*
  151. * Try to reserve the window mem region. If this fails then
  152. * it is likely due to the window being "reseved" by the BIOS.
  153. */
  154. window->rsrc.name = MOD_NAME;
  155. window->rsrc.start = window->phys;
  156. window->rsrc.end = window->phys + window->size - 1;
  157. window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  158. if (request_resource(&iomem_resource, &window->rsrc)) {
  159. window->rsrc.parent = NULL;
  160. printk(KERN_DEBUG MOD_NAME
  161. ": %s(): Unable to register resource"
  162. " 0x%.16llx-0x%.16llx - kernel bug?\n",
  163. __func__,
  164. (unsigned long long)window->rsrc.start,
  165. (unsigned long long)window->rsrc.end);
  166. }
  167. /* Map the firmware hub into my address space. */
  168. window->virt = ioremap_nocache(window->phys, window->size);
  169. if (!window->virt) {
  170. printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",
  171. window->phys, window->size);
  172. goto out;
  173. }
  174. /* Get the first address to look for an rom chip at */
  175. map_top = window->phys;
  176. if ((window->phys & 0x3fffff) != 0) {
  177. map_top = window->phys + 0x400000;
  178. }
  179. #if 1
  180. /* The probe sequence run over the firmware hub lock
  181. * registers sets them to 0x7 (no access).
  182. * Probe at most the last 4M of the address space.
  183. */
  184. if (map_top < 0xffc00000) {
  185. map_top = 0xffc00000;
  186. }
  187. #endif
  188. /* Loop through and look for rom chips */
  189. while((map_top - 1) < 0xffffffffUL) {
  190. struct cfi_private *cfi;
  191. unsigned long offset;
  192. int i;
  193. if (!map) {
  194. map = kmalloc(sizeof(*map), GFP_KERNEL);
  195. }
  196. if (!map) {
  197. printk(KERN_ERR MOD_NAME ": kmalloc failed");
  198. goto out;
  199. }
  200. memset(map, 0, sizeof(*map));
  201. INIT_LIST_HEAD(&map->list);
  202. map->map.name = map->map_name;
  203. map->map.phys = map_top;
  204. offset = map_top - window->phys;
  205. map->map.virt = (void __iomem *)
  206. (((unsigned long)(window->virt)) + offset);
  207. map->map.size = 0xffffffffUL - map_top + 1UL;
  208. /* Set the name of the map to the address I am trying */
  209. sprintf(map->map_name, "%s @%08Lx",
  210. MOD_NAME, (unsigned long long)map->map.phys);
  211. /* Firmware hubs only use vpp when being programmed
  212. * in a factory setting. So in-place programming
  213. * needs to use a different method.
  214. */
  215. for(map->map.bankwidth = 32; map->map.bankwidth;
  216. map->map.bankwidth >>= 1)
  217. {
  218. char **probe_type;
  219. /* Skip bankwidths that are not supported */
  220. if (!map_bankwidth_supported(map->map.bankwidth))
  221. continue;
  222. /* Setup the map methods */
  223. simple_map_init(&map->map);
  224. /* Try all of the probe methods */
  225. probe_type = rom_probe_types;
  226. for(; *probe_type; probe_type++) {
  227. map->mtd = do_map_probe(*probe_type, &map->map);
  228. if (map->mtd)
  229. goto found;
  230. }
  231. }
  232. map_top += ROM_PROBE_STEP_SIZE;
  233. continue;
  234. found:
  235. /* Trim the size if we are larger than the map */
  236. if (map->mtd->size > map->map.size) {
  237. printk(KERN_WARNING MOD_NAME
  238. " rom(%u) larger than window(%lu). fixing...\n",
  239. map->mtd->size, map->map.size);
  240. map->mtd->size = map->map.size;
  241. }
  242. if (window->rsrc.parent) {
  243. /*
  244. * Registering the MTD device in iomem may not be possible
  245. * if there is a BIOS "reserved" and BUSY range. If this
  246. * fails then continue anyway.
  247. */
  248. map->rsrc.name = map->map_name;
  249. map->rsrc.start = map->map.phys;
  250. map->rsrc.end = map->map.phys + map->mtd->size - 1;
  251. map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  252. if (request_resource(&window->rsrc, &map->rsrc)) {
  253. printk(KERN_ERR MOD_NAME
  254. ": cannot reserve MTD resource\n");
  255. map->rsrc.parent = NULL;
  256. }
  257. }
  258. /* Make the whole region visible in the map */
  259. map->map.virt = window->virt;
  260. map->map.phys = window->phys;
  261. cfi = map->map.fldrv_priv;
  262. for(i = 0; i < cfi->numchips; i++) {
  263. cfi->chips[i].start += offset;
  264. }
  265. /* Now that the mtd devices is complete claim and export it */
  266. map->mtd->owner = THIS_MODULE;
  267. if (add_mtd_device(map->mtd)) {
  268. map_destroy(map->mtd);
  269. map->mtd = NULL;
  270. goto out;
  271. }
  272. /* Calculate the new value of map_top */
  273. map_top += map->mtd->size;
  274. /* File away the map structure */
  275. list_add(&map->list, &window->maps);
  276. map = NULL;
  277. }
  278. out:
  279. /* Free any left over map structures */
  280. kfree(map);
  281. /* See if I have any map structures */
  282. if (list_empty(&window->maps)) {
  283. ichxrom_cleanup(window);
  284. return -ENODEV;
  285. }
  286. return 0;
  287. }
  288. static void __devexit ichxrom_remove_one (struct pci_dev *pdev)
  289. {
  290. struct ichxrom_window *window = &ichxrom_window;
  291. ichxrom_cleanup(window);
  292. }
  293. static struct pci_device_id ichxrom_pci_tbl[] __devinitdata = {
  294. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0,
  295. PCI_ANY_ID, PCI_ANY_ID, },
  296. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
  297. PCI_ANY_ID, PCI_ANY_ID, },
  298. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
  299. PCI_ANY_ID, PCI_ANY_ID, },
  300. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
  301. PCI_ANY_ID, PCI_ANY_ID, },
  302. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
  303. PCI_ANY_ID, PCI_ANY_ID, },
  304. { 0, },
  305. };
  306. #if 0
  307. MODULE_DEVICE_TABLE(pci, ichxrom_pci_tbl);
  308. static struct pci_driver ichxrom_driver = {
  309. .name = MOD_NAME,
  310. .id_table = ichxrom_pci_tbl,
  311. .probe = ichxrom_init_one,
  312. .remove = ichxrom_remove_one,
  313. };
  314. #endif
  315. static int __init init_ichxrom(void)
  316. {
  317. struct pci_dev *pdev;
  318. struct pci_device_id *id;
  319. pdev = NULL;
  320. for (id = ichxrom_pci_tbl; id->vendor; id++) {
  321. pdev = pci_get_device(id->vendor, id->device, NULL);
  322. if (pdev) {
  323. break;
  324. }
  325. }
  326. if (pdev) {
  327. return ichxrom_init_one(pdev, &ichxrom_pci_tbl[0]);
  328. }
  329. return -ENXIO;
  330. #if 0
  331. return pci_register_driver(&ichxrom_driver);
  332. #endif
  333. }
  334. static void __exit cleanup_ichxrom(void)
  335. {
  336. ichxrom_remove_one(ichxrom_window.pdev);
  337. }
  338. module_init(init_ichxrom);
  339. module_exit(cleanup_ichxrom);
  340. MODULE_LICENSE("GPL");
  341. MODULE_AUTHOR("Eric Biederman <ebiederman@lnxi.com>");
  342. MODULE_DESCRIPTION("MTD map driver for BIOS chips on the ICHX southbridge");