sm501.c 25 KB

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  1. /* linux/drivers/mfd/sm501.c
  2. *
  3. * Copyright (C) 2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. * Vincent Sanders <vince@simtec.co.uk>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * SM501 MFD driver
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/delay.h>
  16. #include <linux/init.h>
  17. #include <linux/list.h>
  18. #include <linux/device.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pci.h>
  21. #include <linux/sm501.h>
  22. #include <linux/sm501-regs.h>
  23. #include <asm/io.h>
  24. struct sm501_device {
  25. struct list_head list;
  26. struct platform_device pdev;
  27. };
  28. struct sm501_devdata {
  29. spinlock_t reg_lock;
  30. struct mutex clock_lock;
  31. struct list_head devices;
  32. struct device *dev;
  33. struct resource *io_res;
  34. struct resource *mem_res;
  35. struct resource *regs_claim;
  36. struct sm501_platdata *platdata;
  37. int unit_power[20];
  38. unsigned int pdev_id;
  39. unsigned int irq;
  40. void __iomem *regs;
  41. };
  42. #define MHZ (1000 * 1000)
  43. #ifdef DEBUG
  44. static const unsigned int misc_div[] = {
  45. [0] = 1,
  46. [1] = 2,
  47. [2] = 4,
  48. [3] = 8,
  49. [4] = 16,
  50. [5] = 32,
  51. [6] = 64,
  52. [7] = 128,
  53. [8] = 3,
  54. [9] = 6,
  55. [10] = 12,
  56. [11] = 24,
  57. [12] = 48,
  58. [13] = 96,
  59. [14] = 192,
  60. [15] = 384,
  61. };
  62. static const unsigned int px_div[] = {
  63. [0] = 1,
  64. [1] = 2,
  65. [2] = 4,
  66. [3] = 8,
  67. [4] = 16,
  68. [5] = 32,
  69. [6] = 64,
  70. [7] = 128,
  71. [8] = 3,
  72. [9] = 6,
  73. [10] = 12,
  74. [11] = 24,
  75. [12] = 48,
  76. [13] = 96,
  77. [14] = 192,
  78. [15] = 384,
  79. [16] = 5,
  80. [17] = 10,
  81. [18] = 20,
  82. [19] = 40,
  83. [20] = 80,
  84. [21] = 160,
  85. [22] = 320,
  86. [23] = 604,
  87. };
  88. static unsigned long decode_div(unsigned long pll2, unsigned long val,
  89. unsigned int lshft, unsigned int selbit,
  90. unsigned long mask, const unsigned int *dtab)
  91. {
  92. if (val & selbit)
  93. pll2 = 288 * MHZ;
  94. return pll2 / dtab[(val >> lshft) & mask];
  95. }
  96. #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
  97. /* sm501_dump_clk
  98. *
  99. * Print out the current clock configuration for the device
  100. */
  101. static void sm501_dump_clk(struct sm501_devdata *sm)
  102. {
  103. unsigned long misct = readl(sm->regs + SM501_MISC_TIMING);
  104. unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
  105. unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
  106. unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL);
  107. unsigned long sdclk0, sdclk1;
  108. unsigned long pll2 = 0;
  109. switch (misct & 0x30) {
  110. case 0x00:
  111. pll2 = 336 * MHZ;
  112. break;
  113. case 0x10:
  114. pll2 = 288 * MHZ;
  115. break;
  116. case 0x20:
  117. pll2 = 240 * MHZ;
  118. break;
  119. case 0x30:
  120. pll2 = 192 * MHZ;
  121. break;
  122. }
  123. sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
  124. sdclk0 /= misc_div[((misct >> 8) & 0xf)];
  125. sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
  126. sdclk1 /= misc_div[((misct >> 16) & 0xf)];
  127. dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
  128. misct, pm0, pm1);
  129. dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
  130. fmt_freq(pll2), sdclk0, sdclk1);
  131. dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
  132. dev_dbg(sm->dev, "PM0[%c]: "
  133. "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
  134. x "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
  135. (pmc & 3 ) == 0 ? '*' : '-',
  136. fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31, px_div)),
  137. fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15, misc_div)),
  138. fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15, misc_div)),
  139. fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15, misc_div)));
  140. dev_dbg(sm->dev, "PM1[%c]: "
  141. "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
  142. "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
  143. (pmc & 3 ) == 1 ? '*' : '-',
  144. fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31, px_div)),
  145. fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15, misc_div)),
  146. fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15, misc_div)),
  147. fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15, misc_div)));
  148. }
  149. #else
  150. static void sm501_dump_clk(struct sm501_devdata *sm)
  151. {
  152. }
  153. #endif
  154. /* sm501_sync_regs
  155. *
  156. * ensure the
  157. */
  158. static void sm501_sync_regs(struct sm501_devdata *sm)
  159. {
  160. readl(sm->regs);
  161. }
  162. /* sm501_misc_control
  163. *
  164. * alters the misceleneous control parameters
  165. */
  166. int sm501_misc_control(struct device *dev,
  167. unsigned long set, unsigned long clear)
  168. {
  169. struct sm501_devdata *sm = dev_get_drvdata(dev);
  170. unsigned long misc;
  171. unsigned long save;
  172. unsigned long to;
  173. spin_lock_irqsave(&sm->reg_lock, save);
  174. misc = readl(sm->regs + SM501_MISC_CONTROL);
  175. to = (misc & ~clear) | set;
  176. if (to != misc) {
  177. writel(to, sm->regs + SM501_MISC_CONTROL);
  178. sm501_sync_regs(sm);
  179. dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
  180. }
  181. spin_unlock_irqrestore(&sm->reg_lock, save);
  182. return to;
  183. }
  184. EXPORT_SYMBOL_GPL(sm501_misc_control);
  185. /* sm501_modify_reg
  186. *
  187. * Modify a register in the SM501 which may be shared with other
  188. * drivers.
  189. */
  190. unsigned long sm501_modify_reg(struct device *dev,
  191. unsigned long reg,
  192. unsigned long set,
  193. unsigned long clear)
  194. {
  195. struct sm501_devdata *sm = dev_get_drvdata(dev);
  196. unsigned long data;
  197. unsigned long save;
  198. spin_lock_irqsave(&sm->reg_lock, save);
  199. data = readl(sm->regs + reg);
  200. data |= set;
  201. data &= ~clear;
  202. writel(data, sm->regs + reg);
  203. sm501_sync_regs(sm);
  204. spin_unlock_irqrestore(&sm->reg_lock, save);
  205. return data;
  206. }
  207. EXPORT_SYMBOL_GPL(sm501_modify_reg);
  208. unsigned long sm501_gpio_get(struct device *dev,
  209. unsigned long gpio)
  210. {
  211. struct sm501_devdata *sm = dev_get_drvdata(dev);
  212. unsigned long result;
  213. unsigned long reg;
  214. reg = (gpio > 32) ? SM501_GPIO_DATA_HIGH : SM501_GPIO_DATA_LOW;
  215. result = readl(sm->regs + reg);
  216. result >>= (gpio & 31);
  217. return result & 1UL;
  218. }
  219. EXPORT_SYMBOL_GPL(sm501_gpio_get);
  220. void sm501_gpio_set(struct device *dev,
  221. unsigned long gpio,
  222. unsigned int to,
  223. unsigned int dir)
  224. {
  225. struct sm501_devdata *sm = dev_get_drvdata(dev);
  226. unsigned long bit = 1 << (gpio & 31);
  227. unsigned long base;
  228. unsigned long save;
  229. unsigned long val;
  230. base = (gpio > 32) ? SM501_GPIO_DATA_HIGH : SM501_GPIO_DATA_LOW;
  231. base += SM501_GPIO;
  232. spin_lock_irqsave(&sm->reg_lock, save);
  233. val = readl(sm->regs + base) & ~bit;
  234. if (to)
  235. val |= bit;
  236. writel(val, sm->regs + base);
  237. val = readl(sm->regs + SM501_GPIO_DDR_LOW) & ~bit;
  238. if (dir)
  239. val |= bit;
  240. writel(val, sm->regs + SM501_GPIO_DDR_LOW);
  241. sm501_sync_regs(sm);
  242. spin_unlock_irqrestore(&sm->reg_lock, save);
  243. }
  244. EXPORT_SYMBOL_GPL(sm501_gpio_set);
  245. /* sm501_unit_power
  246. *
  247. * alters the power active gate to set specific units on or off
  248. */
  249. int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
  250. {
  251. struct sm501_devdata *sm = dev_get_drvdata(dev);
  252. unsigned long mode;
  253. unsigned long gate;
  254. unsigned long clock;
  255. mutex_lock(&sm->clock_lock);
  256. mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
  257. gate = readl(sm->regs + SM501_CURRENT_GATE);
  258. clock = readl(sm->regs + SM501_CURRENT_CLOCK);
  259. mode &= 3; /* get current power mode */
  260. if (unit >= ARRAY_SIZE(sm->unit_power)) {
  261. dev_err(dev, "%s: bad unit %d\n", __FUNCTION__, unit);
  262. goto already;
  263. }
  264. dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __FUNCTION__, unit,
  265. sm->unit_power[unit], to);
  266. if (to == 0 && sm->unit_power[unit] == 0) {
  267. dev_err(sm->dev, "unit %d is already shutdown\n", unit);
  268. goto already;
  269. }
  270. sm->unit_power[unit] += to ? 1 : -1;
  271. to = sm->unit_power[unit] ? 1 : 0;
  272. if (to) {
  273. if (gate & (1 << unit))
  274. goto already;
  275. gate |= (1 << unit);
  276. } else {
  277. if (!(gate & (1 << unit)))
  278. goto already;
  279. gate &= ~(1 << unit);
  280. }
  281. switch (mode) {
  282. case 1:
  283. writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
  284. writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
  285. mode = 0;
  286. break;
  287. case 2:
  288. case 0:
  289. writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
  290. writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
  291. mode = 1;
  292. break;
  293. default:
  294. return -1;
  295. }
  296. writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
  297. sm501_sync_regs(sm);
  298. dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
  299. gate, clock, mode);
  300. msleep(16);
  301. already:
  302. mutex_unlock(&sm->clock_lock);
  303. return gate;
  304. }
  305. EXPORT_SYMBOL_GPL(sm501_unit_power);
  306. /* Perform a rounded division. */
  307. static long sm501fb_round_div(long num, long denom)
  308. {
  309. /* n / d + 1 / 2 = (2n + d) / 2d */
  310. return (2 * num + denom) / (2 * denom);
  311. }
  312. /* clock value structure. */
  313. struct sm501_clock {
  314. unsigned long mclk;
  315. int divider;
  316. int shift;
  317. };
  318. /* sm501_select_clock
  319. *
  320. * selects nearest discrete clock frequency the SM501 can achive
  321. * the maximum divisor is 3 or 5
  322. */
  323. static unsigned long sm501_select_clock(unsigned long freq,
  324. struct sm501_clock *clock,
  325. int max_div)
  326. {
  327. unsigned long mclk;
  328. int divider;
  329. int shift;
  330. long diff;
  331. long best_diff = 999999999;
  332. /* Try 288MHz and 336MHz clocks. */
  333. for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
  334. /* try dividers 1 and 3 for CRT and for panel,
  335. try divider 5 for panel only.*/
  336. for (divider = 1; divider <= max_div; divider += 2) {
  337. /* try all 8 shift values.*/
  338. for (shift = 0; shift < 8; shift++) {
  339. /* Calculate difference to requested clock */
  340. diff = sm501fb_round_div(mclk, divider << shift) - freq;
  341. if (diff < 0)
  342. diff = -diff;
  343. /* If it is less than the current, use it */
  344. if (diff < best_diff) {
  345. best_diff = diff;
  346. clock->mclk = mclk;
  347. clock->divider = divider;
  348. clock->shift = shift;
  349. }
  350. }
  351. }
  352. }
  353. /* Return best clock. */
  354. return clock->mclk / (clock->divider << clock->shift);
  355. }
  356. /* sm501_set_clock
  357. *
  358. * set one of the four clock sources to the closest available frequency to
  359. * the one specified
  360. */
  361. unsigned long sm501_set_clock(struct device *dev,
  362. int clksrc,
  363. unsigned long req_freq)
  364. {
  365. struct sm501_devdata *sm = dev_get_drvdata(dev);
  366. unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
  367. unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE);
  368. unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK);
  369. unsigned char reg;
  370. unsigned long sm501_freq; /* the actual frequency acheived */
  371. struct sm501_clock to;
  372. /* find achivable discrete frequency and setup register value
  373. * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
  374. * has an extra bit for the divider */
  375. switch (clksrc) {
  376. case SM501_CLOCK_P2XCLK:
  377. /* This clock is divided in half so to achive the
  378. * requested frequency the value must be multiplied by
  379. * 2. This clock also has an additional pre divisor */
  380. sm501_freq = (sm501_select_clock(2 * req_freq, &to, 5) / 2);
  381. reg=to.shift & 0x07;/* bottom 3 bits are shift */
  382. if (to.divider == 3)
  383. reg |= 0x08; /* /3 divider required */
  384. else if (to.divider == 5)
  385. reg |= 0x10; /* /5 divider required */
  386. if (to.mclk != 288000000)
  387. reg |= 0x20; /* which mclk pll is source */
  388. break;
  389. case SM501_CLOCK_V2XCLK:
  390. /* This clock is divided in half so to achive the
  391. * requested frequency the value must be multiplied by 2. */
  392. sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
  393. reg=to.shift & 0x07; /* bottom 3 bits are shift */
  394. if (to.divider == 3)
  395. reg |= 0x08; /* /3 divider required */
  396. if (to.mclk != 288000000)
  397. reg |= 0x10; /* which mclk pll is source */
  398. break;
  399. case SM501_CLOCK_MCLK:
  400. case SM501_CLOCK_M1XCLK:
  401. /* These clocks are the same and not further divided */
  402. sm501_freq = sm501_select_clock( req_freq, &to, 3);
  403. reg=to.shift & 0x07; /* bottom 3 bits are shift */
  404. if (to.divider == 3)
  405. reg |= 0x08; /* /3 divider required */
  406. if (to.mclk != 288000000)
  407. reg |= 0x10; /* which mclk pll is source */
  408. break;
  409. default:
  410. return 0; /* this is bad */
  411. }
  412. mutex_lock(&sm->clock_lock);
  413. mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
  414. gate = readl(sm->regs + SM501_CURRENT_GATE);
  415. clock = readl(sm->regs + SM501_CURRENT_CLOCK);
  416. clock = clock & ~(0xFF << clksrc);
  417. clock |= reg<<clksrc;
  418. mode &= 3; /* find current mode */
  419. switch (mode) {
  420. case 1:
  421. writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
  422. writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
  423. mode = 0;
  424. break;
  425. case 2:
  426. case 0:
  427. writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
  428. writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
  429. mode = 1;
  430. break;
  431. default:
  432. mutex_unlock(&sm->clock_lock);
  433. return -1;
  434. }
  435. writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
  436. sm501_sync_regs(sm);
  437. dev_info(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
  438. gate, clock, mode);
  439. msleep(16);
  440. mutex_unlock(&sm->clock_lock);
  441. sm501_dump_clk(sm);
  442. return sm501_freq;
  443. }
  444. EXPORT_SYMBOL_GPL(sm501_set_clock);
  445. /* sm501_find_clock
  446. *
  447. * finds the closest available frequency for a given clock
  448. */
  449. unsigned long sm501_find_clock(int clksrc,
  450. unsigned long req_freq)
  451. {
  452. unsigned long sm501_freq; /* the frequency achiveable by the 501 */
  453. struct sm501_clock to;
  454. switch (clksrc) {
  455. case SM501_CLOCK_P2XCLK:
  456. sm501_freq = (sm501_select_clock(2 * req_freq, &to, 5) / 2);
  457. break;
  458. case SM501_CLOCK_V2XCLK:
  459. sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
  460. break;
  461. case SM501_CLOCK_MCLK:
  462. case SM501_CLOCK_M1XCLK:
  463. sm501_freq = sm501_select_clock(req_freq, &to, 3);
  464. break;
  465. default:
  466. sm501_freq = 0; /* error */
  467. }
  468. return sm501_freq;
  469. }
  470. EXPORT_SYMBOL_GPL(sm501_find_clock);
  471. static struct sm501_device *to_sm_device(struct platform_device *pdev)
  472. {
  473. return container_of(pdev, struct sm501_device, pdev);
  474. }
  475. /* sm501_device_release
  476. *
  477. * A release function for the platform devices we create to allow us to
  478. * free any items we allocated
  479. */
  480. static void sm501_device_release(struct device *dev)
  481. {
  482. kfree(to_sm_device(to_platform_device(dev)));
  483. }
  484. /* sm501_create_subdev
  485. *
  486. * Create a skeleton platform device with resources for passing to a
  487. * sub-driver
  488. */
  489. static struct platform_device *
  490. sm501_create_subdev(struct sm501_devdata *sm,
  491. char *name, unsigned int res_count)
  492. {
  493. struct sm501_device *smdev;
  494. smdev = kzalloc(sizeof(struct sm501_device) +
  495. sizeof(struct resource) * res_count, GFP_KERNEL);
  496. if (!smdev)
  497. return NULL;
  498. smdev->pdev.dev.release = sm501_device_release;
  499. smdev->pdev.name = name;
  500. smdev->pdev.id = sm->pdev_id;
  501. smdev->pdev.resource = (struct resource *)(smdev+1);
  502. smdev->pdev.num_resources = res_count;
  503. smdev->pdev.dev.parent = sm->dev;
  504. return &smdev->pdev;
  505. }
  506. /* sm501_register_device
  507. *
  508. * Register a platform device created with sm501_create_subdev()
  509. */
  510. static int sm501_register_device(struct sm501_devdata *sm,
  511. struct platform_device *pdev)
  512. {
  513. struct sm501_device *smdev = to_sm_device(pdev);
  514. int ptr;
  515. int ret;
  516. for (ptr = 0; ptr < pdev->num_resources; ptr++) {
  517. printk("%s[%d] flags %08lx: %08llx..%08llx\n",
  518. pdev->name, ptr,
  519. pdev->resource[ptr].flags,
  520. (unsigned long long)pdev->resource[ptr].start,
  521. (unsigned long long)pdev->resource[ptr].end);
  522. }
  523. ret = platform_device_register(pdev);
  524. if (ret >= 0) {
  525. dev_dbg(sm->dev, "registered %s\n", pdev->name);
  526. list_add_tail(&smdev->list, &sm->devices);
  527. } else
  528. dev_err(sm->dev, "error registering %s (%d)\n",
  529. pdev->name, ret);
  530. return ret;
  531. }
  532. /* sm501_create_subio
  533. *
  534. * Fill in an IO resource for a sub device
  535. */
  536. static void sm501_create_subio(struct sm501_devdata *sm,
  537. struct resource *res,
  538. resource_size_t offs,
  539. resource_size_t size)
  540. {
  541. res->flags = IORESOURCE_MEM;
  542. res->parent = sm->io_res;
  543. res->start = sm->io_res->start + offs;
  544. res->end = res->start + size - 1;
  545. }
  546. /* sm501_create_mem
  547. *
  548. * Fill in an MEM resource for a sub device
  549. */
  550. static void sm501_create_mem(struct sm501_devdata *sm,
  551. struct resource *res,
  552. resource_size_t *offs,
  553. resource_size_t size)
  554. {
  555. *offs -= size; /* adjust memory size */
  556. res->flags = IORESOURCE_MEM;
  557. res->parent = sm->mem_res;
  558. res->start = sm->mem_res->start + *offs;
  559. res->end = res->start + size - 1;
  560. }
  561. /* sm501_create_irq
  562. *
  563. * Fill in an IRQ resource for a sub device
  564. */
  565. static void sm501_create_irq(struct sm501_devdata *sm,
  566. struct resource *res)
  567. {
  568. res->flags = IORESOURCE_IRQ;
  569. res->parent = NULL;
  570. res->start = res->end = sm->irq;
  571. }
  572. static int sm501_register_usbhost(struct sm501_devdata *sm,
  573. resource_size_t *mem_avail)
  574. {
  575. struct platform_device *pdev;
  576. pdev = sm501_create_subdev(sm, "sm501-usb", 3);
  577. if (!pdev)
  578. return -ENOMEM;
  579. sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
  580. sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
  581. sm501_create_irq(sm, &pdev->resource[2]);
  582. return sm501_register_device(sm, pdev);
  583. }
  584. static int sm501_register_display(struct sm501_devdata *sm,
  585. resource_size_t *mem_avail)
  586. {
  587. struct platform_device *pdev;
  588. pdev = sm501_create_subdev(sm, "sm501-fb", 4);
  589. if (!pdev)
  590. return -ENOMEM;
  591. sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
  592. sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
  593. sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
  594. sm501_create_irq(sm, &pdev->resource[3]);
  595. return sm501_register_device(sm, pdev);
  596. }
  597. /* sm501_dbg_regs
  598. *
  599. * Debug attribute to attach to parent device to show core registers
  600. */
  601. static ssize_t sm501_dbg_regs(struct device *dev,
  602. struct device_attribute *attr, char *buff)
  603. {
  604. struct sm501_devdata *sm = dev_get_drvdata(dev) ;
  605. unsigned int reg;
  606. char *ptr = buff;
  607. int ret;
  608. for (reg = 0x00; reg < 0x70; reg += 4) {
  609. ret = sprintf(ptr, "%08x = %08x\n",
  610. reg, readl(sm->regs + reg));
  611. ptr += ret;
  612. }
  613. return ptr - buff;
  614. }
  615. static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL);
  616. /* sm501_init_reg
  617. *
  618. * Helper function for the init code to setup a register
  619. */
  620. static inline void sm501_init_reg(struct sm501_devdata *sm,
  621. unsigned long reg,
  622. struct sm501_reg_init *r)
  623. {
  624. unsigned long tmp;
  625. tmp = readl(sm->regs + reg);
  626. tmp |= r->set;
  627. tmp &= ~r->mask;
  628. writel(tmp, sm->regs + reg);
  629. }
  630. /* sm501_init_regs
  631. *
  632. * Setup core register values
  633. */
  634. static void sm501_init_regs(struct sm501_devdata *sm,
  635. struct sm501_initdata *init)
  636. {
  637. sm501_misc_control(sm->dev,
  638. init->misc_control.set,
  639. init->misc_control.mask);
  640. sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
  641. sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
  642. sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
  643. if (init->mclk) {
  644. dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
  645. sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
  646. }
  647. if (init->m1xclk) {
  648. dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
  649. sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
  650. }
  651. }
  652. static unsigned int sm501_mem_local[] = {
  653. [0] = 4*1024*1024,
  654. [1] = 8*1024*1024,
  655. [2] = 16*1024*1024,
  656. [3] = 32*1024*1024,
  657. [4] = 64*1024*1024,
  658. [5] = 2*1024*1024,
  659. };
  660. /* sm501_init_dev
  661. *
  662. * Common init code for an SM501
  663. */
  664. static int sm501_init_dev(struct sm501_devdata *sm)
  665. {
  666. resource_size_t mem_avail;
  667. unsigned long dramctrl;
  668. int ret;
  669. mutex_init(&sm->clock_lock);
  670. spin_lock_init(&sm->reg_lock);
  671. INIT_LIST_HEAD(&sm->devices);
  672. dramctrl = readl(sm->regs + SM501_DRAM_CONTROL);
  673. mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
  674. dev_info(sm->dev, "SM501 At %p: Version %08x, %ld Mb, IRQ %d\n",
  675. sm->regs, readl(sm->regs + SM501_DEVICEID),
  676. (unsigned long)mem_avail >> 20, sm->irq);
  677. dev_info(sm->dev, "CurrentGate %08x\n", readl(sm->regs+0x38));
  678. dev_info(sm->dev, "CurrentClock %08x\n", readl(sm->regs+0x3c));
  679. dev_info(sm->dev, "PowerModeControl %08x\n", readl(sm->regs+0x54));
  680. ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
  681. if (ret)
  682. dev_err(sm->dev, "failed to create debug regs file\n");
  683. sm501_dump_clk(sm);
  684. /* check to see if we have some device initialisation */
  685. if (sm->platdata) {
  686. struct sm501_platdata *pdata = sm->platdata;
  687. if (pdata->init) {
  688. sm501_init_regs(sm, sm->platdata->init);
  689. if (pdata->init->devices & SM501_USE_USB_HOST)
  690. sm501_register_usbhost(sm, &mem_avail);
  691. }
  692. }
  693. /* always create a framebuffer */
  694. sm501_register_display(sm, &mem_avail);
  695. return 0;
  696. }
  697. static int sm501_plat_probe(struct platform_device *dev)
  698. {
  699. struct sm501_devdata *sm;
  700. int err;
  701. sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
  702. if (sm == NULL) {
  703. dev_err(&dev->dev, "no memory for device data\n");
  704. err = -ENOMEM;
  705. goto err1;
  706. }
  707. sm->dev = &dev->dev;
  708. sm->pdev_id = dev->id;
  709. sm->irq = platform_get_irq(dev, 0);
  710. sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
  711. sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  712. sm->platdata = dev->dev.platform_data;
  713. if (sm->irq < 0) {
  714. dev_err(&dev->dev, "failed to get irq resource\n");
  715. err = sm->irq;
  716. goto err_res;
  717. }
  718. if (sm->io_res == NULL || sm->mem_res == NULL) {
  719. dev_err(&dev->dev, "failed to get IO resource\n");
  720. err = -ENOENT;
  721. goto err_res;
  722. }
  723. sm->regs_claim = request_mem_region(sm->io_res->start,
  724. 0x100, "sm501");
  725. if (sm->regs_claim == NULL) {
  726. dev_err(&dev->dev, "cannot claim registers\n");
  727. err= -EBUSY;
  728. goto err_res;
  729. }
  730. platform_set_drvdata(dev, sm);
  731. sm->regs = ioremap(sm->io_res->start,
  732. (sm->io_res->end - sm->io_res->start) - 1);
  733. if (sm->regs == NULL) {
  734. dev_err(&dev->dev, "cannot remap registers\n");
  735. err = -EIO;
  736. goto err_claim;
  737. }
  738. return sm501_init_dev(sm);
  739. err_claim:
  740. release_resource(sm->regs_claim);
  741. kfree(sm->regs_claim);
  742. err_res:
  743. kfree(sm);
  744. err1:
  745. return err;
  746. }
  747. /* Initialisation data for PCI devices */
  748. static struct sm501_initdata sm501_pci_initdata = {
  749. .gpio_high = {
  750. .set = 0x3F000000, /* 24bit panel */
  751. .mask = 0x0,
  752. },
  753. .misc_timing = {
  754. .set = 0x010100, /* SDRAM timing */
  755. .mask = 0x1F1F00,
  756. },
  757. .misc_control = {
  758. .set = SM501_MISC_PNL_24BIT,
  759. .mask = 0,
  760. },
  761. .devices = SM501_USE_ALL,
  762. .mclk = 100 * MHZ,
  763. .m1xclk = 160 * MHZ,
  764. };
  765. static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
  766. .flags = (SM501FB_FLAG_USE_INIT_MODE |
  767. SM501FB_FLAG_USE_HWCURSOR |
  768. SM501FB_FLAG_USE_HWACCEL |
  769. SM501FB_FLAG_DISABLE_AT_EXIT),
  770. };
  771. static struct sm501_platdata_fb sm501_fb_pdata = {
  772. .fb_route = SM501_FB_OWN,
  773. .fb_crt = &sm501_pdata_fbsub,
  774. .fb_pnl = &sm501_pdata_fbsub,
  775. };
  776. static struct sm501_platdata sm501_pci_platdata = {
  777. .init = &sm501_pci_initdata,
  778. .fb = &sm501_fb_pdata,
  779. };
  780. static int sm501_pci_probe(struct pci_dev *dev,
  781. const struct pci_device_id *id)
  782. {
  783. struct sm501_devdata *sm;
  784. int err;
  785. sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
  786. if (sm == NULL) {
  787. dev_err(&dev->dev, "no memory for device data\n");
  788. err = -ENOMEM;
  789. goto err1;
  790. }
  791. /* set a default set of platform data */
  792. dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
  793. /* set a hopefully unique id for our child platform devices */
  794. sm->pdev_id = 32 + dev->devfn;
  795. pci_set_drvdata(dev, sm);
  796. err = pci_enable_device(dev);
  797. if (err) {
  798. dev_err(&dev->dev, "cannot enable device\n");
  799. goto err2;
  800. }
  801. sm->dev = &dev->dev;
  802. sm->irq = dev->irq;
  803. #ifdef __BIG_ENDIAN
  804. /* if the system is big-endian, we most probably have a
  805. * translation in the IO layer making the PCI bus little endian
  806. * so make the framebuffer swapped pixels */
  807. sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
  808. #endif
  809. /* check our resources */
  810. if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
  811. dev_err(&dev->dev, "region #0 is not memory?\n");
  812. err = -EINVAL;
  813. goto err3;
  814. }
  815. if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
  816. dev_err(&dev->dev, "region #1 is not memory?\n");
  817. err = -EINVAL;
  818. goto err3;
  819. }
  820. /* make our resources ready for sharing */
  821. sm->io_res = &dev->resource[1];
  822. sm->mem_res = &dev->resource[0];
  823. sm->regs_claim = request_mem_region(sm->io_res->start,
  824. 0x100, "sm501");
  825. if (sm->regs_claim == NULL) {
  826. dev_err(&dev->dev, "cannot claim registers\n");
  827. err= -EBUSY;
  828. goto err3;
  829. }
  830. sm->regs = ioremap(pci_resource_start(dev, 1),
  831. pci_resource_len(dev, 1));
  832. if (sm->regs == NULL) {
  833. dev_err(&dev->dev, "cannot remap registers\n");
  834. err = -EIO;
  835. goto err4;
  836. }
  837. sm501_init_dev(sm);
  838. return 0;
  839. err4:
  840. release_resource(sm->regs_claim);
  841. kfree(sm->regs_claim);
  842. err3:
  843. pci_disable_device(dev);
  844. err2:
  845. pci_set_drvdata(dev, NULL);
  846. kfree(sm);
  847. err1:
  848. return err;
  849. }
  850. static void sm501_remove_sub(struct sm501_devdata *sm,
  851. struct sm501_device *smdev)
  852. {
  853. list_del(&smdev->list);
  854. platform_device_unregister(&smdev->pdev);
  855. }
  856. static void sm501_dev_remove(struct sm501_devdata *sm)
  857. {
  858. struct sm501_device *smdev, *tmp;
  859. list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
  860. sm501_remove_sub(sm, smdev);
  861. device_remove_file(sm->dev, &dev_attr_dbg_regs);
  862. }
  863. static void sm501_pci_remove(struct pci_dev *dev)
  864. {
  865. struct sm501_devdata *sm = pci_get_drvdata(dev);
  866. sm501_dev_remove(sm);
  867. iounmap(sm->regs);
  868. release_resource(sm->regs_claim);
  869. kfree(sm->regs_claim);
  870. pci_set_drvdata(dev, NULL);
  871. pci_disable_device(dev);
  872. }
  873. static int sm501_plat_remove(struct platform_device *dev)
  874. {
  875. struct sm501_devdata *sm = platform_get_drvdata(dev);
  876. sm501_dev_remove(sm);
  877. iounmap(sm->regs);
  878. release_resource(sm->regs_claim);
  879. kfree(sm->regs_claim);
  880. return 0;
  881. }
  882. static struct pci_device_id sm501_pci_tbl[] = {
  883. { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  884. { 0, },
  885. };
  886. MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
  887. static struct pci_driver sm501_pci_drv = {
  888. .name = "sm501",
  889. .id_table = sm501_pci_tbl,
  890. .probe = sm501_pci_probe,
  891. .remove = sm501_pci_remove,
  892. };
  893. static struct platform_driver sm501_plat_drv = {
  894. .driver = {
  895. .name = "sm501",
  896. .owner = THIS_MODULE,
  897. },
  898. .probe = sm501_plat_probe,
  899. .remove = sm501_plat_remove,
  900. };
  901. static int __init sm501_base_init(void)
  902. {
  903. platform_driver_register(&sm501_plat_drv);
  904. return pci_register_driver(&sm501_pci_drv);
  905. }
  906. static void __exit sm501_base_exit(void)
  907. {
  908. platform_driver_unregister(&sm501_plat_drv);
  909. pci_unregister_driver(&sm501_pci_drv);
  910. }
  911. module_init(sm501_base_init);
  912. module_exit(sm501_base_exit);
  913. MODULE_DESCRIPTION("SM501 Core Driver");
  914. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
  915. MODULE_LICENSE("GPL v2");