tda10023.c 14 KB

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  1. /*
  2. TDA10023 - DVB-C decoder
  3. (as used in Philips CU1216-3 NIM and the Reelbox DVB-C tuner card)
  4. Copyright (C) 2005 Georg Acher, BayCom GmbH (acher at baycom dot de)
  5. Copyright (c) 2006 Hartmut Birr (e9hack at gmail dot com)
  6. Remotely based on tda10021.c
  7. Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
  8. Copyright (C) 2004 Markus Schulz <msc@antzsystem.de>
  9. Support for TDA10021
  10. This program is free software; you can redistribute it and/or modify
  11. it under the terms of the GNU General Public License as published by
  12. the Free Software Foundation; either version 2 of the License, or
  13. (at your option) any later version.
  14. This program is distributed in the hope that it will be useful,
  15. but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. GNU General Public License for more details.
  18. You should have received a copy of the GNU General Public License
  19. along with this program; if not, write to the Free Software
  20. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/errno.h>
  24. #include <linux/init.h>
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/slab.h>
  29. #include <asm/div64.h>
  30. #include "dvb_frontend.h"
  31. #include "tda1002x.h"
  32. struct tda10023_state {
  33. struct i2c_adapter* i2c;
  34. /* configuration settings */
  35. const struct tda1002x_config* config;
  36. struct dvb_frontend frontend;
  37. u8 pwm;
  38. u8 reg0;
  39. };
  40. #define dprintk(x...)
  41. static int verbose;
  42. #define XTAL 28920000UL
  43. #define PLL_M 8UL
  44. #define PLL_P 4UL
  45. #define PLL_N 1UL
  46. #define SYSCLK (XTAL*PLL_M/(PLL_N*PLL_P)) // -> 57840000
  47. static u8 tda10023_inittab[]={
  48. // reg mask val
  49. 0x2a,0xff,0x02, // PLL3, Bypass, Power Down
  50. 0xff,0x64,0x00, // Sleep 100ms
  51. 0x2a,0xff,0x03, // PLL3, Bypass, Power Down
  52. 0xff,0x64,0x00, // Sleep 100ms
  53. 0x28,0xff,PLL_M-1, // PLL1 M=8
  54. 0x29,0xff,((PLL_P-1)<<6)|(PLL_N-1), // PLL2
  55. 0x00,0xff,0x23, // GPR FSAMPLING=1
  56. 0x2a,0xff,0x08, // PLL3 PSACLK=1
  57. 0xff,0x64,0x00, // Sleep 100ms
  58. 0x1f,0xff,0x00, // RESET
  59. 0xff,0x64,0x00, // Sleep 100ms
  60. 0xe6,0x0c,0x04, // RSCFG_IND
  61. 0x10,0xc0,0x80, // DECDVBCFG1 PBER=1
  62. 0x0e,0xff,0x82, // GAIN1
  63. 0x03,0x08,0x08, // CLKCONF DYN=1
  64. 0x2e,0xbf,0x30, // AGCCONF2 TRIAGC=0,POSAGC=ENAGCIF=1 PPWMTUN=0 PPWMIF=0
  65. 0x01,0xff,0x30, // AGCREF
  66. 0x1e,0x84,0x84, // CONTROL SACLK_ON=1
  67. 0x1b,0xff,0xc8, // ADC TWOS=1
  68. 0x3b,0xff,0xff, // IFMAX
  69. 0x3c,0xff,0x00, // IFMIN
  70. 0x34,0xff,0x00, // PWMREF
  71. 0x35,0xff,0xff, // TUNMAX
  72. 0x36,0xff,0x00, // TUNMIN
  73. 0x06,0xff,0x7f, // EQCONF1 POSI=7 ENADAPT=ENEQUAL=DFE=1 // 0x77
  74. 0x1c,0x30,0x30, // EQCONF2 STEPALGO=SGNALGO=1
  75. 0x37,0xff,0xf6, // DELTAF_LSB
  76. 0x38,0xff,0xff, // DELTAF_MSB
  77. 0x02,0xff,0x93, // AGCCONF1 IFS=1 KAGCIF=2 KAGCTUN=3
  78. 0x2d,0xff,0xf6, // SWEEP SWPOS=1 SWDYN=7 SWSTEP=1 SWLEN=2
  79. 0x04,0x10,0x00, // SWRAMP=1
  80. 0x12,0xff,0xa1, // INTP1 POCLKP=1 FEL=1 MFS=0
  81. 0x2b,0x01,0xa1, // INTS1
  82. 0x20,0xff,0x04, // INTP2 SWAPP=? MSBFIRSTP=? INTPSEL=?
  83. 0x2c,0xff,0x0d, // INTP/S TRIP=0 TRIS=0
  84. 0xc4,0xff,0x00,
  85. 0xc3,0x30,0x00,
  86. 0xb5,0xff,0x19, // ERAGC_THD
  87. 0x00,0x03,0x01, // GPR, CLBS soft reset
  88. 0x00,0x03,0x03, // GPR, CLBS soft reset
  89. 0xff,0x64,0x00, // Sleep 100ms
  90. 0xff,0xff,0xff
  91. };
  92. static u8 tda10023_readreg (struct tda10023_state* state, u8 reg)
  93. {
  94. u8 b0 [] = { reg };
  95. u8 b1 [] = { 0 };
  96. struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
  97. { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
  98. int ret;
  99. ret = i2c_transfer (state->i2c, msg, 2);
  100. if (ret != 2)
  101. printk("DVB: TDA10023: %s: readreg error (ret == %i)\n",
  102. __FUNCTION__, ret);
  103. return b1[0];
  104. }
  105. static int tda10023_writereg (struct tda10023_state* state, u8 reg, u8 data)
  106. {
  107. u8 buf[] = { reg, data };
  108. struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
  109. int ret;
  110. ret = i2c_transfer (state->i2c, &msg, 1);
  111. if (ret != 1)
  112. printk("DVB: TDA10023(%d): %s, writereg error "
  113. "(reg == 0x%02x, val == 0x%02x, ret == %i)\n",
  114. state->frontend.dvb->num, __FUNCTION__, reg, data, ret);
  115. return (ret != 1) ? -EREMOTEIO : 0;
  116. }
  117. static int tda10023_writebit (struct tda10023_state* state, u8 reg, u8 mask,u8 data)
  118. {
  119. if (mask==0xff)
  120. return tda10023_writereg(state, reg, data);
  121. else {
  122. u8 val;
  123. val=tda10023_readreg(state,reg);
  124. val&=~mask;
  125. val|=(data&mask);
  126. return tda10023_writereg(state, reg, val);
  127. }
  128. }
  129. static void tda10023_writetab(struct tda10023_state* state, u8* tab)
  130. {
  131. u8 r,m,v;
  132. while (1) {
  133. r=*tab++;
  134. m=*tab++;
  135. v=*tab++;
  136. if (r==0xff) {
  137. if (m==0xff)
  138. break;
  139. else
  140. msleep(m);
  141. }
  142. else
  143. tda10023_writebit(state,r,m,v);
  144. }
  145. }
  146. //get access to tuner
  147. static int lock_tuner(struct tda10023_state* state)
  148. {
  149. u8 buf[2] = { 0x0f, 0xc0 };
  150. struct i2c_msg msg = {.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2};
  151. if(i2c_transfer(state->i2c, &msg, 1) != 1)
  152. {
  153. printk("tda10023: lock tuner fails\n");
  154. return -EREMOTEIO;
  155. }
  156. return 0;
  157. }
  158. //release access from tuner
  159. static int unlock_tuner(struct tda10023_state* state)
  160. {
  161. u8 buf[2] = { 0x0f, 0x40 };
  162. struct i2c_msg msg_post={.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2};
  163. if(i2c_transfer(state->i2c, &msg_post, 1) != 1)
  164. {
  165. printk("tda10023: unlock tuner fails\n");
  166. return -EREMOTEIO;
  167. }
  168. return 0;
  169. }
  170. static int tda10023_setup_reg0 (struct tda10023_state* state, u8 reg0)
  171. {
  172. reg0 |= state->reg0 & 0x63;
  173. tda10023_writereg (state, 0x00, reg0 & 0xfe);
  174. tda10023_writereg (state, 0x00, reg0 | 0x01);
  175. state->reg0 = reg0;
  176. return 0;
  177. }
  178. static int tda10023_set_symbolrate (struct tda10023_state* state, u32 sr)
  179. {
  180. s32 BDR;
  181. s32 BDRI;
  182. s16 SFIL=0;
  183. u16 NDEC = 0;
  184. if (sr > (SYSCLK/(2*4)))
  185. sr=SYSCLK/(2*4);
  186. if (sr<870000)
  187. sr=870000;
  188. if (sr < (u32)(SYSCLK/98.40)) {
  189. NDEC=3;
  190. SFIL=1;
  191. } else if (sr<(u32)(SYSCLK/64.0)) {
  192. NDEC=3;
  193. SFIL=0;
  194. } else if (sr<(u32)(SYSCLK/49.2)) {
  195. NDEC=2;
  196. SFIL=1;
  197. } else if (sr<(u32)(SYSCLK/32.0)) {
  198. NDEC=2;
  199. SFIL=0;
  200. } else if (sr<(u32)(SYSCLK/24.6)) {
  201. NDEC=1;
  202. SFIL=1;
  203. } else if (sr<(u32)(SYSCLK/16.0)) {
  204. NDEC=1;
  205. SFIL=0;
  206. } else if (sr<(u32)(SYSCLK/12.3)) {
  207. NDEC=0;
  208. SFIL=1;
  209. }
  210. BDRI=SYSCLK*16;
  211. BDRI>>=NDEC;
  212. BDRI +=sr/2;
  213. BDRI /=sr;
  214. if (BDRI>255)
  215. BDRI=255;
  216. {
  217. u64 BDRX;
  218. BDRX=1<<(24+NDEC);
  219. BDRX*=sr;
  220. do_div(BDRX,SYSCLK); // BDRX/=SYSCLK;
  221. BDR=(s32)BDRX;
  222. }
  223. // printk("Symbolrate %i, BDR %i BDRI %i, NDEC %i\n",sr,BDR,BDRI,NDEC);
  224. tda10023_writebit (state, 0x03, 0xc0, NDEC<<6);
  225. tda10023_writereg (state, 0x0a, BDR&255);
  226. tda10023_writereg (state, 0x0b, (BDR>>8)&255);
  227. tda10023_writereg (state, 0x0c, (BDR>>16)&31);
  228. tda10023_writereg (state, 0x0d, BDRI);
  229. tda10023_writereg (state, 0x3d, (SFIL<<7));
  230. return 0;
  231. }
  232. static int tda10023_init (struct dvb_frontend *fe)
  233. {
  234. struct tda10023_state* state = fe->demodulator_priv;
  235. dprintk("DVB: TDA10023(%d): init chip\n", fe->adapter->num);
  236. tda10023_writetab(state, tda10023_inittab);
  237. return 0;
  238. }
  239. static int tda10023_set_parameters (struct dvb_frontend *fe,
  240. struct dvb_frontend_parameters *p)
  241. {
  242. struct tda10023_state* state = fe->demodulator_priv;
  243. static int qamvals[6][6] = {
  244. // QAM LOCKTHR MSETH AREF AGCREFNYQ ERAGCNYQ_THD
  245. { (5<<2), 0x78, 0x8c, 0x96, 0x78, 0x4c }, // 4 QAM
  246. { (0<<2), 0x87, 0xa2, 0x91, 0x8c, 0x57 }, // 16 QAM
  247. { (1<<2), 0x64, 0x74, 0x96, 0x8c, 0x57 }, // 32 QAM
  248. { (2<<2), 0x46, 0x43, 0x6a, 0x6a, 0x44 }, // 64 QAM
  249. { (3<<2), 0x36, 0x34, 0x7e, 0x78, 0x4c }, // 128 QAM
  250. { (4<<2), 0x26, 0x23, 0x6c, 0x5c, 0x3c }, // 256 QAM
  251. };
  252. int qam = p->u.qam.modulation;
  253. if (qam < 0 || qam > 5)
  254. return -EINVAL;
  255. if (fe->ops.tuner_ops.set_params) {
  256. fe->ops.tuner_ops.set_params(fe, p);
  257. if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
  258. }
  259. tda10023_set_symbolrate (state, p->u.qam.symbol_rate);
  260. tda10023_writereg (state, 0x05, qamvals[qam][1]);
  261. tda10023_writereg (state, 0x08, qamvals[qam][2]);
  262. tda10023_writereg (state, 0x09, qamvals[qam][3]);
  263. tda10023_writereg (state, 0xb4, qamvals[qam][4]);
  264. tda10023_writereg (state, 0xb6, qamvals[qam][5]);
  265. // tda10023_writereg (state, 0x04, (p->inversion?0x12:0x32));
  266. // tda10023_writebit (state, 0x04, 0x60, (p->inversion?0:0x20));
  267. tda10023_writebit (state, 0x04, 0x40, 0x40);
  268. tda10023_setup_reg0 (state, qamvals[qam][0]);
  269. return 0;
  270. }
  271. static int tda10023_read_status(struct dvb_frontend* fe, fe_status_t* status)
  272. {
  273. struct tda10023_state* state = fe->demodulator_priv;
  274. int sync;
  275. *status = 0;
  276. //0x11[1] == CARLOCK -> Carrier locked
  277. //0x11[2] == FSYNC -> Frame synchronisation
  278. //0x11[3] == FEL -> Front End locked
  279. //0x11[6] == NODVB -> DVB Mode Information
  280. sync = tda10023_readreg (state, 0x11);
  281. if (sync & 2)
  282. *status |= FE_HAS_SIGNAL|FE_HAS_CARRIER;
  283. if (sync & 4)
  284. *status |= FE_HAS_SYNC|FE_HAS_VITERBI;
  285. if (sync & 8)
  286. *status |= FE_HAS_LOCK;
  287. return 0;
  288. }
  289. static int tda10023_read_ber(struct dvb_frontend* fe, u32* ber)
  290. {
  291. struct tda10023_state* state = fe->demodulator_priv;
  292. u8 a,b,c;
  293. a=tda10023_readreg(state, 0x14);
  294. b=tda10023_readreg(state, 0x15);
  295. c=tda10023_readreg(state, 0x16)&0xf;
  296. tda10023_writebit (state, 0x10, 0xc0, 0x00);
  297. *ber = a | (b<<8)| (c<<16);
  298. return 0;
  299. }
  300. static int tda10023_read_signal_strength(struct dvb_frontend* fe, u16* strength)
  301. {
  302. struct tda10023_state* state = fe->demodulator_priv;
  303. u8 ifgain=tda10023_readreg(state, 0x2f);
  304. u16 gain = ((255-tda10023_readreg(state, 0x17))) + (255-ifgain)/16;
  305. // Max raw value is about 0xb0 -> Normalize to >0xf0 after 0x90
  306. if (gain>0x90)
  307. gain=gain+2*(gain-0x90);
  308. if (gain>255)
  309. gain=255;
  310. *strength = (gain<<8)|gain;
  311. return 0;
  312. }
  313. static int tda10023_read_snr(struct dvb_frontend* fe, u16* snr)
  314. {
  315. struct tda10023_state* state = fe->demodulator_priv;
  316. u8 quality = ~tda10023_readreg(state, 0x18);
  317. *snr = (quality << 8) | quality;
  318. return 0;
  319. }
  320. static int tda10023_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
  321. {
  322. struct tda10023_state* state = fe->demodulator_priv;
  323. u8 a,b,c,d;
  324. a= tda10023_readreg (state, 0x74);
  325. b= tda10023_readreg (state, 0x75);
  326. c= tda10023_readreg (state, 0x76);
  327. d= tda10023_readreg (state, 0x77);
  328. *ucblocks = a | (b<<8)|(c<<16)|(d<<24);
  329. tda10023_writebit (state, 0x10, 0x20,0x00);
  330. tda10023_writebit (state, 0x10, 0x20,0x20);
  331. tda10023_writebit (state, 0x13, 0x01, 0x00);
  332. return 0;
  333. }
  334. static int tda10023_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
  335. {
  336. struct tda10023_state* state = fe->demodulator_priv;
  337. int sync,inv;
  338. s8 afc = 0;
  339. sync = tda10023_readreg(state, 0x11);
  340. afc = tda10023_readreg(state, 0x19);
  341. inv = tda10023_readreg(state, 0x04);
  342. if (verbose) {
  343. /* AFC only valid when carrier has been recovered */
  344. printk(sync & 2 ? "DVB: TDA10023(%d): AFC (%d) %dHz\n" :
  345. "DVB: TDA10023(%d): [AFC (%d) %dHz]\n",
  346. state->frontend.dvb->num, afc,
  347. -((s32)p->u.qam.symbol_rate * afc) >> 10);
  348. }
  349. p->inversion = (inv&0x20?0:1);
  350. p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16;
  351. p->u.qam.fec_inner = FEC_NONE;
  352. p->frequency = ((p->frequency + 31250) / 62500) * 62500;
  353. if (sync & 2)
  354. p->frequency -= ((s32)p->u.qam.symbol_rate * afc) >> 10;
  355. return 0;
  356. }
  357. static int tda10023_sleep(struct dvb_frontend* fe)
  358. {
  359. struct tda10023_state* state = fe->demodulator_priv;
  360. tda10023_writereg (state, 0x1b, 0x02); /* pdown ADC */
  361. tda10023_writereg (state, 0x00, 0x80); /* standby */
  362. return 0;
  363. }
  364. static int tda10023_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
  365. {
  366. struct tda10023_state* state = fe->demodulator_priv;
  367. if (enable) {
  368. lock_tuner(state);
  369. } else {
  370. unlock_tuner(state);
  371. }
  372. return 0;
  373. }
  374. static void tda10023_release(struct dvb_frontend* fe)
  375. {
  376. struct tda10023_state* state = fe->demodulator_priv;
  377. kfree(state);
  378. }
  379. static struct dvb_frontend_ops tda10023_ops;
  380. struct dvb_frontend* tda10023_attach(const struct tda1002x_config* config,
  381. struct i2c_adapter* i2c,
  382. u8 pwm)
  383. {
  384. struct tda10023_state* state = NULL;
  385. int i;
  386. /* allocate memory for the internal state */
  387. state = kmalloc(sizeof(struct tda10023_state), GFP_KERNEL);
  388. if (state == NULL) goto error;
  389. /* setup the state */
  390. state->config = config;
  391. state->i2c = i2c;
  392. memcpy(&state->frontend.ops, &tda10023_ops, sizeof(struct dvb_frontend_ops));
  393. state->pwm = pwm;
  394. for (i=0; i < sizeof(tda10023_inittab)/sizeof(*tda10023_inittab);i+=3) {
  395. if (tda10023_inittab[i] == 0x00) {
  396. state->reg0 = tda10023_inittab[i+2];
  397. break;
  398. }
  399. }
  400. // Wakeup if in standby
  401. tda10023_writereg (state, 0x00, 0x33);
  402. /* check if the demod is there */
  403. if ((tda10023_readreg(state, 0x1a) & 0xf0) != 0x70) goto error;
  404. /* create dvb_frontend */
  405. memcpy(&state->frontend.ops, &tda10023_ops, sizeof(struct dvb_frontend_ops));
  406. state->frontend.demodulator_priv = state;
  407. return &state->frontend;
  408. error:
  409. kfree(state);
  410. return NULL;
  411. }
  412. static struct dvb_frontend_ops tda10023_ops = {
  413. .info = {
  414. .name = "Philips TDA10023 DVB-C",
  415. .type = FE_QAM,
  416. .frequency_stepsize = 62500,
  417. .frequency_min = 51000000,
  418. .frequency_max = 858000000,
  419. .symbol_rate_min = (SYSCLK/2)/64, /* SACLK/64 == (SYSCLK/2)/64 */
  420. .symbol_rate_max = (SYSCLK/2)/4, /* SACLK/4 */
  421. .caps = 0x400 | //FE_CAN_QAM_4
  422. FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
  423. FE_CAN_QAM_128 | FE_CAN_QAM_256 |
  424. FE_CAN_FEC_AUTO
  425. },
  426. .release = tda10023_release,
  427. .init = tda10023_init,
  428. .sleep = tda10023_sleep,
  429. .i2c_gate_ctrl = tda10023_i2c_gate_ctrl,
  430. .set_frontend = tda10023_set_parameters,
  431. .get_frontend = tda10023_get_frontend,
  432. .read_status = tda10023_read_status,
  433. .read_ber = tda10023_read_ber,
  434. .read_signal_strength = tda10023_read_signal_strength,
  435. .read_snr = tda10023_read_snr,
  436. .read_ucblocks = tda10023_read_ucblocks,
  437. };
  438. MODULE_DESCRIPTION("Philips TDA10023 DVB-C demodulator driver");
  439. MODULE_AUTHOR("Georg Acher, Hartmut Birr");
  440. MODULE_LICENSE("GPL");
  441. EXPORT_SYMBOL(tda10023_attach);