ucb1400_ts.c 15 KB

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  1. /*
  2. * Philips UCB1400 touchscreen driver
  3. *
  4. * Author: Nicolas Pitre
  5. * Created: September 25, 2006
  6. * Copyright: MontaVista Software, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This code is heavily based on ucb1x00-*.c copyrighted by Russell King
  13. * covering the UCB1100, UCB1200 and UCB1300.. Support for the UCB1400 has
  14. * been made separate from ucb1x00-core/ucb1x00-ts on Russell's request.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/moduleparam.h>
  18. #include <linux/init.h>
  19. #include <linux/completion.h>
  20. #include <linux/delay.h>
  21. #include <linux/input.h>
  22. #include <linux/device.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/suspend.h>
  25. #include <linux/slab.h>
  26. #include <linux/kthread.h>
  27. #include <linux/freezer.h>
  28. #include <sound/driver.h>
  29. #include <sound/core.h>
  30. #include <sound/ac97_codec.h>
  31. /*
  32. * Interesting UCB1400 AC-link registers
  33. */
  34. #define UCB_IE_RIS 0x5e
  35. #define UCB_IE_FAL 0x60
  36. #define UCB_IE_STATUS 0x62
  37. #define UCB_IE_CLEAR 0x62
  38. #define UCB_IE_ADC (1 << 11)
  39. #define UCB_IE_TSPX (1 << 12)
  40. #define UCB_TS_CR 0x64
  41. #define UCB_TS_CR_TSMX_POW (1 << 0)
  42. #define UCB_TS_CR_TSPX_POW (1 << 1)
  43. #define UCB_TS_CR_TSMY_POW (1 << 2)
  44. #define UCB_TS_CR_TSPY_POW (1 << 3)
  45. #define UCB_TS_CR_TSMX_GND (1 << 4)
  46. #define UCB_TS_CR_TSPX_GND (1 << 5)
  47. #define UCB_TS_CR_TSMY_GND (1 << 6)
  48. #define UCB_TS_CR_TSPY_GND (1 << 7)
  49. #define UCB_TS_CR_MODE_INT (0 << 8)
  50. #define UCB_TS_CR_MODE_PRES (1 << 8)
  51. #define UCB_TS_CR_MODE_POS (2 << 8)
  52. #define UCB_TS_CR_BIAS_ENA (1 << 11)
  53. #define UCB_TS_CR_TSPX_LOW (1 << 12)
  54. #define UCB_TS_CR_TSMX_LOW (1 << 13)
  55. #define UCB_ADC_CR 0x66
  56. #define UCB_ADC_SYNC_ENA (1 << 0)
  57. #define UCB_ADC_VREFBYP_CON (1 << 1)
  58. #define UCB_ADC_INP_TSPX (0 << 2)
  59. #define UCB_ADC_INP_TSMX (1 << 2)
  60. #define UCB_ADC_INP_TSPY (2 << 2)
  61. #define UCB_ADC_INP_TSMY (3 << 2)
  62. #define UCB_ADC_INP_AD0 (4 << 2)
  63. #define UCB_ADC_INP_AD1 (5 << 2)
  64. #define UCB_ADC_INP_AD2 (6 << 2)
  65. #define UCB_ADC_INP_AD3 (7 << 2)
  66. #define UCB_ADC_EXT_REF (1 << 5)
  67. #define UCB_ADC_START (1 << 7)
  68. #define UCB_ADC_ENA (1 << 15)
  69. #define UCB_ADC_DATA 0x68
  70. #define UCB_ADC_DAT_VALID (1 << 15)
  71. #define UCB_ADC_DAT_VALUE(x) ((x) & 0x3ff)
  72. #define UCB_ID 0x7e
  73. #define UCB_ID_1400 0x4304
  74. struct ucb1400 {
  75. struct snd_ac97 *ac97;
  76. struct input_dev *ts_idev;
  77. int irq;
  78. wait_queue_head_t ts_wait;
  79. struct task_struct *ts_task;
  80. unsigned int irq_pending; /* not bit field shared */
  81. unsigned int ts_restart:1;
  82. unsigned int adcsync:1;
  83. };
  84. static int adcsync;
  85. static int ts_delay = 55; /* us */
  86. static int ts_delay_pressure; /* us */
  87. static inline u16 ucb1400_reg_read(struct ucb1400 *ucb, u16 reg)
  88. {
  89. return ucb->ac97->bus->ops->read(ucb->ac97, reg);
  90. }
  91. static inline void ucb1400_reg_write(struct ucb1400 *ucb, u16 reg, u16 val)
  92. {
  93. ucb->ac97->bus->ops->write(ucb->ac97, reg, val);
  94. }
  95. static inline void ucb1400_adc_enable(struct ucb1400 *ucb)
  96. {
  97. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
  98. }
  99. static unsigned int ucb1400_adc_read(struct ucb1400 *ucb, u16 adc_channel)
  100. {
  101. unsigned int val;
  102. if (ucb->adcsync)
  103. adc_channel |= UCB_ADC_SYNC_ENA;
  104. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | adc_channel);
  105. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | adc_channel | UCB_ADC_START);
  106. for (;;) {
  107. val = ucb1400_reg_read(ucb, UCB_ADC_DATA);
  108. if (val & UCB_ADC_DAT_VALID)
  109. break;
  110. /* yield to other processes */
  111. set_current_state(TASK_INTERRUPTIBLE);
  112. schedule_timeout(1);
  113. }
  114. return UCB_ADC_DAT_VALUE(val);
  115. }
  116. static inline void ucb1400_adc_disable(struct ucb1400 *ucb)
  117. {
  118. ucb1400_reg_write(ucb, UCB_ADC_CR, 0);
  119. }
  120. /* Switch to interrupt mode. */
  121. static inline void ucb1400_ts_mode_int(struct ucb1400 *ucb)
  122. {
  123. ucb1400_reg_write(ucb, UCB_TS_CR,
  124. UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
  125. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
  126. UCB_TS_CR_MODE_INT);
  127. }
  128. /*
  129. * Switch to pressure mode, and read pressure. We don't need to wait
  130. * here, since both plates are being driven.
  131. */
  132. static inline unsigned int ucb1400_ts_read_pressure(struct ucb1400 *ucb)
  133. {
  134. ucb1400_reg_write(ucb, UCB_TS_CR,
  135. UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
  136. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
  137. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  138. udelay(ts_delay_pressure);
  139. return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPY);
  140. }
  141. /*
  142. * Switch to X position mode and measure Y plate. We switch the plate
  143. * configuration in pressure mode, then switch to position mode. This
  144. * gives a faster response time. Even so, we need to wait about 55us
  145. * for things to stabilise.
  146. */
  147. static inline unsigned int ucb1400_ts_read_xpos(struct ucb1400 *ucb)
  148. {
  149. ucb1400_reg_write(ucb, UCB_TS_CR,
  150. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  151. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  152. ucb1400_reg_write(ucb, UCB_TS_CR,
  153. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  154. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  155. ucb1400_reg_write(ucb, UCB_TS_CR,
  156. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  157. UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
  158. udelay(ts_delay);
  159. return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPY);
  160. }
  161. /*
  162. * Switch to Y position mode and measure X plate. We switch the plate
  163. * configuration in pressure mode, then switch to position mode. This
  164. * gives a faster response time. Even so, we need to wait about 55us
  165. * for things to stabilise.
  166. */
  167. static inline unsigned int ucb1400_ts_read_ypos(struct ucb1400 *ucb)
  168. {
  169. ucb1400_reg_write(ucb, UCB_TS_CR,
  170. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  171. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  172. ucb1400_reg_write(ucb, UCB_TS_CR,
  173. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  174. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  175. ucb1400_reg_write(ucb, UCB_TS_CR,
  176. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  177. UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
  178. udelay(ts_delay);
  179. return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPX);
  180. }
  181. /*
  182. * Switch to X plate resistance mode. Set MX to ground, PX to
  183. * supply. Measure current.
  184. */
  185. static inline unsigned int ucb1400_ts_read_xres(struct ucb1400 *ucb)
  186. {
  187. ucb1400_reg_write(ucb, UCB_TS_CR,
  188. UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
  189. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  190. return ucb1400_adc_read(ucb, 0);
  191. }
  192. /*
  193. * Switch to Y plate resistance mode. Set MY to ground, PY to
  194. * supply. Measure current.
  195. */
  196. static inline unsigned int ucb1400_ts_read_yres(struct ucb1400 *ucb)
  197. {
  198. ucb1400_reg_write(ucb, UCB_TS_CR,
  199. UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
  200. UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
  201. return ucb1400_adc_read(ucb, 0);
  202. }
  203. static inline int ucb1400_ts_pen_down(struct ucb1400 *ucb)
  204. {
  205. unsigned short val = ucb1400_reg_read(ucb, UCB_TS_CR);
  206. return (val & (UCB_TS_CR_TSPX_LOW | UCB_TS_CR_TSMX_LOW));
  207. }
  208. static inline void ucb1400_ts_irq_enable(struct ucb1400 *ucb)
  209. {
  210. ucb1400_reg_write(ucb, UCB_IE_CLEAR, UCB_IE_TSPX);
  211. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  212. ucb1400_reg_write(ucb, UCB_IE_FAL, UCB_IE_TSPX);
  213. }
  214. static inline void ucb1400_ts_irq_disable(struct ucb1400 *ucb)
  215. {
  216. ucb1400_reg_write(ucb, UCB_IE_FAL, 0);
  217. }
  218. static void ucb1400_ts_evt_add(struct input_dev *idev, u16 pressure, u16 x, u16 y)
  219. {
  220. input_report_abs(idev, ABS_X, x);
  221. input_report_abs(idev, ABS_Y, y);
  222. input_report_abs(idev, ABS_PRESSURE, pressure);
  223. input_sync(idev);
  224. }
  225. static void ucb1400_ts_event_release(struct input_dev *idev)
  226. {
  227. input_report_abs(idev, ABS_PRESSURE, 0);
  228. input_sync(idev);
  229. }
  230. static void ucb1400_handle_pending_irq(struct ucb1400 *ucb)
  231. {
  232. unsigned int isr;
  233. isr = ucb1400_reg_read(ucb, UCB_IE_STATUS);
  234. ucb1400_reg_write(ucb, UCB_IE_CLEAR, isr);
  235. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  236. if (isr & UCB_IE_TSPX)
  237. ucb1400_ts_irq_disable(ucb);
  238. else
  239. printk(KERN_ERR "ucb1400: unexpected IE_STATUS = %#x\n", isr);
  240. enable_irq(ucb->irq);
  241. }
  242. static int ucb1400_ts_thread(void *_ucb)
  243. {
  244. struct ucb1400 *ucb = _ucb;
  245. struct task_struct *tsk = current;
  246. int valid = 0;
  247. tsk->policy = SCHED_FIFO;
  248. tsk->rt_priority = 1;
  249. while (!kthread_should_stop()) {
  250. unsigned int x, y, p;
  251. long timeout;
  252. ucb->ts_restart = 0;
  253. if (ucb->irq_pending) {
  254. ucb->irq_pending = 0;
  255. ucb1400_handle_pending_irq(ucb);
  256. }
  257. ucb1400_adc_enable(ucb);
  258. x = ucb1400_ts_read_xpos(ucb);
  259. y = ucb1400_ts_read_ypos(ucb);
  260. p = ucb1400_ts_read_pressure(ucb);
  261. ucb1400_adc_disable(ucb);
  262. /* Switch back to interrupt mode. */
  263. ucb1400_ts_mode_int(ucb);
  264. msleep(10);
  265. if (ucb1400_ts_pen_down(ucb)) {
  266. ucb1400_ts_irq_enable(ucb);
  267. /*
  268. * If we spat out a valid sample set last time,
  269. * spit out a "pen off" sample here.
  270. */
  271. if (valid) {
  272. ucb1400_ts_event_release(ucb->ts_idev);
  273. valid = 0;
  274. }
  275. timeout = MAX_SCHEDULE_TIMEOUT;
  276. } else {
  277. valid = 1;
  278. ucb1400_ts_evt_add(ucb->ts_idev, p, x, y);
  279. timeout = msecs_to_jiffies(10);
  280. }
  281. wait_event_interruptible_timeout(ucb->ts_wait,
  282. ucb->irq_pending || ucb->ts_restart || kthread_should_stop(),
  283. timeout);
  284. try_to_freeze();
  285. }
  286. /* Send the "pen off" if we are stopping with the pen still active */
  287. if (valid)
  288. ucb1400_ts_event_release(ucb->ts_idev);
  289. ucb->ts_task = NULL;
  290. return 0;
  291. }
  292. /*
  293. * A restriction with interrupts exists when using the ucb1400, as
  294. * the codec read/write routines may sleep while waiting for codec
  295. * access completion and uses semaphores for access control to the
  296. * AC97 bus. A complete codec read cycle could take anywhere from
  297. * 60 to 100uSec so we *definitely* don't want to spin inside the
  298. * interrupt handler waiting for codec access. So, we handle the
  299. * interrupt by scheduling a RT kernel thread to run in process
  300. * context instead of interrupt context.
  301. */
  302. static irqreturn_t ucb1400_hard_irq(int irqnr, void *devid)
  303. {
  304. struct ucb1400 *ucb = devid;
  305. if (irqnr == ucb->irq) {
  306. disable_irq(ucb->irq);
  307. ucb->irq_pending = 1;
  308. wake_up(&ucb->ts_wait);
  309. return IRQ_HANDLED;
  310. }
  311. return IRQ_NONE;
  312. }
  313. static int ucb1400_ts_open(struct input_dev *idev)
  314. {
  315. struct ucb1400 *ucb = input_get_drvdata(idev);
  316. int ret = 0;
  317. BUG_ON(ucb->ts_task);
  318. ucb->ts_task = kthread_run(ucb1400_ts_thread, ucb, "UCB1400_ts");
  319. if (IS_ERR(ucb->ts_task)) {
  320. ret = PTR_ERR(ucb->ts_task);
  321. ucb->ts_task = NULL;
  322. }
  323. return ret;
  324. }
  325. static void ucb1400_ts_close(struct input_dev *idev)
  326. {
  327. struct ucb1400 *ucb = input_get_drvdata(idev);
  328. if (ucb->ts_task)
  329. kthread_stop(ucb->ts_task);
  330. ucb1400_ts_irq_disable(ucb);
  331. ucb1400_reg_write(ucb, UCB_TS_CR, 0);
  332. }
  333. #ifdef CONFIG_PM
  334. static int ucb1400_ts_resume(struct device *dev)
  335. {
  336. struct ucb1400 *ucb = dev_get_drvdata(dev);
  337. if (ucb->ts_task) {
  338. /*
  339. * Restart the TS thread to ensure the
  340. * TS interrupt mode is set up again
  341. * after sleep.
  342. */
  343. ucb->ts_restart = 1;
  344. wake_up(&ucb->ts_wait);
  345. }
  346. return 0;
  347. }
  348. #else
  349. #define ucb1400_ts_resume NULL
  350. #endif
  351. #ifndef NO_IRQ
  352. #define NO_IRQ 0
  353. #endif
  354. /*
  355. * Try to probe our interrupt, rather than relying on lots of
  356. * hard-coded machine dependencies.
  357. */
  358. static int ucb1400_detect_irq(struct ucb1400 *ucb)
  359. {
  360. unsigned long mask, timeout;
  361. mask = probe_irq_on();
  362. if (!mask) {
  363. probe_irq_off(mask);
  364. return -EBUSY;
  365. }
  366. /* Enable the ADC interrupt. */
  367. ucb1400_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
  368. ucb1400_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
  369. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  370. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  371. /* Cause an ADC interrupt. */
  372. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
  373. ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
  374. /* Wait for the conversion to complete. */
  375. timeout = jiffies + HZ/2;
  376. while (!(ucb1400_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VALID)) {
  377. cpu_relax();
  378. if (time_after(jiffies, timeout)) {
  379. printk(KERN_ERR "ucb1400: timed out in IRQ probe\n");
  380. probe_irq_off(mask);
  381. return -ENODEV;
  382. }
  383. }
  384. ucb1400_reg_write(ucb, UCB_ADC_CR, 0);
  385. /* Disable and clear interrupt. */
  386. ucb1400_reg_write(ucb, UCB_IE_RIS, 0);
  387. ucb1400_reg_write(ucb, UCB_IE_FAL, 0);
  388. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  389. ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
  390. /* Read triggered interrupt. */
  391. ucb->irq = probe_irq_off(mask);
  392. if (ucb->irq < 0 || ucb->irq == NO_IRQ)
  393. return -ENODEV;
  394. return 0;
  395. }
  396. static int ucb1400_ts_probe(struct device *dev)
  397. {
  398. struct ucb1400 *ucb;
  399. struct input_dev *idev;
  400. int error, id, x_res, y_res;
  401. ucb = kzalloc(sizeof(struct ucb1400), GFP_KERNEL);
  402. idev = input_allocate_device();
  403. if (!ucb || !idev) {
  404. error = -ENOMEM;
  405. goto err_free_devs;
  406. }
  407. ucb->ts_idev = idev;
  408. ucb->adcsync = adcsync;
  409. ucb->ac97 = to_ac97_t(dev);
  410. init_waitqueue_head(&ucb->ts_wait);
  411. id = ucb1400_reg_read(ucb, UCB_ID);
  412. if (id != UCB_ID_1400) {
  413. error = -ENODEV;
  414. goto err_free_devs;
  415. }
  416. error = ucb1400_detect_irq(ucb);
  417. if (error) {
  418. printk(KERN_ERR "UCB1400: IRQ probe failed\n");
  419. goto err_free_devs;
  420. }
  421. error = request_irq(ucb->irq, ucb1400_hard_irq, IRQF_TRIGGER_RISING,
  422. "UCB1400", ucb);
  423. if (error) {
  424. printk(KERN_ERR "ucb1400: unable to grab irq%d: %d\n",
  425. ucb->irq, error);
  426. goto err_free_devs;
  427. }
  428. printk(KERN_DEBUG "UCB1400: found IRQ %d\n", ucb->irq);
  429. input_set_drvdata(idev, ucb);
  430. idev->dev.parent = dev;
  431. idev->name = "UCB1400 touchscreen interface";
  432. idev->id.vendor = ucb1400_reg_read(ucb, AC97_VENDOR_ID1);
  433. idev->id.product = id;
  434. idev->open = ucb1400_ts_open;
  435. idev->close = ucb1400_ts_close;
  436. idev->evbit[0] = BIT(EV_ABS);
  437. ucb1400_adc_enable(ucb);
  438. x_res = ucb1400_ts_read_xres(ucb);
  439. y_res = ucb1400_ts_read_yres(ucb);
  440. ucb1400_adc_disable(ucb);
  441. printk(KERN_DEBUG "UCB1400: x/y = %d/%d\n", x_res, y_res);
  442. input_set_abs_params(idev, ABS_X, 0, x_res, 0, 0);
  443. input_set_abs_params(idev, ABS_Y, 0, y_res, 0, 0);
  444. input_set_abs_params(idev, ABS_PRESSURE, 0, 0, 0, 0);
  445. error = input_register_device(idev);
  446. if (error)
  447. goto err_free_irq;
  448. dev_set_drvdata(dev, ucb);
  449. return 0;
  450. err_free_irq:
  451. free_irq(ucb->irq, ucb);
  452. err_free_devs:
  453. input_free_device(idev);
  454. kfree(ucb);
  455. return error;
  456. }
  457. static int ucb1400_ts_remove(struct device *dev)
  458. {
  459. struct ucb1400 *ucb = dev_get_drvdata(dev);
  460. free_irq(ucb->irq, ucb);
  461. input_unregister_device(ucb->ts_idev);
  462. dev_set_drvdata(dev, NULL);
  463. kfree(ucb);
  464. return 0;
  465. }
  466. static struct device_driver ucb1400_ts_driver = {
  467. .name = "ucb1400_ts",
  468. .owner = THIS_MODULE,
  469. .bus = &ac97_bus_type,
  470. .probe = ucb1400_ts_probe,
  471. .remove = ucb1400_ts_remove,
  472. .resume = ucb1400_ts_resume,
  473. };
  474. static int __init ucb1400_ts_init(void)
  475. {
  476. return driver_register(&ucb1400_ts_driver);
  477. }
  478. static void __exit ucb1400_ts_exit(void)
  479. {
  480. driver_unregister(&ucb1400_ts_driver);
  481. }
  482. module_param(adcsync, bool, 0444);
  483. MODULE_PARM_DESC(adcsync, "Synchronize touch readings with ADCSYNC pin.");
  484. module_param(ts_delay, int, 0444);
  485. MODULE_PARM_DESC(ts_delay, "Delay between panel setup and position read. Default = 55us.");
  486. module_param(ts_delay_pressure, int, 0444);
  487. MODULE_PARM_DESC(ts_delay_pressure,
  488. "delay between panel setup and pressure read. Default = 0us.");
  489. module_init(ucb1400_ts_init);
  490. module_exit(ucb1400_ts_exit);
  491. MODULE_DESCRIPTION("Philips UCB1400 touchscreen driver");
  492. MODULE_LICENSE("GPL");