mthca_memfree.c 18 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Cisco Systems. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id$
  35. */
  36. #include <linux/mm.h>
  37. #include <linux/scatterlist.h>
  38. #include <asm/page.h>
  39. #include "mthca_memfree.h"
  40. #include "mthca_dev.h"
  41. #include "mthca_cmd.h"
  42. /*
  43. * We allocate in as big chunks as we can, up to a maximum of 256 KB
  44. * per chunk.
  45. */
  46. enum {
  47. MTHCA_ICM_ALLOC_SIZE = 1 << 18,
  48. MTHCA_TABLE_CHUNK_SIZE = 1 << 18
  49. };
  50. struct mthca_user_db_table {
  51. struct mutex mutex;
  52. struct {
  53. u64 uvirt;
  54. struct scatterlist mem;
  55. int refcount;
  56. } page[0];
  57. };
  58. static void mthca_free_icm_pages(struct mthca_dev *dev, struct mthca_icm_chunk *chunk)
  59. {
  60. int i;
  61. if (chunk->nsg > 0)
  62. pci_unmap_sg(dev->pdev, chunk->mem, chunk->npages,
  63. PCI_DMA_BIDIRECTIONAL);
  64. for (i = 0; i < chunk->npages; ++i)
  65. __free_pages(chunk->mem[i].page,
  66. get_order(chunk->mem[i].length));
  67. }
  68. static void mthca_free_icm_coherent(struct mthca_dev *dev, struct mthca_icm_chunk *chunk)
  69. {
  70. int i;
  71. for (i = 0; i < chunk->npages; ++i) {
  72. dma_free_coherent(&dev->pdev->dev, chunk->mem[i].length,
  73. lowmem_page_address(chunk->mem[i].page),
  74. sg_dma_address(&chunk->mem[i]));
  75. }
  76. }
  77. void mthca_free_icm(struct mthca_dev *dev, struct mthca_icm *icm, int coherent)
  78. {
  79. struct mthca_icm_chunk *chunk, *tmp;
  80. if (!icm)
  81. return;
  82. list_for_each_entry_safe(chunk, tmp, &icm->chunk_list, list) {
  83. if (coherent)
  84. mthca_free_icm_coherent(dev, chunk);
  85. else
  86. mthca_free_icm_pages(dev, chunk);
  87. kfree(chunk);
  88. }
  89. kfree(icm);
  90. }
  91. static int mthca_alloc_icm_pages(struct scatterlist *mem, int order, gfp_t gfp_mask)
  92. {
  93. mem->page = alloc_pages(gfp_mask, order);
  94. if (!mem->page)
  95. return -ENOMEM;
  96. mem->length = PAGE_SIZE << order;
  97. mem->offset = 0;
  98. return 0;
  99. }
  100. static int mthca_alloc_icm_coherent(struct device *dev, struct scatterlist *mem,
  101. int order, gfp_t gfp_mask)
  102. {
  103. void *buf = dma_alloc_coherent(dev, PAGE_SIZE << order, &sg_dma_address(mem),
  104. gfp_mask);
  105. if (!buf)
  106. return -ENOMEM;
  107. sg_set_buf(mem, buf, PAGE_SIZE << order);
  108. BUG_ON(mem->offset);
  109. sg_dma_len(mem) = PAGE_SIZE << order;
  110. return 0;
  111. }
  112. struct mthca_icm *mthca_alloc_icm(struct mthca_dev *dev, int npages,
  113. gfp_t gfp_mask, int coherent)
  114. {
  115. struct mthca_icm *icm;
  116. struct mthca_icm_chunk *chunk = NULL;
  117. int cur_order;
  118. int ret;
  119. /* We use sg_set_buf for coherent allocs, which assumes low memory */
  120. BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM));
  121. icm = kmalloc(sizeof *icm, gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
  122. if (!icm)
  123. return icm;
  124. icm->refcount = 0;
  125. INIT_LIST_HEAD(&icm->chunk_list);
  126. cur_order = get_order(MTHCA_ICM_ALLOC_SIZE);
  127. while (npages > 0) {
  128. if (!chunk) {
  129. chunk = kmalloc(sizeof *chunk,
  130. gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
  131. if (!chunk)
  132. goto fail;
  133. chunk->npages = 0;
  134. chunk->nsg = 0;
  135. list_add_tail(&chunk->list, &icm->chunk_list);
  136. }
  137. while (1 << cur_order > npages)
  138. --cur_order;
  139. if (coherent)
  140. ret = mthca_alloc_icm_coherent(&dev->pdev->dev,
  141. &chunk->mem[chunk->npages],
  142. cur_order, gfp_mask);
  143. else
  144. ret = mthca_alloc_icm_pages(&chunk->mem[chunk->npages],
  145. cur_order, gfp_mask);
  146. if (!ret) {
  147. ++chunk->npages;
  148. if (coherent)
  149. ++chunk->nsg;
  150. else if (chunk->npages == MTHCA_ICM_CHUNK_LEN) {
  151. chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
  152. chunk->npages,
  153. PCI_DMA_BIDIRECTIONAL);
  154. if (chunk->nsg <= 0)
  155. goto fail;
  156. }
  157. if (chunk->npages == MTHCA_ICM_CHUNK_LEN)
  158. chunk = NULL;
  159. npages -= 1 << cur_order;
  160. } else {
  161. --cur_order;
  162. if (cur_order < 0)
  163. goto fail;
  164. }
  165. }
  166. if (!coherent && chunk) {
  167. chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
  168. chunk->npages,
  169. PCI_DMA_BIDIRECTIONAL);
  170. if (chunk->nsg <= 0)
  171. goto fail;
  172. }
  173. return icm;
  174. fail:
  175. mthca_free_icm(dev, icm, coherent);
  176. return NULL;
  177. }
  178. int mthca_table_get(struct mthca_dev *dev, struct mthca_icm_table *table, int obj)
  179. {
  180. int i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE;
  181. int ret = 0;
  182. u8 status;
  183. mutex_lock(&table->mutex);
  184. if (table->icm[i]) {
  185. ++table->icm[i]->refcount;
  186. goto out;
  187. }
  188. table->icm[i] = mthca_alloc_icm(dev, MTHCA_TABLE_CHUNK_SIZE >> PAGE_SHIFT,
  189. (table->lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
  190. __GFP_NOWARN, table->coherent);
  191. if (!table->icm[i]) {
  192. ret = -ENOMEM;
  193. goto out;
  194. }
  195. if (mthca_MAP_ICM(dev, table->icm[i], table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
  196. &status) || status) {
  197. mthca_free_icm(dev, table->icm[i], table->coherent);
  198. table->icm[i] = NULL;
  199. ret = -ENOMEM;
  200. goto out;
  201. }
  202. ++table->icm[i]->refcount;
  203. out:
  204. mutex_unlock(&table->mutex);
  205. return ret;
  206. }
  207. void mthca_table_put(struct mthca_dev *dev, struct mthca_icm_table *table, int obj)
  208. {
  209. int i;
  210. u8 status;
  211. if (!mthca_is_memfree(dev))
  212. return;
  213. i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE;
  214. mutex_lock(&table->mutex);
  215. if (--table->icm[i]->refcount == 0) {
  216. mthca_UNMAP_ICM(dev, table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
  217. MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
  218. &status);
  219. mthca_free_icm(dev, table->icm[i], table->coherent);
  220. table->icm[i] = NULL;
  221. }
  222. mutex_unlock(&table->mutex);
  223. }
  224. void *mthca_table_find(struct mthca_icm_table *table, int obj, dma_addr_t *dma_handle)
  225. {
  226. int idx, offset, dma_offset, i;
  227. struct mthca_icm_chunk *chunk;
  228. struct mthca_icm *icm;
  229. struct page *page = NULL;
  230. if (!table->lowmem)
  231. return NULL;
  232. mutex_lock(&table->mutex);
  233. idx = (obj & (table->num_obj - 1)) * table->obj_size;
  234. icm = table->icm[idx / MTHCA_TABLE_CHUNK_SIZE];
  235. dma_offset = offset = idx % MTHCA_TABLE_CHUNK_SIZE;
  236. if (!icm)
  237. goto out;
  238. list_for_each_entry(chunk, &icm->chunk_list, list) {
  239. for (i = 0; i < chunk->npages; ++i) {
  240. if (dma_handle && dma_offset >= 0) {
  241. if (sg_dma_len(&chunk->mem[i]) > dma_offset)
  242. *dma_handle = sg_dma_address(&chunk->mem[i]) +
  243. dma_offset;
  244. dma_offset -= sg_dma_len(&chunk->mem[i]);
  245. }
  246. /* DMA mapping can merge pages but not split them,
  247. * so if we found the page, dma_handle has already
  248. * been assigned to. */
  249. if (chunk->mem[i].length > offset) {
  250. page = chunk->mem[i].page;
  251. goto out;
  252. }
  253. offset -= chunk->mem[i].length;
  254. }
  255. }
  256. out:
  257. mutex_unlock(&table->mutex);
  258. return page ? lowmem_page_address(page) + offset : NULL;
  259. }
  260. int mthca_table_get_range(struct mthca_dev *dev, struct mthca_icm_table *table,
  261. int start, int end)
  262. {
  263. int inc = MTHCA_TABLE_CHUNK_SIZE / table->obj_size;
  264. int i, err;
  265. for (i = start; i <= end; i += inc) {
  266. err = mthca_table_get(dev, table, i);
  267. if (err)
  268. goto fail;
  269. }
  270. return 0;
  271. fail:
  272. while (i > start) {
  273. i -= inc;
  274. mthca_table_put(dev, table, i);
  275. }
  276. return err;
  277. }
  278. void mthca_table_put_range(struct mthca_dev *dev, struct mthca_icm_table *table,
  279. int start, int end)
  280. {
  281. int i;
  282. if (!mthca_is_memfree(dev))
  283. return;
  284. for (i = start; i <= end; i += MTHCA_TABLE_CHUNK_SIZE / table->obj_size)
  285. mthca_table_put(dev, table, i);
  286. }
  287. struct mthca_icm_table *mthca_alloc_icm_table(struct mthca_dev *dev,
  288. u64 virt, int obj_size,
  289. int nobj, int reserved,
  290. int use_lowmem, int use_coherent)
  291. {
  292. struct mthca_icm_table *table;
  293. int num_icm;
  294. unsigned chunk_size;
  295. int i;
  296. u8 status;
  297. num_icm = (obj_size * nobj + MTHCA_TABLE_CHUNK_SIZE - 1) / MTHCA_TABLE_CHUNK_SIZE;
  298. table = kmalloc(sizeof *table + num_icm * sizeof *table->icm, GFP_KERNEL);
  299. if (!table)
  300. return NULL;
  301. table->virt = virt;
  302. table->num_icm = num_icm;
  303. table->num_obj = nobj;
  304. table->obj_size = obj_size;
  305. table->lowmem = use_lowmem;
  306. table->coherent = use_coherent;
  307. mutex_init(&table->mutex);
  308. for (i = 0; i < num_icm; ++i)
  309. table->icm[i] = NULL;
  310. for (i = 0; i * MTHCA_TABLE_CHUNK_SIZE < reserved * obj_size; ++i) {
  311. chunk_size = MTHCA_TABLE_CHUNK_SIZE;
  312. if ((i + 1) * MTHCA_TABLE_CHUNK_SIZE > nobj * obj_size)
  313. chunk_size = nobj * obj_size - i * MTHCA_TABLE_CHUNK_SIZE;
  314. table->icm[i] = mthca_alloc_icm(dev, chunk_size >> PAGE_SHIFT,
  315. (use_lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
  316. __GFP_NOWARN, use_coherent);
  317. if (!table->icm[i])
  318. goto err;
  319. if (mthca_MAP_ICM(dev, table->icm[i], virt + i * MTHCA_TABLE_CHUNK_SIZE,
  320. &status) || status) {
  321. mthca_free_icm(dev, table->icm[i], table->coherent);
  322. table->icm[i] = NULL;
  323. goto err;
  324. }
  325. /*
  326. * Add a reference to this ICM chunk so that it never
  327. * gets freed (since it contains reserved firmware objects).
  328. */
  329. ++table->icm[i]->refcount;
  330. }
  331. return table;
  332. err:
  333. for (i = 0; i < num_icm; ++i)
  334. if (table->icm[i]) {
  335. mthca_UNMAP_ICM(dev, virt + i * MTHCA_TABLE_CHUNK_SIZE,
  336. MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
  337. &status);
  338. mthca_free_icm(dev, table->icm[i], table->coherent);
  339. }
  340. kfree(table);
  341. return NULL;
  342. }
  343. void mthca_free_icm_table(struct mthca_dev *dev, struct mthca_icm_table *table)
  344. {
  345. int i;
  346. u8 status;
  347. for (i = 0; i < table->num_icm; ++i)
  348. if (table->icm[i]) {
  349. mthca_UNMAP_ICM(dev, table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
  350. MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
  351. &status);
  352. mthca_free_icm(dev, table->icm[i], table->coherent);
  353. }
  354. kfree(table);
  355. }
  356. static u64 mthca_uarc_virt(struct mthca_dev *dev, struct mthca_uar *uar, int page)
  357. {
  358. return dev->uar_table.uarc_base +
  359. uar->index * dev->uar_table.uarc_size +
  360. page * MTHCA_ICM_PAGE_SIZE;
  361. }
  362. int mthca_map_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
  363. struct mthca_user_db_table *db_tab, int index, u64 uaddr)
  364. {
  365. int ret = 0;
  366. u8 status;
  367. int i;
  368. if (!mthca_is_memfree(dev))
  369. return 0;
  370. if (index < 0 || index > dev->uar_table.uarc_size / 8)
  371. return -EINVAL;
  372. mutex_lock(&db_tab->mutex);
  373. i = index / MTHCA_DB_REC_PER_PAGE;
  374. if ((db_tab->page[i].refcount >= MTHCA_DB_REC_PER_PAGE) ||
  375. (db_tab->page[i].uvirt && db_tab->page[i].uvirt != uaddr) ||
  376. (uaddr & 4095)) {
  377. ret = -EINVAL;
  378. goto out;
  379. }
  380. if (db_tab->page[i].refcount) {
  381. ++db_tab->page[i].refcount;
  382. goto out;
  383. }
  384. ret = get_user_pages(current, current->mm, uaddr & PAGE_MASK, 1, 1, 0,
  385. &db_tab->page[i].mem.page, NULL);
  386. if (ret < 0)
  387. goto out;
  388. db_tab->page[i].mem.length = MTHCA_ICM_PAGE_SIZE;
  389. db_tab->page[i].mem.offset = uaddr & ~PAGE_MASK;
  390. ret = pci_map_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
  391. if (ret < 0) {
  392. put_page(db_tab->page[i].mem.page);
  393. goto out;
  394. }
  395. ret = mthca_MAP_ICM_page(dev, sg_dma_address(&db_tab->page[i].mem),
  396. mthca_uarc_virt(dev, uar, i), &status);
  397. if (!ret && status)
  398. ret = -EINVAL;
  399. if (ret) {
  400. pci_unmap_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
  401. put_page(db_tab->page[i].mem.page);
  402. goto out;
  403. }
  404. db_tab->page[i].uvirt = uaddr;
  405. db_tab->page[i].refcount = 1;
  406. out:
  407. mutex_unlock(&db_tab->mutex);
  408. return ret;
  409. }
  410. void mthca_unmap_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
  411. struct mthca_user_db_table *db_tab, int index)
  412. {
  413. if (!mthca_is_memfree(dev))
  414. return;
  415. /*
  416. * To make our bookkeeping simpler, we don't unmap DB
  417. * pages until we clean up the whole db table.
  418. */
  419. mutex_lock(&db_tab->mutex);
  420. --db_tab->page[index / MTHCA_DB_REC_PER_PAGE].refcount;
  421. mutex_unlock(&db_tab->mutex);
  422. }
  423. struct mthca_user_db_table *mthca_init_user_db_tab(struct mthca_dev *dev)
  424. {
  425. struct mthca_user_db_table *db_tab;
  426. int npages;
  427. int i;
  428. if (!mthca_is_memfree(dev))
  429. return NULL;
  430. npages = dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE;
  431. db_tab = kmalloc(sizeof *db_tab + npages * sizeof *db_tab->page, GFP_KERNEL);
  432. if (!db_tab)
  433. return ERR_PTR(-ENOMEM);
  434. mutex_init(&db_tab->mutex);
  435. for (i = 0; i < npages; ++i) {
  436. db_tab->page[i].refcount = 0;
  437. db_tab->page[i].uvirt = 0;
  438. }
  439. return db_tab;
  440. }
  441. void mthca_cleanup_user_db_tab(struct mthca_dev *dev, struct mthca_uar *uar,
  442. struct mthca_user_db_table *db_tab)
  443. {
  444. int i;
  445. u8 status;
  446. if (!mthca_is_memfree(dev))
  447. return;
  448. for (i = 0; i < dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE; ++i) {
  449. if (db_tab->page[i].uvirt) {
  450. mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, uar, i), 1, &status);
  451. pci_unmap_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
  452. put_page(db_tab->page[i].mem.page);
  453. }
  454. }
  455. kfree(db_tab);
  456. }
  457. int mthca_alloc_db(struct mthca_dev *dev, enum mthca_db_type type,
  458. u32 qn, __be32 **db)
  459. {
  460. int group;
  461. int start, end, dir;
  462. int i, j;
  463. struct mthca_db_page *page;
  464. int ret = 0;
  465. u8 status;
  466. mutex_lock(&dev->db_tab->mutex);
  467. switch (type) {
  468. case MTHCA_DB_TYPE_CQ_ARM:
  469. case MTHCA_DB_TYPE_SQ:
  470. group = 0;
  471. start = 0;
  472. end = dev->db_tab->max_group1;
  473. dir = 1;
  474. break;
  475. case MTHCA_DB_TYPE_CQ_SET_CI:
  476. case MTHCA_DB_TYPE_RQ:
  477. case MTHCA_DB_TYPE_SRQ:
  478. group = 1;
  479. start = dev->db_tab->npages - 1;
  480. end = dev->db_tab->min_group2;
  481. dir = -1;
  482. break;
  483. default:
  484. ret = -EINVAL;
  485. goto out;
  486. }
  487. for (i = start; i != end; i += dir)
  488. if (dev->db_tab->page[i].db_rec &&
  489. !bitmap_full(dev->db_tab->page[i].used,
  490. MTHCA_DB_REC_PER_PAGE)) {
  491. page = dev->db_tab->page + i;
  492. goto found;
  493. }
  494. for (i = start; i != end; i += dir)
  495. if (!dev->db_tab->page[i].db_rec) {
  496. page = dev->db_tab->page + i;
  497. goto alloc;
  498. }
  499. if (dev->db_tab->max_group1 >= dev->db_tab->min_group2 - 1) {
  500. ret = -ENOMEM;
  501. goto out;
  502. }
  503. if (group == 0)
  504. ++dev->db_tab->max_group1;
  505. else
  506. --dev->db_tab->min_group2;
  507. page = dev->db_tab->page + end;
  508. alloc:
  509. page->db_rec = dma_alloc_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  510. &page->mapping, GFP_KERNEL);
  511. if (!page->db_rec) {
  512. ret = -ENOMEM;
  513. goto out;
  514. }
  515. memset(page->db_rec, 0, MTHCA_ICM_PAGE_SIZE);
  516. ret = mthca_MAP_ICM_page(dev, page->mapping,
  517. mthca_uarc_virt(dev, &dev->driver_uar, i), &status);
  518. if (!ret && status)
  519. ret = -EINVAL;
  520. if (ret) {
  521. dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  522. page->db_rec, page->mapping);
  523. goto out;
  524. }
  525. bitmap_zero(page->used, MTHCA_DB_REC_PER_PAGE);
  526. found:
  527. j = find_first_zero_bit(page->used, MTHCA_DB_REC_PER_PAGE);
  528. set_bit(j, page->used);
  529. if (group == 1)
  530. j = MTHCA_DB_REC_PER_PAGE - 1 - j;
  531. ret = i * MTHCA_DB_REC_PER_PAGE + j;
  532. page->db_rec[j] = cpu_to_be64((qn << 8) | (type << 5));
  533. *db = (__be32 *) &page->db_rec[j];
  534. out:
  535. mutex_unlock(&dev->db_tab->mutex);
  536. return ret;
  537. }
  538. void mthca_free_db(struct mthca_dev *dev, int type, int db_index)
  539. {
  540. int i, j;
  541. struct mthca_db_page *page;
  542. u8 status;
  543. i = db_index / MTHCA_DB_REC_PER_PAGE;
  544. j = db_index % MTHCA_DB_REC_PER_PAGE;
  545. page = dev->db_tab->page + i;
  546. mutex_lock(&dev->db_tab->mutex);
  547. page->db_rec[j] = 0;
  548. if (i >= dev->db_tab->min_group2)
  549. j = MTHCA_DB_REC_PER_PAGE - 1 - j;
  550. clear_bit(j, page->used);
  551. if (bitmap_empty(page->used, MTHCA_DB_REC_PER_PAGE) &&
  552. i >= dev->db_tab->max_group1 - 1) {
  553. mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, &dev->driver_uar, i), 1, &status);
  554. dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  555. page->db_rec, page->mapping);
  556. page->db_rec = NULL;
  557. if (i == dev->db_tab->max_group1) {
  558. --dev->db_tab->max_group1;
  559. /* XXX may be able to unmap more pages now */
  560. }
  561. if (i == dev->db_tab->min_group2)
  562. ++dev->db_tab->min_group2;
  563. }
  564. mutex_unlock(&dev->db_tab->mutex);
  565. }
  566. int mthca_init_db_tab(struct mthca_dev *dev)
  567. {
  568. int i;
  569. if (!mthca_is_memfree(dev))
  570. return 0;
  571. dev->db_tab = kmalloc(sizeof *dev->db_tab, GFP_KERNEL);
  572. if (!dev->db_tab)
  573. return -ENOMEM;
  574. mutex_init(&dev->db_tab->mutex);
  575. dev->db_tab->npages = dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE;
  576. dev->db_tab->max_group1 = 0;
  577. dev->db_tab->min_group2 = dev->db_tab->npages - 1;
  578. dev->db_tab->page = kmalloc(dev->db_tab->npages *
  579. sizeof *dev->db_tab->page,
  580. GFP_KERNEL);
  581. if (!dev->db_tab->page) {
  582. kfree(dev->db_tab);
  583. return -ENOMEM;
  584. }
  585. for (i = 0; i < dev->db_tab->npages; ++i)
  586. dev->db_tab->page[i].db_rec = NULL;
  587. return 0;
  588. }
  589. void mthca_cleanup_db_tab(struct mthca_dev *dev)
  590. {
  591. int i;
  592. u8 status;
  593. if (!mthca_is_memfree(dev))
  594. return;
  595. /*
  596. * Because we don't always free our UARC pages when they
  597. * become empty to make mthca_free_db() simpler we need to
  598. * make a sweep through the doorbell pages and free any
  599. * leftover pages now.
  600. */
  601. for (i = 0; i < dev->db_tab->npages; ++i) {
  602. if (!dev->db_tab->page[i].db_rec)
  603. continue;
  604. if (!bitmap_empty(dev->db_tab->page[i].used, MTHCA_DB_REC_PER_PAGE))
  605. mthca_warn(dev, "Kernel UARC page %d not empty\n", i);
  606. mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, &dev->driver_uar, i), 1, &status);
  607. dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  608. dev->db_tab->page[i].db_rec,
  609. dev->db_tab->page[i].mapping);
  610. }
  611. kfree(dev->db_tab->page);
  612. kfree(dev->db_tab);
  613. }