mthca_main.c 37 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397
  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/module.h>
  37. #include <linux/init.h>
  38. #include <linux/errno.h>
  39. #include <linux/pci.h>
  40. #include <linux/interrupt.h>
  41. #include "mthca_dev.h"
  42. #include "mthca_config_reg.h"
  43. #include "mthca_cmd.h"
  44. #include "mthca_profile.h"
  45. #include "mthca_memfree.h"
  46. MODULE_AUTHOR("Roland Dreier");
  47. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  48. MODULE_LICENSE("Dual BSD/GPL");
  49. MODULE_VERSION(DRV_VERSION);
  50. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  51. int mthca_debug_level = 0;
  52. module_param_named(debug_level, mthca_debug_level, int, 0644);
  53. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  54. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  55. #ifdef CONFIG_PCI_MSI
  56. static int msi_x = 0;
  57. module_param(msi_x, int, 0444);
  58. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  59. static int msi = 0;
  60. module_param(msi, int, 0444);
  61. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  62. #else /* CONFIG_PCI_MSI */
  63. #define msi_x (0)
  64. #define msi (0)
  65. #endif /* CONFIG_PCI_MSI */
  66. static int tune_pci = 0;
  67. module_param(tune_pci, int, 0444);
  68. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  69. DEFINE_MUTEX(mthca_device_mutex);
  70. #define MTHCA_DEFAULT_NUM_QP (1 << 16)
  71. #define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
  72. #define MTHCA_DEFAULT_NUM_CQ (1 << 16)
  73. #define MTHCA_DEFAULT_NUM_MCG (1 << 13)
  74. #define MTHCA_DEFAULT_NUM_MPT (1 << 17)
  75. #define MTHCA_DEFAULT_NUM_MTT (1 << 20)
  76. #define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
  77. #define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
  78. #define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
  79. static struct mthca_profile hca_profile = {
  80. .num_qp = MTHCA_DEFAULT_NUM_QP,
  81. .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
  82. .num_cq = MTHCA_DEFAULT_NUM_CQ,
  83. .num_mcg = MTHCA_DEFAULT_NUM_MCG,
  84. .num_mpt = MTHCA_DEFAULT_NUM_MPT,
  85. .num_mtt = MTHCA_DEFAULT_NUM_MTT,
  86. .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
  87. .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
  88. .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
  89. };
  90. module_param_named(num_qp, hca_profile.num_qp, int, 0444);
  91. MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
  92. module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
  93. MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
  94. module_param_named(num_cq, hca_profile.num_cq, int, 0444);
  95. MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
  96. module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
  97. MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
  98. module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
  99. MODULE_PARM_DESC(num_mpt,
  100. "maximum number of memory protection table entries per HCA");
  101. module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
  102. MODULE_PARM_DESC(num_mtt,
  103. "maximum number of memory translation table segments per HCA");
  104. module_param_named(num_udav, hca_profile.num_udav, int, 0444);
  105. MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
  106. module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
  107. MODULE_PARM_DESC(fmr_reserved_mtts,
  108. "number of memory translation table segments reserved for FMR");
  109. static const char mthca_version[] __devinitdata =
  110. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  111. DRV_VERSION " (" DRV_RELDATE ")\n";
  112. static int mthca_tune_pci(struct mthca_dev *mdev)
  113. {
  114. int cap;
  115. u16 val;
  116. if (!tune_pci)
  117. return 0;
  118. /* First try to max out Read Byte Count */
  119. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  120. if (cap) {
  121. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  122. mthca_err(mdev, "Couldn't read PCI-X command register, "
  123. "aborting.\n");
  124. return -ENODEV;
  125. }
  126. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  127. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  128. mthca_err(mdev, "Couldn't write PCI-X command register, "
  129. "aborting.\n");
  130. return -ENODEV;
  131. }
  132. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  133. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  134. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  135. if (cap) {
  136. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  137. mthca_err(mdev, "Couldn't read PCI Express device control "
  138. "register, aborting.\n");
  139. return -ENODEV;
  140. }
  141. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  142. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  143. mthca_err(mdev, "Couldn't write PCI Express device control "
  144. "register, aborting.\n");
  145. return -ENODEV;
  146. }
  147. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  148. mthca_info(mdev, "No PCI Express capability, "
  149. "not setting Max Read Request Size.\n");
  150. return 0;
  151. }
  152. static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  153. {
  154. int err;
  155. u8 status;
  156. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  157. if (err) {
  158. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  159. return err;
  160. }
  161. if (status) {
  162. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  163. "aborting.\n", status);
  164. return -EINVAL;
  165. }
  166. if (dev_lim->min_page_sz > PAGE_SIZE) {
  167. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  168. "kernel PAGE_SIZE of %ld, aborting.\n",
  169. dev_lim->min_page_sz, PAGE_SIZE);
  170. return -ENODEV;
  171. }
  172. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  173. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  174. "aborting.\n",
  175. dev_lim->num_ports, MTHCA_MAX_PORTS);
  176. return -ENODEV;
  177. }
  178. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  179. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  180. "PCI resource 2 size of 0x%llx, aborting.\n",
  181. dev_lim->uar_size,
  182. (unsigned long long)pci_resource_len(mdev->pdev, 2));
  183. return -ENODEV;
  184. }
  185. mdev->limits.num_ports = dev_lim->num_ports;
  186. mdev->limits.vl_cap = dev_lim->max_vl;
  187. mdev->limits.mtu_cap = dev_lim->max_mtu;
  188. mdev->limits.gid_table_len = dev_lim->max_gids;
  189. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  190. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  191. mdev->limits.max_sg = dev_lim->max_sg;
  192. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  193. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  194. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  195. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  196. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  197. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  198. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  199. mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
  200. /*
  201. * Subtract 1 from the limit because we need to allocate a
  202. * spare CQE so the HCA HW can tell the difference between an
  203. * empty CQ and a full CQ.
  204. */
  205. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  206. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  207. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  208. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  209. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  210. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  211. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  212. mdev->limits.port_width_cap = dev_lim->max_port_width;
  213. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  214. mdev->limits.flags = dev_lim->flags;
  215. /*
  216. * For old FW that doesn't return static rate support, use a
  217. * value of 0x3 (only static rate values of 0 or 1 are handled),
  218. * except on Sinai, where even old FW can handle static rate
  219. * values of 2 and 3.
  220. */
  221. if (dev_lim->stat_rate_support)
  222. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  223. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  224. mdev->limits.stat_rate_support = 0xf;
  225. else
  226. mdev->limits.stat_rate_support = 0x3;
  227. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  228. May be doable since hardware supports it for SRQ.
  229. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  230. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  231. supported by driver. */
  232. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  233. IB_DEVICE_PORT_ACTIVE_EVENT |
  234. IB_DEVICE_SYS_IMAGE_GUID |
  235. IB_DEVICE_RC_RNR_NAK_GEN;
  236. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  237. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  238. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  239. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  240. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  241. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  242. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  243. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  244. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  245. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  246. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  247. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  248. return 0;
  249. }
  250. static int mthca_init_tavor(struct mthca_dev *mdev)
  251. {
  252. u8 status;
  253. int err;
  254. struct mthca_dev_lim dev_lim;
  255. struct mthca_profile profile;
  256. struct mthca_init_hca_param init_hca;
  257. err = mthca_SYS_EN(mdev, &status);
  258. if (err) {
  259. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  260. return err;
  261. }
  262. if (status) {
  263. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  264. "aborting.\n", status);
  265. return -EINVAL;
  266. }
  267. err = mthca_QUERY_FW(mdev, &status);
  268. if (err) {
  269. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  270. goto err_disable;
  271. }
  272. if (status) {
  273. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  274. "aborting.\n", status);
  275. err = -EINVAL;
  276. goto err_disable;
  277. }
  278. err = mthca_QUERY_DDR(mdev, &status);
  279. if (err) {
  280. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  281. goto err_disable;
  282. }
  283. if (status) {
  284. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  285. "aborting.\n", status);
  286. err = -EINVAL;
  287. goto err_disable;
  288. }
  289. err = mthca_dev_lim(mdev, &dev_lim);
  290. if (err) {
  291. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  292. goto err_disable;
  293. }
  294. profile = hca_profile;
  295. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  296. profile.uarc_size = 0;
  297. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  298. profile.num_srq = dev_lim.max_srqs;
  299. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  300. if (err < 0)
  301. goto err_disable;
  302. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  303. if (err) {
  304. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  305. goto err_disable;
  306. }
  307. if (status) {
  308. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  309. "aborting.\n", status);
  310. err = -EINVAL;
  311. goto err_disable;
  312. }
  313. return 0;
  314. err_disable:
  315. mthca_SYS_DIS(mdev, &status);
  316. return err;
  317. }
  318. static int mthca_load_fw(struct mthca_dev *mdev)
  319. {
  320. u8 status;
  321. int err;
  322. /* FIXME: use HCA-attached memory for FW if present */
  323. mdev->fw.arbel.fw_icm =
  324. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  325. GFP_HIGHUSER | __GFP_NOWARN, 0);
  326. if (!mdev->fw.arbel.fw_icm) {
  327. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  328. return -ENOMEM;
  329. }
  330. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  331. if (err) {
  332. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  333. goto err_free;
  334. }
  335. if (status) {
  336. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  337. err = -EINVAL;
  338. goto err_free;
  339. }
  340. err = mthca_RUN_FW(mdev, &status);
  341. if (err) {
  342. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  343. goto err_unmap_fa;
  344. }
  345. if (status) {
  346. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  347. err = -EINVAL;
  348. goto err_unmap_fa;
  349. }
  350. return 0;
  351. err_unmap_fa:
  352. mthca_UNMAP_FA(mdev, &status);
  353. err_free:
  354. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  355. return err;
  356. }
  357. static int mthca_init_icm(struct mthca_dev *mdev,
  358. struct mthca_dev_lim *dev_lim,
  359. struct mthca_init_hca_param *init_hca,
  360. u64 icm_size)
  361. {
  362. u64 aux_pages;
  363. u8 status;
  364. int err;
  365. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  366. if (err) {
  367. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  368. return err;
  369. }
  370. if (status) {
  371. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  372. "aborting.\n", status);
  373. return -EINVAL;
  374. }
  375. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  376. (unsigned long long) icm_size >> 10,
  377. (unsigned long long) aux_pages << 2);
  378. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  379. GFP_HIGHUSER | __GFP_NOWARN, 0);
  380. if (!mdev->fw.arbel.aux_icm) {
  381. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  382. return -ENOMEM;
  383. }
  384. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  385. if (err) {
  386. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  387. goto err_free_aux;
  388. }
  389. if (status) {
  390. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  391. err = -EINVAL;
  392. goto err_free_aux;
  393. }
  394. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  395. if (err) {
  396. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  397. goto err_unmap_aux;
  398. }
  399. /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */
  400. mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * MTHCA_MTT_SEG_SIZE,
  401. dma_get_cache_alignment()) / MTHCA_MTT_SEG_SIZE;
  402. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  403. MTHCA_MTT_SEG_SIZE,
  404. mdev->limits.num_mtt_segs,
  405. mdev->limits.reserved_mtts,
  406. 1, 0);
  407. if (!mdev->mr_table.mtt_table) {
  408. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  409. err = -ENOMEM;
  410. goto err_unmap_eq;
  411. }
  412. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  413. dev_lim->mpt_entry_sz,
  414. mdev->limits.num_mpts,
  415. mdev->limits.reserved_mrws,
  416. 1, 1);
  417. if (!mdev->mr_table.mpt_table) {
  418. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  419. err = -ENOMEM;
  420. goto err_unmap_mtt;
  421. }
  422. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  423. dev_lim->qpc_entry_sz,
  424. mdev->limits.num_qps,
  425. mdev->limits.reserved_qps,
  426. 0, 0);
  427. if (!mdev->qp_table.qp_table) {
  428. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  429. err = -ENOMEM;
  430. goto err_unmap_mpt;
  431. }
  432. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  433. dev_lim->eqpc_entry_sz,
  434. mdev->limits.num_qps,
  435. mdev->limits.reserved_qps,
  436. 0, 0);
  437. if (!mdev->qp_table.eqp_table) {
  438. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  439. err = -ENOMEM;
  440. goto err_unmap_qp;
  441. }
  442. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  443. MTHCA_RDB_ENTRY_SIZE,
  444. mdev->limits.num_qps <<
  445. mdev->qp_table.rdb_shift, 0,
  446. 0, 0);
  447. if (!mdev->qp_table.rdb_table) {
  448. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  449. err = -ENOMEM;
  450. goto err_unmap_eqp;
  451. }
  452. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  453. dev_lim->cqc_entry_sz,
  454. mdev->limits.num_cqs,
  455. mdev->limits.reserved_cqs,
  456. 0, 0);
  457. if (!mdev->cq_table.table) {
  458. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  459. err = -ENOMEM;
  460. goto err_unmap_rdb;
  461. }
  462. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  463. mdev->srq_table.table =
  464. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  465. dev_lim->srq_entry_sz,
  466. mdev->limits.num_srqs,
  467. mdev->limits.reserved_srqs,
  468. 0, 0);
  469. if (!mdev->srq_table.table) {
  470. mthca_err(mdev, "Failed to map SRQ context memory, "
  471. "aborting.\n");
  472. err = -ENOMEM;
  473. goto err_unmap_cq;
  474. }
  475. }
  476. /*
  477. * It's not strictly required, but for simplicity just map the
  478. * whole multicast group table now. The table isn't very big
  479. * and it's a lot easier than trying to track ref counts.
  480. */
  481. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  482. MTHCA_MGM_ENTRY_SIZE,
  483. mdev->limits.num_mgms +
  484. mdev->limits.num_amgms,
  485. mdev->limits.num_mgms +
  486. mdev->limits.num_amgms,
  487. 0, 0);
  488. if (!mdev->mcg_table.table) {
  489. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  490. err = -ENOMEM;
  491. goto err_unmap_srq;
  492. }
  493. return 0;
  494. err_unmap_srq:
  495. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  496. mthca_free_icm_table(mdev, mdev->srq_table.table);
  497. err_unmap_cq:
  498. mthca_free_icm_table(mdev, mdev->cq_table.table);
  499. err_unmap_rdb:
  500. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  501. err_unmap_eqp:
  502. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  503. err_unmap_qp:
  504. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  505. err_unmap_mpt:
  506. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  507. err_unmap_mtt:
  508. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  509. err_unmap_eq:
  510. mthca_unmap_eq_icm(mdev);
  511. err_unmap_aux:
  512. mthca_UNMAP_ICM_AUX(mdev, &status);
  513. err_free_aux:
  514. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  515. return err;
  516. }
  517. static void mthca_free_icms(struct mthca_dev *mdev)
  518. {
  519. u8 status;
  520. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  521. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  522. mthca_free_icm_table(mdev, mdev->srq_table.table);
  523. mthca_free_icm_table(mdev, mdev->cq_table.table);
  524. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  525. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  526. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  527. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  528. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  529. mthca_unmap_eq_icm(mdev);
  530. mthca_UNMAP_ICM_AUX(mdev, &status);
  531. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  532. }
  533. static int mthca_init_arbel(struct mthca_dev *mdev)
  534. {
  535. struct mthca_dev_lim dev_lim;
  536. struct mthca_profile profile;
  537. struct mthca_init_hca_param init_hca;
  538. u64 icm_size;
  539. u8 status;
  540. int err;
  541. err = mthca_QUERY_FW(mdev, &status);
  542. if (err) {
  543. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  544. return err;
  545. }
  546. if (status) {
  547. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  548. "aborting.\n", status);
  549. return -EINVAL;
  550. }
  551. err = mthca_ENABLE_LAM(mdev, &status);
  552. if (err) {
  553. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  554. return err;
  555. }
  556. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  557. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  558. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  559. } else if (status) {
  560. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  561. "aborting.\n", status);
  562. return -EINVAL;
  563. }
  564. err = mthca_load_fw(mdev);
  565. if (err) {
  566. mthca_err(mdev, "Failed to start FW, aborting.\n");
  567. goto err_disable;
  568. }
  569. err = mthca_dev_lim(mdev, &dev_lim);
  570. if (err) {
  571. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  572. goto err_stop_fw;
  573. }
  574. profile = hca_profile;
  575. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  576. profile.num_udav = 0;
  577. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  578. profile.num_srq = dev_lim.max_srqs;
  579. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  580. if ((int) icm_size < 0) {
  581. err = icm_size;
  582. goto err_stop_fw;
  583. }
  584. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  585. if (err)
  586. goto err_stop_fw;
  587. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  588. if (err) {
  589. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  590. goto err_free_icm;
  591. }
  592. if (status) {
  593. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  594. "aborting.\n", status);
  595. err = -EINVAL;
  596. goto err_free_icm;
  597. }
  598. return 0;
  599. err_free_icm:
  600. mthca_free_icms(mdev);
  601. err_stop_fw:
  602. mthca_UNMAP_FA(mdev, &status);
  603. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  604. err_disable:
  605. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  606. mthca_DISABLE_LAM(mdev, &status);
  607. return err;
  608. }
  609. static void mthca_close_hca(struct mthca_dev *mdev)
  610. {
  611. u8 status;
  612. mthca_CLOSE_HCA(mdev, 0, &status);
  613. if (mthca_is_memfree(mdev)) {
  614. mthca_free_icms(mdev);
  615. mthca_UNMAP_FA(mdev, &status);
  616. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  617. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  618. mthca_DISABLE_LAM(mdev, &status);
  619. } else
  620. mthca_SYS_DIS(mdev, &status);
  621. }
  622. static int mthca_init_hca(struct mthca_dev *mdev)
  623. {
  624. u8 status;
  625. int err;
  626. struct mthca_adapter adapter;
  627. if (mthca_is_memfree(mdev))
  628. err = mthca_init_arbel(mdev);
  629. else
  630. err = mthca_init_tavor(mdev);
  631. if (err)
  632. return err;
  633. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  634. if (err) {
  635. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  636. goto err_close;
  637. }
  638. if (status) {
  639. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  640. "aborting.\n", status);
  641. err = -EINVAL;
  642. goto err_close;
  643. }
  644. mdev->eq_table.inta_pin = adapter.inta_pin;
  645. mdev->rev_id = adapter.revision_id;
  646. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  647. return 0;
  648. err_close:
  649. mthca_close_hca(mdev);
  650. return err;
  651. }
  652. static int mthca_setup_hca(struct mthca_dev *dev)
  653. {
  654. int err;
  655. u8 status;
  656. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  657. err = mthca_init_uar_table(dev);
  658. if (err) {
  659. mthca_err(dev, "Failed to initialize "
  660. "user access region table, aborting.\n");
  661. return err;
  662. }
  663. err = mthca_uar_alloc(dev, &dev->driver_uar);
  664. if (err) {
  665. mthca_err(dev, "Failed to allocate driver access region, "
  666. "aborting.\n");
  667. goto err_uar_table_free;
  668. }
  669. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  670. if (!dev->kar) {
  671. mthca_err(dev, "Couldn't map kernel access region, "
  672. "aborting.\n");
  673. err = -ENOMEM;
  674. goto err_uar_free;
  675. }
  676. err = mthca_init_pd_table(dev);
  677. if (err) {
  678. mthca_err(dev, "Failed to initialize "
  679. "protection domain table, aborting.\n");
  680. goto err_kar_unmap;
  681. }
  682. err = mthca_init_mr_table(dev);
  683. if (err) {
  684. mthca_err(dev, "Failed to initialize "
  685. "memory region table, aborting.\n");
  686. goto err_pd_table_free;
  687. }
  688. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  689. if (err) {
  690. mthca_err(dev, "Failed to create driver PD, "
  691. "aborting.\n");
  692. goto err_mr_table_free;
  693. }
  694. err = mthca_init_eq_table(dev);
  695. if (err) {
  696. mthca_err(dev, "Failed to initialize "
  697. "event queue table, aborting.\n");
  698. goto err_pd_free;
  699. }
  700. err = mthca_cmd_use_events(dev);
  701. if (err) {
  702. mthca_err(dev, "Failed to switch to event-driven "
  703. "firmware commands, aborting.\n");
  704. goto err_eq_table_free;
  705. }
  706. err = mthca_NOP(dev, &status);
  707. if (err || status) {
  708. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  709. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  710. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  711. dev->pdev->irq);
  712. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  713. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  714. else
  715. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  716. goto err_cmd_poll;
  717. }
  718. mthca_dbg(dev, "NOP command IRQ test passed\n");
  719. err = mthca_init_cq_table(dev);
  720. if (err) {
  721. mthca_err(dev, "Failed to initialize "
  722. "completion queue table, aborting.\n");
  723. goto err_cmd_poll;
  724. }
  725. err = mthca_init_srq_table(dev);
  726. if (err) {
  727. mthca_err(dev, "Failed to initialize "
  728. "shared receive queue table, aborting.\n");
  729. goto err_cq_table_free;
  730. }
  731. err = mthca_init_qp_table(dev);
  732. if (err) {
  733. mthca_err(dev, "Failed to initialize "
  734. "queue pair table, aborting.\n");
  735. goto err_srq_table_free;
  736. }
  737. err = mthca_init_av_table(dev);
  738. if (err) {
  739. mthca_err(dev, "Failed to initialize "
  740. "address vector table, aborting.\n");
  741. goto err_qp_table_free;
  742. }
  743. err = mthca_init_mcg_table(dev);
  744. if (err) {
  745. mthca_err(dev, "Failed to initialize "
  746. "multicast group table, aborting.\n");
  747. goto err_av_table_free;
  748. }
  749. return 0;
  750. err_av_table_free:
  751. mthca_cleanup_av_table(dev);
  752. err_qp_table_free:
  753. mthca_cleanup_qp_table(dev);
  754. err_srq_table_free:
  755. mthca_cleanup_srq_table(dev);
  756. err_cq_table_free:
  757. mthca_cleanup_cq_table(dev);
  758. err_cmd_poll:
  759. mthca_cmd_use_polling(dev);
  760. err_eq_table_free:
  761. mthca_cleanup_eq_table(dev);
  762. err_pd_free:
  763. mthca_pd_free(dev, &dev->driver_pd);
  764. err_mr_table_free:
  765. mthca_cleanup_mr_table(dev);
  766. err_pd_table_free:
  767. mthca_cleanup_pd_table(dev);
  768. err_kar_unmap:
  769. iounmap(dev->kar);
  770. err_uar_free:
  771. mthca_uar_free(dev, &dev->driver_uar);
  772. err_uar_table_free:
  773. mthca_cleanup_uar_table(dev);
  774. return err;
  775. }
  776. static int mthca_request_regions(struct pci_dev *pdev, int ddr_hidden)
  777. {
  778. int err;
  779. /*
  780. * We can't just use pci_request_regions() because the MSI-X
  781. * table is right in the middle of the first BAR. If we did
  782. * pci_request_region and grab all of the first BAR, then
  783. * setting up MSI-X would fail, since the PCI core wants to do
  784. * request_mem_region on the MSI-X vector table.
  785. *
  786. * So just request what we need right now, and request any
  787. * other regions we need when setting up EQs.
  788. */
  789. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  790. MTHCA_HCR_SIZE, DRV_NAME))
  791. return -EBUSY;
  792. err = pci_request_region(pdev, 2, DRV_NAME);
  793. if (err)
  794. goto err_bar2_failed;
  795. if (!ddr_hidden) {
  796. err = pci_request_region(pdev, 4, DRV_NAME);
  797. if (err)
  798. goto err_bar4_failed;
  799. }
  800. return 0;
  801. err_bar4_failed:
  802. pci_release_region(pdev, 2);
  803. err_bar2_failed:
  804. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  805. MTHCA_HCR_SIZE);
  806. return err;
  807. }
  808. static void mthca_release_regions(struct pci_dev *pdev,
  809. int ddr_hidden)
  810. {
  811. if (!ddr_hidden)
  812. pci_release_region(pdev, 4);
  813. pci_release_region(pdev, 2);
  814. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  815. MTHCA_HCR_SIZE);
  816. }
  817. static int mthca_enable_msi_x(struct mthca_dev *mdev)
  818. {
  819. struct msix_entry entries[3];
  820. int err;
  821. entries[0].entry = 0;
  822. entries[1].entry = 1;
  823. entries[2].entry = 2;
  824. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  825. if (err) {
  826. if (err > 0)
  827. mthca_info(mdev, "Only %d MSI-X vectors available, "
  828. "not using MSI-X\n", err);
  829. return err;
  830. }
  831. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  832. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  833. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  834. return 0;
  835. }
  836. /* Types of supported HCA */
  837. enum {
  838. TAVOR, /* MT23108 */
  839. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  840. ARBEL_NATIVE, /* MT25208 with extended features */
  841. SINAI /* MT25204 */
  842. };
  843. #define MTHCA_FW_VER(major, minor, subminor) \
  844. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  845. static struct {
  846. u64 latest_fw;
  847. u32 flags;
  848. } mthca_hca_table[] = {
  849. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0),
  850. .flags = 0 },
  851. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200),
  852. .flags = MTHCA_FLAG_PCIE },
  853. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 2, 0),
  854. .flags = MTHCA_FLAG_MEMFREE |
  855. MTHCA_FLAG_PCIE },
  856. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0),
  857. .flags = MTHCA_FLAG_MEMFREE |
  858. MTHCA_FLAG_PCIE |
  859. MTHCA_FLAG_SINAI_OPT }
  860. };
  861. static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
  862. {
  863. int ddr_hidden = 0;
  864. int err;
  865. struct mthca_dev *mdev;
  866. printk(KERN_INFO PFX "Initializing %s\n",
  867. pci_name(pdev));
  868. err = pci_enable_device(pdev);
  869. if (err) {
  870. dev_err(&pdev->dev, "Cannot enable PCI device, "
  871. "aborting.\n");
  872. return err;
  873. }
  874. /*
  875. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  876. * be present)
  877. */
  878. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  879. pci_resource_len(pdev, 0) != 1 << 20) {
  880. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  881. err = -ENODEV;
  882. goto err_disable_pdev;
  883. }
  884. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  885. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  886. err = -ENODEV;
  887. goto err_disable_pdev;
  888. }
  889. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  890. ddr_hidden = 1;
  891. err = mthca_request_regions(pdev, ddr_hidden);
  892. if (err) {
  893. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  894. "aborting.\n");
  895. goto err_disable_pdev;
  896. }
  897. pci_set_master(pdev);
  898. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  899. if (err) {
  900. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  901. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  902. if (err) {
  903. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  904. goto err_free_res;
  905. }
  906. }
  907. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  908. if (err) {
  909. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  910. "consistent PCI DMA mask.\n");
  911. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  912. if (err) {
  913. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  914. "aborting.\n");
  915. goto err_free_res;
  916. }
  917. }
  918. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  919. if (!mdev) {
  920. dev_err(&pdev->dev, "Device struct alloc failed, "
  921. "aborting.\n");
  922. err = -ENOMEM;
  923. goto err_free_res;
  924. }
  925. mdev->pdev = pdev;
  926. mdev->mthca_flags = mthca_hca_table[hca_type].flags;
  927. if (ddr_hidden)
  928. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  929. /*
  930. * Now reset the HCA before we touch the PCI capabilities or
  931. * attempt a firmware command, since a boot ROM may have left
  932. * the HCA in an undefined state.
  933. */
  934. err = mthca_reset(mdev);
  935. if (err) {
  936. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  937. goto err_free_dev;
  938. }
  939. if (msi_x && !mthca_enable_msi_x(mdev))
  940. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  941. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  942. !pci_enable_msi(pdev))
  943. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  944. if (mthca_cmd_init(mdev)) {
  945. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  946. goto err_free_dev;
  947. }
  948. err = mthca_tune_pci(mdev);
  949. if (err)
  950. goto err_cmd;
  951. err = mthca_init_hca(mdev);
  952. if (err)
  953. goto err_cmd;
  954. if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
  955. mthca_warn(mdev, "HCA FW version %d.%d.%3d is old (%d.%d.%3d is current).\n",
  956. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  957. (int) (mdev->fw_ver & 0xffff),
  958. (int) (mthca_hca_table[hca_type].latest_fw >> 32),
  959. (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
  960. (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
  961. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  962. }
  963. err = mthca_setup_hca(mdev);
  964. if (err)
  965. goto err_close;
  966. err = mthca_register_device(mdev);
  967. if (err)
  968. goto err_cleanup;
  969. err = mthca_create_agents(mdev);
  970. if (err)
  971. goto err_unregister;
  972. pci_set_drvdata(pdev, mdev);
  973. mdev->hca_type = hca_type;
  974. return 0;
  975. err_unregister:
  976. mthca_unregister_device(mdev);
  977. err_cleanup:
  978. mthca_cleanup_mcg_table(mdev);
  979. mthca_cleanup_av_table(mdev);
  980. mthca_cleanup_qp_table(mdev);
  981. mthca_cleanup_srq_table(mdev);
  982. mthca_cleanup_cq_table(mdev);
  983. mthca_cmd_use_polling(mdev);
  984. mthca_cleanup_eq_table(mdev);
  985. mthca_pd_free(mdev, &mdev->driver_pd);
  986. mthca_cleanup_mr_table(mdev);
  987. mthca_cleanup_pd_table(mdev);
  988. mthca_cleanup_uar_table(mdev);
  989. err_close:
  990. mthca_close_hca(mdev);
  991. err_cmd:
  992. mthca_cmd_cleanup(mdev);
  993. err_free_dev:
  994. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  995. pci_disable_msix(pdev);
  996. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  997. pci_disable_msi(pdev);
  998. ib_dealloc_device(&mdev->ib_dev);
  999. err_free_res:
  1000. mthca_release_regions(pdev, ddr_hidden);
  1001. err_disable_pdev:
  1002. pci_disable_device(pdev);
  1003. pci_set_drvdata(pdev, NULL);
  1004. return err;
  1005. }
  1006. static void __mthca_remove_one(struct pci_dev *pdev)
  1007. {
  1008. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  1009. u8 status;
  1010. int p;
  1011. if (mdev) {
  1012. mthca_free_agents(mdev);
  1013. mthca_unregister_device(mdev);
  1014. for (p = 1; p <= mdev->limits.num_ports; ++p)
  1015. mthca_CLOSE_IB(mdev, p, &status);
  1016. mthca_cleanup_mcg_table(mdev);
  1017. mthca_cleanup_av_table(mdev);
  1018. mthca_cleanup_qp_table(mdev);
  1019. mthca_cleanup_srq_table(mdev);
  1020. mthca_cleanup_cq_table(mdev);
  1021. mthca_cmd_use_polling(mdev);
  1022. mthca_cleanup_eq_table(mdev);
  1023. mthca_pd_free(mdev, &mdev->driver_pd);
  1024. mthca_cleanup_mr_table(mdev);
  1025. mthca_cleanup_pd_table(mdev);
  1026. iounmap(mdev->kar);
  1027. mthca_uar_free(mdev, &mdev->driver_uar);
  1028. mthca_cleanup_uar_table(mdev);
  1029. mthca_close_hca(mdev);
  1030. mthca_cmd_cleanup(mdev);
  1031. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  1032. pci_disable_msix(pdev);
  1033. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  1034. pci_disable_msi(pdev);
  1035. ib_dealloc_device(&mdev->ib_dev);
  1036. mthca_release_regions(pdev, mdev->mthca_flags &
  1037. MTHCA_FLAG_DDR_HIDDEN);
  1038. pci_disable_device(pdev);
  1039. pci_set_drvdata(pdev, NULL);
  1040. }
  1041. }
  1042. int __mthca_restart_one(struct pci_dev *pdev)
  1043. {
  1044. struct mthca_dev *mdev;
  1045. mdev = pci_get_drvdata(pdev);
  1046. if (!mdev)
  1047. return -ENODEV;
  1048. __mthca_remove_one(pdev);
  1049. return __mthca_init_one(pdev, mdev->hca_type);
  1050. }
  1051. static int __devinit mthca_init_one(struct pci_dev *pdev,
  1052. const struct pci_device_id *id)
  1053. {
  1054. static int mthca_version_printed = 0;
  1055. int ret;
  1056. mutex_lock(&mthca_device_mutex);
  1057. if (!mthca_version_printed) {
  1058. printk(KERN_INFO "%s", mthca_version);
  1059. ++mthca_version_printed;
  1060. }
  1061. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  1062. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  1063. pci_name(pdev), id->driver_data);
  1064. mutex_unlock(&mthca_device_mutex);
  1065. return -ENODEV;
  1066. }
  1067. ret = __mthca_init_one(pdev, id->driver_data);
  1068. mutex_unlock(&mthca_device_mutex);
  1069. return ret;
  1070. }
  1071. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  1072. {
  1073. mutex_lock(&mthca_device_mutex);
  1074. __mthca_remove_one(pdev);
  1075. mutex_unlock(&mthca_device_mutex);
  1076. }
  1077. static struct pci_device_id mthca_pci_table[] = {
  1078. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1079. .driver_data = TAVOR },
  1080. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1081. .driver_data = TAVOR },
  1082. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1083. .driver_data = ARBEL_COMPAT },
  1084. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1085. .driver_data = ARBEL_COMPAT },
  1086. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1087. .driver_data = ARBEL_NATIVE },
  1088. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1089. .driver_data = ARBEL_NATIVE },
  1090. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1091. .driver_data = SINAI },
  1092. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1093. .driver_data = SINAI },
  1094. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1095. .driver_data = SINAI },
  1096. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1097. .driver_data = SINAI },
  1098. { 0, }
  1099. };
  1100. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1101. static struct pci_driver mthca_driver = {
  1102. .name = DRV_NAME,
  1103. .id_table = mthca_pci_table,
  1104. .probe = mthca_init_one,
  1105. .remove = __devexit_p(mthca_remove_one)
  1106. };
  1107. static void __init __mthca_check_profile_val(const char *name, int *pval,
  1108. int pval_default)
  1109. {
  1110. /* value must be positive and power of 2 */
  1111. int old_pval = *pval;
  1112. if (old_pval <= 0)
  1113. *pval = pval_default;
  1114. else
  1115. *pval = roundup_pow_of_two(old_pval);
  1116. if (old_pval != *pval) {
  1117. printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
  1118. old_pval, name);
  1119. printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
  1120. }
  1121. }
  1122. #define mthca_check_profile_val(name, default) \
  1123. __mthca_check_profile_val(#name, &hca_profile.name, default)
  1124. static void __init mthca_validate_profile(void)
  1125. {
  1126. mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
  1127. mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
  1128. mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
  1129. mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
  1130. mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
  1131. mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
  1132. mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
  1133. mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
  1134. if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
  1135. printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
  1136. hca_profile.fmr_reserved_mtts);
  1137. printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
  1138. hca_profile.num_mtt);
  1139. hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
  1140. printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
  1141. hca_profile.fmr_reserved_mtts);
  1142. }
  1143. }
  1144. static int __init mthca_init(void)
  1145. {
  1146. int ret;
  1147. mthca_validate_profile();
  1148. ret = mthca_catas_init();
  1149. if (ret)
  1150. return ret;
  1151. ret = pci_register_driver(&mthca_driver);
  1152. if (ret < 0) {
  1153. mthca_catas_cleanup();
  1154. return ret;
  1155. }
  1156. return 0;
  1157. }
  1158. static void __exit mthca_cleanup(void)
  1159. {
  1160. pci_unregister_driver(&mthca_driver);
  1161. mthca_catas_cleanup();
  1162. }
  1163. module_init(mthca_init);
  1164. module_exit(mthca_cleanup);