atiixp.c 8.3 KB

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  1. /*
  2. * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
  3. *
  4. * Copyright (C) 2003 ATI Inc. <hyu@ati.com>
  5. * Copyright (C) 2004 Bartlomiej Zolnierkiewicz
  6. *
  7. */
  8. #include <linux/types.h>
  9. #include <linux/module.h>
  10. #include <linux/kernel.h>
  11. #include <linux/ioport.h>
  12. #include <linux/pci.h>
  13. #include <linux/hdreg.h>
  14. #include <linux/ide.h>
  15. #include <linux/delay.h>
  16. #include <linux/init.h>
  17. #include <asm/io.h>
  18. #define ATIIXP_IDE_PIO_TIMING 0x40
  19. #define ATIIXP_IDE_MDMA_TIMING 0x44
  20. #define ATIIXP_IDE_PIO_CONTROL 0x48
  21. #define ATIIXP_IDE_PIO_MODE 0x4a
  22. #define ATIIXP_IDE_UDMA_CONTROL 0x54
  23. #define ATIIXP_IDE_UDMA_MODE 0x56
  24. typedef struct {
  25. u8 command_width;
  26. u8 recover_width;
  27. } atiixp_ide_timing;
  28. static atiixp_ide_timing pio_timing[] = {
  29. { 0x05, 0x0d },
  30. { 0x04, 0x07 },
  31. { 0x03, 0x04 },
  32. { 0x02, 0x02 },
  33. { 0x02, 0x00 },
  34. };
  35. static atiixp_ide_timing mdma_timing[] = {
  36. { 0x07, 0x07 },
  37. { 0x02, 0x01 },
  38. { 0x02, 0x00 },
  39. };
  40. static int save_mdma_mode[4];
  41. static DEFINE_SPINLOCK(atiixp_lock);
  42. /**
  43. * atiixp_dma_2_pio - return the PIO mode matching DMA
  44. * @xfer_rate: transfer speed
  45. *
  46. * Returns the nearest equivalent PIO timing for the PIO or DMA
  47. * mode requested by the controller.
  48. */
  49. static u8 atiixp_dma_2_pio(u8 xfer_rate) {
  50. switch(xfer_rate) {
  51. case XFER_UDMA_6:
  52. case XFER_UDMA_5:
  53. case XFER_UDMA_4:
  54. case XFER_UDMA_3:
  55. case XFER_UDMA_2:
  56. case XFER_UDMA_1:
  57. case XFER_UDMA_0:
  58. case XFER_MW_DMA_2:
  59. case XFER_PIO_4:
  60. return 4;
  61. case XFER_MW_DMA_1:
  62. case XFER_PIO_3:
  63. return 3;
  64. case XFER_SW_DMA_2:
  65. case XFER_PIO_2:
  66. return 2;
  67. case XFER_MW_DMA_0:
  68. case XFER_SW_DMA_1:
  69. case XFER_SW_DMA_0:
  70. case XFER_PIO_1:
  71. case XFER_PIO_0:
  72. case XFER_PIO_SLOW:
  73. default:
  74. return 0;
  75. }
  76. }
  77. static void atiixp_dma_host_on(ide_drive_t *drive)
  78. {
  79. struct pci_dev *dev = drive->hwif->pci_dev;
  80. unsigned long flags;
  81. u16 tmp16;
  82. spin_lock_irqsave(&atiixp_lock, flags);
  83. pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
  84. if (save_mdma_mode[drive->dn])
  85. tmp16 &= ~(1 << drive->dn);
  86. else
  87. tmp16 |= (1 << drive->dn);
  88. pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
  89. spin_unlock_irqrestore(&atiixp_lock, flags);
  90. ide_dma_host_on(drive);
  91. }
  92. static void atiixp_dma_host_off(ide_drive_t *drive)
  93. {
  94. struct pci_dev *dev = drive->hwif->pci_dev;
  95. unsigned long flags;
  96. u16 tmp16;
  97. spin_lock_irqsave(&atiixp_lock, flags);
  98. pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
  99. tmp16 &= ~(1 << drive->dn);
  100. pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
  101. spin_unlock_irqrestore(&atiixp_lock, flags);
  102. ide_dma_host_off(drive);
  103. }
  104. /**
  105. * atiixp_tune_drive - tune a drive attached to a ATIIXP
  106. * @drive: drive to tune
  107. * @pio: desired PIO mode
  108. *
  109. * Set the interface PIO mode.
  110. */
  111. static void atiixp_tuneproc(ide_drive_t *drive, u8 pio)
  112. {
  113. struct pci_dev *dev = drive->hwif->pci_dev;
  114. unsigned long flags;
  115. int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
  116. u32 pio_timing_data;
  117. u16 pio_mode_data;
  118. spin_lock_irqsave(&atiixp_lock, flags);
  119. pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
  120. pio_mode_data &= ~(0x07 << (drive->dn * 4));
  121. pio_mode_data |= (pio << (drive->dn * 4));
  122. pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
  123. pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
  124. pio_timing_data &= ~(0xff << timing_shift);
  125. pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
  126. (pio_timing[pio].command_width << (timing_shift + 4));
  127. pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
  128. spin_unlock_irqrestore(&atiixp_lock, flags);
  129. }
  130. /**
  131. * atiixp_tune_chipset - tune a ATIIXP interface
  132. * @drive: IDE drive to tune
  133. * @xferspeed: speed to configure
  134. *
  135. * Set a ATIIXP interface channel to the desired speeds. This involves
  136. * requires the right timing data into the ATIIXP configuration space
  137. * then setting the drive parameters appropriately
  138. */
  139. static int atiixp_speedproc(ide_drive_t *drive, u8 xferspeed)
  140. {
  141. struct pci_dev *dev = drive->hwif->pci_dev;
  142. unsigned long flags;
  143. int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
  144. u32 tmp32;
  145. u16 tmp16;
  146. u8 speed, pio;
  147. speed = ide_rate_filter(drive, xferspeed);
  148. spin_lock_irqsave(&atiixp_lock, flags);
  149. save_mdma_mode[drive->dn] = 0;
  150. if (speed >= XFER_UDMA_0) {
  151. pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
  152. tmp16 &= ~(0x07 << (drive->dn * 4));
  153. tmp16 |= ((speed & 0x07) << (drive->dn * 4));
  154. pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
  155. } else {
  156. if ((speed >= XFER_MW_DMA_0) && (speed <= XFER_MW_DMA_2)) {
  157. save_mdma_mode[drive->dn] = speed;
  158. pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
  159. tmp32 &= ~(0xff << timing_shift);
  160. tmp32 |= (mdma_timing[speed & 0x03].recover_width << timing_shift) |
  161. (mdma_timing[speed & 0x03].command_width << (timing_shift + 4));
  162. pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
  163. }
  164. }
  165. spin_unlock_irqrestore(&atiixp_lock, flags);
  166. if (speed >= XFER_SW_DMA_0)
  167. pio = atiixp_dma_2_pio(speed);
  168. else
  169. pio = speed - XFER_PIO_0;
  170. atiixp_tuneproc(drive, pio);
  171. return ide_config_drive_speed(drive, speed);
  172. }
  173. /**
  174. * atiixp_dma_check - set up an IDE device
  175. * @drive: IDE drive to configure
  176. *
  177. * Set up the ATIIXP interface for the best available speed on this
  178. * interface, preferring DMA to PIO.
  179. */
  180. static int atiixp_dma_check(ide_drive_t *drive)
  181. {
  182. u8 tspeed, speed;
  183. drive->init_speed = 0;
  184. if (ide_tune_dma(drive))
  185. return 0;
  186. if (ide_use_fast_pio(drive)) {
  187. tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
  188. speed = atiixp_dma_2_pio(XFER_PIO_0 + tspeed) + XFER_PIO_0;
  189. atiixp_speedproc(drive, speed);
  190. }
  191. return -1;
  192. }
  193. /**
  194. * init_hwif_atiixp - fill in the hwif for the ATIIXP
  195. * @hwif: IDE interface
  196. *
  197. * Set up the ide_hwif_t for the ATIIXP interface according to the
  198. * capabilities of the hardware.
  199. */
  200. static void __devinit init_hwif_atiixp(ide_hwif_t *hwif)
  201. {
  202. u8 udma_mode = 0;
  203. u8 ch = hwif->channel;
  204. struct pci_dev *pdev = hwif->pci_dev;
  205. if (!hwif->irq)
  206. hwif->irq = ch ? 15 : 14;
  207. hwif->autodma = 0;
  208. hwif->tuneproc = &atiixp_tuneproc;
  209. hwif->speedproc = &atiixp_speedproc;
  210. hwif->drives[0].autotune = 1;
  211. hwif->drives[1].autotune = 1;
  212. if (!hwif->dma_base)
  213. return;
  214. hwif->atapi_dma = 1;
  215. hwif->ultra_mask = 0x3f;
  216. hwif->mwdma_mask = 0x06;
  217. hwif->swdma_mask = 0x04;
  218. pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
  219. if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
  220. hwif->udma_four = 1;
  221. else
  222. hwif->udma_four = 0;
  223. hwif->dma_host_on = &atiixp_dma_host_on;
  224. hwif->dma_host_off = &atiixp_dma_host_off;
  225. hwif->ide_dma_check = &atiixp_dma_check;
  226. if (!noautodma)
  227. hwif->autodma = 1;
  228. hwif->drives[1].autodma = hwif->autodma;
  229. hwif->drives[0].autodma = hwif->autodma;
  230. }
  231. static ide_pci_device_t atiixp_pci_info[] __devinitdata = {
  232. { /* 0 */
  233. .name = "ATIIXP",
  234. .init_hwif = init_hwif_atiixp,
  235. .channels = 2,
  236. .autodma = AUTODMA,
  237. .enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
  238. .bootable = ON_BOARD,
  239. },{ /* 1 */
  240. .name = "SB600_PATA",
  241. .init_hwif = init_hwif_atiixp,
  242. .channels = 1,
  243. .autodma = AUTODMA,
  244. .enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
  245. .bootable = ON_BOARD,
  246. },
  247. };
  248. /**
  249. * atiixp_init_one - called when a ATIIXP is found
  250. * @dev: the atiixp device
  251. * @id: the matching pci id
  252. *
  253. * Called when the PCI registration layer (or the IDE initialization)
  254. * finds a device matching our IDE device tables.
  255. */
  256. static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  257. {
  258. return ide_setup_pci_device(dev, &atiixp_pci_info[id->driver_data]);
  259. }
  260. static struct pci_device_id atiixp_pci_tbl[] = {
  261. { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  262. { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  263. { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  264. { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
  265. { 0, },
  266. };
  267. MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
  268. static struct pci_driver driver = {
  269. .name = "ATIIXP_IDE",
  270. .id_table = atiixp_pci_tbl,
  271. .probe = atiixp_init_one,
  272. };
  273. static int __init atiixp_ide_init(void)
  274. {
  275. return ide_pci_register_driver(&driver);
  276. }
  277. module_init(atiixp_ide_init);
  278. MODULE_AUTHOR("HUI YU");
  279. MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
  280. MODULE_LICENSE("GPL");