omap_wdt.c 9.0 KB

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  1. /*
  2. * linux/drivers/char/watchdog/omap_wdt.c
  3. *
  4. * Watchdog driver for the TI OMAP 16xx & 24xx 32KHz (non-secure) watchdog
  5. *
  6. * Author: MontaVista Software, Inc.
  7. * <gdavis@mvista.com> or <source@mvista.com>
  8. *
  9. * 2003 (c) MontaVista Software, Inc. This file is licensed under the
  10. * terms of the GNU General Public License version 2. This program is
  11. * licensed "as is" without any warranty of any kind, whether express
  12. * or implied.
  13. *
  14. * History:
  15. *
  16. * 20030527: George G. Davis <gdavis@mvista.com>
  17. * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
  18. * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
  19. * Based on SoftDog driver by Alan Cox <alan@redhat.com>
  20. *
  21. * Copyright (c) 2004 Texas Instruments.
  22. * 1. Modified to support OMAP1610 32-KHz watchdog timer
  23. * 2. Ported to 2.6 kernel
  24. *
  25. * Copyright (c) 2005 David Brownell
  26. * Use the driver model and standard identifiers; handle bigger timeouts.
  27. */
  28. #include <linux/module.h>
  29. #include <linux/types.h>
  30. #include <linux/kernel.h>
  31. #include <linux/fs.h>
  32. #include <linux/mm.h>
  33. #include <linux/miscdevice.h>
  34. #include <linux/watchdog.h>
  35. #include <linux/reboot.h>
  36. #include <linux/init.h>
  37. #include <linux/err.h>
  38. #include <linux/platform_device.h>
  39. #include <linux/moduleparam.h>
  40. #include <linux/clk.h>
  41. #include <asm/io.h>
  42. #include <asm/uaccess.h>
  43. #include <asm/hardware.h>
  44. #include <asm/bitops.h>
  45. #include <asm/arch/prcm.h>
  46. #include "omap_wdt.h"
  47. static unsigned timer_margin;
  48. module_param(timer_margin, uint, 0);
  49. MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
  50. static int omap_wdt_users;
  51. static struct clk *armwdt_ck = NULL;
  52. static struct clk *mpu_wdt_ick = NULL;
  53. static struct clk *mpu_wdt_fck = NULL;
  54. static unsigned int wdt_trgr_pattern = 0x1234;
  55. static void omap_wdt_ping(void)
  56. {
  57. /* wait for posted write to complete */
  58. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
  59. cpu_relax();
  60. wdt_trgr_pattern = ~wdt_trgr_pattern;
  61. omap_writel(wdt_trgr_pattern, (OMAP_WATCHDOG_TGR));
  62. /* wait for posted write to complete */
  63. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
  64. cpu_relax();
  65. /* reloaded WCRR from WLDR */
  66. }
  67. static void omap_wdt_enable(void)
  68. {
  69. /* Sequence to enable the watchdog */
  70. omap_writel(0xBBBB, OMAP_WATCHDOG_SPR);
  71. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
  72. cpu_relax();
  73. omap_writel(0x4444, OMAP_WATCHDOG_SPR);
  74. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
  75. cpu_relax();
  76. }
  77. static void omap_wdt_disable(void)
  78. {
  79. /* sequence required to disable watchdog */
  80. omap_writel(0xAAAA, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  81. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
  82. cpu_relax();
  83. omap_writel(0x5555, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  84. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
  85. cpu_relax();
  86. }
  87. static void omap_wdt_adjust_timeout(unsigned new_timeout)
  88. {
  89. if (new_timeout < TIMER_MARGIN_MIN)
  90. new_timeout = TIMER_MARGIN_DEFAULT;
  91. if (new_timeout > TIMER_MARGIN_MAX)
  92. new_timeout = TIMER_MARGIN_MAX;
  93. timer_margin = new_timeout;
  94. }
  95. static void omap_wdt_set_timeout(void)
  96. {
  97. u32 pre_margin = GET_WLDR_VAL(timer_margin);
  98. /* just count up at 32 KHz */
  99. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
  100. cpu_relax();
  101. omap_writel(pre_margin, OMAP_WATCHDOG_LDR);
  102. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
  103. cpu_relax();
  104. }
  105. /*
  106. * Allow only one task to hold it open
  107. */
  108. static int omap_wdt_open(struct inode *inode, struct file *file)
  109. {
  110. if (test_and_set_bit(1, (unsigned long *)&omap_wdt_users))
  111. return -EBUSY;
  112. if (cpu_is_omap16xx())
  113. clk_enable(armwdt_ck); /* Enable the clock */
  114. if (cpu_is_omap24xx()) {
  115. clk_enable(mpu_wdt_ick); /* Enable the interface clock */
  116. clk_enable(mpu_wdt_fck); /* Enable the functional clock */
  117. }
  118. /* initialize prescaler */
  119. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
  120. cpu_relax();
  121. omap_writel((1 << 5) | (PTV << 2), OMAP_WATCHDOG_CNTRL);
  122. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
  123. cpu_relax();
  124. omap_wdt_set_timeout();
  125. omap_wdt_enable();
  126. return 0;
  127. }
  128. static int omap_wdt_release(struct inode *inode, struct file *file)
  129. {
  130. /*
  131. * Shut off the timer unless NOWAYOUT is defined.
  132. */
  133. #ifndef CONFIG_WATCHDOG_NOWAYOUT
  134. omap_wdt_disable();
  135. if (cpu_is_omap16xx()) {
  136. clk_disable(armwdt_ck); /* Disable the clock */
  137. clk_put(armwdt_ck);
  138. armwdt_ck = NULL;
  139. }
  140. if (cpu_is_omap24xx()) {
  141. clk_disable(mpu_wdt_ick); /* Disable the clock */
  142. clk_disable(mpu_wdt_fck); /* Disable the clock */
  143. clk_put(mpu_wdt_ick);
  144. clk_put(mpu_wdt_fck);
  145. mpu_wdt_ick = NULL;
  146. mpu_wdt_fck = NULL;
  147. }
  148. #else
  149. printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
  150. #endif
  151. omap_wdt_users = 0;
  152. return 0;
  153. }
  154. static ssize_t
  155. omap_wdt_write(struct file *file, const char __user *data,
  156. size_t len, loff_t *ppos)
  157. {
  158. /* Refresh LOAD_TIME. */
  159. if (len)
  160. omap_wdt_ping();
  161. return len;
  162. }
  163. static int
  164. omap_wdt_ioctl(struct inode *inode, struct file *file,
  165. unsigned int cmd, unsigned long arg)
  166. {
  167. int new_margin;
  168. static struct watchdog_info ident = {
  169. .identity = "OMAP Watchdog",
  170. .options = WDIOF_SETTIMEOUT,
  171. .firmware_version = 0,
  172. };
  173. switch (cmd) {
  174. default:
  175. return -ENOIOCTLCMD;
  176. case WDIOC_GETSUPPORT:
  177. return copy_to_user((struct watchdog_info __user *)arg, &ident,
  178. sizeof(ident));
  179. case WDIOC_GETSTATUS:
  180. return put_user(0, (int __user *)arg);
  181. case WDIOC_GETBOOTSTATUS:
  182. if (cpu_is_omap16xx())
  183. return put_user(omap_readw(ARM_SYSST),
  184. (int __user *)arg);
  185. if (cpu_is_omap24xx())
  186. return put_user(omap_prcm_get_reset_sources(),
  187. (int __user *)arg);
  188. case WDIOC_KEEPALIVE:
  189. omap_wdt_ping();
  190. return 0;
  191. case WDIOC_SETTIMEOUT:
  192. if (get_user(new_margin, (int __user *)arg))
  193. return -EFAULT;
  194. omap_wdt_adjust_timeout(new_margin);
  195. omap_wdt_disable();
  196. omap_wdt_set_timeout();
  197. omap_wdt_enable();
  198. omap_wdt_ping();
  199. /* Fall */
  200. case WDIOC_GETTIMEOUT:
  201. return put_user(timer_margin, (int __user *)arg);
  202. }
  203. }
  204. static const struct file_operations omap_wdt_fops = {
  205. .owner = THIS_MODULE,
  206. .write = omap_wdt_write,
  207. .ioctl = omap_wdt_ioctl,
  208. .open = omap_wdt_open,
  209. .release = omap_wdt_release,
  210. };
  211. static struct miscdevice omap_wdt_miscdev = {
  212. .minor = WATCHDOG_MINOR,
  213. .name = "watchdog",
  214. .fops = &omap_wdt_fops
  215. };
  216. static int __init omap_wdt_probe(struct platform_device *pdev)
  217. {
  218. struct resource *res, *mem;
  219. int ret;
  220. /* reserve static register mappings */
  221. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  222. if (!res)
  223. return -ENOENT;
  224. mem = request_mem_region(res->start, res->end - res->start + 1,
  225. pdev->name);
  226. if (mem == NULL)
  227. return -EBUSY;
  228. platform_set_drvdata(pdev, mem);
  229. omap_wdt_users = 0;
  230. if (cpu_is_omap16xx()) {
  231. armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
  232. if (IS_ERR(armwdt_ck)) {
  233. ret = PTR_ERR(armwdt_ck);
  234. armwdt_ck = NULL;
  235. goto fail;
  236. }
  237. }
  238. if (cpu_is_omap24xx()) {
  239. mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
  240. if (IS_ERR(mpu_wdt_ick)) {
  241. ret = PTR_ERR(mpu_wdt_ick);
  242. mpu_wdt_ick = NULL;
  243. goto fail;
  244. }
  245. mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
  246. if (IS_ERR(mpu_wdt_fck)) {
  247. ret = PTR_ERR(mpu_wdt_fck);
  248. mpu_wdt_fck = NULL;
  249. goto fail;
  250. }
  251. }
  252. omap_wdt_disable();
  253. omap_wdt_adjust_timeout(timer_margin);
  254. omap_wdt_miscdev.parent = &pdev->dev;
  255. ret = misc_register(&omap_wdt_miscdev);
  256. if (ret)
  257. goto fail;
  258. pr_info("OMAP Watchdog Timer: initial timeout %d sec\n", timer_margin);
  259. /* autogate OCP interface clock */
  260. omap_writel(0x01, OMAP_WATCHDOG_SYS_CONFIG);
  261. return 0;
  262. fail:
  263. if (armwdt_ck)
  264. clk_put(armwdt_ck);
  265. if (mpu_wdt_ick)
  266. clk_put(mpu_wdt_ick);
  267. if (mpu_wdt_fck)
  268. clk_put(mpu_wdt_fck);
  269. release_resource(mem);
  270. return ret;
  271. }
  272. static void omap_wdt_shutdown(struct platform_device *pdev)
  273. {
  274. omap_wdt_disable();
  275. }
  276. static int omap_wdt_remove(struct platform_device *pdev)
  277. {
  278. struct resource *mem = platform_get_drvdata(pdev);
  279. misc_deregister(&omap_wdt_miscdev);
  280. release_resource(mem);
  281. if (armwdt_ck)
  282. clk_put(armwdt_ck);
  283. if (mpu_wdt_ick)
  284. clk_put(mpu_wdt_ick);
  285. if (mpu_wdt_fck)
  286. clk_put(mpu_wdt_fck);
  287. return 0;
  288. }
  289. #ifdef CONFIG_PM
  290. /* REVISIT ... not clear this is the best way to handle system suspend; and
  291. * it's very inappropriate for selective device suspend (e.g. suspending this
  292. * through sysfs rather than by stopping the watchdog daemon). Also, this
  293. * may not play well enough with NOWAYOUT...
  294. */
  295. static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
  296. {
  297. if (omap_wdt_users)
  298. omap_wdt_disable();
  299. return 0;
  300. }
  301. static int omap_wdt_resume(struct platform_device *pdev)
  302. {
  303. if (omap_wdt_users) {
  304. omap_wdt_enable();
  305. omap_wdt_ping();
  306. }
  307. return 0;
  308. }
  309. #else
  310. #define omap_wdt_suspend NULL
  311. #define omap_wdt_resume NULL
  312. #endif
  313. static struct platform_driver omap_wdt_driver = {
  314. .probe = omap_wdt_probe,
  315. .remove = omap_wdt_remove,
  316. .shutdown = omap_wdt_shutdown,
  317. .suspend = omap_wdt_suspend,
  318. .resume = omap_wdt_resume,
  319. .driver = {
  320. .owner = THIS_MODULE,
  321. .name = "omap_wdt",
  322. },
  323. };
  324. static int __init omap_wdt_init(void)
  325. {
  326. return platform_driver_register(&omap_wdt_driver);
  327. }
  328. static void __exit omap_wdt_exit(void)
  329. {
  330. platform_driver_unregister(&omap_wdt_driver);
  331. }
  332. module_init(omap_wdt_init);
  333. module_exit(omap_wdt_exit);
  334. MODULE_AUTHOR("George G. Davis");
  335. MODULE_LICENSE("GPL");
  336. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);