tlb_64.c 6.4 KB

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  1. /*
  2. * This file contains the routines for flushing entries from the
  3. * TLB and MMU hash table.
  4. *
  5. * Derived from arch/ppc64/mm/init.c:
  6. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  7. *
  8. * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  9. * and Cort Dougan (PReP) (cort@cs.nmt.edu)
  10. * Copyright (C) 1996 Paul Mackerras
  11. * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
  12. *
  13. * Derived from "arch/i386/mm/init.c"
  14. * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
  15. *
  16. * Dave Engebretsen <engebret@us.ibm.com>
  17. * Rework for PPC64 port.
  18. *
  19. * This program is free software; you can redistribute it and/or
  20. * modify it under the terms of the GNU General Public License
  21. * as published by the Free Software Foundation; either version
  22. * 2 of the License, or (at your option) any later version.
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/mm.h>
  26. #include <linux/init.h>
  27. #include <linux/percpu.h>
  28. #include <linux/hardirq.h>
  29. #include <asm/pgalloc.h>
  30. #include <asm/tlbflush.h>
  31. #include <asm/tlb.h>
  32. #include <asm/bug.h>
  33. DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
  34. /* This is declared as we are using the more or less generic
  35. * include/asm-powerpc/tlb.h file -- tgall
  36. */
  37. DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  38. DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
  39. unsigned long pte_freelist_forced_free;
  40. struct pte_freelist_batch
  41. {
  42. struct rcu_head rcu;
  43. unsigned int index;
  44. pgtable_free_t tables[0];
  45. };
  46. DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
  47. unsigned long pte_freelist_forced_free;
  48. #define PTE_FREELIST_SIZE \
  49. ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
  50. / sizeof(pgtable_free_t))
  51. #ifdef CONFIG_SMP
  52. static void pte_free_smp_sync(void *arg)
  53. {
  54. /* Do nothing, just ensure we sync with all CPUs */
  55. }
  56. #endif
  57. /* This is only called when we are critically out of memory
  58. * (and fail to get a page in pte_free_tlb).
  59. */
  60. static void pgtable_free_now(pgtable_free_t pgf)
  61. {
  62. pte_freelist_forced_free++;
  63. smp_call_function(pte_free_smp_sync, NULL, 0, 1);
  64. pgtable_free(pgf);
  65. }
  66. static void pte_free_rcu_callback(struct rcu_head *head)
  67. {
  68. struct pte_freelist_batch *batch =
  69. container_of(head, struct pte_freelist_batch, rcu);
  70. unsigned int i;
  71. for (i = 0; i < batch->index; i++)
  72. pgtable_free(batch->tables[i]);
  73. free_page((unsigned long)batch);
  74. }
  75. static void pte_free_submit(struct pte_freelist_batch *batch)
  76. {
  77. INIT_RCU_HEAD(&batch->rcu);
  78. call_rcu(&batch->rcu, pte_free_rcu_callback);
  79. }
  80. void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf)
  81. {
  82. /* This is safe since tlb_gather_mmu has disabled preemption */
  83. cpumask_t local_cpumask = cpumask_of_cpu(smp_processor_id());
  84. struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
  85. if (atomic_read(&tlb->mm->mm_users) < 2 ||
  86. cpus_equal(tlb->mm->cpu_vm_mask, local_cpumask)) {
  87. pgtable_free(pgf);
  88. return;
  89. }
  90. if (*batchp == NULL) {
  91. *batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC);
  92. if (*batchp == NULL) {
  93. pgtable_free_now(pgf);
  94. return;
  95. }
  96. (*batchp)->index = 0;
  97. }
  98. (*batchp)->tables[(*batchp)->index++] = pgf;
  99. if ((*batchp)->index == PTE_FREELIST_SIZE) {
  100. pte_free_submit(*batchp);
  101. *batchp = NULL;
  102. }
  103. }
  104. /*
  105. * A linux PTE was changed and the corresponding hash table entry
  106. * neesd to be flushed. This function will either perform the flush
  107. * immediately or will batch it up if the current CPU has an active
  108. * batch on it.
  109. *
  110. * Must be called from within some kind of spinlock/non-preempt region...
  111. */
  112. void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
  113. pte_t *ptep, unsigned long pte, int huge)
  114. {
  115. struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
  116. unsigned long vsid, vaddr;
  117. unsigned int psize;
  118. real_pte_t rpte;
  119. int i;
  120. i = batch->index;
  121. /* We mask the address for the base page size. Huge pages will
  122. * have applied their own masking already
  123. */
  124. addr &= PAGE_MASK;
  125. /* Get page size (maybe move back to caller).
  126. *
  127. * NOTE: when using special 64K mappings in 4K environment like
  128. * for SPEs, we obtain the page size from the slice, which thus
  129. * must still exist (and thus the VMA not reused) at the time
  130. * of this call
  131. */
  132. if (huge) {
  133. #ifdef CONFIG_HUGETLB_PAGE
  134. psize = mmu_huge_psize;
  135. #else
  136. BUG();
  137. psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
  138. #endif
  139. } else
  140. psize = pte_pagesize_index(mm, addr, pte);
  141. /* Build full vaddr */
  142. if (!is_kernel_addr(addr)) {
  143. vsid = get_vsid(mm->context.id, addr);
  144. WARN_ON(vsid == 0);
  145. } else
  146. vsid = get_kernel_vsid(addr);
  147. vaddr = (vsid << 28 ) | (addr & 0x0fffffff);
  148. rpte = __real_pte(__pte(pte), ptep);
  149. /*
  150. * Check if we have an active batch on this CPU. If not, just
  151. * flush now and return. For now, we don global invalidates
  152. * in that case, might be worth testing the mm cpu mask though
  153. * and decide to use local invalidates instead...
  154. */
  155. if (!batch->active) {
  156. flush_hash_page(vaddr, rpte, psize, 0);
  157. return;
  158. }
  159. /*
  160. * This can happen when we are in the middle of a TLB batch and
  161. * we encounter memory pressure (eg copy_page_range when it tries
  162. * to allocate a new pte). If we have to reclaim memory and end
  163. * up scanning and resetting referenced bits then our batch context
  164. * will change mid stream.
  165. *
  166. * We also need to ensure only one page size is present in a given
  167. * batch
  168. */
  169. if (i != 0 && (mm != batch->mm || batch->psize != psize)) {
  170. __flush_tlb_pending(batch);
  171. i = 0;
  172. }
  173. if (i == 0) {
  174. batch->mm = mm;
  175. batch->psize = psize;
  176. }
  177. batch->pte[i] = rpte;
  178. batch->vaddr[i] = vaddr;
  179. batch->index = ++i;
  180. if (i >= PPC64_TLB_BATCH_NR)
  181. __flush_tlb_pending(batch);
  182. }
  183. /*
  184. * This function is called when terminating an mmu batch or when a batch
  185. * is full. It will perform the flush of all the entries currently stored
  186. * in a batch.
  187. *
  188. * Must be called from within some kind of spinlock/non-preempt region...
  189. */
  190. void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
  191. {
  192. cpumask_t tmp;
  193. int i, local = 0;
  194. i = batch->index;
  195. tmp = cpumask_of_cpu(smp_processor_id());
  196. if (cpus_equal(batch->mm->cpu_vm_mask, tmp))
  197. local = 1;
  198. if (i == 1)
  199. flush_hash_page(batch->vaddr[0], batch->pte[0],
  200. batch->psize, local);
  201. else
  202. flush_hash_range(i, local);
  203. batch->index = 0;
  204. }
  205. void pte_free_finish(void)
  206. {
  207. /* This is safe since tlb_gather_mmu has disabled preemption */
  208. struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
  209. if (*batchp == NULL)
  210. return;
  211. pte_free_submit(*batchp);
  212. *batchp = NULL;
  213. }