hash_low_32.S 17 KB

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  1. /*
  2. * $Id: hashtable.S,v 1.6 1999/10/08 01:56:15 paulus Exp $
  3. *
  4. * PowerPC version
  5. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  6. * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
  7. * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  8. * Adapted for Power Macintosh by Paul Mackerras.
  9. * Low-level exception handlers and MMU support
  10. * rewritten by Paul Mackerras.
  11. * Copyright (C) 1996 Paul Mackerras.
  12. *
  13. * This file contains low-level assembler routines for managing
  14. * the PowerPC MMU hash table. (PPC 8xx processors don't use a
  15. * hash table, so this file is not used on them.)
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License
  19. * as published by the Free Software Foundation; either version
  20. * 2 of the License, or (at your option) any later version.
  21. *
  22. */
  23. #include <asm/reg.h>
  24. #include <asm/page.h>
  25. #include <asm/pgtable.h>
  26. #include <asm/cputable.h>
  27. #include <asm/ppc_asm.h>
  28. #include <asm/thread_info.h>
  29. #include <asm/asm-offsets.h>
  30. #ifdef CONFIG_SMP
  31. .comm mmu_hash_lock,4
  32. #endif /* CONFIG_SMP */
  33. /*
  34. * Sync CPUs with hash_page taking & releasing the hash
  35. * table lock
  36. */
  37. #ifdef CONFIG_SMP
  38. .text
  39. _GLOBAL(hash_page_sync)
  40. lis r8,mmu_hash_lock@h
  41. ori r8,r8,mmu_hash_lock@l
  42. lis r0,0x0fff
  43. b 10f
  44. 11: lwz r6,0(r8)
  45. cmpwi 0,r6,0
  46. bne 11b
  47. 10: lwarx r6,0,r8
  48. cmpwi 0,r6,0
  49. bne- 11b
  50. stwcx. r0,0,r8
  51. bne- 10b
  52. isync
  53. eieio
  54. li r0,0
  55. stw r0,0(r8)
  56. blr
  57. #endif
  58. /*
  59. * Load a PTE into the hash table, if possible.
  60. * The address is in r4, and r3 contains an access flag:
  61. * _PAGE_RW (0x400) if a write.
  62. * r9 contains the SRR1 value, from which we use the MSR_PR bit.
  63. * SPRG3 contains the physical address of the current task's thread.
  64. *
  65. * Returns to the caller if the access is illegal or there is no
  66. * mapping for the address. Otherwise it places an appropriate PTE
  67. * in the hash table and returns from the exception.
  68. * Uses r0, r3 - r8, ctr, lr.
  69. */
  70. .text
  71. _GLOBAL(hash_page)
  72. tophys(r7,0) /* gets -KERNELBASE into r7 */
  73. #ifdef CONFIG_SMP
  74. addis r8,r7,mmu_hash_lock@h
  75. ori r8,r8,mmu_hash_lock@l
  76. lis r0,0x0fff
  77. b 10f
  78. 11: lwz r6,0(r8)
  79. cmpwi 0,r6,0
  80. bne 11b
  81. 10: lwarx r6,0,r8
  82. cmpwi 0,r6,0
  83. bne- 11b
  84. stwcx. r0,0,r8
  85. bne- 10b
  86. isync
  87. #endif
  88. /* Get PTE (linux-style) and check access */
  89. lis r0,KERNELBASE@h /* check if kernel address */
  90. cmplw 0,r4,r0
  91. mfspr r8,SPRN_SPRG3 /* current task's THREAD (phys) */
  92. ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
  93. lwz r5,PGDIR(r8) /* virt page-table root */
  94. blt+ 112f /* assume user more likely */
  95. lis r5,swapper_pg_dir@ha /* if kernel address, use */
  96. addi r5,r5,swapper_pg_dir@l /* kernel page table */
  97. rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
  98. 112: add r5,r5,r7 /* convert to phys addr */
  99. rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
  100. lwz r8,0(r5) /* get pmd entry */
  101. rlwinm. r8,r8,0,0,19 /* extract address of pte page */
  102. #ifdef CONFIG_SMP
  103. beq- hash_page_out /* return if no mapping */
  104. #else
  105. /* XXX it seems like the 601 will give a machine fault on the
  106. rfi if its alignment is wrong (bottom 4 bits of address are
  107. 8 or 0xc) and we have had a not-taken conditional branch
  108. to the address following the rfi. */
  109. beqlr-
  110. #endif
  111. rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */
  112. rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
  113. ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
  114. /*
  115. * Update the linux PTE atomically. We do the lwarx up-front
  116. * because almost always, there won't be a permission violation
  117. * and there won't already be an HPTE, and thus we will have
  118. * to update the PTE to set _PAGE_HASHPTE. -- paulus.
  119. */
  120. retry:
  121. lwarx r6,0,r8 /* get linux-style pte */
  122. andc. r5,r3,r6 /* check access & ~permission */
  123. #ifdef CONFIG_SMP
  124. bne- hash_page_out /* return if access not permitted */
  125. #else
  126. bnelr-
  127. #endif
  128. or r5,r0,r6 /* set accessed/dirty bits */
  129. stwcx. r5,0,r8 /* attempt to update PTE */
  130. bne- retry /* retry if someone got there first */
  131. mfsrin r3,r4 /* get segment reg for segment */
  132. mfctr r0
  133. stw r0,_CTR(r11)
  134. bl create_hpte /* add the hash table entry */
  135. #ifdef CONFIG_SMP
  136. eieio
  137. addis r8,r7,mmu_hash_lock@ha
  138. li r0,0
  139. stw r0,mmu_hash_lock@l(r8)
  140. #endif
  141. /* Return from the exception */
  142. lwz r5,_CTR(r11)
  143. mtctr r5
  144. lwz r0,GPR0(r11)
  145. lwz r7,GPR7(r11)
  146. lwz r8,GPR8(r11)
  147. b fast_exception_return
  148. #ifdef CONFIG_SMP
  149. hash_page_out:
  150. eieio
  151. addis r8,r7,mmu_hash_lock@ha
  152. li r0,0
  153. stw r0,mmu_hash_lock@l(r8)
  154. blr
  155. #endif /* CONFIG_SMP */
  156. /*
  157. * Add an entry for a particular page to the hash table.
  158. *
  159. * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval)
  160. *
  161. * We assume any necessary modifications to the pte (e.g. setting
  162. * the accessed bit) have already been done and that there is actually
  163. * a hash table in use (i.e. we're not on a 603).
  164. */
  165. _GLOBAL(add_hash_page)
  166. mflr r0
  167. stw r0,4(r1)
  168. /* Convert context and va to VSID */
  169. mulli r3,r3,897*16 /* multiply context by context skew */
  170. rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
  171. mulli r0,r0,0x111 /* multiply by ESID skew */
  172. add r3,r3,r0 /* note create_hpte trims to 24 bits */
  173. #ifdef CONFIG_SMP
  174. rlwinm r8,r1,0,0,18 /* use cpu number to make tag */
  175. lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */
  176. oris r8,r8,12
  177. #endif /* CONFIG_SMP */
  178. /*
  179. * We disable interrupts here, even on UP, because we don't
  180. * want to race with hash_page, and because we want the
  181. * _PAGE_HASHPTE bit to be a reliable indication of whether
  182. * the HPTE exists (or at least whether one did once).
  183. * We also turn off the MMU for data accesses so that we
  184. * we can't take a hash table miss (assuming the code is
  185. * covered by a BAT). -- paulus
  186. */
  187. mfmsr r10
  188. SYNC
  189. rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
  190. rlwinm r0,r0,0,28,26 /* clear MSR_DR */
  191. mtmsr r0
  192. SYNC_601
  193. isync
  194. tophys(r7,0)
  195. #ifdef CONFIG_SMP
  196. addis r9,r7,mmu_hash_lock@ha
  197. addi r9,r9,mmu_hash_lock@l
  198. 10: lwarx r0,0,r9 /* take the mmu_hash_lock */
  199. cmpi 0,r0,0
  200. bne- 11f
  201. stwcx. r8,0,r9
  202. beq+ 12f
  203. 11: lwz r0,0(r9)
  204. cmpi 0,r0,0
  205. beq 10b
  206. b 11b
  207. 12: isync
  208. #endif
  209. /*
  210. * Fetch the linux pte and test and set _PAGE_HASHPTE atomically.
  211. * If _PAGE_HASHPTE was already set, we don't replace the existing
  212. * HPTE, so we just unlock and return.
  213. */
  214. mr r8,r5
  215. rlwimi r8,r4,22,20,29
  216. 1: lwarx r6,0,r8
  217. andi. r0,r6,_PAGE_HASHPTE
  218. bne 9f /* if HASHPTE already set, done */
  219. ori r5,r6,_PAGE_HASHPTE
  220. stwcx. r5,0,r8
  221. bne- 1b
  222. bl create_hpte
  223. 9:
  224. #ifdef CONFIG_SMP
  225. eieio
  226. li r0,0
  227. stw r0,0(r9) /* clear mmu_hash_lock */
  228. #endif
  229. /* reenable interrupts and DR */
  230. mtmsr r10
  231. SYNC_601
  232. isync
  233. lwz r0,4(r1)
  234. mtlr r0
  235. blr
  236. /*
  237. * This routine adds a hardware PTE to the hash table.
  238. * It is designed to be called with the MMU either on or off.
  239. * r3 contains the VSID, r4 contains the virtual address,
  240. * r5 contains the linux PTE, r6 contains the old value of the
  241. * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the
  242. * offset to be added to addresses (0 if the MMU is on,
  243. * -KERNELBASE if it is off).
  244. * On SMP, the caller should have the mmu_hash_lock held.
  245. * We assume that the caller has (or will) set the _PAGE_HASHPTE
  246. * bit in the linux PTE in memory. The value passed in r6 should
  247. * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set
  248. * this routine will skip the search for an existing HPTE.
  249. * This procedure modifies r0, r3 - r6, r8, cr0.
  250. * -- paulus.
  251. *
  252. * For speed, 4 of the instructions get patched once the size and
  253. * physical address of the hash table are known. These definitions
  254. * of Hash_base and Hash_bits below are just an example.
  255. */
  256. Hash_base = 0xc0180000
  257. Hash_bits = 12 /* e.g. 256kB hash table */
  258. Hash_msk = (((1 << Hash_bits) - 1) * 64)
  259. /* defines for the PTE format for 32-bit PPCs */
  260. #define PTE_SIZE 8
  261. #define PTEG_SIZE 64
  262. #define LG_PTEG_SIZE 6
  263. #define LDPTEu lwzu
  264. #define LDPTE lwz
  265. #define STPTE stw
  266. #define CMPPTE cmpw
  267. #define PTE_H 0x40
  268. #define PTE_V 0x80000000
  269. #define TST_V(r) rlwinm. r,r,0,0,0
  270. #define SET_V(r) oris r,r,PTE_V@h
  271. #define CLR_V(r,t) rlwinm r,r,0,1,31
  272. #define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1)
  273. #define HASH_RIGHT 31-LG_PTEG_SIZE
  274. _GLOBAL(create_hpte)
  275. /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
  276. rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */
  277. rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
  278. and r8,r8,r0 /* writable if _RW & _DIRTY */
  279. rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */
  280. rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
  281. ori r8,r8,0xe14 /* clear out reserved bits and M */
  282. andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */
  283. BEGIN_FTR_SECTION
  284. ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */
  285. END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
  286. /* Construct the high word of the PPC-style PTE (r5) */
  287. rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
  288. rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */
  289. SET_V(r5) /* set V (valid) bit */
  290. /* Get the address of the primary PTE group in the hash table (r3) */
  291. _GLOBAL(hash_page_patch_A)
  292. addis r0,r7,Hash_base@h /* base address of hash table */
  293. rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
  294. rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
  295. xor r3,r3,r0 /* make primary hash */
  296. li r0,8 /* PTEs/group */
  297. /*
  298. * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search
  299. * if it is clear, meaning that the HPTE isn't there already...
  300. */
  301. andi. r6,r6,_PAGE_HASHPTE
  302. beq+ 10f /* no PTE: go look for an empty slot */
  303. tlbie r4
  304. addis r4,r7,htab_hash_searches@ha
  305. lwz r6,htab_hash_searches@l(r4)
  306. addi r6,r6,1 /* count how many searches we do */
  307. stw r6,htab_hash_searches@l(r4)
  308. /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
  309. mtctr r0
  310. addi r4,r3,-PTE_SIZE
  311. 1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */
  312. CMPPTE 0,r6,r5
  313. bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
  314. beq+ found_slot
  315. /* Search the secondary PTEG for a matching PTE */
  316. ori r5,r5,PTE_H /* set H (secondary hash) bit */
  317. _GLOBAL(hash_page_patch_B)
  318. xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
  319. xori r4,r4,(-PTEG_SIZE & 0xffff)
  320. addi r4,r4,-PTE_SIZE
  321. mtctr r0
  322. 2: LDPTEu r6,PTE_SIZE(r4)
  323. CMPPTE 0,r6,r5
  324. bdnzf 2,2b
  325. beq+ found_slot
  326. xori r5,r5,PTE_H /* clear H bit again */
  327. /* Search the primary PTEG for an empty slot */
  328. 10: mtctr r0
  329. addi r4,r3,-PTE_SIZE /* search primary PTEG */
  330. 1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */
  331. TST_V(r6) /* test valid bit */
  332. bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
  333. beq+ found_empty
  334. /* update counter of times that the primary PTEG is full */
  335. addis r4,r7,primary_pteg_full@ha
  336. lwz r6,primary_pteg_full@l(r4)
  337. addi r6,r6,1
  338. stw r6,primary_pteg_full@l(r4)
  339. /* Search the secondary PTEG for an empty slot */
  340. ori r5,r5,PTE_H /* set H (secondary hash) bit */
  341. _GLOBAL(hash_page_patch_C)
  342. xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
  343. xori r4,r4,(-PTEG_SIZE & 0xffff)
  344. addi r4,r4,-PTE_SIZE
  345. mtctr r0
  346. 2: LDPTEu r6,PTE_SIZE(r4)
  347. TST_V(r6)
  348. bdnzf 2,2b
  349. beq+ found_empty
  350. xori r5,r5,PTE_H /* clear H bit again */
  351. /*
  352. * Choose an arbitrary slot in the primary PTEG to overwrite.
  353. * Since both the primary and secondary PTEGs are full, and we
  354. * have no information that the PTEs in the primary PTEG are
  355. * more important or useful than those in the secondary PTEG,
  356. * and we know there is a definite (although small) speed
  357. * advantage to putting the PTE in the primary PTEG, we always
  358. * put the PTE in the primary PTEG.
  359. *
  360. * In addition, we skip any slot that is mapping kernel text in
  361. * order to avoid a deadlock when not using BAT mappings if
  362. * trying to hash in the kernel hash code itself after it has
  363. * already taken the hash table lock. This works in conjunction
  364. * with pre-faulting of the kernel text.
  365. *
  366. * If the hash table bucket is full of kernel text entries, we'll
  367. * lockup here but that shouldn't happen
  368. */
  369. 1: addis r4,r7,next_slot@ha /* get next evict slot */
  370. lwz r6,next_slot@l(r4)
  371. addi r6,r6,PTE_SIZE /* search for candidate */
  372. andi. r6,r6,7*PTE_SIZE
  373. stw r6,next_slot@l(r4)
  374. add r4,r3,r6
  375. LDPTE r0,PTE_SIZE/2(r4) /* get PTE second word */
  376. clrrwi r0,r0,12
  377. lis r6,etext@h
  378. ori r6,r6,etext@l /* get etext */
  379. tophys(r6,r6)
  380. cmpl cr0,r0,r6 /* compare and try again */
  381. blt 1b
  382. #ifndef CONFIG_SMP
  383. /* Store PTE in PTEG */
  384. found_empty:
  385. STPTE r5,0(r4)
  386. found_slot:
  387. STPTE r8,PTE_SIZE/2(r4)
  388. #else /* CONFIG_SMP */
  389. /*
  390. * Between the tlbie above and updating the hash table entry below,
  391. * another CPU could read the hash table entry and put it in its TLB.
  392. * There are 3 cases:
  393. * 1. using an empty slot
  394. * 2. updating an earlier entry to change permissions (i.e. enable write)
  395. * 3. taking over the PTE for an unrelated address
  396. *
  397. * In each case it doesn't really matter if the other CPUs have the old
  398. * PTE in their TLB. So we don't need to bother with another tlbie here,
  399. * which is convenient as we've overwritten the register that had the
  400. * address. :-) The tlbie above is mainly to make sure that this CPU comes
  401. * and gets the new PTE from the hash table.
  402. *
  403. * We do however have to make sure that the PTE is never in an invalid
  404. * state with the V bit set.
  405. */
  406. found_empty:
  407. found_slot:
  408. CLR_V(r5,r0) /* clear V (valid) bit in PTE */
  409. STPTE r5,0(r4)
  410. sync
  411. TLBSYNC
  412. STPTE r8,PTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */
  413. sync
  414. SET_V(r5)
  415. STPTE r5,0(r4) /* finally set V bit in PTE */
  416. #endif /* CONFIG_SMP */
  417. sync /* make sure pte updates get to memory */
  418. blr
  419. .comm next_slot,4
  420. .comm primary_pteg_full,4
  421. .comm htab_hash_searches,4
  422. /*
  423. * Flush the entry for a particular page from the hash table.
  424. *
  425. * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval,
  426. * int count)
  427. *
  428. * We assume that there is a hash table in use (Hash != 0).
  429. */
  430. _GLOBAL(flush_hash_pages)
  431. tophys(r7,0)
  432. /*
  433. * We disable interrupts here, even on UP, because we want
  434. * the _PAGE_HASHPTE bit to be a reliable indication of
  435. * whether the HPTE exists (or at least whether one did once).
  436. * We also turn off the MMU for data accesses so that we
  437. * we can't take a hash table miss (assuming the code is
  438. * covered by a BAT). -- paulus
  439. */
  440. mfmsr r10
  441. SYNC
  442. rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
  443. rlwinm r0,r0,0,28,26 /* clear MSR_DR */
  444. mtmsr r0
  445. SYNC_601
  446. isync
  447. /* First find a PTE in the range that has _PAGE_HASHPTE set */
  448. rlwimi r5,r4,22,20,29
  449. 1: lwz r0,0(r5)
  450. cmpwi cr1,r6,1
  451. andi. r0,r0,_PAGE_HASHPTE
  452. bne 2f
  453. ble cr1,19f
  454. addi r4,r4,0x1000
  455. addi r5,r5,4
  456. addi r6,r6,-1
  457. b 1b
  458. /* Convert context and va to VSID */
  459. 2: mulli r3,r3,897*16 /* multiply context by context skew */
  460. rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
  461. mulli r0,r0,0x111 /* multiply by ESID skew */
  462. add r3,r3,r0 /* note code below trims to 24 bits */
  463. /* Construct the high word of the PPC-style PTE (r11) */
  464. rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
  465. rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */
  466. SET_V(r11) /* set V (valid) bit */
  467. #ifdef CONFIG_SMP
  468. addis r9,r7,mmu_hash_lock@ha
  469. addi r9,r9,mmu_hash_lock@l
  470. rlwinm r8,r1,0,0,18
  471. add r8,r8,r7
  472. lwz r8,TI_CPU(r8)
  473. oris r8,r8,9
  474. 10: lwarx r0,0,r9
  475. cmpi 0,r0,0
  476. bne- 11f
  477. stwcx. r8,0,r9
  478. beq+ 12f
  479. 11: lwz r0,0(r9)
  480. cmpi 0,r0,0
  481. beq 10b
  482. b 11b
  483. 12: isync
  484. #endif
  485. /*
  486. * Check the _PAGE_HASHPTE bit in the linux PTE. If it is
  487. * already clear, we're done (for this pte). If not,
  488. * clear it (atomically) and proceed. -- paulus.
  489. */
  490. 33: lwarx r8,0,r5 /* fetch the pte */
  491. andi. r0,r8,_PAGE_HASHPTE
  492. beq 8f /* done if HASHPTE is already clear */
  493. rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */
  494. stwcx. r8,0,r5 /* update the pte */
  495. bne- 33b
  496. /* Get the address of the primary PTE group in the hash table (r3) */
  497. _GLOBAL(flush_hash_patch_A)
  498. addis r8,r7,Hash_base@h /* base address of hash table */
  499. rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
  500. rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
  501. xor r8,r0,r8 /* make primary hash */
  502. /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
  503. li r0,8 /* PTEs/group */
  504. mtctr r0
  505. addi r12,r8,-PTE_SIZE
  506. 1: LDPTEu r0,PTE_SIZE(r12) /* get next PTE */
  507. CMPPTE 0,r0,r11
  508. bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
  509. beq+ 3f
  510. /* Search the secondary PTEG for a matching PTE */
  511. ori r11,r11,PTE_H /* set H (secondary hash) bit */
  512. li r0,8 /* PTEs/group */
  513. _GLOBAL(flush_hash_patch_B)
  514. xoris r12,r8,Hash_msk>>16 /* compute secondary hash */
  515. xori r12,r12,(-PTEG_SIZE & 0xffff)
  516. addi r12,r12,-PTE_SIZE
  517. mtctr r0
  518. 2: LDPTEu r0,PTE_SIZE(r12)
  519. CMPPTE 0,r0,r11
  520. bdnzf 2,2b
  521. xori r11,r11,PTE_H /* clear H again */
  522. bne- 4f /* should rarely fail to find it */
  523. 3: li r0,0
  524. STPTE r0,0(r12) /* invalidate entry */
  525. 4: sync
  526. tlbie r4 /* in hw tlb too */
  527. sync
  528. 8: ble cr1,9f /* if all ptes checked */
  529. 81: addi r6,r6,-1
  530. addi r5,r5,4 /* advance to next pte */
  531. addi r4,r4,0x1000
  532. lwz r0,0(r5) /* check next pte */
  533. cmpwi cr1,r6,1
  534. andi. r0,r0,_PAGE_HASHPTE
  535. bne 33b
  536. bgt cr1,81b
  537. 9:
  538. #ifdef CONFIG_SMP
  539. TLBSYNC
  540. li r0,0
  541. stw r0,0(r9) /* clear mmu_hash_lock */
  542. #endif
  543. 19: mtmsr r10
  544. SYNC_601
  545. isync
  546. blr