prpmc2800.dts 7.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315
  1. /* Device Tree Source for Motorola PrPMC2800
  2. *
  3. * Author: Mark A. Greer <mgreer@mvista.com>
  4. *
  5. * 2007 (c) MontaVista, Software, Inc. This file is licensed under
  6. * the terms of the GNU General Public License version 2. This program
  7. * is licensed "as is" without any warranty of any kind, whether express
  8. * or implied.
  9. *
  10. * Property values that are labeled as "Default" will be updated by bootwrapper
  11. * if it can determine the exact PrPMC type.
  12. *
  13. * To build:
  14. * dtc -I dts -O asm -o prpmc2800.S -b 0 prpmc2800.dts
  15. * dtc -I dts -O dtb -o prpmc2800.dtb -b 0 prpmc2800.dts
  16. */
  17. / {
  18. #address-cells = <1>;
  19. #size-cells = <1>;
  20. model = "PrPMC280/PrPMC2800"; /* Default */
  21. compatible = "motorola,PrPMC2800";
  22. coherency-off;
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,7447 {
  27. device_type = "cpu";
  28. reg = <0>;
  29. clock-frequency = <2bb0b140>; /* Default (733 MHz) */
  30. bus-frequency = <7f28155>; /* 133.333333 MHz */
  31. timebase-frequency = <1fca055>; /* 33.333333 MHz */
  32. i-cache-line-size = <20>;
  33. d-cache-line-size = <20>;
  34. i-cache-size = <8000>;
  35. d-cache-size = <8000>;
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <00000000 20000000>; /* Default (512MB) */
  41. };
  42. mv64x60@f1000000 { /* Marvell Discovery */
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. #interrupt-cells = <1>;
  46. model = "mv64360"; /* Default */
  47. compatible = "marvell,mv64x60";
  48. clock-frequency = <7f28155>; /* 133.333333 MHz */
  49. reg = <f1000000 00010000>;
  50. virtual-reg = <f1000000>;
  51. ranges = <88000000 88000000 01000000 /* PCI 0 I/O Space */
  52. 80000000 80000000 08000000 /* PCI 0 MEM Space */
  53. a0000000 a0000000 04000000 /* User FLASH */
  54. 00000000 f1000000 00010000 /* Bridge's regs */
  55. f2000000 f2000000 00040000>; /* Integrated SRAM */
  56. flash@a0000000 {
  57. device_type = "rom";
  58. compatible = "direct-mapped";
  59. reg = <a0000000 4000000>; /* Default (64MB) */
  60. probe-type = "CFI";
  61. bank-width = <4>;
  62. partitions = <00000000 00100000 /* RO */
  63. 00100000 00040001 /* RW */
  64. 00140000 00400000 /* RO */
  65. 00540000 039c0000 /* RO */
  66. 03f00000 00100000>; /* RO */
  67. partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B";
  68. };
  69. mdio {
  70. #address-cells = <1>;
  71. #size-cells = <0>;
  72. device_type = "mdio";
  73. compatible = "marvell,mv64x60-mdio";
  74. ethernet-phy@1 {
  75. device_type = "ethernet-phy";
  76. compatible = "broadcom,bcm5421";
  77. interrupts = <4c>; /* GPP 12 */
  78. interrupt-parent = <&/mv64x60/pic>;
  79. reg = <1>;
  80. };
  81. ethernet-phy@3 {
  82. device_type = "ethernet-phy";
  83. compatible = "broadcom,bcm5421";
  84. interrupts = <4c>; /* GPP 12 */
  85. interrupt-parent = <&/mv64x60/pic>;
  86. reg = <3>;
  87. };
  88. };
  89. ethernet@2000 {
  90. reg = <2000 2000>;
  91. eth0 {
  92. device_type = "network";
  93. compatible = "marvell,mv64x60-eth";
  94. block-index = <0>;
  95. interrupts = <20>;
  96. interrupt-parent = <&/mv64x60/pic>;
  97. phy = <&/mv64x60/mdio/ethernet-phy@1>;
  98. local-mac-address = [ 00 00 00 00 00 00 ];
  99. };
  100. eth1 {
  101. device_type = "network";
  102. compatible = "marvell,mv64x60-eth";
  103. block-index = <1>;
  104. interrupts = <21>;
  105. interrupt-parent = <&/mv64x60/pic>;
  106. phy = <&/mv64x60/mdio/ethernet-phy@3>;
  107. local-mac-address = [ 00 00 00 00 00 00 ];
  108. };
  109. };
  110. sdma@4000 {
  111. device_type = "dma";
  112. compatible = "marvell,mv64x60-sdma";
  113. reg = <4000 c18>;
  114. virtual-reg = <f1004000>;
  115. interrupt-base = <0>;
  116. interrupts = <24>;
  117. interrupt-parent = <&/mv64x60/pic>;
  118. };
  119. sdma@6000 {
  120. device_type = "dma";
  121. compatible = "marvell,mv64x60-sdma";
  122. reg = <6000 c18>;
  123. virtual-reg = <f1006000>;
  124. interrupt-base = <0>;
  125. interrupts = <26>;
  126. interrupt-parent = <&/mv64x60/pic>;
  127. };
  128. brg@b200 {
  129. compatible = "marvell,mv64x60-brg";
  130. reg = <b200 8>;
  131. clock-src = <8>;
  132. clock-frequency = <7ed6b40>;
  133. current-speed = <2580>;
  134. bcr = <0>;
  135. };
  136. brg@b208 {
  137. compatible = "marvell,mv64x60-brg";
  138. reg = <b208 8>;
  139. clock-src = <8>;
  140. clock-frequency = <7ed6b40>;
  141. current-speed = <2580>;
  142. bcr = <0>;
  143. };
  144. cunit@f200 {
  145. reg = <f200 200>;
  146. };
  147. mpscrouting@b400 {
  148. reg = <b400 c>;
  149. };
  150. mpscintr@b800 {
  151. reg = <b800 100>;
  152. virtual-reg = <f100b800>;
  153. };
  154. mpsc@8000 {
  155. device_type = "serial";
  156. compatible = "marvell,mpsc";
  157. reg = <8000 38>;
  158. virtual-reg = <f1008000>;
  159. sdma = <&/mv64x60/sdma@4000>;
  160. brg = <&/mv64x60/brg@b200>;
  161. cunit = <&/mv64x60/cunit@f200>;
  162. mpscrouting = <&/mv64x60/mpscrouting@b400>;
  163. mpscintr = <&/mv64x60/mpscintr@b800>;
  164. block-index = <0>;
  165. max_idle = <28>;
  166. chr_1 = <0>;
  167. chr_2 = <0>;
  168. chr_10 = <3>;
  169. mpcr = <0>;
  170. interrupts = <28>;
  171. interrupt-parent = <&/mv64x60/pic>;
  172. };
  173. mpsc@9000 {
  174. device_type = "serial";
  175. compatible = "marvell,mpsc";
  176. reg = <9000 38>;
  177. virtual-reg = <f1009000>;
  178. sdma = <&/mv64x60/sdma@6000>;
  179. brg = <&/mv64x60/brg@b208>;
  180. cunit = <&/mv64x60/cunit@f200>;
  181. mpscrouting = <&/mv64x60/mpscrouting@b400>;
  182. mpscintr = <&/mv64x60/mpscintr@b800>;
  183. block-index = <1>;
  184. max_idle = <28>;
  185. chr_1 = <0>;
  186. chr_2 = <0>;
  187. chr_10 = <3>;
  188. mpcr = <0>;
  189. interrupts = <2a>;
  190. interrupt-parent = <&/mv64x60/pic>;
  191. };
  192. i2c@c000 {
  193. device_type = "i2c";
  194. compatible = "marvell,mv64x60-i2c";
  195. reg = <c000 20>;
  196. virtual-reg = <f100c000>;
  197. freq_m = <8>;
  198. freq_n = <3>;
  199. timeout = <3e8>; /* 1000 = 1 second */
  200. retries = <1>;
  201. interrupts = <25>;
  202. interrupt-parent = <&/mv64x60/pic>;
  203. };
  204. pic {
  205. #interrupt-cells = <1>;
  206. #address-cells = <0>;
  207. compatible = "marvell,mv64x60-pic";
  208. reg = <0000 88>;
  209. interrupt-controller;
  210. };
  211. mpp@f000 {
  212. compatible = "marvell,mv64x60-mpp";
  213. reg = <f000 10>;
  214. };
  215. gpp@f100 {
  216. compatible = "marvell,mv64x60-gpp";
  217. reg = <f100 20>;
  218. };
  219. pci@80000000 {
  220. #address-cells = <3>;
  221. #size-cells = <2>;
  222. #interrupt-cells = <1>;
  223. device_type = "pci";
  224. compatible = "marvell,mv64x60-pci";
  225. reg = <0cf8 8>;
  226. ranges = <01000000 0 0 88000000 0 01000000
  227. 02000000 0 80000000 80000000 0 08000000>;
  228. bus-range = <0 ff>;
  229. clock-frequency = <3EF1480>;
  230. interrupt-pci-iack = <0c34>;
  231. interrupt-parent = <&/mv64x60/pic>;
  232. interrupt-map-mask = <f800 0 0 7>;
  233. interrupt-map = <
  234. /* IDSEL 0x0a */
  235. 5000 0 0 1 &/mv64x60/pic 50
  236. 5000 0 0 2 &/mv64x60/pic 51
  237. 5000 0 0 3 &/mv64x60/pic 5b
  238. 5000 0 0 4 &/mv64x60/pic 5d
  239. /* IDSEL 0x0b */
  240. 5800 0 0 1 &/mv64x60/pic 5b
  241. 5800 0 0 2 &/mv64x60/pic 5d
  242. 5800 0 0 3 &/mv64x60/pic 50
  243. 5800 0 0 4 &/mv64x60/pic 51
  244. /* IDSEL 0x0c */
  245. 6000 0 0 1 &/mv64x60/pic 5b
  246. 6000 0 0 2 &/mv64x60/pic 5d
  247. 6000 0 0 3 &/mv64x60/pic 50
  248. 6000 0 0 4 &/mv64x60/pic 51
  249. /* IDSEL 0x0d */
  250. 6800 0 0 1 &/mv64x60/pic 5d
  251. 6800 0 0 2 &/mv64x60/pic 50
  252. 6800 0 0 3 &/mv64x60/pic 51
  253. 6800 0 0 4 &/mv64x60/pic 5b
  254. >;
  255. };
  256. cpu-error@0070 {
  257. compatible = "marvell,mv64x60-cpu-error";
  258. reg = <0070 10 0128 28>;
  259. interrupts = <03>;
  260. interrupt-parent = <&/mv64x60/pic>;
  261. };
  262. sram-ctrl@0380 {
  263. compatible = "marvell,mv64x60-sram-ctrl";
  264. reg = <0380 80>;
  265. interrupts = <0d>;
  266. interrupt-parent = <&/mv64x60/pic>;
  267. };
  268. pci-error@1d40 {
  269. compatible = "marvell,mv64x60-pci-error";
  270. reg = <1d40 40 0c28 4>;
  271. interrupts = <0c>;
  272. interrupt-parent = <&/mv64x60/pic>;
  273. };
  274. mem-ctrl@1400 {
  275. compatible = "marvell,mv64x60-mem-ctrl";
  276. reg = <1400 60>;
  277. interrupts = <11>;
  278. interrupt-parent = <&/mv64x60/pic>;
  279. };
  280. };
  281. chosen {
  282. bootargs = "ip=on console=ttyMM0";
  283. linux,stdout-path = "/mv64x60@f1000000/mpsc@8000";
  284. };
  285. };