a20r.c 4.5 KB

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  1. /*
  2. * A20R specific code
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
  9. */
  10. #include <linux/init.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/serial_8250.h>
  14. #include <asm/sni.h>
  15. #include <asm/time.h>
  16. #include <asm/ds1216.h>
  17. #define PORT(_base,_irq) \
  18. { \
  19. .iobase = _base, \
  20. .irq = _irq, \
  21. .uartclk = 1843200, \
  22. .iotype = UPIO_PORT, \
  23. .flags = UPF_BOOT_AUTOCONF, \
  24. }
  25. static struct plat_serial8250_port a20r_data[] = {
  26. PORT(0x3f8, 4),
  27. PORT(0x2f8, 3),
  28. { },
  29. };
  30. static struct platform_device a20r_serial8250_device = {
  31. .name = "serial8250",
  32. .id = PLAT8250_DEV_PLATFORM,
  33. .dev = {
  34. .platform_data = a20r_data,
  35. },
  36. };
  37. static struct resource snirm_82596_rsrc[] = {
  38. {
  39. .start = 0xb8000000,
  40. .end = 0xb8000004,
  41. .flags = IORESOURCE_MEM
  42. },
  43. {
  44. .start = 0xb8010000,
  45. .end = 0xb8010004,
  46. .flags = IORESOURCE_MEM
  47. },
  48. {
  49. .start = 0xbff00000,
  50. .end = 0xbff00020,
  51. .flags = IORESOURCE_MEM
  52. },
  53. {
  54. .start = 22,
  55. .end = 22,
  56. .flags = IORESOURCE_IRQ
  57. },
  58. {
  59. .flags = 0x01 /* 16bit mpu port access */
  60. }
  61. };
  62. static struct platform_device snirm_82596_pdev = {
  63. .name = "snirm_82596",
  64. .num_resources = ARRAY_SIZE(snirm_82596_rsrc),
  65. .resource = snirm_82596_rsrc
  66. };
  67. static struct resource snirm_53c710_rsrc[] = {
  68. {
  69. .start = 0xb9000000,
  70. .end = 0xb90fffff,
  71. .flags = IORESOURCE_MEM
  72. },
  73. {
  74. .start = 19,
  75. .end = 19,
  76. .flags = IORESOURCE_IRQ
  77. }
  78. };
  79. static struct platform_device snirm_53c710_pdev = {
  80. .name = "snirm_53c710",
  81. .num_resources = ARRAY_SIZE(snirm_53c710_rsrc),
  82. .resource = snirm_53c710_rsrc
  83. };
  84. static struct resource sc26xx_rsrc[] = {
  85. {
  86. .start = 0xbc070000,
  87. .end = 0xbc0700ff,
  88. .flags = IORESOURCE_MEM
  89. },
  90. {
  91. .start = 20,
  92. .end = 20,
  93. .flags = IORESOURCE_IRQ
  94. }
  95. };
  96. static struct platform_device sc26xx_pdev = {
  97. .name = "SC26xx",
  98. .num_resources = ARRAY_SIZE(sc26xx_rsrc),
  99. .resource = sc26xx_rsrc
  100. };
  101. static u32 a20r_ack_hwint(void)
  102. {
  103. u32 status = read_c0_status();
  104. write_c0_status (status | 0x00010000);
  105. asm volatile(
  106. " .set push \n"
  107. " .set noat \n"
  108. " .set noreorder \n"
  109. " lw $1, 0(%0) \n"
  110. " sb $0, 0(%1) \n"
  111. " sync \n"
  112. " lb %1, 0(%1) \n"
  113. " b 1f \n"
  114. " ori %1, $1, 2 \n"
  115. " .align 8 \n"
  116. "1: \n"
  117. " nop \n"
  118. " sw %1, 0(%0) \n"
  119. " sync \n"
  120. " li %1, 0x20 \n"
  121. "2: \n"
  122. " nop \n"
  123. " bnez %1,2b \n"
  124. " addiu %1, -1 \n"
  125. " sw $1, 0(%0) \n"
  126. " sync \n"
  127. ".set pop \n"
  128. :
  129. : "Jr" (PCIMT_UCONF), "Jr" (0xbc000000));
  130. write_c0_status(status);
  131. return status;
  132. }
  133. static inline void unmask_a20r_irq(unsigned int irq)
  134. {
  135. set_c0_status(0x100 << (irq - SNI_A20R_IRQ_BASE));
  136. irq_enable_hazard();
  137. }
  138. static inline void mask_a20r_irq(unsigned int irq)
  139. {
  140. clear_c0_status(0x100 << (irq - SNI_A20R_IRQ_BASE));
  141. irq_disable_hazard();
  142. }
  143. static void end_a20r_irq(unsigned int irq)
  144. {
  145. if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
  146. a20r_ack_hwint();
  147. unmask_a20r_irq(irq);
  148. }
  149. }
  150. static struct irq_chip a20r_irq_type = {
  151. .typename = "A20R",
  152. .ack = mask_a20r_irq,
  153. .mask = mask_a20r_irq,
  154. .mask_ack = mask_a20r_irq,
  155. .unmask = unmask_a20r_irq,
  156. .end = end_a20r_irq,
  157. };
  158. /*
  159. * hwint 0 receive all interrupts
  160. */
  161. static void a20r_hwint(void)
  162. {
  163. u32 cause, status;
  164. int irq;
  165. clear_c0_status (IE_IRQ0);
  166. status = a20r_ack_hwint();
  167. cause = read_c0_cause();
  168. irq = ffs(((cause & status) >> 8) & 0xf8);
  169. if (likely(irq > 0))
  170. do_IRQ(SNI_A20R_IRQ_BASE + irq - 1);
  171. set_c0_status(IE_IRQ0);
  172. }
  173. void __init sni_a20r_irq_init(void)
  174. {
  175. int i;
  176. for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
  177. set_irq_chip(i, &a20r_irq_type);
  178. sni_hwint = a20r_hwint;
  179. change_c0_status(ST0_IM, IE_IRQ0);
  180. setup_irq (SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);
  181. }
  182. void sni_a20r_init(void)
  183. {
  184. ds1216_base = (volatile unsigned char *) SNI_DS1216_A20R_BASE;
  185. rtc_mips_get_time = ds1216_get_cmos_time;
  186. }
  187. static int __init snirm_a20r_setup_devinit(void)
  188. {
  189. switch (sni_brd_type) {
  190. case SNI_BRD_TOWER_OASIC:
  191. case SNI_BRD_MINITOWER:
  192. platform_device_register(&snirm_82596_pdev);
  193. platform_device_register(&snirm_53c710_pdev);
  194. platform_device_register(&sc26xx_pdev);
  195. platform_device_register(&a20r_serial8250_device);
  196. break;
  197. }
  198. return 0;
  199. }
  200. device_initcall(snirm_a20r_setup_devinit);