pcibr_provider.c 6.5 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2001-2004, 2006 Silicon Graphics, Inc. All rights reserved.
  7. */
  8. #include <linux/interrupt.h>
  9. #include <linux/types.h>
  10. #include <linux/pci.h>
  11. #include <asm/sn/addrs.h>
  12. #include <asm/sn/geo.h>
  13. #include <asm/sn/pcibr_provider.h>
  14. #include <asm/sn/pcibus_provider_defs.h>
  15. #include <asm/sn/pcidev.h>
  16. #include <asm/sn/sn_sal.h>
  17. #include <asm/sn/sn2/sn_hwperf.h>
  18. #include "xtalk/xwidgetdev.h"
  19. #include "xtalk/hubdev.h"
  20. int
  21. sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp,
  22. char **ssdt)
  23. {
  24. struct ia64_sal_retval ret_stuff;
  25. u64 busnum;
  26. u64 segment;
  27. ret_stuff.status = 0;
  28. ret_stuff.v0 = 0;
  29. segment = soft->pbi_buscommon.bs_persist_segment;
  30. busnum = soft->pbi_buscommon.bs_persist_busnum;
  31. SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_ENABLE, segment,
  32. busnum, (u64) device, (u64) resp, (u64)ia64_tpa(ssdt),
  33. 0, 0);
  34. return (int)ret_stuff.v0;
  35. }
  36. int
  37. sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
  38. void *resp)
  39. {
  40. struct ia64_sal_retval ret_stuff;
  41. u64 busnum;
  42. u64 segment;
  43. ret_stuff.status = 0;
  44. ret_stuff.v0 = 0;
  45. segment = soft->pbi_buscommon.bs_persist_segment;
  46. busnum = soft->pbi_buscommon.bs_persist_busnum;
  47. SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_SLOT_DISABLE,
  48. segment, busnum, (u64) device, (u64) action,
  49. (u64) resp, 0, 0);
  50. return (int)ret_stuff.v0;
  51. }
  52. static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
  53. {
  54. struct ia64_sal_retval ret_stuff;
  55. u64 busnum;
  56. int segment;
  57. ret_stuff.status = 0;
  58. ret_stuff.v0 = 0;
  59. segment = soft->pbi_buscommon.bs_persist_segment;
  60. busnum = soft->pbi_buscommon.bs_persist_busnum;
  61. SAL_CALL_NOLOCK(ret_stuff,
  62. (u64) SN_SAL_IOIF_ERROR_INTERRUPT,
  63. (u64) segment, (u64) busnum, 0, 0, 0, 0, 0);
  64. return (int)ret_stuff.v0;
  65. }
  66. u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus)
  67. {
  68. s64 rc;
  69. u16 ioboard;
  70. nasid_t nasid = NASID_GET(SN_PCIBUS_BUSSOFT(pci_bus)->bs_base);
  71. rc = ia64_sn_sysctl_ioboard_get(nasid, &ioboard);
  72. if (rc) {
  73. printk(KERN_WARNING "ia64_sn_sysctl_ioboard_get failed: %ld\n",
  74. rc);
  75. return 0;
  76. }
  77. return ioboard;
  78. }
  79. /*
  80. * PCI Bridge Error interrupt handler. Gets invoked whenever a PCI
  81. * bridge sends an error interrupt.
  82. */
  83. static irqreturn_t
  84. pcibr_error_intr_handler(int irq, void *arg)
  85. {
  86. struct pcibus_info *soft = (struct pcibus_info *)arg;
  87. if (sal_pcibr_error_interrupt(soft) < 0) {
  88. panic("pcibr_error_intr_handler(): Fatal Bridge Error");
  89. }
  90. return IRQ_HANDLED;
  91. }
  92. void *
  93. pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
  94. {
  95. int nasid, cnode, j;
  96. struct hubdev_info *hubdev_info;
  97. struct pcibus_info *soft;
  98. struct sn_flush_device_kernel *sn_flush_device_kernel;
  99. struct sn_flush_device_common *common;
  100. if (! IS_PCI_BRIDGE_ASIC(prom_bussoft->bs_asic_type)) {
  101. return NULL;
  102. }
  103. /*
  104. * Allocate kernel bus soft and copy from prom.
  105. */
  106. soft = kmalloc(sizeof(struct pcibus_info), GFP_KERNEL);
  107. if (!soft) {
  108. return NULL;
  109. }
  110. memcpy(soft, prom_bussoft, sizeof(struct pcibus_info));
  111. soft->pbi_buscommon.bs_base =
  112. (((u64) soft->pbi_buscommon.
  113. bs_base << 4) >> 4) | __IA64_UNCACHED_OFFSET;
  114. spin_lock_init(&soft->pbi_lock);
  115. /*
  116. * register the bridge's error interrupt handler
  117. */
  118. if (request_irq(SGI_PCIASIC_ERROR, pcibr_error_intr_handler,
  119. IRQF_SHARED, "PCIBR error", (void *)(soft))) {
  120. printk(KERN_WARNING
  121. "pcibr cannot allocate interrupt for error handler\n");
  122. }
  123. /*
  124. * Update the Bridge with the "kernel" pagesize
  125. */
  126. if (PAGE_SIZE < 16384) {
  127. pcireg_control_bit_clr(soft, PCIBR_CTRL_PAGE_SIZE);
  128. } else {
  129. pcireg_control_bit_set(soft, PCIBR_CTRL_PAGE_SIZE);
  130. }
  131. nasid = NASID_GET(soft->pbi_buscommon.bs_base);
  132. cnode = nasid_to_cnodeid(nasid);
  133. hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
  134. if (hubdev_info->hdi_flush_nasid_list.widget_p) {
  135. sn_flush_device_kernel = hubdev_info->hdi_flush_nasid_list.
  136. widget_p[(int)soft->pbi_buscommon.bs_xid];
  137. if (sn_flush_device_kernel) {
  138. for (j = 0; j < DEV_PER_WIDGET;
  139. j++, sn_flush_device_kernel++) {
  140. common = sn_flush_device_kernel->common;
  141. if (common->sfdl_slot == -1)
  142. continue;
  143. if ((common->sfdl_persistent_segment ==
  144. soft->pbi_buscommon.bs_persist_segment) &&
  145. (common->sfdl_persistent_busnum ==
  146. soft->pbi_buscommon.bs_persist_busnum))
  147. common->sfdl_pcibus_info =
  148. soft;
  149. }
  150. }
  151. }
  152. /* Setup the PMU ATE map */
  153. soft->pbi_int_ate_resource.lowest_free_index = 0;
  154. soft->pbi_int_ate_resource.ate =
  155. kzalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL);
  156. if (!soft->pbi_int_ate_resource.ate) {
  157. kfree(soft);
  158. return NULL;
  159. }
  160. return soft;
  161. }
  162. void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info)
  163. {
  164. struct pcidev_info *pcidev_info;
  165. struct pcibus_info *pcibus_info;
  166. int bit = sn_irq_info->irq_int_bit;
  167. if (! sn_irq_info->irq_bridge)
  168. return;
  169. pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
  170. if (pcidev_info) {
  171. pcibus_info =
  172. (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
  173. pdi_pcibus_info;
  174. pcireg_force_intr_set(pcibus_info, bit);
  175. }
  176. }
  177. void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
  178. {
  179. struct pcidev_info *pcidev_info;
  180. struct pcibus_info *pcibus_info;
  181. int bit = sn_irq_info->irq_int_bit;
  182. u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;
  183. pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
  184. if (pcidev_info) {
  185. pcibus_info =
  186. (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
  187. pdi_pcibus_info;
  188. /* Disable the device's IRQ */
  189. pcireg_intr_enable_bit_clr(pcibus_info, (1 << bit));
  190. /* Change the device's IRQ */
  191. pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);
  192. /* Re-enable the device's IRQ */
  193. pcireg_intr_enable_bit_set(pcibus_info, (1 << bit));
  194. pcibr_force_interrupt(sn_irq_info);
  195. }
  196. }
  197. /*
  198. * Provider entries for PIC/CP
  199. */
  200. struct sn_pcibus_provider pcibr_provider = {
  201. .dma_map = pcibr_dma_map,
  202. .dma_map_consistent = pcibr_dma_map_consistent,
  203. .dma_unmap = pcibr_dma_unmap,
  204. .bus_fixup = pcibr_bus_fixup,
  205. .force_interrupt = pcibr_force_interrupt,
  206. .target_interrupt = pcibr_target_interrupt
  207. };
  208. int
  209. pcibr_init_provider(void)
  210. {
  211. sn_pci_provider[PCIIO_ASIC_TYPE_PIC] = &pcibr_provider;
  212. sn_pci_provider[PCIIO_ASIC_TYPE_TIOCP] = &pcibr_provider;
  213. return 0;
  214. }
  215. EXPORT_SYMBOL_GPL(sal_pcibr_slot_enable);
  216. EXPORT_SYMBOL_GPL(sal_pcibr_slot_disable);
  217. EXPORT_SYMBOL_GPL(sn_ioboard_to_pci_bus);