at91sam9263.dtsi 17 KB

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  1. /*
  2. * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
  3. *
  4. * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5. *
  6. * Licensed under GPLv2 only.
  7. */
  8. #include "skeleton.dtsi"
  9. #include <dt-bindings/pinctrl/at91.h>
  10. #include <dt-bindings/interrupt-controller/irq.h>
  11. #include <dt-bindings/gpio/gpio.h>
  12. / {
  13. model = "Atmel AT91SAM9263 family SoC";
  14. compatible = "atmel,at91sam9263";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. gpio0 = &pioA;
  22. gpio1 = &pioB;
  23. gpio2 = &pioC;
  24. gpio3 = &pioD;
  25. gpio4 = &pioE;
  26. tcb0 = &tcb0;
  27. i2c0 = &i2c0;
  28. ssc0 = &ssc0;
  29. ssc1 = &ssc1;
  30. };
  31. cpus {
  32. cpu@0 {
  33. compatible = "arm,arm926ejs";
  34. };
  35. };
  36. memory {
  37. reg = <0x20000000 0x08000000>;
  38. };
  39. ahb {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. ranges;
  44. apb {
  45. compatible = "simple-bus";
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. ranges;
  49. aic: interrupt-controller@fffff000 {
  50. #interrupt-cells = <3>;
  51. compatible = "atmel,at91rm9200-aic";
  52. interrupt-controller;
  53. reg = <0xfffff000 0x200>;
  54. atmel,external-irqs = <30 31>;
  55. };
  56. pmc: pmc@fffffc00 {
  57. compatible = "atmel,at91rm9200-pmc";
  58. reg = <0xfffffc00 0x100>;
  59. };
  60. ramc: ramc@ffffe200 {
  61. compatible = "atmel,at91sam9260-sdramc";
  62. reg = <0xffffe200 0x200
  63. 0xffffe800 0x200>;
  64. };
  65. pit: timer@fffffd30 {
  66. compatible = "atmel,at91sam9260-pit";
  67. reg = <0xfffffd30 0xf>;
  68. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  69. };
  70. tcb0: timer@fff7c000 {
  71. compatible = "atmel,at91rm9200-tcb";
  72. reg = <0xfff7c000 0x100>;
  73. interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
  74. };
  75. rstc@fffffd00 {
  76. compatible = "atmel,at91sam9260-rstc";
  77. reg = <0xfffffd00 0x10>;
  78. };
  79. shdwc@fffffd10 {
  80. compatible = "atmel,at91sam9260-shdwc";
  81. reg = <0xfffffd10 0x10>;
  82. };
  83. pinctrl@fffff200 {
  84. #address-cells = <1>;
  85. #size-cells = <1>;
  86. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  87. ranges = <0xfffff200 0xfffff200 0xa00>;
  88. atmel,mux-mask = <
  89. /* A B */
  90. 0xfffffffb 0xffffe07f /* pioA */
  91. 0x0007ffff 0x39072fff /* pioB */
  92. 0xffffffff 0x3ffffff8 /* pioC */
  93. 0xfffffbff 0xffffffff /* pioD */
  94. 0xffe00fff 0xfbfcff00 /* pioE */
  95. >;
  96. /* shared pinctrl settings */
  97. dbgu {
  98. pinctrl_dbgu: dbgu-0 {
  99. atmel,pins =
  100. <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */
  101. AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */
  102. };
  103. };
  104. usart0 {
  105. pinctrl_usart0: usart0-0 {
  106. atmel,pins =
  107. <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */
  108. AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
  109. };
  110. pinctrl_usart0_rts: usart0_rts-0 {
  111. atmel,pins =
  112. <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */
  113. };
  114. pinctrl_usart0_cts: usart0_cts-0 {
  115. atmel,pins =
  116. <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */
  117. };
  118. };
  119. usart1 {
  120. pinctrl_usart1: usart1-0 {
  121. atmel,pins =
  122. <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
  123. AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */
  124. };
  125. pinctrl_usart1_rts: usart1_rts-0 {
  126. atmel,pins =
  127. <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */
  128. };
  129. pinctrl_usart1_cts: usart1_cts-0 {
  130. atmel,pins =
  131. <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */
  132. };
  133. };
  134. usart2 {
  135. pinctrl_usart2: usart2-0 {
  136. atmel,pins =
  137. <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */
  138. AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */
  139. };
  140. pinctrl_usart2_rts: usart2_rts-0 {
  141. atmel,pins =
  142. <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */
  143. };
  144. pinctrl_usart2_cts: usart2_cts-0 {
  145. atmel,pins =
  146. <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */
  147. };
  148. };
  149. nand {
  150. pinctrl_nand: nand-0 {
  151. atmel,pins =
  152. <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/
  153. AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */
  154. };
  155. };
  156. macb {
  157. pinctrl_macb_rmii: macb_rmii-0 {
  158. atmel,pins =
  159. <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
  160. AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
  161. AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
  162. AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
  163. AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
  164. AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
  165. AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
  166. AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
  167. AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
  168. AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
  169. };
  170. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  171. atmel,pins =
  172. <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
  173. AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
  174. AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */
  175. AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */
  176. AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */
  177. AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
  178. AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
  179. AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */
  180. };
  181. };
  182. mmc0 {
  183. pinctrl_mmc0_clk: mmc0_clk-0 {
  184. atmel,pins =
  185. <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */
  186. };
  187. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  188. atmel,pins =
  189. <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
  190. AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */
  191. };
  192. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  193. atmel,pins =
  194. <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
  195. AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
  196. AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
  197. };
  198. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  199. atmel,pins =
  200. <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
  201. AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */
  202. };
  203. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  204. atmel,pins =
  205. <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
  206. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
  207. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
  208. };
  209. };
  210. mmc1 {
  211. pinctrl_mmc1_clk: mmc1_clk-0 {
  212. atmel,pins =
  213. <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
  214. };
  215. pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
  216. atmel,pins =
  217. <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
  218. AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */
  219. };
  220. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  221. atmel,pins =
  222. <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
  223. AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */
  224. AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */
  225. };
  226. pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
  227. atmel,pins =
  228. <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */
  229. AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */
  230. };
  231. pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
  232. atmel,pins =
  233. <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */
  234. AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
  235. AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */
  236. };
  237. };
  238. ssc0 {
  239. pinctrl_ssc0_tx: ssc0_tx-0 {
  240. atmel,pins =
  241. <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */
  242. AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */
  243. AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
  244. };
  245. pinctrl_ssc0_rx: ssc0_rx-0 {
  246. atmel,pins =
  247. <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */
  248. AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */
  249. AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */
  250. };
  251. };
  252. ssc1 {
  253. pinctrl_ssc1_tx: ssc1_tx-0 {
  254. atmel,pins =
  255. <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
  256. AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
  257. AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
  258. };
  259. pinctrl_ssc1_rx: ssc1_rx-0 {
  260. atmel,pins =
  261. <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
  262. AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
  263. AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
  264. };
  265. };
  266. spi0 {
  267. pinctrl_spi0: spi0-0 {
  268. atmel,pins =
  269. <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */
  270. AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */
  271. AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */
  272. };
  273. };
  274. spi1 {
  275. pinctrl_spi1: spi1-0 {
  276. atmel,pins =
  277. <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */
  278. AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */
  279. AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */
  280. };
  281. };
  282. tcb0 {
  283. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  284. atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  285. };
  286. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  287. atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  288. };
  289. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  290. atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  291. };
  292. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  293. atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  294. };
  295. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  296. atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  297. };
  298. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  299. atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  300. };
  301. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  302. atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  303. };
  304. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  305. atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  306. };
  307. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  308. atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  309. };
  310. };
  311. pioA: gpio@fffff200 {
  312. compatible = "atmel,at91rm9200-gpio";
  313. reg = <0xfffff200 0x200>;
  314. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  315. #gpio-cells = <2>;
  316. gpio-controller;
  317. interrupt-controller;
  318. #interrupt-cells = <2>;
  319. };
  320. pioB: gpio@fffff400 {
  321. compatible = "atmel,at91rm9200-gpio";
  322. reg = <0xfffff400 0x200>;
  323. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  324. #gpio-cells = <2>;
  325. gpio-controller;
  326. interrupt-controller;
  327. #interrupt-cells = <2>;
  328. };
  329. pioC: gpio@fffff600 {
  330. compatible = "atmel,at91rm9200-gpio";
  331. reg = <0xfffff600 0x200>;
  332. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  333. #gpio-cells = <2>;
  334. gpio-controller;
  335. interrupt-controller;
  336. #interrupt-cells = <2>;
  337. };
  338. pioD: gpio@fffff800 {
  339. compatible = "atmel,at91rm9200-gpio";
  340. reg = <0xfffff800 0x200>;
  341. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  342. #gpio-cells = <2>;
  343. gpio-controller;
  344. interrupt-controller;
  345. #interrupt-cells = <2>;
  346. };
  347. pioE: gpio@fffffa00 {
  348. compatible = "atmel,at91rm9200-gpio";
  349. reg = <0xfffffa00 0x200>;
  350. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  351. #gpio-cells = <2>;
  352. gpio-controller;
  353. interrupt-controller;
  354. #interrupt-cells = <2>;
  355. };
  356. };
  357. dbgu: serial@ffffee00 {
  358. compatible = "atmel,at91sam9260-usart";
  359. reg = <0xffffee00 0x200>;
  360. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  361. pinctrl-names = "default";
  362. pinctrl-0 = <&pinctrl_dbgu>;
  363. status = "disabled";
  364. };
  365. usart0: serial@fff8c000 {
  366. compatible = "atmel,at91sam9260-usart";
  367. reg = <0xfff8c000 0x200>;
  368. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  369. atmel,use-dma-rx;
  370. atmel,use-dma-tx;
  371. pinctrl-names = "default";
  372. pinctrl-0 = <&pinctrl_usart0>;
  373. status = "disabled";
  374. };
  375. usart1: serial@fff90000 {
  376. compatible = "atmel,at91sam9260-usart";
  377. reg = <0xfff90000 0x200>;
  378. interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
  379. atmel,use-dma-rx;
  380. atmel,use-dma-tx;
  381. pinctrl-names = "default";
  382. pinctrl-0 = <&pinctrl_usart1>;
  383. status = "disabled";
  384. };
  385. usart2: serial@fff94000 {
  386. compatible = "atmel,at91sam9260-usart";
  387. reg = <0xfff94000 0x200>;
  388. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
  389. atmel,use-dma-rx;
  390. atmel,use-dma-tx;
  391. pinctrl-names = "default";
  392. pinctrl-0 = <&pinctrl_usart2>;
  393. status = "disabled";
  394. };
  395. ssc0: ssc@fff98000 {
  396. compatible = "atmel,at91rm9200-ssc";
  397. reg = <0xfff98000 0x4000>;
  398. interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
  399. pinctrl-names = "default";
  400. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  401. status = "disabled";
  402. };
  403. ssc1: ssc@fff9c000 {
  404. compatible = "atmel,at91rm9200-ssc";
  405. reg = <0xfff9c000 0x4000>;
  406. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
  407. pinctrl-names = "default";
  408. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  409. status = "disabled";
  410. };
  411. macb0: ethernet@fffbc000 {
  412. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  413. reg = <0xfffbc000 0x100>;
  414. interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
  415. pinctrl-names = "default";
  416. pinctrl-0 = <&pinctrl_macb_rmii>;
  417. status = "disabled";
  418. };
  419. usb1: gadget@fff78000 {
  420. compatible = "atmel,at91rm9200-udc";
  421. reg = <0xfff78000 0x4000>;
  422. interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
  423. status = "disabled";
  424. };
  425. i2c0: i2c@fff88000 {
  426. compatible = "atmel,at91sam9263-i2c";
  427. reg = <0xfff88000 0x100>;
  428. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
  429. #address-cells = <1>;
  430. #size-cells = <0>;
  431. status = "disabled";
  432. };
  433. mmc0: mmc@fff80000 {
  434. compatible = "atmel,hsmci";
  435. reg = <0xfff80000 0x600>;
  436. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
  437. #address-cells = <1>;
  438. #size-cells = <0>;
  439. status = "disabled";
  440. };
  441. mmc1: mmc@fff84000 {
  442. compatible = "atmel,hsmci";
  443. reg = <0xfff84000 0x600>;
  444. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
  445. #address-cells = <1>;
  446. #size-cells = <0>;
  447. status = "disabled";
  448. };
  449. watchdog@fffffd40 {
  450. compatible = "atmel,at91sam9260-wdt";
  451. reg = <0xfffffd40 0x10>;
  452. status = "disabled";
  453. };
  454. spi0: spi@fffa4000 {
  455. #address-cells = <1>;
  456. #size-cells = <0>;
  457. compatible = "atmel,at91rm9200-spi";
  458. reg = <0xfffa4000 0x200>;
  459. interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
  460. pinctrl-names = "default";
  461. pinctrl-0 = <&pinctrl_spi0>;
  462. status = "disabled";
  463. };
  464. spi1: spi@fffa8000 {
  465. #address-cells = <1>;
  466. #size-cells = <0>;
  467. compatible = "atmel,at91rm9200-spi";
  468. reg = <0xfffa8000 0x200>;
  469. interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
  470. pinctrl-names = "default";
  471. pinctrl-0 = <&pinctrl_spi1>;
  472. status = "disabled";
  473. };
  474. };
  475. nand0: nand@40000000 {
  476. compatible = "atmel,at91rm9200-nand";
  477. #address-cells = <1>;
  478. #size-cells = <1>;
  479. reg = <0x40000000 0x10000000
  480. 0xffffe000 0x200
  481. >;
  482. atmel,nand-addr-offset = <21>;
  483. atmel,nand-cmd-offset = <22>;
  484. pinctrl-names = "default";
  485. pinctrl-0 = <&pinctrl_nand>;
  486. gpios = <&pioA 22 GPIO_ACTIVE_HIGH
  487. &pioD 15 GPIO_ACTIVE_HIGH
  488. 0
  489. >;
  490. status = "disabled";
  491. };
  492. usb0: ohci@00a00000 {
  493. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  494. reg = <0x00a00000 0x100000>;
  495. interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
  496. status = "disabled";
  497. };
  498. };
  499. i2c@0 {
  500. compatible = "i2c-gpio";
  501. gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
  502. &pioB 5 GPIO_ACTIVE_HIGH /* scl */
  503. >;
  504. i2c-gpio,sda-open-drain;
  505. i2c-gpio,scl-open-drain;
  506. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  507. #address-cells = <1>;
  508. #size-cells = <0>;
  509. status = "disabled";
  510. };
  511. };