dmar.h 6.1 KB

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  1. /*
  2. * Copyright (c) 2006, Intel Corporation.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License along with
  14. * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15. * Place - Suite 330, Boston, MA 02111-1307 USA.
  16. *
  17. * Copyright (C) Ashok Raj <ashok.raj@intel.com>
  18. * Copyright (C) Shaohua Li <shaohua.li@intel.com>
  19. */
  20. #ifndef __DMAR_H__
  21. #define __DMAR_H__
  22. #include <linux/acpi.h>
  23. #include <linux/types.h>
  24. #include <linux/msi.h>
  25. #include <linux/irqreturn.h>
  26. struct intel_iommu;
  27. #if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
  28. struct dmar_drhd_unit {
  29. struct list_head list; /* list of drhd units */
  30. struct acpi_dmar_header *hdr; /* ACPI header */
  31. u64 reg_base_addr; /* register base address*/
  32. struct pci_dev **devices; /* target device array */
  33. int devices_cnt; /* target device count */
  34. u16 segment; /* PCI domain */
  35. u8 ignored:1; /* ignore drhd */
  36. u8 include_all:1;
  37. struct intel_iommu *iommu;
  38. };
  39. extern struct list_head dmar_drhd_units;
  40. #define for_each_drhd_unit(drhd) \
  41. list_for_each_entry(drhd, &dmar_drhd_units, list)
  42. #define for_each_active_iommu(i, drhd) \
  43. list_for_each_entry(drhd, &dmar_drhd_units, list) \
  44. if (i=drhd->iommu, drhd->ignored) {} else
  45. #define for_each_iommu(i, drhd) \
  46. list_for_each_entry(drhd, &dmar_drhd_units, list) \
  47. if (i=drhd->iommu, 0) {} else
  48. extern int dmar_table_init(void);
  49. extern int dmar_dev_scope_init(void);
  50. /* Intel IOMMU detection */
  51. extern int detect_intel_iommu(void);
  52. extern int enable_drhd_fault_handling(void);
  53. extern int parse_ioapics_under_ir(void);
  54. extern int alloc_iommu(struct dmar_drhd_unit *);
  55. #else
  56. static inline int detect_intel_iommu(void)
  57. {
  58. return -ENODEV;
  59. }
  60. static inline int dmar_table_init(void)
  61. {
  62. return -ENODEV;
  63. }
  64. static inline int enable_drhd_fault_handling(void)
  65. {
  66. return -1;
  67. }
  68. #endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
  69. struct irte {
  70. union {
  71. struct {
  72. __u64 present : 1,
  73. fpd : 1,
  74. dst_mode : 1,
  75. redir_hint : 1,
  76. trigger_mode : 1,
  77. dlvry_mode : 3,
  78. avail : 4,
  79. __reserved_1 : 4,
  80. vector : 8,
  81. __reserved_2 : 8,
  82. dest_id : 32;
  83. };
  84. __u64 low;
  85. };
  86. union {
  87. struct {
  88. __u64 sid : 16,
  89. sq : 2,
  90. svt : 2,
  91. __reserved_3 : 44;
  92. };
  93. __u64 high;
  94. };
  95. };
  96. #ifdef CONFIG_INTR_REMAP
  97. extern int intr_remapping_enabled;
  98. extern int intr_remapping_supported(void);
  99. extern int enable_intr_remapping(int);
  100. extern void disable_intr_remapping(void);
  101. extern int reenable_intr_remapping(int);
  102. extern int get_irte(int irq, struct irte *entry);
  103. extern int modify_irte(int irq, struct irte *irte_modified);
  104. extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
  105. extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
  106. u16 sub_handle);
  107. extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
  108. extern int free_irte(int irq);
  109. extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
  110. extern struct intel_iommu *map_ioapic_to_ir(int apic);
  111. extern struct intel_iommu *map_hpet_to_ir(u8 id);
  112. extern int set_ioapic_sid(struct irte *irte, int apic);
  113. extern int set_hpet_sid(struct irte *irte, u8 id);
  114. extern int set_msi_sid(struct irte *irte, struct pci_dev *dev);
  115. #else
  116. static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
  117. {
  118. return -1;
  119. }
  120. static inline int modify_irte(int irq, struct irte *irte_modified)
  121. {
  122. return -1;
  123. }
  124. static inline int free_irte(int irq)
  125. {
  126. return -1;
  127. }
  128. static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
  129. {
  130. return -1;
  131. }
  132. static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
  133. u16 sub_handle)
  134. {
  135. return -1;
  136. }
  137. static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
  138. {
  139. return NULL;
  140. }
  141. static inline struct intel_iommu *map_ioapic_to_ir(int apic)
  142. {
  143. return NULL;
  144. }
  145. static inline struct intel_iommu *map_hpet_to_ir(unsigned int hpet_id)
  146. {
  147. return NULL;
  148. }
  149. static inline int set_ioapic_sid(struct irte *irte, int apic)
  150. {
  151. return 0;
  152. }
  153. static inline int set_hpet_sid(struct irte *irte, u8 id)
  154. {
  155. return -1;
  156. }
  157. static inline int set_msi_sid(struct irte *irte, struct pci_dev *dev)
  158. {
  159. return 0;
  160. }
  161. #define intr_remapping_enabled (0)
  162. static inline int enable_intr_remapping(int eim)
  163. {
  164. return -1;
  165. }
  166. static inline void disable_intr_remapping(void)
  167. {
  168. }
  169. static inline int reenable_intr_remapping(int eim)
  170. {
  171. return 0;
  172. }
  173. #endif
  174. /* Can't use the common MSI interrupt functions
  175. * since DMAR is not a pci device
  176. */
  177. struct irq_data;
  178. extern void dmar_msi_unmask(struct irq_data *data);
  179. extern void dmar_msi_mask(struct irq_data *data);
  180. extern void dmar_msi_read(int irq, struct msi_msg *msg);
  181. extern void dmar_msi_write(int irq, struct msi_msg *msg);
  182. extern int dmar_set_interrupt(struct intel_iommu *iommu);
  183. extern irqreturn_t dmar_fault(int irq, void *dev_id);
  184. extern int arch_setup_dmar_msi(unsigned int irq);
  185. #ifdef CONFIG_DMAR
  186. extern int iommu_detected, no_iommu;
  187. extern struct list_head dmar_rmrr_units;
  188. struct dmar_rmrr_unit {
  189. struct list_head list; /* list of rmrr units */
  190. struct acpi_dmar_header *hdr; /* ACPI header */
  191. u64 base_address; /* reserved base address*/
  192. u64 end_address; /* reserved end address */
  193. struct pci_dev **devices; /* target devices */
  194. int devices_cnt; /* target device count */
  195. };
  196. #define for_each_rmrr_units(rmrr) \
  197. list_for_each_entry(rmrr, &dmar_rmrr_units, list)
  198. struct dmar_atsr_unit {
  199. struct list_head list; /* list of ATSR units */
  200. struct acpi_dmar_header *hdr; /* ACPI header */
  201. struct pci_dev **devices; /* target devices */
  202. int devices_cnt; /* target device count */
  203. u8 include_all:1; /* include all ports */
  204. };
  205. extern int intel_iommu_init(void);
  206. #else /* !CONFIG_DMAR: */
  207. static inline int intel_iommu_init(void) { return -ENODEV; }
  208. #endif /* CONFIG_DMAR */
  209. #endif /* __DMAR_H__ */