iwl-core.c 88 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/sched.h>
  32. #include <net/mac80211.h>
  33. #include "iwl-eeprom.h"
  34. #include "iwl-dev.h" /* FIXME: remove */
  35. #include "iwl-debug.h"
  36. #include "iwl-core.h"
  37. #include "iwl-io.h"
  38. #include "iwl-power.h"
  39. #include "iwl-sta.h"
  40. #include "iwl-helpers.h"
  41. MODULE_DESCRIPTION("iwl core");
  42. MODULE_VERSION(IWLWIFI_VERSION);
  43. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  44. MODULE_LICENSE("GPL");
  45. /*
  46. * set bt_coex_active to true, uCode will do kill/defer
  47. * every time the priority line is asserted (BT is sending signals on the
  48. * priority line in the PCIx).
  49. * set bt_coex_active to false, uCode will ignore the BT activity and
  50. * perform the normal operation
  51. *
  52. * User might experience transmit issue on some platform due to WiFi/BT
  53. * co-exist problem. The possible behaviors are:
  54. * Able to scan and finding all the available AP
  55. * Not able to associate with any AP
  56. * On those platforms, WiFi communication can be restored by set
  57. * "bt_coex_active" module parameter to "false"
  58. *
  59. * default: bt_coex_active = true (BT_COEX_ENABLE)
  60. */
  61. static bool bt_coex_active = true;
  62. module_param(bt_coex_active, bool, S_IRUGO);
  63. MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist\n");
  64. static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
  65. {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
  66. 0, COEX_UNASSOC_IDLE_FLAGS},
  67. {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
  68. 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
  69. {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
  70. 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
  71. {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
  72. 0, COEX_CALIBRATION_FLAGS},
  73. {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
  74. 0, COEX_PERIODIC_CALIBRATION_FLAGS},
  75. {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
  76. 0, COEX_CONNECTION_ESTAB_FLAGS},
  77. {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
  78. 0, COEX_ASSOCIATED_IDLE_FLAGS},
  79. {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
  80. 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
  81. {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
  82. 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
  83. {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
  84. 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
  85. {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
  86. {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
  87. {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
  88. 0, COEX_STAND_ALONE_DEBUG_FLAGS},
  89. {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
  90. 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
  91. {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
  92. {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
  93. };
  94. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  95. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  96. IWL_RATE_SISO_##s##M_PLCP, \
  97. IWL_RATE_MIMO2_##s##M_PLCP,\
  98. IWL_RATE_MIMO3_##s##M_PLCP,\
  99. IWL_RATE_##r##M_IEEE, \
  100. IWL_RATE_##ip##M_INDEX, \
  101. IWL_RATE_##in##M_INDEX, \
  102. IWL_RATE_##rp##M_INDEX, \
  103. IWL_RATE_##rn##M_INDEX, \
  104. IWL_RATE_##pp##M_INDEX, \
  105. IWL_RATE_##np##M_INDEX }
  106. u32 iwl_debug_level;
  107. EXPORT_SYMBOL(iwl_debug_level);
  108. /*
  109. * Parameter order:
  110. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  111. *
  112. * If there isn't a valid next or previous rate then INV is used which
  113. * maps to IWL_RATE_INVALID
  114. *
  115. */
  116. const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  117. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  118. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  119. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  120. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  121. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  122. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  123. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  124. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  125. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  126. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  127. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  128. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  129. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  130. /* FIXME:RS: ^^ should be INV (legacy) */
  131. };
  132. EXPORT_SYMBOL(iwl_rates);
  133. /**
  134. * translate ucode response to mac80211 tx status control values
  135. */
  136. void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  137. struct ieee80211_tx_info *info)
  138. {
  139. struct ieee80211_tx_rate *r = &info->control.rates[0];
  140. info->antenna_sel_tx =
  141. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  142. if (rate_n_flags & RATE_MCS_HT_MSK)
  143. r->flags |= IEEE80211_TX_RC_MCS;
  144. if (rate_n_flags & RATE_MCS_GF_MSK)
  145. r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
  146. if (rate_n_flags & RATE_MCS_HT40_MSK)
  147. r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
  148. if (rate_n_flags & RATE_MCS_DUP_MSK)
  149. r->flags |= IEEE80211_TX_RC_DUP_DATA;
  150. if (rate_n_flags & RATE_MCS_SGI_MSK)
  151. r->flags |= IEEE80211_TX_RC_SHORT_GI;
  152. r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
  153. }
  154. EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
  155. int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
  156. {
  157. int idx = 0;
  158. /* HT rate format */
  159. if (rate_n_flags & RATE_MCS_HT_MSK) {
  160. idx = (rate_n_flags & 0xff);
  161. if (idx >= IWL_RATE_MIMO3_6M_PLCP)
  162. idx = idx - IWL_RATE_MIMO3_6M_PLCP;
  163. else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  164. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  165. idx += IWL_FIRST_OFDM_RATE;
  166. /* skip 9M not supported in ht*/
  167. if (idx >= IWL_RATE_9M_INDEX)
  168. idx += 1;
  169. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  170. return idx;
  171. /* legacy rate format, search for match in table */
  172. } else {
  173. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  174. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  175. return idx;
  176. }
  177. return -1;
  178. }
  179. EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
  180. int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
  181. {
  182. int idx = 0;
  183. int band_offset = 0;
  184. /* HT rate format: mac80211 wants an MCS number, which is just LSB */
  185. if (rate_n_flags & RATE_MCS_HT_MSK) {
  186. idx = (rate_n_flags & 0xff);
  187. return idx;
  188. /* Legacy rate format, search for match in table */
  189. } else {
  190. if (band == IEEE80211_BAND_5GHZ)
  191. band_offset = IWL_FIRST_OFDM_RATE;
  192. for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
  193. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  194. return idx - band_offset;
  195. }
  196. return -1;
  197. }
  198. u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
  199. {
  200. int i;
  201. u8 ind = ant;
  202. for (i = 0; i < RATE_ANT_NUM - 1; i++) {
  203. ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
  204. if (priv->hw_params.valid_tx_ant & BIT(ind))
  205. return ind;
  206. }
  207. return ant;
  208. }
  209. EXPORT_SYMBOL(iwl_toggle_tx_ant);
  210. const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  211. EXPORT_SYMBOL(iwl_bcast_addr);
  212. /* This function both allocates and initializes hw and priv. */
  213. struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
  214. struct ieee80211_ops *hw_ops)
  215. {
  216. struct iwl_priv *priv;
  217. /* mac80211 allocates memory for this device instance, including
  218. * space for this driver's private structure */
  219. struct ieee80211_hw *hw =
  220. ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
  221. if (hw == NULL) {
  222. printk(KERN_ERR "%s: Can not allocate network device\n",
  223. cfg->name);
  224. goto out;
  225. }
  226. priv = hw->priv;
  227. priv->hw = hw;
  228. out:
  229. return hw;
  230. }
  231. EXPORT_SYMBOL(iwl_alloc_all);
  232. void iwl_hw_detect(struct iwl_priv *priv)
  233. {
  234. priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
  235. priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
  236. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
  237. }
  238. EXPORT_SYMBOL(iwl_hw_detect);
  239. int iwl_hw_nic_init(struct iwl_priv *priv)
  240. {
  241. unsigned long flags;
  242. struct iwl_rx_queue *rxq = &priv->rxq;
  243. int ret;
  244. /* nic_init */
  245. spin_lock_irqsave(&priv->lock, flags);
  246. priv->cfg->ops->lib->apm_ops.init(priv);
  247. /* Set interrupt coalescing calibration timer to default (512 usecs) */
  248. iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
  249. spin_unlock_irqrestore(&priv->lock, flags);
  250. ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
  251. priv->cfg->ops->lib->apm_ops.config(priv);
  252. /* Allocate the RX queue, or reset if it is already allocated */
  253. if (!rxq->bd) {
  254. ret = iwl_rx_queue_alloc(priv);
  255. if (ret) {
  256. IWL_ERR(priv, "Unable to initialize Rx queue\n");
  257. return -ENOMEM;
  258. }
  259. } else
  260. iwl_rx_queue_reset(priv, rxq);
  261. iwl_rx_replenish(priv);
  262. iwl_rx_init(priv, rxq);
  263. spin_lock_irqsave(&priv->lock, flags);
  264. rxq->need_update = 1;
  265. iwl_rx_queue_update_write_ptr(priv, rxq);
  266. spin_unlock_irqrestore(&priv->lock, flags);
  267. /* Allocate and init all Tx and Command queues */
  268. ret = iwl_txq_ctx_reset(priv);
  269. if (ret)
  270. return ret;
  271. set_bit(STATUS_INIT, &priv->status);
  272. return 0;
  273. }
  274. EXPORT_SYMBOL(iwl_hw_nic_init);
  275. /*
  276. * QoS support
  277. */
  278. void iwl_activate_qos(struct iwl_priv *priv, u8 force)
  279. {
  280. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  281. return;
  282. priv->qos_data.def_qos_parm.qos_flags = 0;
  283. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  284. !priv->qos_data.qos_cap.q_AP.txop_request)
  285. priv->qos_data.def_qos_parm.qos_flags |=
  286. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  287. if (priv->qos_data.qos_active)
  288. priv->qos_data.def_qos_parm.qos_flags |=
  289. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  290. if (priv->current_ht_config.is_ht)
  291. priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  292. if (force || iwl_is_associated(priv)) {
  293. IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  294. priv->qos_data.qos_active,
  295. priv->qos_data.def_qos_parm.qos_flags);
  296. iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
  297. sizeof(struct iwl_qosparam_cmd),
  298. &priv->qos_data.def_qos_parm, NULL);
  299. }
  300. }
  301. EXPORT_SYMBOL(iwl_activate_qos);
  302. /*
  303. * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
  304. * (802.11b) (802.11a/g)
  305. * AC_BK 15 1023 7 0 0
  306. * AC_BE 15 1023 3 0 0
  307. * AC_VI 7 15 2 6.016ms 3.008ms
  308. * AC_VO 3 7 2 3.264ms 1.504ms
  309. */
  310. void iwl_reset_qos(struct iwl_priv *priv)
  311. {
  312. u16 cw_min = 15;
  313. u16 cw_max = 1023;
  314. u8 aifs = 2;
  315. bool is_legacy = false;
  316. unsigned long flags;
  317. int i;
  318. spin_lock_irqsave(&priv->lock, flags);
  319. /* QoS always active in AP and ADHOC mode
  320. * In STA mode wait for association
  321. */
  322. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  323. priv->iw_mode == NL80211_IFTYPE_AP)
  324. priv->qos_data.qos_active = 1;
  325. else
  326. priv->qos_data.qos_active = 0;
  327. /* check for legacy mode */
  328. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  329. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  330. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  331. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  332. cw_min = 31;
  333. is_legacy = 1;
  334. }
  335. if (priv->qos_data.qos_active)
  336. aifs = 3;
  337. /* AC_BE */
  338. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  339. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  340. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  341. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  342. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  343. if (priv->qos_data.qos_active) {
  344. /* AC_BK */
  345. i = 1;
  346. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  347. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  348. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  349. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  350. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  351. /* AC_VI */
  352. i = 2;
  353. priv->qos_data.def_qos_parm.ac[i].cw_min =
  354. cpu_to_le16((cw_min + 1) / 2 - 1);
  355. priv->qos_data.def_qos_parm.ac[i].cw_max =
  356. cpu_to_le16(cw_min);
  357. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  358. if (is_legacy)
  359. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  360. cpu_to_le16(6016);
  361. else
  362. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  363. cpu_to_le16(3008);
  364. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  365. /* AC_VO */
  366. i = 3;
  367. priv->qos_data.def_qos_parm.ac[i].cw_min =
  368. cpu_to_le16((cw_min + 1) / 4 - 1);
  369. priv->qos_data.def_qos_parm.ac[i].cw_max =
  370. cpu_to_le16((cw_min + 1) / 2 - 1);
  371. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  372. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  373. if (is_legacy)
  374. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  375. cpu_to_le16(3264);
  376. else
  377. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  378. cpu_to_le16(1504);
  379. } else {
  380. for (i = 1; i < 4; i++) {
  381. priv->qos_data.def_qos_parm.ac[i].cw_min =
  382. cpu_to_le16(cw_min);
  383. priv->qos_data.def_qos_parm.ac[i].cw_max =
  384. cpu_to_le16(cw_max);
  385. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  386. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  387. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  388. }
  389. }
  390. IWL_DEBUG_QOS(priv, "set QoS to default \n");
  391. spin_unlock_irqrestore(&priv->lock, flags);
  392. }
  393. EXPORT_SYMBOL(iwl_reset_qos);
  394. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  395. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  396. static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
  397. struct ieee80211_sta_ht_cap *ht_info,
  398. enum ieee80211_band band)
  399. {
  400. u16 max_bit_rate = 0;
  401. u8 rx_chains_num = priv->hw_params.rx_chains_num;
  402. u8 tx_chains_num = priv->hw_params.tx_chains_num;
  403. ht_info->cap = 0;
  404. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  405. ht_info->ht_supported = true;
  406. if (priv->cfg->ht_greenfield_support)
  407. ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
  408. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  409. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  410. if (priv->hw_params.ht40_channel & BIT(band)) {
  411. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  412. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  413. ht_info->mcs.rx_mask[4] = 0x01;
  414. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  415. }
  416. if (priv->cfg->mod_params->amsdu_size_8K)
  417. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  418. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  419. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  420. ht_info->mcs.rx_mask[0] = 0xFF;
  421. if (rx_chains_num >= 2)
  422. ht_info->mcs.rx_mask[1] = 0xFF;
  423. if (rx_chains_num >= 3)
  424. ht_info->mcs.rx_mask[2] = 0xFF;
  425. /* Highest supported Rx data rate */
  426. max_bit_rate *= rx_chains_num;
  427. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  428. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  429. /* Tx MCS capabilities */
  430. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  431. if (tx_chains_num != rx_chains_num) {
  432. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  433. ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
  434. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  435. }
  436. }
  437. /**
  438. * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
  439. */
  440. int iwlcore_init_geos(struct iwl_priv *priv)
  441. {
  442. struct iwl_channel_info *ch;
  443. struct ieee80211_supported_band *sband;
  444. struct ieee80211_channel *channels;
  445. struct ieee80211_channel *geo_ch;
  446. struct ieee80211_rate *rates;
  447. int i = 0;
  448. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  449. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  450. IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
  451. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  452. return 0;
  453. }
  454. channels = kzalloc(sizeof(struct ieee80211_channel) *
  455. priv->channel_count, GFP_KERNEL);
  456. if (!channels)
  457. return -ENOMEM;
  458. rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
  459. GFP_KERNEL);
  460. if (!rates) {
  461. kfree(channels);
  462. return -ENOMEM;
  463. }
  464. /* 5.2GHz channels start after the 2.4GHz channels */
  465. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  466. sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
  467. /* just OFDM */
  468. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  469. sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
  470. if (priv->cfg->sku & IWL_SKU_N)
  471. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  472. IEEE80211_BAND_5GHZ);
  473. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  474. sband->channels = channels;
  475. /* OFDM & CCK */
  476. sband->bitrates = rates;
  477. sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
  478. if (priv->cfg->sku & IWL_SKU_N)
  479. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  480. IEEE80211_BAND_2GHZ);
  481. priv->ieee_channels = channels;
  482. priv->ieee_rates = rates;
  483. for (i = 0; i < priv->channel_count; i++) {
  484. ch = &priv->channel_info[i];
  485. /* FIXME: might be removed if scan is OK */
  486. if (!is_channel_valid(ch))
  487. continue;
  488. if (is_channel_a_band(ch))
  489. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  490. else
  491. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  492. geo_ch = &sband->channels[sband->n_channels++];
  493. geo_ch->center_freq =
  494. ieee80211_channel_to_frequency(ch->channel);
  495. geo_ch->max_power = ch->max_power_avg;
  496. geo_ch->max_antenna_gain = 0xff;
  497. geo_ch->hw_value = ch->channel;
  498. if (is_channel_valid(ch)) {
  499. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  500. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  501. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  502. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  503. if (ch->flags & EEPROM_CHANNEL_RADAR)
  504. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  505. geo_ch->flags |= ch->ht40_extension_channel;
  506. if (ch->max_power_avg > priv->tx_power_device_lmt)
  507. priv->tx_power_device_lmt = ch->max_power_avg;
  508. } else {
  509. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  510. }
  511. IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
  512. ch->channel, geo_ch->center_freq,
  513. is_channel_a_band(ch) ? "5.2" : "2.4",
  514. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  515. "restricted" : "valid",
  516. geo_ch->flags);
  517. }
  518. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  519. priv->cfg->sku & IWL_SKU_A) {
  520. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  521. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  522. priv->pci_dev->device,
  523. priv->pci_dev->subsystem_device);
  524. priv->cfg->sku &= ~IWL_SKU_A;
  525. }
  526. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  527. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  528. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  529. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  530. return 0;
  531. }
  532. EXPORT_SYMBOL(iwlcore_init_geos);
  533. /*
  534. * iwlcore_free_geos - undo allocations in iwlcore_init_geos
  535. */
  536. void iwlcore_free_geos(struct iwl_priv *priv)
  537. {
  538. kfree(priv->ieee_channels);
  539. kfree(priv->ieee_rates);
  540. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  541. }
  542. EXPORT_SYMBOL(iwlcore_free_geos);
  543. /*
  544. * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this
  545. * function.
  546. */
  547. void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
  548. __le32 *tx_flags)
  549. {
  550. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  551. *tx_flags |= TX_CMD_FLG_RTS_MSK;
  552. *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  553. } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  554. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  555. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  556. }
  557. }
  558. EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag);
  559. static bool is_single_rx_stream(struct iwl_priv *priv)
  560. {
  561. return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
  562. priv->current_ht_config.single_chain_sufficient;
  563. }
  564. static u8 iwl_is_channel_extension(struct iwl_priv *priv,
  565. enum ieee80211_band band,
  566. u16 channel, u8 extension_chan_offset)
  567. {
  568. const struct iwl_channel_info *ch_info;
  569. ch_info = iwl_get_channel_info(priv, band, channel);
  570. if (!is_channel_valid(ch_info))
  571. return 0;
  572. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  573. return !(ch_info->ht40_extension_channel &
  574. IEEE80211_CHAN_NO_HT40PLUS);
  575. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  576. return !(ch_info->ht40_extension_channel &
  577. IEEE80211_CHAN_NO_HT40MINUS);
  578. return 0;
  579. }
  580. u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
  581. struct ieee80211_sta_ht_cap *sta_ht_inf)
  582. {
  583. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  584. if (!ht_conf->is_ht || !ht_conf->is_40mhz)
  585. return 0;
  586. /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  587. * the bit will not set if it is pure 40MHz case
  588. */
  589. if (sta_ht_inf) {
  590. if (!sta_ht_inf->ht_supported)
  591. return 0;
  592. }
  593. #ifdef CONFIG_IWLWIFI_DEBUG
  594. if (priv->disable_ht40)
  595. return 0;
  596. #endif
  597. return iwl_is_channel_extension(priv, priv->band,
  598. le16_to_cpu(priv->staging_rxon.channel),
  599. ht_conf->extension_chan_offset);
  600. }
  601. EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
  602. static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  603. {
  604. u16 new_val = 0;
  605. u16 beacon_factor = 0;
  606. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  607. new_val = beacon_val / beacon_factor;
  608. if (!new_val)
  609. new_val = max_beacon_val;
  610. return new_val;
  611. }
  612. void iwl_setup_rxon_timing(struct iwl_priv *priv)
  613. {
  614. u64 tsf;
  615. s32 interval_tm, rem;
  616. unsigned long flags;
  617. struct ieee80211_conf *conf = NULL;
  618. u16 beacon_int;
  619. conf = ieee80211_get_hw_conf(priv->hw);
  620. spin_lock_irqsave(&priv->lock, flags);
  621. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  622. priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
  623. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  624. beacon_int = priv->beacon_int;
  625. priv->rxon_timing.atim_window = 0;
  626. } else {
  627. beacon_int = priv->vif->bss_conf.beacon_int;
  628. /* TODO: we need to get atim_window from upper stack
  629. * for now we set to 0 */
  630. priv->rxon_timing.atim_window = 0;
  631. }
  632. beacon_int = iwl_adjust_beacon_interval(beacon_int,
  633. priv->hw_params.max_beacon_itrvl * 1024);
  634. priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
  635. tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
  636. interval_tm = beacon_int * 1024;
  637. rem = do_div(tsf, interval_tm);
  638. priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  639. spin_unlock_irqrestore(&priv->lock, flags);
  640. IWL_DEBUG_ASSOC(priv,
  641. "beacon interval %d beacon timer %d beacon tim %d\n",
  642. le16_to_cpu(priv->rxon_timing.beacon_interval),
  643. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  644. le16_to_cpu(priv->rxon_timing.atim_window));
  645. }
  646. EXPORT_SYMBOL(iwl_setup_rxon_timing);
  647. void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  648. {
  649. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  650. if (hw_decrypt)
  651. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  652. else
  653. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  654. }
  655. EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
  656. /**
  657. * iwl_check_rxon_cmd - validate RXON structure is valid
  658. *
  659. * NOTE: This is really only useful during development and can eventually
  660. * be #ifdef'd out once the driver is stable and folks aren't actively
  661. * making changes
  662. */
  663. int iwl_check_rxon_cmd(struct iwl_priv *priv)
  664. {
  665. int error = 0;
  666. int counter = 1;
  667. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  668. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  669. error |= le32_to_cpu(rxon->flags &
  670. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  671. RXON_FLG_RADAR_DETECT_MSK));
  672. if (error)
  673. IWL_WARN(priv, "check 24G fields %d | %d\n",
  674. counter++, error);
  675. } else {
  676. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  677. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  678. if (error)
  679. IWL_WARN(priv, "check 52 fields %d | %d\n",
  680. counter++, error);
  681. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  682. if (error)
  683. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  684. counter++, error);
  685. }
  686. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  687. if (error)
  688. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  689. /* make sure basic rates 6Mbps and 1Mbps are supported */
  690. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  691. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  692. if (error)
  693. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  694. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  695. if (error)
  696. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  697. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  698. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  699. if (error)
  700. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  701. counter++, error);
  702. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  703. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  704. if (error)
  705. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  706. counter++, error);
  707. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  708. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  709. if (error)
  710. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  711. counter++, error);
  712. if (error)
  713. IWL_WARN(priv, "Tuning to channel %d\n",
  714. le16_to_cpu(rxon->channel));
  715. if (error) {
  716. IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
  717. return -1;
  718. }
  719. return 0;
  720. }
  721. EXPORT_SYMBOL(iwl_check_rxon_cmd);
  722. /**
  723. * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  724. * @priv: staging_rxon is compared to active_rxon
  725. *
  726. * If the RXON structure is changing enough to require a new tune,
  727. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  728. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  729. */
  730. int iwl_full_rxon_required(struct iwl_priv *priv)
  731. {
  732. /* These items are only settable from the full RXON command */
  733. if (!(iwl_is_associated(priv)) ||
  734. compare_ether_addr(priv->staging_rxon.bssid_addr,
  735. priv->active_rxon.bssid_addr) ||
  736. compare_ether_addr(priv->staging_rxon.node_addr,
  737. priv->active_rxon.node_addr) ||
  738. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  739. priv->active_rxon.wlap_bssid_addr) ||
  740. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  741. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  742. (priv->staging_rxon.air_propagation !=
  743. priv->active_rxon.air_propagation) ||
  744. (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
  745. priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
  746. (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
  747. priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
  748. (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
  749. priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
  750. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  751. return 1;
  752. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  753. * be updated with the RXON_ASSOC command -- however only some
  754. * flag transitions are allowed using RXON_ASSOC */
  755. /* Check if we are not switching bands */
  756. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  757. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  758. return 1;
  759. /* Check if we are switching association toggle */
  760. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  761. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  762. return 1;
  763. return 0;
  764. }
  765. EXPORT_SYMBOL(iwl_full_rxon_required);
  766. u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
  767. {
  768. /*
  769. * Assign the lowest rate -- should really get this from
  770. * the beacon skb from mac80211.
  771. */
  772. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  773. return IWL_RATE_1M_PLCP;
  774. else
  775. return IWL_RATE_6M_PLCP;
  776. }
  777. EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
  778. void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
  779. {
  780. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  781. if (!ht_conf->is_ht) {
  782. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  783. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
  784. RXON_FLG_HT40_PROT_MSK |
  785. RXON_FLG_HT_PROT_MSK);
  786. return;
  787. }
  788. /* FIXME: if the definition of ht_protection changed, the "translation"
  789. * will be needed for rxon->flags
  790. */
  791. rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
  792. /* Set up channel bandwidth:
  793. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  794. /* clear the HT channel mode before set the mode */
  795. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  796. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  797. if (iwl_is_ht40_tx_allowed(priv, NULL)) {
  798. /* pure ht40 */
  799. if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  800. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  801. /* Note: control channel is opposite of extension channel */
  802. switch (ht_conf->extension_chan_offset) {
  803. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  804. rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  805. break;
  806. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  807. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  808. break;
  809. }
  810. } else {
  811. /* Note: control channel is opposite of extension channel */
  812. switch (ht_conf->extension_chan_offset) {
  813. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  814. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  815. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  816. break;
  817. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  818. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  819. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  820. break;
  821. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  822. default:
  823. /* channel location only valid if in Mixed mode */
  824. IWL_ERR(priv, "invalid extension channel offset\n");
  825. break;
  826. }
  827. }
  828. } else {
  829. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  830. }
  831. if (priv->cfg->ops->hcmd->set_rxon_chain)
  832. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  833. IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
  834. "extension channel offset 0x%x\n",
  835. le32_to_cpu(rxon->flags), ht_conf->ht_protection,
  836. ht_conf->extension_chan_offset);
  837. return;
  838. }
  839. EXPORT_SYMBOL(iwl_set_rxon_ht);
  840. #define IWL_NUM_RX_CHAINS_MULTIPLE 3
  841. #define IWL_NUM_RX_CHAINS_SINGLE 2
  842. #define IWL_NUM_IDLE_CHAINS_DUAL 2
  843. #define IWL_NUM_IDLE_CHAINS_SINGLE 1
  844. /*
  845. * Determine how many receiver/antenna chains to use.
  846. *
  847. * More provides better reception via diversity. Fewer saves power
  848. * at the expense of throughput, but only when not in powersave to
  849. * start with.
  850. *
  851. * MIMO (dual stream) requires at least 2, but works better with 3.
  852. * This does not determine *which* chains to use, just how many.
  853. */
  854. static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
  855. {
  856. /* # of Rx chains to use when expecting MIMO. */
  857. if (is_single_rx_stream(priv))
  858. return IWL_NUM_RX_CHAINS_SINGLE;
  859. else
  860. return IWL_NUM_RX_CHAINS_MULTIPLE;
  861. }
  862. /*
  863. * When we are in power saving mode, unless device support spatial
  864. * multiplexing power save, use the active count for rx chain count.
  865. */
  866. static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
  867. {
  868. /* # Rx chains when idling, depending on SMPS mode */
  869. switch (priv->current_ht_config.smps) {
  870. case IEEE80211_SMPS_STATIC:
  871. case IEEE80211_SMPS_DYNAMIC:
  872. return IWL_NUM_IDLE_CHAINS_SINGLE;
  873. case IEEE80211_SMPS_OFF:
  874. return active_cnt;
  875. default:
  876. WARN(1, "invalid SMPS mode %d",
  877. priv->current_ht_config.smps);
  878. return active_cnt;
  879. }
  880. }
  881. /* up to 4 chains */
  882. static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
  883. {
  884. u8 res;
  885. res = (chain_bitmap & BIT(0)) >> 0;
  886. res += (chain_bitmap & BIT(1)) >> 1;
  887. res += (chain_bitmap & BIT(2)) >> 2;
  888. res += (chain_bitmap & BIT(3)) >> 3;
  889. return res;
  890. }
  891. /**
  892. * iwl_is_monitor_mode - Determine if interface in monitor mode
  893. *
  894. * priv->iw_mode is set in add_interface, but add_interface is
  895. * never called for monitor mode. The only way mac80211 informs us about
  896. * monitor mode is through configuring filters (call to configure_filter).
  897. */
  898. bool iwl_is_monitor_mode(struct iwl_priv *priv)
  899. {
  900. return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
  901. }
  902. EXPORT_SYMBOL(iwl_is_monitor_mode);
  903. /**
  904. * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  905. *
  906. * Selects how many and which Rx receivers/antennas/chains to use.
  907. * This should not be used for scan command ... it puts data in wrong place.
  908. */
  909. void iwl_set_rxon_chain(struct iwl_priv *priv)
  910. {
  911. bool is_single = is_single_rx_stream(priv);
  912. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  913. u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
  914. u32 active_chains;
  915. u16 rx_chain;
  916. /* Tell uCode which antennas are actually connected.
  917. * Before first association, we assume all antennas are connected.
  918. * Just after first association, iwl_chain_noise_calibration()
  919. * checks which antennas actually *are* connected. */
  920. if (priv->chain_noise_data.active_chains)
  921. active_chains = priv->chain_noise_data.active_chains;
  922. else
  923. active_chains = priv->hw_params.valid_rx_ant;
  924. rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
  925. /* How many receivers should we use? */
  926. active_rx_cnt = iwl_get_active_rx_chain_count(priv);
  927. idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
  928. /* correct rx chain count according hw settings
  929. * and chain noise calibration
  930. */
  931. valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
  932. if (valid_rx_cnt < active_rx_cnt)
  933. active_rx_cnt = valid_rx_cnt;
  934. if (valid_rx_cnt < idle_rx_cnt)
  935. idle_rx_cnt = valid_rx_cnt;
  936. rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
  937. rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
  938. /* copied from 'iwl_bg_request_scan()' */
  939. /* Force use of chains B and C (0x6) for Rx for 4965
  940. * Avoid A (0x1) because of its off-channel reception on A-band.
  941. * MIMO is not used here, but value is required */
  942. if (iwl_is_monitor_mode(priv) &&
  943. !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
  944. ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
  945. rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
  946. rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
  947. rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
  948. rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
  949. }
  950. priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
  951. if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
  952. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  953. else
  954. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  955. IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
  956. priv->staging_rxon.rx_chain,
  957. active_rx_cnt, idle_rx_cnt);
  958. WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
  959. active_rx_cnt < idle_rx_cnt);
  960. }
  961. EXPORT_SYMBOL(iwl_set_rxon_chain);
  962. /**
  963. * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
  964. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  965. * @channel: Any channel valid for the requested phymode
  966. * In addition to setting the staging RXON, priv->phymode is also set.
  967. *
  968. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  969. * in the staging RXON flag structure based on the phymode
  970. */
  971. int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
  972. {
  973. enum ieee80211_band band = ch->band;
  974. u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
  975. if (!iwl_get_channel_info(priv, band, channel)) {
  976. IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
  977. channel, band);
  978. return -EINVAL;
  979. }
  980. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  981. (priv->band == band))
  982. return 0;
  983. priv->staging_rxon.channel = cpu_to_le16(channel);
  984. if (band == IEEE80211_BAND_5GHZ)
  985. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  986. else
  987. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  988. priv->band = band;
  989. IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
  990. return 0;
  991. }
  992. EXPORT_SYMBOL(iwl_set_rxon_channel);
  993. void iwl_set_flags_for_band(struct iwl_priv *priv,
  994. enum ieee80211_band band)
  995. {
  996. if (band == IEEE80211_BAND_5GHZ) {
  997. priv->staging_rxon.flags &=
  998. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  999. | RXON_FLG_CCK_MSK);
  1000. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1001. } else {
  1002. /* Copied from iwl_post_associate() */
  1003. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1004. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1005. else
  1006. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1007. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1008. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1009. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1010. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1011. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1012. }
  1013. }
  1014. /*
  1015. * initialize rxon structure with default values from eeprom
  1016. */
  1017. void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
  1018. {
  1019. const struct iwl_channel_info *ch_info;
  1020. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1021. switch (mode) {
  1022. case NL80211_IFTYPE_AP:
  1023. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1024. break;
  1025. case NL80211_IFTYPE_STATION:
  1026. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1027. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1028. break;
  1029. case NL80211_IFTYPE_ADHOC:
  1030. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1031. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1032. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1033. RXON_FILTER_ACCEPT_GRP_MSK;
  1034. break;
  1035. default:
  1036. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1037. break;
  1038. }
  1039. #if 0
  1040. /* TODO: Figure out when short_preamble would be set and cache from
  1041. * that */
  1042. if (!hw_to_local(priv->hw)->short_preamble)
  1043. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1044. else
  1045. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1046. #endif
  1047. ch_info = iwl_get_channel_info(priv, priv->band,
  1048. le16_to_cpu(priv->active_rxon.channel));
  1049. if (!ch_info)
  1050. ch_info = &priv->channel_info[0];
  1051. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1052. priv->band = ch_info->band;
  1053. iwl_set_flags_for_band(priv, priv->band);
  1054. priv->staging_rxon.ofdm_basic_rates =
  1055. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1056. priv->staging_rxon.cck_basic_rates =
  1057. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1058. /* clear both MIX and PURE40 mode flag */
  1059. priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
  1060. RXON_FLG_CHANNEL_MODE_PURE_40);
  1061. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1062. memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
  1063. priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
  1064. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
  1065. priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
  1066. }
  1067. EXPORT_SYMBOL(iwl_connection_init_rx_config);
  1068. static void iwl_set_rate(struct iwl_priv *priv)
  1069. {
  1070. const struct ieee80211_supported_band *hw = NULL;
  1071. struct ieee80211_rate *rate;
  1072. int i;
  1073. hw = iwl_get_hw_mode(priv, priv->band);
  1074. if (!hw) {
  1075. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  1076. return;
  1077. }
  1078. priv->active_rate = 0;
  1079. for (i = 0; i < hw->n_bitrates; i++) {
  1080. rate = &(hw->bitrates[i]);
  1081. if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
  1082. priv->active_rate |= (1 << rate->hw_value);
  1083. }
  1084. IWL_DEBUG_RATE(priv, "Set active_rate = %0x\n", priv->active_rate);
  1085. priv->staging_rxon.cck_basic_rates =
  1086. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1087. priv->staging_rxon.ofdm_basic_rates =
  1088. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1089. }
  1090. void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  1091. {
  1092. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1093. struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
  1094. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  1095. if (priv->switch_rxon.switch_in_progress) {
  1096. if (!le32_to_cpu(csa->status) &&
  1097. (csa->channel == priv->switch_rxon.channel)) {
  1098. rxon->channel = csa->channel;
  1099. priv->staging_rxon.channel = csa->channel;
  1100. IWL_DEBUG_11H(priv, "CSA notif: channel %d\n",
  1101. le16_to_cpu(csa->channel));
  1102. } else
  1103. IWL_ERR(priv, "CSA notif (fail) : channel %d\n",
  1104. le16_to_cpu(csa->channel));
  1105. priv->switch_rxon.switch_in_progress = false;
  1106. }
  1107. }
  1108. EXPORT_SYMBOL(iwl_rx_csa);
  1109. #ifdef CONFIG_IWLWIFI_DEBUG
  1110. void iwl_print_rx_config_cmd(struct iwl_priv *priv)
  1111. {
  1112. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  1113. IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
  1114. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  1115. IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  1116. IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  1117. IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
  1118. le32_to_cpu(rxon->filter_flags));
  1119. IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
  1120. IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
  1121. rxon->ofdm_basic_rates);
  1122. IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  1123. IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
  1124. IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  1125. IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  1126. }
  1127. EXPORT_SYMBOL(iwl_print_rx_config_cmd);
  1128. #endif
  1129. /**
  1130. * iwl_irq_handle_error - called for HW or SW error interrupt from card
  1131. */
  1132. void iwl_irq_handle_error(struct iwl_priv *priv)
  1133. {
  1134. /* Set the FW error flag -- cleared on iwl_down */
  1135. set_bit(STATUS_FW_ERROR, &priv->status);
  1136. /* Cancel currently queued command. */
  1137. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  1138. priv->cfg->ops->lib->dump_nic_error_log(priv);
  1139. if (priv->cfg->ops->lib->dump_csr)
  1140. priv->cfg->ops->lib->dump_csr(priv);
  1141. if (priv->cfg->ops->lib->dump_fh)
  1142. priv->cfg->ops->lib->dump_fh(priv, NULL, false);
  1143. priv->cfg->ops->lib->dump_nic_event_log(priv, false, NULL, false);
  1144. #ifdef CONFIG_IWLWIFI_DEBUG
  1145. if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS)
  1146. iwl_print_rx_config_cmd(priv);
  1147. #endif
  1148. wake_up_interruptible(&priv->wait_command_queue);
  1149. /* Keep the restart process from trying to send host
  1150. * commands by clearing the INIT status bit */
  1151. clear_bit(STATUS_READY, &priv->status);
  1152. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1153. IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
  1154. "Restarting adapter due to uCode error.\n");
  1155. if (priv->cfg->mod_params->restart_fw)
  1156. queue_work(priv->workqueue, &priv->restart);
  1157. }
  1158. }
  1159. EXPORT_SYMBOL(iwl_irq_handle_error);
  1160. int iwl_apm_stop_master(struct iwl_priv *priv)
  1161. {
  1162. int ret = 0;
  1163. /* stop device's busmaster DMA activity */
  1164. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  1165. ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
  1166. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  1167. if (ret)
  1168. IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
  1169. IWL_DEBUG_INFO(priv, "stop master\n");
  1170. return ret;
  1171. }
  1172. EXPORT_SYMBOL(iwl_apm_stop_master);
  1173. void iwl_apm_stop(struct iwl_priv *priv)
  1174. {
  1175. IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
  1176. /* Stop device's DMA activity */
  1177. iwl_apm_stop_master(priv);
  1178. /* Reset the entire device */
  1179. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  1180. udelay(10);
  1181. /*
  1182. * Clear "initialization complete" bit to move adapter from
  1183. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  1184. */
  1185. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  1186. }
  1187. EXPORT_SYMBOL(iwl_apm_stop);
  1188. /*
  1189. * Start up NIC's basic functionality after it has been reset
  1190. * (e.g. after platform boot, or shutdown via iwl_apm_stop())
  1191. * NOTE: This does not load uCode nor start the embedded processor
  1192. */
  1193. int iwl_apm_init(struct iwl_priv *priv)
  1194. {
  1195. int ret = 0;
  1196. u16 lctl;
  1197. IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
  1198. /*
  1199. * Use "set_bit" below rather than "write", to preserve any hardware
  1200. * bits already set by default after reset.
  1201. */
  1202. /* Disable L0S exit timer (platform NMI Work/Around) */
  1203. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  1204. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  1205. /*
  1206. * Disable L0s without affecting L1;
  1207. * don't wait for ICH L0s (ICH bug W/A)
  1208. */
  1209. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  1210. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  1211. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  1212. iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  1213. /*
  1214. * Enable HAP INTA (interrupt from management bus) to
  1215. * wake device's PCI Express link L1a -> L0s
  1216. * NOTE: This is no-op for 3945 (non-existant bit)
  1217. */
  1218. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1219. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  1220. /*
  1221. * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
  1222. * Check if BIOS (or OS) enabled L1-ASPM on this device.
  1223. * If so (likely), disable L0S, so device moves directly L0->L1;
  1224. * costs negligible amount of power savings.
  1225. * If not (unlikely), enable L0S, so there is at least some
  1226. * power savings, even without L1.
  1227. */
  1228. if (priv->cfg->set_l0s) {
  1229. lctl = iwl_pcie_link_ctl(priv);
  1230. if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
  1231. PCI_CFG_LINK_CTRL_VAL_L1_EN) {
  1232. /* L1-ASPM enabled; disable(!) L0S */
  1233. iwl_set_bit(priv, CSR_GIO_REG,
  1234. CSR_GIO_REG_VAL_L0S_ENABLED);
  1235. IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
  1236. } else {
  1237. /* L1-ASPM disabled; enable(!) L0S */
  1238. iwl_clear_bit(priv, CSR_GIO_REG,
  1239. CSR_GIO_REG_VAL_L0S_ENABLED);
  1240. IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
  1241. }
  1242. }
  1243. /* Configure analog phase-lock-loop before activating to D0A */
  1244. if (priv->cfg->pll_cfg_val)
  1245. iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val);
  1246. /*
  1247. * Set "initialization complete" bit to move adapter from
  1248. * D0U* --> D0A* (powered-up active) state.
  1249. */
  1250. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  1251. /*
  1252. * Wait for clock stabilization; once stabilized, access to
  1253. * device-internal resources is supported, e.g. iwl_write_prph()
  1254. * and accesses to uCode SRAM.
  1255. */
  1256. ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  1257. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  1258. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  1259. if (ret < 0) {
  1260. IWL_DEBUG_INFO(priv, "Failed to init the card\n");
  1261. goto out;
  1262. }
  1263. /*
  1264. * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
  1265. * BSM (Boostrap State Machine) is only in 3945 and 4965;
  1266. * later devices (i.e. 5000 and later) have non-volatile SRAM,
  1267. * and don't need BSM to restore data after power-saving sleep.
  1268. *
  1269. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  1270. * do not disable clocks. This preserves any hardware bits already
  1271. * set by default in "CLK_CTRL_REG" after reset.
  1272. */
  1273. if (priv->cfg->use_bsm)
  1274. iwl_write_prph(priv, APMG_CLK_EN_REG,
  1275. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  1276. else
  1277. iwl_write_prph(priv, APMG_CLK_EN_REG,
  1278. APMG_CLK_VAL_DMA_CLK_RQT);
  1279. udelay(20);
  1280. /* Disable L1-Active */
  1281. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  1282. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  1283. out:
  1284. return ret;
  1285. }
  1286. EXPORT_SYMBOL(iwl_apm_init);
  1287. void iwl_configure_filter(struct ieee80211_hw *hw,
  1288. unsigned int changed_flags,
  1289. unsigned int *total_flags,
  1290. u64 multicast)
  1291. {
  1292. struct iwl_priv *priv = hw->priv;
  1293. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  1294. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  1295. changed_flags, *total_flags);
  1296. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  1297. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  1298. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  1299. else
  1300. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  1301. }
  1302. if (changed_flags & FIF_ALLMULTI) {
  1303. if (*total_flags & FIF_ALLMULTI)
  1304. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  1305. else
  1306. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  1307. }
  1308. if (changed_flags & FIF_CONTROL) {
  1309. if (*total_flags & FIF_CONTROL)
  1310. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  1311. else
  1312. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  1313. }
  1314. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1315. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1316. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  1317. else
  1318. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  1319. }
  1320. /* We avoid iwl_commit_rxon here to commit the new filter flags
  1321. * since mac80211 will call ieee80211_hw_config immediately.
  1322. * (mc_list is not supported at this time). Otherwise, we need to
  1323. * queue a background iwl_commit_rxon work.
  1324. */
  1325. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  1326. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  1327. }
  1328. EXPORT_SYMBOL(iwl_configure_filter);
  1329. int iwl_set_hw_params(struct iwl_priv *priv)
  1330. {
  1331. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  1332. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1333. if (priv->cfg->mod_params->amsdu_size_8K)
  1334. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
  1335. else
  1336. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
  1337. priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
  1338. if (priv->cfg->mod_params->disable_11n)
  1339. priv->cfg->sku &= ~IWL_SKU_N;
  1340. /* Device-specific setup */
  1341. return priv->cfg->ops->lib->set_hw_params(priv);
  1342. }
  1343. EXPORT_SYMBOL(iwl_set_hw_params);
  1344. int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
  1345. {
  1346. int ret = 0;
  1347. s8 prev_tx_power = priv->tx_power_user_lmt;
  1348. if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
  1349. IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
  1350. tx_power,
  1351. IWL_TX_POWER_TARGET_POWER_MIN);
  1352. return -EINVAL;
  1353. }
  1354. if (tx_power > priv->tx_power_device_lmt) {
  1355. IWL_WARN(priv,
  1356. "Requested user TXPOWER %d above upper limit %d.\n",
  1357. tx_power, priv->tx_power_device_lmt);
  1358. return -EINVAL;
  1359. }
  1360. if (priv->tx_power_user_lmt != tx_power)
  1361. force = true;
  1362. /* if nic is not up don't send command */
  1363. if (iwl_is_ready_rf(priv)) {
  1364. priv->tx_power_user_lmt = tx_power;
  1365. if (force && priv->cfg->ops->lib->send_tx_power)
  1366. ret = priv->cfg->ops->lib->send_tx_power(priv);
  1367. else if (!priv->cfg->ops->lib->send_tx_power)
  1368. ret = -EOPNOTSUPP;
  1369. /*
  1370. * if fail to set tx_power, restore the orig. tx power
  1371. */
  1372. if (ret)
  1373. priv->tx_power_user_lmt = prev_tx_power;
  1374. }
  1375. /*
  1376. * Even this is an async host command, the command
  1377. * will always report success from uCode
  1378. * So once driver can placing the command into the queue
  1379. * successfully, driver can use priv->tx_power_user_lmt
  1380. * to reflect the current tx power
  1381. */
  1382. return ret;
  1383. }
  1384. EXPORT_SYMBOL(iwl_set_tx_power);
  1385. irqreturn_t iwl_isr_legacy(int irq, void *data)
  1386. {
  1387. struct iwl_priv *priv = data;
  1388. u32 inta, inta_mask;
  1389. u32 inta_fh;
  1390. if (!priv)
  1391. return IRQ_NONE;
  1392. spin_lock(&priv->lock);
  1393. /* Disable (but don't clear!) interrupts here to avoid
  1394. * back-to-back ISRs and sporadic interrupts from our NIC.
  1395. * If we have something to service, the tasklet will re-enable ints.
  1396. * If we *don't* have something, we'll re-enable before leaving here. */
  1397. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1398. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1399. /* Discover which interrupts are active/pending */
  1400. inta = iwl_read32(priv, CSR_INT);
  1401. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1402. /* Ignore interrupt if there's nothing in NIC to service.
  1403. * This may be due to IRQ shared with another device,
  1404. * or due to sporadic interrupts thrown from our NIC. */
  1405. if (!inta && !inta_fh) {
  1406. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
  1407. goto none;
  1408. }
  1409. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1410. /* Hardware disappeared. It might have already raised
  1411. * an interrupt */
  1412. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1413. goto unplugged;
  1414. }
  1415. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1416. inta, inta_mask, inta_fh);
  1417. inta &= ~CSR_INT_BIT_SCD;
  1418. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1419. if (likely(inta || inta_fh))
  1420. tasklet_schedule(&priv->irq_tasklet);
  1421. unplugged:
  1422. spin_unlock(&priv->lock);
  1423. return IRQ_HANDLED;
  1424. none:
  1425. /* re-enable interrupts here since we don't have anything to service. */
  1426. /* only Re-enable if diabled by irq */
  1427. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1428. iwl_enable_interrupts(priv);
  1429. spin_unlock(&priv->lock);
  1430. return IRQ_NONE;
  1431. }
  1432. EXPORT_SYMBOL(iwl_isr_legacy);
  1433. int iwl_send_bt_config(struct iwl_priv *priv)
  1434. {
  1435. struct iwl_bt_cmd bt_cmd = {
  1436. .lead_time = BT_LEAD_TIME_DEF,
  1437. .max_kill = BT_MAX_KILL_DEF,
  1438. .kill_ack_mask = 0,
  1439. .kill_cts_mask = 0,
  1440. };
  1441. if (!bt_coex_active)
  1442. bt_cmd.flags = BT_COEX_DISABLE;
  1443. else
  1444. bt_cmd.flags = BT_COEX_ENABLE;
  1445. IWL_DEBUG_INFO(priv, "BT coex %s\n",
  1446. (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
  1447. return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1448. sizeof(struct iwl_bt_cmd), &bt_cmd);
  1449. }
  1450. EXPORT_SYMBOL(iwl_send_bt_config);
  1451. int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear)
  1452. {
  1453. struct iwl_statistics_cmd statistics_cmd = {
  1454. .configuration_flags =
  1455. clear ? IWL_STATS_CONF_CLEAR_STATS : 0,
  1456. };
  1457. if (flags & CMD_ASYNC)
  1458. return iwl_send_cmd_pdu_async(priv, REPLY_STATISTICS_CMD,
  1459. sizeof(struct iwl_statistics_cmd),
  1460. &statistics_cmd, NULL);
  1461. else
  1462. return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD,
  1463. sizeof(struct iwl_statistics_cmd),
  1464. &statistics_cmd);
  1465. }
  1466. EXPORT_SYMBOL(iwl_send_statistics_request);
  1467. /**
  1468. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1469. * using sample data 100 bytes apart. If these sample points are good,
  1470. * it's a pretty good bet that everything between them is good, too.
  1471. */
  1472. static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1473. {
  1474. u32 val;
  1475. int ret = 0;
  1476. u32 errcnt = 0;
  1477. u32 i;
  1478. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1479. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1480. /* read data comes through single port, auto-incr addr */
  1481. /* NOTE: Use the debugless read so we don't flood kernel log
  1482. * if IWL_DL_IO is set */
  1483. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1484. i + IWL49_RTC_INST_LOWER_BOUND);
  1485. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1486. if (val != le32_to_cpu(*image)) {
  1487. ret = -EIO;
  1488. errcnt++;
  1489. if (errcnt >= 3)
  1490. break;
  1491. }
  1492. }
  1493. return ret;
  1494. }
  1495. /**
  1496. * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
  1497. * looking at all data.
  1498. */
  1499. static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
  1500. u32 len)
  1501. {
  1502. u32 val;
  1503. u32 save_len = len;
  1504. int ret = 0;
  1505. u32 errcnt;
  1506. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1507. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1508. IWL49_RTC_INST_LOWER_BOUND);
  1509. errcnt = 0;
  1510. for (; len > 0; len -= sizeof(u32), image++) {
  1511. /* read data comes through single port, auto-incr addr */
  1512. /* NOTE: Use the debugless read so we don't flood kernel log
  1513. * if IWL_DL_IO is set */
  1514. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1515. if (val != le32_to_cpu(*image)) {
  1516. IWL_ERR(priv, "uCode INST section is invalid at "
  1517. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1518. save_len - len, val, le32_to_cpu(*image));
  1519. ret = -EIO;
  1520. errcnt++;
  1521. if (errcnt >= 20)
  1522. break;
  1523. }
  1524. }
  1525. if (!errcnt)
  1526. IWL_DEBUG_INFO(priv,
  1527. "ucode image in INSTRUCTION memory is good\n");
  1528. return ret;
  1529. }
  1530. /**
  1531. * iwl_verify_ucode - determine which instruction image is in SRAM,
  1532. * and verify its contents
  1533. */
  1534. int iwl_verify_ucode(struct iwl_priv *priv)
  1535. {
  1536. __le32 *image;
  1537. u32 len;
  1538. int ret;
  1539. /* Try bootstrap */
  1540. image = (__le32 *)priv->ucode_boot.v_addr;
  1541. len = priv->ucode_boot.len;
  1542. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1543. if (!ret) {
  1544. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1545. return 0;
  1546. }
  1547. /* Try initialize */
  1548. image = (__le32 *)priv->ucode_init.v_addr;
  1549. len = priv->ucode_init.len;
  1550. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1551. if (!ret) {
  1552. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1553. return 0;
  1554. }
  1555. /* Try runtime/protocol */
  1556. image = (__le32 *)priv->ucode_code.v_addr;
  1557. len = priv->ucode_code.len;
  1558. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1559. if (!ret) {
  1560. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1561. return 0;
  1562. }
  1563. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1564. /* Since nothing seems to match, show first several data entries in
  1565. * instruction SRAM, so maybe visual inspection will give a clue.
  1566. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1567. image = (__le32 *)priv->ucode_boot.v_addr;
  1568. len = priv->ucode_boot.len;
  1569. ret = iwl_verify_inst_full(priv, image, len);
  1570. return ret;
  1571. }
  1572. EXPORT_SYMBOL(iwl_verify_ucode);
  1573. void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  1574. {
  1575. struct iwl_ct_kill_config cmd;
  1576. struct iwl_ct_kill_throttling_config adv_cmd;
  1577. unsigned long flags;
  1578. int ret = 0;
  1579. spin_lock_irqsave(&priv->lock, flags);
  1580. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1581. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1582. spin_unlock_irqrestore(&priv->lock, flags);
  1583. priv->thermal_throttle.ct_kill_toggle = false;
  1584. if (priv->cfg->support_ct_kill_exit) {
  1585. adv_cmd.critical_temperature_enter =
  1586. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1587. adv_cmd.critical_temperature_exit =
  1588. cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
  1589. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1590. sizeof(adv_cmd), &adv_cmd);
  1591. if (ret)
  1592. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1593. else
  1594. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1595. "succeeded, "
  1596. "critical temperature enter is %d,"
  1597. "exit is %d\n",
  1598. priv->hw_params.ct_kill_threshold,
  1599. priv->hw_params.ct_kill_exit_threshold);
  1600. } else {
  1601. cmd.critical_temperature_R =
  1602. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1603. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1604. sizeof(cmd), &cmd);
  1605. if (ret)
  1606. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1607. else
  1608. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1609. "succeeded, "
  1610. "critical temperature is %d\n",
  1611. priv->hw_params.ct_kill_threshold);
  1612. }
  1613. }
  1614. EXPORT_SYMBOL(iwl_rf_kill_ct_config);
  1615. /*
  1616. * CARD_STATE_CMD
  1617. *
  1618. * Use: Sets the device's internal card state to enable, disable, or halt
  1619. *
  1620. * When in the 'enable' state the card operates as normal.
  1621. * When in the 'disable' state, the card enters into a low power mode.
  1622. * When in the 'halt' state, the card is shut down and must be fully
  1623. * restarted to come back on.
  1624. */
  1625. int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
  1626. {
  1627. struct iwl_host_cmd cmd = {
  1628. .id = REPLY_CARD_STATE_CMD,
  1629. .len = sizeof(u32),
  1630. .data = &flags,
  1631. .flags = meta_flag,
  1632. };
  1633. return iwl_send_cmd(priv, &cmd);
  1634. }
  1635. void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
  1636. struct iwl_rx_mem_buffer *rxb)
  1637. {
  1638. #ifdef CONFIG_IWLWIFI_DEBUG
  1639. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1640. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  1641. IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
  1642. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  1643. #endif
  1644. }
  1645. EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
  1646. void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  1647. struct iwl_rx_mem_buffer *rxb)
  1648. {
  1649. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1650. u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1651. IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
  1652. "notification for %s:\n", len,
  1653. get_cmd_string(pkt->hdr.cmd));
  1654. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
  1655. }
  1656. EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
  1657. void iwl_rx_reply_error(struct iwl_priv *priv,
  1658. struct iwl_rx_mem_buffer *rxb)
  1659. {
  1660. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1661. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  1662. "seq 0x%04X ser 0x%08X\n",
  1663. le32_to_cpu(pkt->u.err_resp.error_type),
  1664. get_cmd_string(pkt->u.err_resp.cmd_id),
  1665. pkt->u.err_resp.cmd_id,
  1666. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  1667. le32_to_cpu(pkt->u.err_resp.error_info));
  1668. }
  1669. EXPORT_SYMBOL(iwl_rx_reply_error);
  1670. void iwl_clear_isr_stats(struct iwl_priv *priv)
  1671. {
  1672. memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
  1673. }
  1674. int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1675. const struct ieee80211_tx_queue_params *params)
  1676. {
  1677. struct iwl_priv *priv = hw->priv;
  1678. unsigned long flags;
  1679. int q;
  1680. IWL_DEBUG_MAC80211(priv, "enter\n");
  1681. if (!iwl_is_ready_rf(priv)) {
  1682. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  1683. return -EIO;
  1684. }
  1685. if (queue >= AC_NUM) {
  1686. IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
  1687. return 0;
  1688. }
  1689. q = AC_NUM - 1 - queue;
  1690. spin_lock_irqsave(&priv->lock, flags);
  1691. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  1692. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  1693. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  1694. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  1695. cpu_to_le16((params->txop * 32));
  1696. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  1697. priv->qos_data.qos_active = 1;
  1698. if (priv->iw_mode == NL80211_IFTYPE_AP)
  1699. iwl_activate_qos(priv, 1);
  1700. else if (priv->assoc_id && iwl_is_associated(priv))
  1701. iwl_activate_qos(priv, 0);
  1702. spin_unlock_irqrestore(&priv->lock, flags);
  1703. IWL_DEBUG_MAC80211(priv, "leave\n");
  1704. return 0;
  1705. }
  1706. EXPORT_SYMBOL(iwl_mac_conf_tx);
  1707. static void iwl_ht_conf(struct iwl_priv *priv,
  1708. struct ieee80211_bss_conf *bss_conf)
  1709. {
  1710. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  1711. struct ieee80211_sta *sta;
  1712. IWL_DEBUG_MAC80211(priv, "enter: \n");
  1713. if (!ht_conf->is_ht)
  1714. return;
  1715. ht_conf->ht_protection =
  1716. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  1717. ht_conf->non_GF_STA_present =
  1718. !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  1719. ht_conf->single_chain_sufficient = false;
  1720. switch (priv->iw_mode) {
  1721. case NL80211_IFTYPE_STATION:
  1722. rcu_read_lock();
  1723. sta = ieee80211_find_sta(priv->vif, priv->bssid);
  1724. if (sta) {
  1725. struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
  1726. int maxstreams;
  1727. maxstreams = (ht_cap->mcs.tx_params &
  1728. IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
  1729. >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  1730. maxstreams += 1;
  1731. if ((ht_cap->mcs.rx_mask[1] == 0) &&
  1732. (ht_cap->mcs.rx_mask[2] == 0))
  1733. ht_conf->single_chain_sufficient = true;
  1734. if (maxstreams <= 1)
  1735. ht_conf->single_chain_sufficient = true;
  1736. } else {
  1737. /*
  1738. * If at all, this can only happen through a race
  1739. * when the AP disconnects us while we're still
  1740. * setting up the connection, in that case mac80211
  1741. * will soon tell us about that.
  1742. */
  1743. ht_conf->single_chain_sufficient = true;
  1744. }
  1745. rcu_read_unlock();
  1746. break;
  1747. case NL80211_IFTYPE_ADHOC:
  1748. ht_conf->single_chain_sufficient = true;
  1749. break;
  1750. default:
  1751. break;
  1752. }
  1753. IWL_DEBUG_MAC80211(priv, "leave\n");
  1754. }
  1755. static inline void iwl_set_no_assoc(struct iwl_priv *priv)
  1756. {
  1757. priv->assoc_id = 0;
  1758. iwl_led_disassociate(priv);
  1759. /*
  1760. * inform the ucode that there is no longer an
  1761. * association and that no more packets should be
  1762. * sent
  1763. */
  1764. priv->staging_rxon.filter_flags &=
  1765. ~RXON_FILTER_ASSOC_MSK;
  1766. priv->staging_rxon.assoc_id = 0;
  1767. iwlcore_commit_rxon(priv);
  1768. }
  1769. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  1770. void iwl_bss_info_changed(struct ieee80211_hw *hw,
  1771. struct ieee80211_vif *vif,
  1772. struct ieee80211_bss_conf *bss_conf,
  1773. u32 changes)
  1774. {
  1775. struct iwl_priv *priv = hw->priv;
  1776. int ret;
  1777. IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
  1778. if (!iwl_is_alive(priv))
  1779. return;
  1780. mutex_lock(&priv->mutex);
  1781. if (changes & BSS_CHANGED_BEACON &&
  1782. priv->iw_mode == NL80211_IFTYPE_AP) {
  1783. dev_kfree_skb(priv->ibss_beacon);
  1784. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  1785. }
  1786. if (changes & BSS_CHANGED_BEACON_INT) {
  1787. priv->beacon_int = bss_conf->beacon_int;
  1788. /* TODO: in AP mode, do something to make this take effect */
  1789. }
  1790. if (changes & BSS_CHANGED_BSSID) {
  1791. IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
  1792. /*
  1793. * If there is currently a HW scan going on in the
  1794. * background then we need to cancel it else the RXON
  1795. * below/in post_associate will fail.
  1796. */
  1797. if (iwl_scan_cancel_timeout(priv, 100)) {
  1798. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  1799. IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
  1800. mutex_unlock(&priv->mutex);
  1801. return;
  1802. }
  1803. /* mac80211 only sets assoc when in STATION mode */
  1804. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  1805. bss_conf->assoc) {
  1806. memcpy(priv->staging_rxon.bssid_addr,
  1807. bss_conf->bssid, ETH_ALEN);
  1808. /* currently needed in a few places */
  1809. memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
  1810. } else {
  1811. priv->staging_rxon.filter_flags &=
  1812. ~RXON_FILTER_ASSOC_MSK;
  1813. }
  1814. }
  1815. /*
  1816. * This needs to be after setting the BSSID in case
  1817. * mac80211 decides to do both changes at once because
  1818. * it will invoke post_associate.
  1819. */
  1820. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  1821. changes & BSS_CHANGED_BEACON) {
  1822. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  1823. if (beacon)
  1824. iwl_mac_beacon_update(hw, beacon);
  1825. }
  1826. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  1827. IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
  1828. bss_conf->use_short_preamble);
  1829. if (bss_conf->use_short_preamble)
  1830. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1831. else
  1832. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1833. }
  1834. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  1835. IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
  1836. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  1837. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  1838. else
  1839. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  1840. }
  1841. if (changes & BSS_CHANGED_BASIC_RATES) {
  1842. /* XXX use this information
  1843. *
  1844. * To do that, remove code from iwl_set_rate() and put something
  1845. * like this here:
  1846. *
  1847. if (A-band)
  1848. priv->staging_rxon.ofdm_basic_rates =
  1849. bss_conf->basic_rates;
  1850. else
  1851. priv->staging_rxon.ofdm_basic_rates =
  1852. bss_conf->basic_rates >> 4;
  1853. priv->staging_rxon.cck_basic_rates =
  1854. bss_conf->basic_rates & 0xF;
  1855. */
  1856. }
  1857. if (changes & BSS_CHANGED_HT) {
  1858. iwl_ht_conf(priv, bss_conf);
  1859. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1860. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1861. }
  1862. if (changes & BSS_CHANGED_ASSOC) {
  1863. IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
  1864. if (bss_conf->assoc) {
  1865. priv->assoc_id = bss_conf->aid;
  1866. priv->beacon_int = bss_conf->beacon_int;
  1867. priv->timestamp = bss_conf->timestamp;
  1868. priv->assoc_capability = bss_conf->assoc_capability;
  1869. iwl_led_associate(priv);
  1870. /*
  1871. * We have just associated, don't start scan too early
  1872. * leave time for EAPOL exchange to complete.
  1873. *
  1874. * XXX: do this in mac80211
  1875. */
  1876. priv->next_scan_jiffies = jiffies +
  1877. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  1878. if (!iwl_is_rfkill(priv))
  1879. priv->cfg->ops->lib->post_associate(priv);
  1880. } else
  1881. iwl_set_no_assoc(priv);
  1882. }
  1883. if (changes && iwl_is_associated(priv) && priv->assoc_id) {
  1884. IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
  1885. changes);
  1886. ret = iwl_send_rxon_assoc(priv);
  1887. if (!ret) {
  1888. /* Sync active_rxon with latest change. */
  1889. memcpy((void *)&priv->active_rxon,
  1890. &priv->staging_rxon,
  1891. sizeof(struct iwl_rxon_cmd));
  1892. }
  1893. }
  1894. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  1895. if (vif->bss_conf.enable_beacon) {
  1896. memcpy(priv->staging_rxon.bssid_addr,
  1897. bss_conf->bssid, ETH_ALEN);
  1898. memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
  1899. iwlcore_config_ap(priv);
  1900. } else
  1901. iwl_set_no_assoc(priv);
  1902. }
  1903. mutex_unlock(&priv->mutex);
  1904. IWL_DEBUG_MAC80211(priv, "leave\n");
  1905. }
  1906. EXPORT_SYMBOL(iwl_bss_info_changed);
  1907. int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  1908. {
  1909. struct iwl_priv *priv = hw->priv;
  1910. unsigned long flags;
  1911. __le64 timestamp;
  1912. IWL_DEBUG_MAC80211(priv, "enter\n");
  1913. if (!iwl_is_ready_rf(priv)) {
  1914. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  1915. return -EIO;
  1916. }
  1917. spin_lock_irqsave(&priv->lock, flags);
  1918. if (priv->ibss_beacon)
  1919. dev_kfree_skb(priv->ibss_beacon);
  1920. priv->ibss_beacon = skb;
  1921. priv->assoc_id = 0;
  1922. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  1923. priv->timestamp = le64_to_cpu(timestamp);
  1924. IWL_DEBUG_MAC80211(priv, "leave\n");
  1925. spin_unlock_irqrestore(&priv->lock, flags);
  1926. iwl_reset_qos(priv);
  1927. priv->cfg->ops->lib->post_associate(priv);
  1928. return 0;
  1929. }
  1930. EXPORT_SYMBOL(iwl_mac_beacon_update);
  1931. int iwl_set_mode(struct iwl_priv *priv, int mode)
  1932. {
  1933. if (mode == NL80211_IFTYPE_ADHOC) {
  1934. const struct iwl_channel_info *ch_info;
  1935. ch_info = iwl_get_channel_info(priv,
  1936. priv->band,
  1937. le16_to_cpu(priv->staging_rxon.channel));
  1938. if (!ch_info || !is_channel_ibss(ch_info)) {
  1939. IWL_ERR(priv, "channel %d not IBSS channel\n",
  1940. le16_to_cpu(priv->staging_rxon.channel));
  1941. return -EINVAL;
  1942. }
  1943. }
  1944. iwl_connection_init_rx_config(priv, mode);
  1945. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1946. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1947. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1948. iwl_clear_stations_table(priv);
  1949. /* dont commit rxon if rf-kill is on*/
  1950. if (!iwl_is_ready_rf(priv))
  1951. return -EAGAIN;
  1952. iwlcore_commit_rxon(priv);
  1953. return 0;
  1954. }
  1955. EXPORT_SYMBOL(iwl_set_mode);
  1956. int iwl_mac_add_interface(struct ieee80211_hw *hw,
  1957. struct ieee80211_vif *vif)
  1958. {
  1959. struct iwl_priv *priv = hw->priv;
  1960. int err = 0;
  1961. IWL_DEBUG_MAC80211(priv, "enter: type %d\n", vif->type);
  1962. mutex_lock(&priv->mutex);
  1963. if (priv->vif) {
  1964. IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
  1965. err = -EOPNOTSUPP;
  1966. goto out;
  1967. }
  1968. priv->vif = vif;
  1969. priv->iw_mode = vif->type;
  1970. if (vif->addr) {
  1971. IWL_DEBUG_MAC80211(priv, "Set %pM\n", vif->addr);
  1972. memcpy(priv->mac_addr, vif->addr, ETH_ALEN);
  1973. }
  1974. if (iwl_set_mode(priv, vif->type) == -EAGAIN)
  1975. /* we are not ready, will run again when ready */
  1976. set_bit(STATUS_MODE_PENDING, &priv->status);
  1977. out:
  1978. mutex_unlock(&priv->mutex);
  1979. IWL_DEBUG_MAC80211(priv, "leave\n");
  1980. return err;
  1981. }
  1982. EXPORT_SYMBOL(iwl_mac_add_interface);
  1983. void iwl_mac_remove_interface(struct ieee80211_hw *hw,
  1984. struct ieee80211_vif *vif)
  1985. {
  1986. struct iwl_priv *priv = hw->priv;
  1987. IWL_DEBUG_MAC80211(priv, "enter\n");
  1988. mutex_lock(&priv->mutex);
  1989. if (iwl_is_ready_rf(priv)) {
  1990. iwl_scan_cancel_timeout(priv, 100);
  1991. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1992. iwlcore_commit_rxon(priv);
  1993. }
  1994. if (priv->vif == vif) {
  1995. priv->vif = NULL;
  1996. memset(priv->bssid, 0, ETH_ALEN);
  1997. }
  1998. mutex_unlock(&priv->mutex);
  1999. IWL_DEBUG_MAC80211(priv, "leave\n");
  2000. }
  2001. EXPORT_SYMBOL(iwl_mac_remove_interface);
  2002. /**
  2003. * iwl_mac_config - mac80211 config callback
  2004. *
  2005. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  2006. * be set inappropriately and the driver currently sets the hardware up to
  2007. * use it whenever needed.
  2008. */
  2009. int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
  2010. {
  2011. struct iwl_priv *priv = hw->priv;
  2012. const struct iwl_channel_info *ch_info;
  2013. struct ieee80211_conf *conf = &hw->conf;
  2014. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  2015. unsigned long flags = 0;
  2016. int ret = 0;
  2017. u16 ch;
  2018. int scan_active = 0;
  2019. mutex_lock(&priv->mutex);
  2020. IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
  2021. conf->channel->hw_value, changed);
  2022. if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
  2023. test_bit(STATUS_SCANNING, &priv->status))) {
  2024. scan_active = 1;
  2025. IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
  2026. }
  2027. if (changed & (IEEE80211_CONF_CHANGE_SMPS |
  2028. IEEE80211_CONF_CHANGE_CHANNEL)) {
  2029. /* mac80211 uses static for non-HT which is what we want */
  2030. priv->current_ht_config.smps = conf->smps_mode;
  2031. /*
  2032. * Recalculate chain counts.
  2033. *
  2034. * If monitor mode is enabled then mac80211 will
  2035. * set up the SM PS mode to OFF if an HT channel is
  2036. * configured.
  2037. */
  2038. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2039. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2040. }
  2041. /* during scanning mac80211 will delay channel setting until
  2042. * scan finish with changed = 0
  2043. */
  2044. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  2045. if (scan_active)
  2046. goto set_ch_out;
  2047. ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
  2048. ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
  2049. if (!is_channel_valid(ch_info)) {
  2050. IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
  2051. ret = -EINVAL;
  2052. goto set_ch_out;
  2053. }
  2054. spin_lock_irqsave(&priv->lock, flags);
  2055. /* Configure HT40 channels */
  2056. ht_conf->is_ht = conf_is_ht(conf);
  2057. if (ht_conf->is_ht) {
  2058. if (conf_is_ht40_minus(conf)) {
  2059. ht_conf->extension_chan_offset =
  2060. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2061. ht_conf->is_40mhz = true;
  2062. } else if (conf_is_ht40_plus(conf)) {
  2063. ht_conf->extension_chan_offset =
  2064. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2065. ht_conf->is_40mhz = true;
  2066. } else {
  2067. ht_conf->extension_chan_offset =
  2068. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2069. ht_conf->is_40mhz = false;
  2070. }
  2071. } else
  2072. ht_conf->is_40mhz = false;
  2073. /* Default to no protection. Protection mode will later be set
  2074. * from BSS config in iwl_ht_conf */
  2075. ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
  2076. /* if we are switching from ht to 2.4 clear flags
  2077. * from any ht related info since 2.4 does not
  2078. * support ht */
  2079. if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
  2080. priv->staging_rxon.flags = 0;
  2081. iwl_set_rxon_channel(priv, conf->channel);
  2082. iwl_set_rxon_ht(priv, ht_conf);
  2083. iwl_set_flags_for_band(priv, conf->channel->band);
  2084. spin_unlock_irqrestore(&priv->lock, flags);
  2085. if (iwl_is_associated(priv) &&
  2086. (le16_to_cpu(priv->active_rxon.channel) != ch) &&
  2087. priv->cfg->ops->lib->set_channel_switch) {
  2088. iwl_set_rate(priv);
  2089. /*
  2090. * at this point, staging_rxon has the
  2091. * configuration for channel switch
  2092. */
  2093. ret = priv->cfg->ops->lib->set_channel_switch(priv,
  2094. ch);
  2095. if (!ret) {
  2096. iwl_print_rx_config_cmd(priv);
  2097. goto out;
  2098. }
  2099. priv->switch_rxon.switch_in_progress = false;
  2100. }
  2101. set_ch_out:
  2102. /* The list of supported rates and rate mask can be different
  2103. * for each band; since the band may have changed, reset
  2104. * the rate mask to what mac80211 lists */
  2105. iwl_set_rate(priv);
  2106. }
  2107. if (changed & (IEEE80211_CONF_CHANGE_PS |
  2108. IEEE80211_CONF_CHANGE_IDLE)) {
  2109. ret = iwl_power_update_mode(priv, false);
  2110. if (ret)
  2111. IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
  2112. }
  2113. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  2114. IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
  2115. priv->tx_power_user_lmt, conf->power_level);
  2116. iwl_set_tx_power(priv, conf->power_level, false);
  2117. }
  2118. if (!iwl_is_ready(priv)) {
  2119. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2120. goto out;
  2121. }
  2122. if (scan_active)
  2123. goto out;
  2124. if (memcmp(&priv->active_rxon,
  2125. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  2126. iwlcore_commit_rxon(priv);
  2127. else
  2128. IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
  2129. out:
  2130. IWL_DEBUG_MAC80211(priv, "leave\n");
  2131. mutex_unlock(&priv->mutex);
  2132. return ret;
  2133. }
  2134. EXPORT_SYMBOL(iwl_mac_config);
  2135. void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
  2136. {
  2137. struct iwl_priv *priv = hw->priv;
  2138. unsigned long flags;
  2139. mutex_lock(&priv->mutex);
  2140. IWL_DEBUG_MAC80211(priv, "enter\n");
  2141. spin_lock_irqsave(&priv->lock, flags);
  2142. memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
  2143. spin_unlock_irqrestore(&priv->lock, flags);
  2144. iwl_reset_qos(priv);
  2145. spin_lock_irqsave(&priv->lock, flags);
  2146. priv->assoc_id = 0;
  2147. priv->assoc_capability = 0;
  2148. priv->assoc_station_added = 0;
  2149. /* new association get rid of ibss beacon skb */
  2150. if (priv->ibss_beacon)
  2151. dev_kfree_skb(priv->ibss_beacon);
  2152. priv->ibss_beacon = NULL;
  2153. priv->beacon_int = priv->vif->bss_conf.beacon_int;
  2154. priv->timestamp = 0;
  2155. spin_unlock_irqrestore(&priv->lock, flags);
  2156. if (!iwl_is_ready_rf(priv)) {
  2157. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2158. mutex_unlock(&priv->mutex);
  2159. return;
  2160. }
  2161. /* we are restarting association process
  2162. * clear RXON_FILTER_ASSOC_MSK bit
  2163. */
  2164. iwl_scan_cancel_timeout(priv, 100);
  2165. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2166. iwlcore_commit_rxon(priv);
  2167. iwl_set_rate(priv);
  2168. mutex_unlock(&priv->mutex);
  2169. IWL_DEBUG_MAC80211(priv, "leave\n");
  2170. }
  2171. EXPORT_SYMBOL(iwl_mac_reset_tsf);
  2172. int iwl_alloc_txq_mem(struct iwl_priv *priv)
  2173. {
  2174. if (!priv->txq)
  2175. priv->txq = kzalloc(
  2176. sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues,
  2177. GFP_KERNEL);
  2178. if (!priv->txq) {
  2179. IWL_ERR(priv, "Not enough memory for txq \n");
  2180. return -ENOMEM;
  2181. }
  2182. return 0;
  2183. }
  2184. EXPORT_SYMBOL(iwl_alloc_txq_mem);
  2185. void iwl_free_txq_mem(struct iwl_priv *priv)
  2186. {
  2187. kfree(priv->txq);
  2188. priv->txq = NULL;
  2189. }
  2190. EXPORT_SYMBOL(iwl_free_txq_mem);
  2191. int iwl_send_wimax_coex(struct iwl_priv *priv)
  2192. {
  2193. struct iwl_wimax_coex_cmd uninitialized_var(coex_cmd);
  2194. if (priv->cfg->support_wimax_coexist) {
  2195. /* UnMask wake up src at associated sleep */
  2196. coex_cmd.flags |= COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
  2197. /* UnMask wake up src at unassociated sleep */
  2198. coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
  2199. memcpy(coex_cmd.sta_prio, cu_priorities,
  2200. sizeof(struct iwl_wimax_coex_event_entry) *
  2201. COEX_NUM_OF_EVENTS);
  2202. /* enabling the coexistence feature */
  2203. coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
  2204. /* enabling the priorities tables */
  2205. coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
  2206. } else {
  2207. /* coexistence is disabled */
  2208. memset(&coex_cmd, 0, sizeof(coex_cmd));
  2209. }
  2210. return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
  2211. sizeof(coex_cmd), &coex_cmd);
  2212. }
  2213. EXPORT_SYMBOL(iwl_send_wimax_coex);
  2214. #ifdef CONFIG_IWLWIFI_DEBUGFS
  2215. #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
  2216. void iwl_reset_traffic_log(struct iwl_priv *priv)
  2217. {
  2218. priv->tx_traffic_idx = 0;
  2219. priv->rx_traffic_idx = 0;
  2220. if (priv->tx_traffic)
  2221. memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  2222. if (priv->rx_traffic)
  2223. memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  2224. }
  2225. int iwl_alloc_traffic_mem(struct iwl_priv *priv)
  2226. {
  2227. u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
  2228. if (iwl_debug_level & IWL_DL_TX) {
  2229. if (!priv->tx_traffic) {
  2230. priv->tx_traffic =
  2231. kzalloc(traffic_size, GFP_KERNEL);
  2232. if (!priv->tx_traffic)
  2233. return -ENOMEM;
  2234. }
  2235. }
  2236. if (iwl_debug_level & IWL_DL_RX) {
  2237. if (!priv->rx_traffic) {
  2238. priv->rx_traffic =
  2239. kzalloc(traffic_size, GFP_KERNEL);
  2240. if (!priv->rx_traffic)
  2241. return -ENOMEM;
  2242. }
  2243. }
  2244. iwl_reset_traffic_log(priv);
  2245. return 0;
  2246. }
  2247. EXPORT_SYMBOL(iwl_alloc_traffic_mem);
  2248. void iwl_free_traffic_mem(struct iwl_priv *priv)
  2249. {
  2250. kfree(priv->tx_traffic);
  2251. priv->tx_traffic = NULL;
  2252. kfree(priv->rx_traffic);
  2253. priv->rx_traffic = NULL;
  2254. }
  2255. EXPORT_SYMBOL(iwl_free_traffic_mem);
  2256. void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
  2257. u16 length, struct ieee80211_hdr *header)
  2258. {
  2259. __le16 fc;
  2260. u16 len;
  2261. if (likely(!(iwl_debug_level & IWL_DL_TX)))
  2262. return;
  2263. if (!priv->tx_traffic)
  2264. return;
  2265. fc = header->frame_control;
  2266. if (ieee80211_is_data(fc)) {
  2267. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  2268. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  2269. memcpy((priv->tx_traffic +
  2270. (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  2271. header, len);
  2272. priv->tx_traffic_idx =
  2273. (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  2274. }
  2275. }
  2276. EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
  2277. void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
  2278. u16 length, struct ieee80211_hdr *header)
  2279. {
  2280. __le16 fc;
  2281. u16 len;
  2282. if (likely(!(iwl_debug_level & IWL_DL_RX)))
  2283. return;
  2284. if (!priv->rx_traffic)
  2285. return;
  2286. fc = header->frame_control;
  2287. if (ieee80211_is_data(fc)) {
  2288. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  2289. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  2290. memcpy((priv->rx_traffic +
  2291. (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  2292. header, len);
  2293. priv->rx_traffic_idx =
  2294. (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  2295. }
  2296. }
  2297. EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
  2298. const char *get_mgmt_string(int cmd)
  2299. {
  2300. switch (cmd) {
  2301. IWL_CMD(MANAGEMENT_ASSOC_REQ);
  2302. IWL_CMD(MANAGEMENT_ASSOC_RESP);
  2303. IWL_CMD(MANAGEMENT_REASSOC_REQ);
  2304. IWL_CMD(MANAGEMENT_REASSOC_RESP);
  2305. IWL_CMD(MANAGEMENT_PROBE_REQ);
  2306. IWL_CMD(MANAGEMENT_PROBE_RESP);
  2307. IWL_CMD(MANAGEMENT_BEACON);
  2308. IWL_CMD(MANAGEMENT_ATIM);
  2309. IWL_CMD(MANAGEMENT_DISASSOC);
  2310. IWL_CMD(MANAGEMENT_AUTH);
  2311. IWL_CMD(MANAGEMENT_DEAUTH);
  2312. IWL_CMD(MANAGEMENT_ACTION);
  2313. default:
  2314. return "UNKNOWN";
  2315. }
  2316. }
  2317. const char *get_ctrl_string(int cmd)
  2318. {
  2319. switch (cmd) {
  2320. IWL_CMD(CONTROL_BACK_REQ);
  2321. IWL_CMD(CONTROL_BACK);
  2322. IWL_CMD(CONTROL_PSPOLL);
  2323. IWL_CMD(CONTROL_RTS);
  2324. IWL_CMD(CONTROL_CTS);
  2325. IWL_CMD(CONTROL_ACK);
  2326. IWL_CMD(CONTROL_CFEND);
  2327. IWL_CMD(CONTROL_CFENDACK);
  2328. default:
  2329. return "UNKNOWN";
  2330. }
  2331. }
  2332. void iwl_clear_traffic_stats(struct iwl_priv *priv)
  2333. {
  2334. memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
  2335. memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
  2336. priv->led_tpt = 0;
  2337. }
  2338. /*
  2339. * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
  2340. * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
  2341. * Use debugFs to display the rx/rx_statistics
  2342. * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
  2343. * information will be recorded, but DATA pkt still will be recorded
  2344. * for the reason of iwl_led.c need to control the led blinking based on
  2345. * number of tx and rx data.
  2346. *
  2347. */
  2348. void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
  2349. {
  2350. struct traffic_stats *stats;
  2351. if (is_tx)
  2352. stats = &priv->tx_stats;
  2353. else
  2354. stats = &priv->rx_stats;
  2355. if (ieee80211_is_mgmt(fc)) {
  2356. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  2357. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  2358. stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
  2359. break;
  2360. case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
  2361. stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
  2362. break;
  2363. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  2364. stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
  2365. break;
  2366. case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
  2367. stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
  2368. break;
  2369. case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
  2370. stats->mgmt[MANAGEMENT_PROBE_REQ]++;
  2371. break;
  2372. case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
  2373. stats->mgmt[MANAGEMENT_PROBE_RESP]++;
  2374. break;
  2375. case cpu_to_le16(IEEE80211_STYPE_BEACON):
  2376. stats->mgmt[MANAGEMENT_BEACON]++;
  2377. break;
  2378. case cpu_to_le16(IEEE80211_STYPE_ATIM):
  2379. stats->mgmt[MANAGEMENT_ATIM]++;
  2380. break;
  2381. case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
  2382. stats->mgmt[MANAGEMENT_DISASSOC]++;
  2383. break;
  2384. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  2385. stats->mgmt[MANAGEMENT_AUTH]++;
  2386. break;
  2387. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  2388. stats->mgmt[MANAGEMENT_DEAUTH]++;
  2389. break;
  2390. case cpu_to_le16(IEEE80211_STYPE_ACTION):
  2391. stats->mgmt[MANAGEMENT_ACTION]++;
  2392. break;
  2393. }
  2394. } else if (ieee80211_is_ctl(fc)) {
  2395. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  2396. case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
  2397. stats->ctrl[CONTROL_BACK_REQ]++;
  2398. break;
  2399. case cpu_to_le16(IEEE80211_STYPE_BACK):
  2400. stats->ctrl[CONTROL_BACK]++;
  2401. break;
  2402. case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
  2403. stats->ctrl[CONTROL_PSPOLL]++;
  2404. break;
  2405. case cpu_to_le16(IEEE80211_STYPE_RTS):
  2406. stats->ctrl[CONTROL_RTS]++;
  2407. break;
  2408. case cpu_to_le16(IEEE80211_STYPE_CTS):
  2409. stats->ctrl[CONTROL_CTS]++;
  2410. break;
  2411. case cpu_to_le16(IEEE80211_STYPE_ACK):
  2412. stats->ctrl[CONTROL_ACK]++;
  2413. break;
  2414. case cpu_to_le16(IEEE80211_STYPE_CFEND):
  2415. stats->ctrl[CONTROL_CFEND]++;
  2416. break;
  2417. case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
  2418. stats->ctrl[CONTROL_CFENDACK]++;
  2419. break;
  2420. }
  2421. } else {
  2422. /* data */
  2423. stats->data_cnt++;
  2424. stats->data_bytes += len;
  2425. }
  2426. iwl_leds_background(priv);
  2427. }
  2428. EXPORT_SYMBOL(iwl_update_stats);
  2429. #endif
  2430. const static char *get_csr_string(int cmd)
  2431. {
  2432. switch (cmd) {
  2433. IWL_CMD(CSR_HW_IF_CONFIG_REG);
  2434. IWL_CMD(CSR_INT_COALESCING);
  2435. IWL_CMD(CSR_INT);
  2436. IWL_CMD(CSR_INT_MASK);
  2437. IWL_CMD(CSR_FH_INT_STATUS);
  2438. IWL_CMD(CSR_GPIO_IN);
  2439. IWL_CMD(CSR_RESET);
  2440. IWL_CMD(CSR_GP_CNTRL);
  2441. IWL_CMD(CSR_HW_REV);
  2442. IWL_CMD(CSR_EEPROM_REG);
  2443. IWL_CMD(CSR_EEPROM_GP);
  2444. IWL_CMD(CSR_OTP_GP_REG);
  2445. IWL_CMD(CSR_GIO_REG);
  2446. IWL_CMD(CSR_GP_UCODE_REG);
  2447. IWL_CMD(CSR_GP_DRIVER_REG);
  2448. IWL_CMD(CSR_UCODE_DRV_GP1);
  2449. IWL_CMD(CSR_UCODE_DRV_GP2);
  2450. IWL_CMD(CSR_LED_REG);
  2451. IWL_CMD(CSR_DRAM_INT_TBL_REG);
  2452. IWL_CMD(CSR_GIO_CHICKEN_BITS);
  2453. IWL_CMD(CSR_ANA_PLL_CFG);
  2454. IWL_CMD(CSR_HW_REV_WA_REG);
  2455. IWL_CMD(CSR_DBG_HPET_MEM_REG);
  2456. default:
  2457. return "UNKNOWN";
  2458. }
  2459. }
  2460. void iwl_dump_csr(struct iwl_priv *priv)
  2461. {
  2462. int i;
  2463. u32 csr_tbl[] = {
  2464. CSR_HW_IF_CONFIG_REG,
  2465. CSR_INT_COALESCING,
  2466. CSR_INT,
  2467. CSR_INT_MASK,
  2468. CSR_FH_INT_STATUS,
  2469. CSR_GPIO_IN,
  2470. CSR_RESET,
  2471. CSR_GP_CNTRL,
  2472. CSR_HW_REV,
  2473. CSR_EEPROM_REG,
  2474. CSR_EEPROM_GP,
  2475. CSR_OTP_GP_REG,
  2476. CSR_GIO_REG,
  2477. CSR_GP_UCODE_REG,
  2478. CSR_GP_DRIVER_REG,
  2479. CSR_UCODE_DRV_GP1,
  2480. CSR_UCODE_DRV_GP2,
  2481. CSR_LED_REG,
  2482. CSR_DRAM_INT_TBL_REG,
  2483. CSR_GIO_CHICKEN_BITS,
  2484. CSR_ANA_PLL_CFG,
  2485. CSR_HW_REV_WA_REG,
  2486. CSR_DBG_HPET_MEM_REG
  2487. };
  2488. IWL_ERR(priv, "CSR values:\n");
  2489. IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
  2490. "CSR_INT_PERIODIC_REG)\n");
  2491. for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
  2492. IWL_ERR(priv, " %25s: 0X%08x\n",
  2493. get_csr_string(csr_tbl[i]),
  2494. iwl_read32(priv, csr_tbl[i]));
  2495. }
  2496. }
  2497. EXPORT_SYMBOL(iwl_dump_csr);
  2498. const static char *get_fh_string(int cmd)
  2499. {
  2500. switch (cmd) {
  2501. IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
  2502. IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
  2503. IWL_CMD(FH_RSCSR_CHNL0_WPTR);
  2504. IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
  2505. IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
  2506. IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
  2507. IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
  2508. IWL_CMD(FH_TSSR_TX_STATUS_REG);
  2509. IWL_CMD(FH_TSSR_TX_ERROR_REG);
  2510. default:
  2511. return "UNKNOWN";
  2512. }
  2513. }
  2514. int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
  2515. {
  2516. int i;
  2517. #ifdef CONFIG_IWLWIFI_DEBUG
  2518. int pos = 0;
  2519. size_t bufsz = 0;
  2520. #endif
  2521. u32 fh_tbl[] = {
  2522. FH_RSCSR_CHNL0_STTS_WPTR_REG,
  2523. FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  2524. FH_RSCSR_CHNL0_WPTR,
  2525. FH_MEM_RCSR_CHNL0_CONFIG_REG,
  2526. FH_MEM_RSSR_SHARED_CTRL_REG,
  2527. FH_MEM_RSSR_RX_STATUS_REG,
  2528. FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
  2529. FH_TSSR_TX_STATUS_REG,
  2530. FH_TSSR_TX_ERROR_REG
  2531. };
  2532. #ifdef CONFIG_IWLWIFI_DEBUG
  2533. if (display) {
  2534. bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
  2535. *buf = kmalloc(bufsz, GFP_KERNEL);
  2536. if (!*buf)
  2537. return -ENOMEM;
  2538. pos += scnprintf(*buf + pos, bufsz - pos,
  2539. "FH register values:\n");
  2540. for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
  2541. pos += scnprintf(*buf + pos, bufsz - pos,
  2542. " %34s: 0X%08x\n",
  2543. get_fh_string(fh_tbl[i]),
  2544. iwl_read_direct32(priv, fh_tbl[i]));
  2545. }
  2546. return pos;
  2547. }
  2548. #endif
  2549. IWL_ERR(priv, "FH register values:\n");
  2550. for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
  2551. IWL_ERR(priv, " %34s: 0X%08x\n",
  2552. get_fh_string(fh_tbl[i]),
  2553. iwl_read_direct32(priv, fh_tbl[i]));
  2554. }
  2555. return 0;
  2556. }
  2557. EXPORT_SYMBOL(iwl_dump_fh);
  2558. static void iwl_force_rf_reset(struct iwl_priv *priv)
  2559. {
  2560. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2561. return;
  2562. if (!iwl_is_associated(priv)) {
  2563. IWL_DEBUG_SCAN(priv, "force reset rejected: not associated\n");
  2564. return;
  2565. }
  2566. /*
  2567. * There is no easy and better way to force reset the radio,
  2568. * the only known method is switching channel which will force to
  2569. * reset and tune the radio.
  2570. * Use internal short scan (single channel) operation to should
  2571. * achieve this objective.
  2572. * Driver should reset the radio when number of consecutive missed
  2573. * beacon, or any other uCode error condition detected.
  2574. */
  2575. IWL_DEBUG_INFO(priv, "perform radio reset.\n");
  2576. iwl_internal_short_hw_scan(priv);
  2577. return;
  2578. }
  2579. int iwl_force_reset(struct iwl_priv *priv, int mode)
  2580. {
  2581. struct iwl_force_reset *force_reset;
  2582. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2583. return -EINVAL;
  2584. if (mode >= IWL_MAX_FORCE_RESET) {
  2585. IWL_DEBUG_INFO(priv, "invalid reset request.\n");
  2586. return -EINVAL;
  2587. }
  2588. force_reset = &priv->force_reset[mode];
  2589. force_reset->reset_request_count++;
  2590. if (force_reset->last_force_reset_jiffies &&
  2591. time_after(force_reset->last_force_reset_jiffies +
  2592. force_reset->reset_duration, jiffies)) {
  2593. IWL_DEBUG_INFO(priv, "force reset rejected\n");
  2594. force_reset->reset_reject_count++;
  2595. return -EAGAIN;
  2596. }
  2597. force_reset->reset_success_count++;
  2598. force_reset->last_force_reset_jiffies = jiffies;
  2599. IWL_DEBUG_INFO(priv, "perform force reset (%d)\n", mode);
  2600. switch (mode) {
  2601. case IWL_RF_RESET:
  2602. iwl_force_rf_reset(priv);
  2603. break;
  2604. case IWL_FW_RESET:
  2605. IWL_ERR(priv, "On demand firmware reload\n");
  2606. /* Set the FW error flag -- cleared on iwl_down */
  2607. set_bit(STATUS_FW_ERROR, &priv->status);
  2608. wake_up_interruptible(&priv->wait_command_queue);
  2609. /*
  2610. * Keep the restart process from trying to send host
  2611. * commands by clearing the INIT status bit
  2612. */
  2613. clear_bit(STATUS_READY, &priv->status);
  2614. queue_work(priv->workqueue, &priv->restart);
  2615. break;
  2616. }
  2617. return 0;
  2618. }
  2619. #ifdef CONFIG_PM
  2620. int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  2621. {
  2622. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2623. /*
  2624. * This function is called when system goes into suspend state
  2625. * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
  2626. * first but since iwl_mac_stop() has no knowledge of who the caller is,
  2627. * it will not call apm_ops.stop() to stop the DMA operation.
  2628. * Calling apm_ops.stop here to make sure we stop the DMA.
  2629. */
  2630. priv->cfg->ops->lib->apm_ops.stop(priv);
  2631. pci_save_state(pdev);
  2632. pci_disable_device(pdev);
  2633. pci_set_power_state(pdev, PCI_D3hot);
  2634. return 0;
  2635. }
  2636. EXPORT_SYMBOL(iwl_pci_suspend);
  2637. int iwl_pci_resume(struct pci_dev *pdev)
  2638. {
  2639. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2640. int ret;
  2641. pci_set_power_state(pdev, PCI_D0);
  2642. ret = pci_enable_device(pdev);
  2643. if (ret)
  2644. return ret;
  2645. pci_restore_state(pdev);
  2646. iwl_enable_interrupts(priv);
  2647. return 0;
  2648. }
  2649. EXPORT_SYMBOL(iwl_pci_resume);
  2650. #endif /* CONFIG_PM */