cm_bf533.c 9.6 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf533/boards/cm_bf533.c
  3. * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
  4. * Author: Aidan Williams <aidan@nicta.com.au> Copyright 2005
  5. *
  6. * Created: 2005
  7. * Description: Board description file
  8. *
  9. * Modified:
  10. * Copyright 2004-2006 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <linux/device.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/mtd/mtd.h>
  32. #include <linux/mtd/partitions.h>
  33. #include <linux/spi/spi.h>
  34. #include <linux/spi/flash.h>
  35. #include <linux/usb_isp1362.h>
  36. #include <linux/pata_platform.h>
  37. #include <linux/irq.h>
  38. #include <asm/dma.h>
  39. #include <asm/bfin5xx_spi.h>
  40. /*
  41. * Name the Board for the /proc/cpuinfo
  42. */
  43. const char bfin_board_name[] = "Bluetechnix CM BF533";
  44. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  45. /* all SPI peripherals info goes here */
  46. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  47. static struct mtd_partition bfin_spi_flash_partitions[] = {
  48. {
  49. .name = "bootloader",
  50. .size = 0x00020000,
  51. .offset = 0,
  52. .mask_flags = MTD_CAP_ROM
  53. }, {
  54. .name = "kernel",
  55. .size = 0xe0000,
  56. .offset = 0x20000
  57. }, {
  58. .name = "file system",
  59. .size = 0x700000,
  60. .offset = 0x00100000,
  61. }
  62. };
  63. static struct flash_platform_data bfin_spi_flash_data = {
  64. .name = "m25p80",
  65. .parts = bfin_spi_flash_partitions,
  66. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  67. .type = "m25p64",
  68. };
  69. /* SPI flash chip (m25p64) */
  70. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  71. .enable_dma = 0, /* use dma transfer with this chip*/
  72. .bits_per_word = 8,
  73. };
  74. #endif
  75. /* SPI ADC chip */
  76. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  77. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  78. .enable_dma = 1, /* use dma transfer with this chip*/
  79. .bits_per_word = 16,
  80. };
  81. #endif
  82. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  83. static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
  84. .enable_dma = 0,
  85. .bits_per_word = 16,
  86. };
  87. #endif
  88. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  89. static struct bfin5xx_spi_chip spi_mmc_chip_info = {
  90. .enable_dma = 1,
  91. .bits_per_word = 8,
  92. };
  93. #endif
  94. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  95. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  96. {
  97. /* the modalias must be the same as spi device driver name */
  98. .modalias = "m25p80", /* Name of spi_driver for this device */
  99. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  100. .bus_num = 0, /* Framework bus number */
  101. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  102. .platform_data = &bfin_spi_flash_data,
  103. .controller_data = &spi_flash_chip_info,
  104. .mode = SPI_MODE_3,
  105. },
  106. #endif
  107. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  108. {
  109. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  110. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  111. .bus_num = 0, /* Framework bus number */
  112. .chip_select = 2, /* Framework chip select. */
  113. .platform_data = NULL, /* No spi_driver specific config */
  114. .controller_data = &spi_adc_chip_info,
  115. },
  116. #endif
  117. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  118. {
  119. .modalias = "ad1836-spi",
  120. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  121. .bus_num = 0,
  122. .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
  123. .controller_data = &ad1836_spi_chip_info,
  124. },
  125. #endif
  126. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  127. {
  128. .modalias = "spi_mmc_dummy",
  129. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  130. .bus_num = 0,
  131. .chip_select = 0,
  132. .platform_data = NULL,
  133. .controller_data = &spi_mmc_chip_info,
  134. .mode = SPI_MODE_3,
  135. },
  136. {
  137. .modalias = "spi_mmc",
  138. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  139. .bus_num = 0,
  140. .chip_select = CONFIG_SPI_MMC_CS_CHAN,
  141. .platform_data = NULL,
  142. .controller_data = &spi_mmc_chip_info,
  143. .mode = SPI_MODE_3,
  144. },
  145. #endif
  146. };
  147. /* SPI (0) */
  148. static struct resource bfin_spi0_resource[] = {
  149. [0] = {
  150. .start = SPI0_REGBASE,
  151. .end = SPI0_REGBASE + 0xFF,
  152. .flags = IORESOURCE_MEM,
  153. },
  154. [1] = {
  155. .start = CH_SPI,
  156. .end = CH_SPI,
  157. .flags = IORESOURCE_IRQ,
  158. }
  159. };
  160. /* SPI controller data */
  161. static struct bfin5xx_spi_master bfin_spi0_info = {
  162. .num_chipselect = 8,
  163. .enable_dma = 1, /* master has the ability to do dma transfer */
  164. };
  165. static struct platform_device bfin_spi0_device = {
  166. .name = "bfin-spi",
  167. .id = 0, /* Bus number */
  168. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  169. .resource = bfin_spi0_resource,
  170. .dev = {
  171. .platform_data = &bfin_spi0_info, /* Passed to driver */
  172. },
  173. };
  174. #endif /* spi master and devices */
  175. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  176. static struct platform_device rtc_device = {
  177. .name = "rtc-bfin",
  178. .id = -1,
  179. };
  180. #endif
  181. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  182. static struct resource smc91x_resources[] = {
  183. {
  184. .start = 0x20200300,
  185. .end = 0x20200300 + 16,
  186. .flags = IORESOURCE_MEM,
  187. }, {
  188. .start = IRQ_PF0,
  189. .end = IRQ_PF0,
  190. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  191. },
  192. };
  193. static struct platform_device smc91x_device = {
  194. .name = "smc91x",
  195. .id = 0,
  196. .num_resources = ARRAY_SIZE(smc91x_resources),
  197. .resource = smc91x_resources,
  198. };
  199. #endif
  200. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  201. static struct resource bfin_uart_resources[] = {
  202. {
  203. .start = 0xFFC00400,
  204. .end = 0xFFC004FF,
  205. .flags = IORESOURCE_MEM,
  206. },
  207. };
  208. static struct platform_device bfin_uart_device = {
  209. .name = "bfin-uart",
  210. .id = 1,
  211. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  212. .resource = bfin_uart_resources,
  213. };
  214. #endif
  215. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  216. static struct platform_device bfin_sport0_uart_device = {
  217. .name = "bfin-sport-uart",
  218. .id = 0,
  219. };
  220. static struct platform_device bfin_sport1_uart_device = {
  221. .name = "bfin-sport-uart",
  222. .id = 1,
  223. };
  224. #endif
  225. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  226. static struct resource isp1362_hcd_resources[] = {
  227. {
  228. .start = 0x20308000,
  229. .end = 0x20308000,
  230. .flags = IORESOURCE_MEM,
  231. }, {
  232. .start = 0x20308004,
  233. .end = 0x20308004,
  234. .flags = IORESOURCE_MEM,
  235. }, {
  236. .start = IRQ_PF4,
  237. .end = IRQ_PF4,
  238. .flags = IORESOURCE_IRQ,
  239. },
  240. };
  241. static struct isp1362_platform_data isp1362_priv = {
  242. .sel15Kres = 1,
  243. .clknotstop = 0,
  244. .oc_enable = 0,
  245. .int_act_high = 0,
  246. .int_edge_triggered = 0,
  247. .remote_wakeup_connected = 0,
  248. .no_power_switching = 1,
  249. .power_switching_mode = 0,
  250. };
  251. static struct platform_device isp1362_hcd_device = {
  252. .name = "isp1362-hcd",
  253. .id = 0,
  254. .dev = {
  255. .platform_data = &isp1362_priv,
  256. },
  257. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  258. .resource = isp1362_hcd_resources,
  259. };
  260. #endif
  261. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  262. #define PATA_INT 38
  263. static struct pata_platform_info bfin_pata_platform_data = {
  264. .ioport_shift = 2,
  265. .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
  266. };
  267. static struct resource bfin_pata_resources[] = {
  268. {
  269. .start = 0x2030C000,
  270. .end = 0x2030C01F,
  271. .flags = IORESOURCE_MEM,
  272. },
  273. {
  274. .start = 0x2030D018,
  275. .end = 0x2030D01B,
  276. .flags = IORESOURCE_MEM,
  277. },
  278. {
  279. .start = PATA_INT,
  280. .end = PATA_INT,
  281. .flags = IORESOURCE_IRQ,
  282. },
  283. };
  284. static struct platform_device bfin_pata_device = {
  285. .name = "pata_platform",
  286. .id = -1,
  287. .num_resources = ARRAY_SIZE(bfin_pata_resources),
  288. .resource = bfin_pata_resources,
  289. .dev = {
  290. .platform_data = &bfin_pata_platform_data,
  291. }
  292. };
  293. #endif
  294. static struct platform_device *cm_bf533_devices[] __initdata = {
  295. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  296. &bfin_uart_device,
  297. #endif
  298. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  299. &bfin_sport0_uart_device,
  300. &bfin_sport1_uart_device,
  301. #endif
  302. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  303. &rtc_device,
  304. #endif
  305. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  306. &isp1362_hcd_device,
  307. #endif
  308. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  309. &smc91x_device,
  310. #endif
  311. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  312. &bfin_spi0_device,
  313. #endif
  314. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  315. &bfin_pata_device,
  316. #endif
  317. };
  318. static int __init cm_bf533_init(void)
  319. {
  320. printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
  321. platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
  322. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  323. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  324. #endif
  325. #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
  326. irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
  327. #endif
  328. return 0;
  329. }
  330. arch_initcall(cm_bf533_init);