setup.c 37 KB

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  1. /*
  2. * arch/blackfin/kernel/setup.c
  3. *
  4. * Copyright 2004-2006 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/console.h>
  12. #include <linux/bootmem.h>
  13. #include <linux/seq_file.h>
  14. #include <linux/cpu.h>
  15. #include <linux/mm.h>
  16. #include <linux/module.h>
  17. #include <linux/tty.h>
  18. #include <linux/pfn.h>
  19. #ifdef CONFIG_MTD_UCLINUX
  20. #include <linux/mtd/map.h>
  21. #include <linux/ext2_fs.h>
  22. #include <linux/cramfs_fs.h>
  23. #include <linux/romfs_fs.h>
  24. #endif
  25. #include <asm/cplb.h>
  26. #include <asm/cacheflush.h>
  27. #include <asm/blackfin.h>
  28. #include <asm/cplbinit.h>
  29. #include <asm/div64.h>
  30. #include <asm/cpu.h>
  31. #include <asm/fixed_code.h>
  32. #include <asm/early_printk.h>
  33. u16 _bfin_swrst;
  34. EXPORT_SYMBOL(_bfin_swrst);
  35. unsigned long memory_start, memory_end, physical_mem_end;
  36. unsigned long _rambase, _ramstart, _ramend;
  37. unsigned long reserved_mem_dcache_on;
  38. unsigned long reserved_mem_icache_on;
  39. EXPORT_SYMBOL(memory_start);
  40. EXPORT_SYMBOL(memory_end);
  41. EXPORT_SYMBOL(physical_mem_end);
  42. EXPORT_SYMBOL(_ramend);
  43. EXPORT_SYMBOL(reserved_mem_dcache_on);
  44. #ifdef CONFIG_MTD_UCLINUX
  45. extern struct map_info uclinux_ram_map;
  46. unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
  47. unsigned long _ebss;
  48. EXPORT_SYMBOL(memory_mtd_end);
  49. EXPORT_SYMBOL(memory_mtd_start);
  50. EXPORT_SYMBOL(mtd_size);
  51. #endif
  52. char __initdata command_line[COMMAND_LINE_SIZE];
  53. void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat,
  54. *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr;
  55. /* boot memmap, for parsing "memmap=" */
  56. #define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
  57. #define BFIN_MEMMAP_RAM 1
  58. #define BFIN_MEMMAP_RESERVED 2
  59. static struct bfin_memmap {
  60. int nr_map;
  61. struct bfin_memmap_entry {
  62. unsigned long long addr; /* start of memory segment */
  63. unsigned long long size;
  64. unsigned long type;
  65. } map[BFIN_MEMMAP_MAX];
  66. } bfin_memmap __initdata;
  67. /* for memmap sanitization */
  68. struct change_member {
  69. struct bfin_memmap_entry *pentry; /* pointer to original entry */
  70. unsigned long long addr; /* address for this change point */
  71. };
  72. static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
  73. static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
  74. static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
  75. static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
  76. DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
  77. static int early_init_clkin_hz(char *buf);
  78. #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
  79. void __init generate_cplb_tables(void)
  80. {
  81. unsigned int cpu;
  82. generate_cplb_tables_all();
  83. /* Generate per-CPU I&D CPLB tables */
  84. for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
  85. generate_cplb_tables_cpu(cpu);
  86. }
  87. #endif
  88. void __cpuinit bfin_setup_caches(unsigned int cpu)
  89. {
  90. #ifdef CONFIG_BFIN_ICACHE
  91. bfin_icache_init(icplb_tbl[cpu]);
  92. #endif
  93. #ifdef CONFIG_BFIN_DCACHE
  94. bfin_dcache_init(dcplb_tbl[cpu]);
  95. #endif
  96. /*
  97. * In cache coherence emulation mode, we need to have the
  98. * D-cache enabled before running any atomic operation which
  99. * might invove cache invalidation (i.e. spinlock, rwlock).
  100. * So printk's are deferred until then.
  101. */
  102. #ifdef CONFIG_BFIN_ICACHE
  103. printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
  104. printk(KERN_INFO " External memory:"
  105. # ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
  106. " cacheable"
  107. # else
  108. " uncacheable"
  109. # endif
  110. " in instruction cache\n");
  111. if (L2_LENGTH)
  112. printk(KERN_INFO " L2 SRAM :"
  113. # ifdef CONFIG_BFIN_L2_ICACHEABLE
  114. " cacheable"
  115. # else
  116. " uncacheable"
  117. # endif
  118. " in instruction cache\n");
  119. #else
  120. printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
  121. #endif
  122. #ifdef CONFIG_BFIN_DCACHE
  123. printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
  124. printk(KERN_INFO " External memory:"
  125. # if defined CONFIG_BFIN_EXTMEM_WRITEBACK
  126. " cacheable (write-back)"
  127. # elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
  128. " cacheable (write-through)"
  129. # else
  130. " uncacheable"
  131. # endif
  132. " in data cache\n");
  133. if (L2_LENGTH)
  134. printk(KERN_INFO " L2 SRAM :"
  135. # if defined CONFIG_BFIN_L2_WRITEBACK
  136. " cacheable (write-back)"
  137. # elif defined CONFIG_BFIN_L2_WRITETHROUGH
  138. " cacheable (write-through)"
  139. # else
  140. " uncacheable"
  141. # endif
  142. " in data cache\n");
  143. #else
  144. printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
  145. #endif
  146. }
  147. void __cpuinit bfin_setup_cpudata(unsigned int cpu)
  148. {
  149. struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
  150. cpudata->idle = current;
  151. cpudata->loops_per_jiffy = loops_per_jiffy;
  152. cpudata->imemctl = bfin_read_IMEM_CONTROL();
  153. cpudata->dmemctl = bfin_read_DMEM_CONTROL();
  154. }
  155. void __init bfin_cache_init(void)
  156. {
  157. #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
  158. generate_cplb_tables();
  159. #endif
  160. bfin_setup_caches(0);
  161. }
  162. void __init bfin_relocate_l1_mem(void)
  163. {
  164. unsigned long l1_code_length;
  165. unsigned long l1_data_a_length;
  166. unsigned long l1_data_b_length;
  167. unsigned long l2_length;
  168. /*
  169. * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
  170. * we know that everything about l1 text/data is nice and aligned,
  171. * so copy by 4 byte chunks, and don't worry about overlapping
  172. * src/dest.
  173. *
  174. * We can't use the dma_memcpy functions, since they can call
  175. * scheduler functions which might be in L1 :( and core writes
  176. * into L1 instruction cause bad access errors, so we are stuck,
  177. * we are required to use DMA, but can't use the common dma
  178. * functions. We can't use memcpy either - since that might be
  179. * going to be in the relocated L1
  180. */
  181. blackfin_dma_early_init();
  182. /* if necessary, copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
  183. l1_code_length = _etext_l1 - _stext_l1;
  184. if (l1_code_length)
  185. early_dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
  186. /* if necessary, copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */
  187. l1_data_a_length = _sbss_l1 - _sdata_l1;
  188. if (l1_data_a_length)
  189. early_dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
  190. /* if necessary, copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */
  191. l1_data_b_length = _sbss_b_l1 - _sdata_b_l1;
  192. if (l1_data_b_length)
  193. early_dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
  194. l1_data_a_length, l1_data_b_length);
  195. early_dma_memcpy_done();
  196. /* if necessary, copy _stext_l2 to _edata_l2 to L2 SRAM */
  197. if (L2_LENGTH != 0) {
  198. l2_length = _sbss_l2 - _stext_l2;
  199. if (l2_length)
  200. memcpy(_stext_l2, _l2_lma_start, l2_length);
  201. }
  202. }
  203. /* add_memory_region to memmap */
  204. static void __init add_memory_region(unsigned long long start,
  205. unsigned long long size, int type)
  206. {
  207. int i;
  208. i = bfin_memmap.nr_map;
  209. if (i == BFIN_MEMMAP_MAX) {
  210. printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
  211. return;
  212. }
  213. bfin_memmap.map[i].addr = start;
  214. bfin_memmap.map[i].size = size;
  215. bfin_memmap.map[i].type = type;
  216. bfin_memmap.nr_map++;
  217. }
  218. /*
  219. * Sanitize the boot memmap, removing overlaps.
  220. */
  221. static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
  222. {
  223. struct change_member *change_tmp;
  224. unsigned long current_type, last_type;
  225. unsigned long long last_addr;
  226. int chgidx, still_changing;
  227. int overlap_entries;
  228. int new_entry;
  229. int old_nr, new_nr, chg_nr;
  230. int i;
  231. /*
  232. Visually we're performing the following (1,2,3,4 = memory types)
  233. Sample memory map (w/overlaps):
  234. ____22__________________
  235. ______________________4_
  236. ____1111________________
  237. _44_____________________
  238. 11111111________________
  239. ____________________33__
  240. ___________44___________
  241. __________33333_________
  242. ______________22________
  243. ___________________2222_
  244. _________111111111______
  245. _____________________11_
  246. _________________4______
  247. Sanitized equivalent (no overlap):
  248. 1_______________________
  249. _44_____________________
  250. ___1____________________
  251. ____22__________________
  252. ______11________________
  253. _________1______________
  254. __________3_____________
  255. ___________44___________
  256. _____________33_________
  257. _______________2________
  258. ________________1_______
  259. _________________4______
  260. ___________________2____
  261. ____________________33__
  262. ______________________4_
  263. */
  264. /* if there's only one memory region, don't bother */
  265. if (*pnr_map < 2)
  266. return -1;
  267. old_nr = *pnr_map;
  268. /* bail out if we find any unreasonable addresses in memmap */
  269. for (i = 0; i < old_nr; i++)
  270. if (map[i].addr + map[i].size < map[i].addr)
  271. return -1;
  272. /* create pointers for initial change-point information (for sorting) */
  273. for (i = 0; i < 2*old_nr; i++)
  274. change_point[i] = &change_point_list[i];
  275. /* record all known change-points (starting and ending addresses),
  276. omitting those that are for empty memory regions */
  277. chgidx = 0;
  278. for (i = 0; i < old_nr; i++) {
  279. if (map[i].size != 0) {
  280. change_point[chgidx]->addr = map[i].addr;
  281. change_point[chgidx++]->pentry = &map[i];
  282. change_point[chgidx]->addr = map[i].addr + map[i].size;
  283. change_point[chgidx++]->pentry = &map[i];
  284. }
  285. }
  286. chg_nr = chgidx; /* true number of change-points */
  287. /* sort change-point list by memory addresses (low -> high) */
  288. still_changing = 1;
  289. while (still_changing) {
  290. still_changing = 0;
  291. for (i = 1; i < chg_nr; i++) {
  292. /* if <current_addr> > <last_addr>, swap */
  293. /* or, if current=<start_addr> & last=<end_addr>, swap */
  294. if ((change_point[i]->addr < change_point[i-1]->addr) ||
  295. ((change_point[i]->addr == change_point[i-1]->addr) &&
  296. (change_point[i]->addr == change_point[i]->pentry->addr) &&
  297. (change_point[i-1]->addr != change_point[i-1]->pentry->addr))
  298. ) {
  299. change_tmp = change_point[i];
  300. change_point[i] = change_point[i-1];
  301. change_point[i-1] = change_tmp;
  302. still_changing = 1;
  303. }
  304. }
  305. }
  306. /* create a new memmap, removing overlaps */
  307. overlap_entries = 0; /* number of entries in the overlap table */
  308. new_entry = 0; /* index for creating new memmap entries */
  309. last_type = 0; /* start with undefined memory type */
  310. last_addr = 0; /* start with 0 as last starting address */
  311. /* loop through change-points, determining affect on the new memmap */
  312. for (chgidx = 0; chgidx < chg_nr; chgidx++) {
  313. /* keep track of all overlapping memmap entries */
  314. if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
  315. /* add map entry to overlap list (> 1 entry implies an overlap) */
  316. overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
  317. } else {
  318. /* remove entry from list (order independent, so swap with last) */
  319. for (i = 0; i < overlap_entries; i++) {
  320. if (overlap_list[i] == change_point[chgidx]->pentry)
  321. overlap_list[i] = overlap_list[overlap_entries-1];
  322. }
  323. overlap_entries--;
  324. }
  325. /* if there are overlapping entries, decide which "type" to use */
  326. /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
  327. current_type = 0;
  328. for (i = 0; i < overlap_entries; i++)
  329. if (overlap_list[i]->type > current_type)
  330. current_type = overlap_list[i]->type;
  331. /* continue building up new memmap based on this information */
  332. if (current_type != last_type) {
  333. if (last_type != 0) {
  334. new_map[new_entry].size =
  335. change_point[chgidx]->addr - last_addr;
  336. /* move forward only if the new size was non-zero */
  337. if (new_map[new_entry].size != 0)
  338. if (++new_entry >= BFIN_MEMMAP_MAX)
  339. break; /* no more space left for new entries */
  340. }
  341. if (current_type != 0) {
  342. new_map[new_entry].addr = change_point[chgidx]->addr;
  343. new_map[new_entry].type = current_type;
  344. last_addr = change_point[chgidx]->addr;
  345. }
  346. last_type = current_type;
  347. }
  348. }
  349. new_nr = new_entry; /* retain count for new entries */
  350. /* copy new mapping into original location */
  351. memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
  352. *pnr_map = new_nr;
  353. return 0;
  354. }
  355. static void __init print_memory_map(char *who)
  356. {
  357. int i;
  358. for (i = 0; i < bfin_memmap.nr_map; i++) {
  359. printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
  360. bfin_memmap.map[i].addr,
  361. bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
  362. switch (bfin_memmap.map[i].type) {
  363. case BFIN_MEMMAP_RAM:
  364. printk(KERN_CONT "(usable)\n");
  365. break;
  366. case BFIN_MEMMAP_RESERVED:
  367. printk(KERN_CONT "(reserved)\n");
  368. break;
  369. default:
  370. printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type);
  371. break;
  372. }
  373. }
  374. }
  375. static __init int parse_memmap(char *arg)
  376. {
  377. unsigned long long start_at, mem_size;
  378. if (!arg)
  379. return -EINVAL;
  380. mem_size = memparse(arg, &arg);
  381. if (*arg == '@') {
  382. start_at = memparse(arg+1, &arg);
  383. add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
  384. } else if (*arg == '$') {
  385. start_at = memparse(arg+1, &arg);
  386. add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
  387. }
  388. return 0;
  389. }
  390. /*
  391. * Initial parsing of the command line. Currently, we support:
  392. * - Controlling the linux memory size: mem=xxx[KMG]
  393. * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
  394. * $ -> reserved memory is dcacheable
  395. * # -> reserved memory is icacheable
  396. * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
  397. * @ from <start> to <start>+<mem>, type RAM
  398. * $ from <start> to <start>+<mem>, type RESERVED
  399. */
  400. static __init void parse_cmdline_early(char *cmdline_p)
  401. {
  402. char c = ' ', *to = cmdline_p;
  403. unsigned int memsize;
  404. for (;;) {
  405. if (c == ' ') {
  406. if (!memcmp(to, "mem=", 4)) {
  407. to += 4;
  408. memsize = memparse(to, &to);
  409. if (memsize)
  410. _ramend = memsize;
  411. } else if (!memcmp(to, "max_mem=", 8)) {
  412. to += 8;
  413. memsize = memparse(to, &to);
  414. if (memsize) {
  415. physical_mem_end = memsize;
  416. if (*to != ' ') {
  417. if (*to == '$'
  418. || *(to + 1) == '$')
  419. reserved_mem_dcache_on = 1;
  420. if (*to == '#'
  421. || *(to + 1) == '#')
  422. reserved_mem_icache_on = 1;
  423. }
  424. }
  425. } else if (!memcmp(to, "clkin_hz=", 9)) {
  426. to += 9;
  427. early_init_clkin_hz(to);
  428. #ifdef CONFIG_EARLY_PRINTK
  429. } else if (!memcmp(to, "earlyprintk=", 12)) {
  430. to += 12;
  431. setup_early_printk(to);
  432. #endif
  433. } else if (!memcmp(to, "memmap=", 7)) {
  434. to += 7;
  435. parse_memmap(to);
  436. }
  437. }
  438. c = *(to++);
  439. if (!c)
  440. break;
  441. }
  442. }
  443. /*
  444. * Setup memory defaults from user config.
  445. * The physical memory layout looks like:
  446. *
  447. * [_rambase, _ramstart]: kernel image
  448. * [memory_start, memory_end]: dynamic memory managed by kernel
  449. * [memory_end, _ramend]: reserved memory
  450. * [memory_mtd_start(memory_end),
  451. * memory_mtd_start + mtd_size]: rootfs (if any)
  452. * [_ramend - DMA_UNCACHED_REGION,
  453. * _ramend]: uncached DMA region
  454. * [_ramend, physical_mem_end]: memory not managed by kernel
  455. */
  456. static __init void memory_setup(void)
  457. {
  458. #ifdef CONFIG_MTD_UCLINUX
  459. unsigned long mtd_phys = 0;
  460. #endif
  461. _rambase = (unsigned long)_stext;
  462. _ramstart = (unsigned long)_end;
  463. if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
  464. console_init();
  465. panic("DMA region exceeds memory limit: %lu.",
  466. _ramend - _ramstart);
  467. }
  468. memory_end = _ramend - DMA_UNCACHED_REGION;
  469. #ifdef CONFIG_MPU
  470. /* Round up to multiple of 4MB */
  471. memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
  472. #else
  473. memory_start = PAGE_ALIGN(_ramstart);
  474. #endif
  475. #if defined(CONFIG_MTD_UCLINUX)
  476. /* generic memory mapped MTD driver */
  477. memory_mtd_end = memory_end;
  478. mtd_phys = _ramstart;
  479. mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
  480. # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
  481. if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
  482. mtd_size =
  483. PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
  484. # endif
  485. # if defined(CONFIG_CRAMFS)
  486. if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
  487. mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
  488. # endif
  489. # if defined(CONFIG_ROMFS_FS)
  490. if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
  491. && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
  492. mtd_size =
  493. PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
  494. # if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
  495. /* Due to a Hardware Anomaly we need to limit the size of usable
  496. * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
  497. * 05000263 - Hardware loop corrupted when taking an ICPLB exception
  498. */
  499. # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
  500. if (memory_end >= 56 * 1024 * 1024)
  501. memory_end = 56 * 1024 * 1024;
  502. # else
  503. if (memory_end >= 60 * 1024 * 1024)
  504. memory_end = 60 * 1024 * 1024;
  505. # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
  506. # endif /* ANOMALY_05000263 */
  507. # endif /* CONFIG_ROMFS_FS */
  508. /* Since the default MTD_UCLINUX has no magic number, we just blindly
  509. * read 8 past the end of the kernel's image, and look at it.
  510. * When no image is attached, mtd_size is set to a random number
  511. * Do some basic sanity checks before operating on things
  512. */
  513. if (mtd_size == 0 || memory_end <= mtd_size) {
  514. pr_emerg("Could not find valid ram mtd attached.\n");
  515. } else {
  516. memory_end -= mtd_size;
  517. /* Relocate MTD image to the top of memory after the uncached memory area */
  518. uclinux_ram_map.phys = memory_mtd_start = memory_end;
  519. uclinux_ram_map.size = mtd_size;
  520. pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n",
  521. _end, mtd_size, (void *)memory_mtd_start);
  522. dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
  523. }
  524. #endif /* CONFIG_MTD_UCLINUX */
  525. #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
  526. /* Due to a Hardware Anomaly we need to limit the size of usable
  527. * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
  528. * 05000263 - Hardware loop corrupted when taking an ICPLB exception
  529. */
  530. #if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
  531. if (memory_end >= 56 * 1024 * 1024)
  532. memory_end = 56 * 1024 * 1024;
  533. #else
  534. if (memory_end >= 60 * 1024 * 1024)
  535. memory_end = 60 * 1024 * 1024;
  536. #endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
  537. printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
  538. #endif /* ANOMALY_05000263 */
  539. #ifdef CONFIG_MPU
  540. page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
  541. page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
  542. #endif
  543. #if !defined(CONFIG_MTD_UCLINUX)
  544. /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
  545. memory_end -= SIZE_4K;
  546. #endif
  547. init_mm.start_code = (unsigned long)_stext;
  548. init_mm.end_code = (unsigned long)_etext;
  549. init_mm.end_data = (unsigned long)_edata;
  550. init_mm.brk = (unsigned long)0;
  551. printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
  552. printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
  553. printk(KERN_INFO "Memory map:\n"
  554. " fixedcode = 0x%p-0x%p\n"
  555. " text = 0x%p-0x%p\n"
  556. " rodata = 0x%p-0x%p\n"
  557. " bss = 0x%p-0x%p\n"
  558. " data = 0x%p-0x%p\n"
  559. " stack = 0x%p-0x%p\n"
  560. " init = 0x%p-0x%p\n"
  561. " available = 0x%p-0x%p\n"
  562. #ifdef CONFIG_MTD_UCLINUX
  563. " rootfs = 0x%p-0x%p\n"
  564. #endif
  565. #if DMA_UNCACHED_REGION > 0
  566. " DMA Zone = 0x%p-0x%p\n"
  567. #endif
  568. , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
  569. _stext, _etext,
  570. __start_rodata, __end_rodata,
  571. __bss_start, __bss_stop,
  572. _sdata, _edata,
  573. (void *)&init_thread_union,
  574. (void *)((int)(&init_thread_union) + 0x2000),
  575. __init_begin, __init_end,
  576. (void *)_ramstart, (void *)memory_end
  577. #ifdef CONFIG_MTD_UCLINUX
  578. , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
  579. #endif
  580. #if DMA_UNCACHED_REGION > 0
  581. , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
  582. #endif
  583. );
  584. }
  585. /*
  586. * Find the lowest, highest page frame number we have available
  587. */
  588. void __init find_min_max_pfn(void)
  589. {
  590. int i;
  591. max_pfn = 0;
  592. min_low_pfn = memory_end;
  593. for (i = 0; i < bfin_memmap.nr_map; i++) {
  594. unsigned long start, end;
  595. /* RAM? */
  596. if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
  597. continue;
  598. start = PFN_UP(bfin_memmap.map[i].addr);
  599. end = PFN_DOWN(bfin_memmap.map[i].addr +
  600. bfin_memmap.map[i].size);
  601. if (start >= end)
  602. continue;
  603. if (end > max_pfn)
  604. max_pfn = end;
  605. if (start < min_low_pfn)
  606. min_low_pfn = start;
  607. }
  608. }
  609. static __init void setup_bootmem_allocator(void)
  610. {
  611. int bootmap_size;
  612. int i;
  613. unsigned long start_pfn, end_pfn;
  614. unsigned long curr_pfn, last_pfn, size;
  615. /* mark memory between memory_start and memory_end usable */
  616. add_memory_region(memory_start,
  617. memory_end - memory_start, BFIN_MEMMAP_RAM);
  618. /* sanity check for overlap */
  619. sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
  620. print_memory_map("boot memmap");
  621. /* intialize globals in linux/bootmem.h */
  622. find_min_max_pfn();
  623. /* pfn of the last usable page frame */
  624. if (max_pfn > memory_end >> PAGE_SHIFT)
  625. max_pfn = memory_end >> PAGE_SHIFT;
  626. /* pfn of last page frame directly mapped by kernel */
  627. max_low_pfn = max_pfn;
  628. /* pfn of the first usable page frame after kernel image*/
  629. if (min_low_pfn < memory_start >> PAGE_SHIFT)
  630. min_low_pfn = memory_start >> PAGE_SHIFT;
  631. start_pfn = PAGE_OFFSET >> PAGE_SHIFT;
  632. end_pfn = memory_end >> PAGE_SHIFT;
  633. /*
  634. * give all the memory to the bootmap allocator, tell it to put the
  635. * boot mem_map at the start of memory.
  636. */
  637. bootmap_size = init_bootmem_node(NODE_DATA(0),
  638. memory_start >> PAGE_SHIFT, /* map goes here */
  639. start_pfn, end_pfn);
  640. /* register the memmap regions with the bootmem allocator */
  641. for (i = 0; i < bfin_memmap.nr_map; i++) {
  642. /*
  643. * Reserve usable memory
  644. */
  645. if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
  646. continue;
  647. /*
  648. * We are rounding up the start address of usable memory:
  649. */
  650. curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
  651. if (curr_pfn >= end_pfn)
  652. continue;
  653. /*
  654. * ... and at the end of the usable range downwards:
  655. */
  656. last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
  657. bfin_memmap.map[i].size);
  658. if (last_pfn > end_pfn)
  659. last_pfn = end_pfn;
  660. /*
  661. * .. finally, did all the rounding and playing
  662. * around just make the area go away?
  663. */
  664. if (last_pfn <= curr_pfn)
  665. continue;
  666. size = last_pfn - curr_pfn;
  667. free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
  668. }
  669. /* reserve memory before memory_start, including bootmap */
  670. reserve_bootmem(PAGE_OFFSET,
  671. memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET,
  672. BOOTMEM_DEFAULT);
  673. }
  674. #define EBSZ_TO_MEG(ebsz) \
  675. ({ \
  676. int meg = 0; \
  677. switch (ebsz & 0xf) { \
  678. case 0x1: meg = 16; break; \
  679. case 0x3: meg = 32; break; \
  680. case 0x5: meg = 64; break; \
  681. case 0x7: meg = 128; break; \
  682. case 0x9: meg = 256; break; \
  683. case 0xb: meg = 512; break; \
  684. } \
  685. meg; \
  686. })
  687. static inline int __init get_mem_size(void)
  688. {
  689. #if defined(EBIU_SDBCTL)
  690. # if defined(BF561_FAMILY)
  691. int ret = 0;
  692. u32 sdbctl = bfin_read_EBIU_SDBCTL();
  693. ret += EBSZ_TO_MEG(sdbctl >> 0);
  694. ret += EBSZ_TO_MEG(sdbctl >> 8);
  695. ret += EBSZ_TO_MEG(sdbctl >> 16);
  696. ret += EBSZ_TO_MEG(sdbctl >> 24);
  697. return ret;
  698. # else
  699. return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
  700. # endif
  701. #elif defined(EBIU_DDRCTL1)
  702. u32 ddrctl = bfin_read_EBIU_DDRCTL1();
  703. int ret = 0;
  704. switch (ddrctl & 0xc0000) {
  705. case DEVSZ_64: ret = 64 / 8;
  706. case DEVSZ_128: ret = 128 / 8;
  707. case DEVSZ_256: ret = 256 / 8;
  708. case DEVSZ_512: ret = 512 / 8;
  709. }
  710. switch (ddrctl & 0x30000) {
  711. case DEVWD_4: ret *= 2;
  712. case DEVWD_8: ret *= 2;
  713. case DEVWD_16: break;
  714. }
  715. if ((ddrctl & 0xc000) == 0x4000)
  716. ret *= 2;
  717. return ret;
  718. #endif
  719. BUG();
  720. }
  721. void __init setup_arch(char **cmdline_p)
  722. {
  723. unsigned long sclk, cclk;
  724. /* Check to make sure we are running on the right processor */
  725. if (unlikely(CPUID != bfin_cpuid()))
  726. printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
  727. CPU, bfin_cpuid(), bfin_revid());
  728. #ifdef CONFIG_DUMMY_CONSOLE
  729. conswitchp = &dummy_con;
  730. #endif
  731. #if defined(CONFIG_CMDLINE_BOOL)
  732. strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
  733. command_line[sizeof(command_line) - 1] = 0;
  734. #endif
  735. /* Keep a copy of command line */
  736. *cmdline_p = &command_line[0];
  737. memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
  738. boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
  739. memset(&bfin_memmap, 0, sizeof(bfin_memmap));
  740. /* If the user does not specify things on the command line, use
  741. * what the bootloader set things up as
  742. */
  743. physical_mem_end = 0;
  744. parse_cmdline_early(&command_line[0]);
  745. if (_ramend == 0)
  746. _ramend = get_mem_size() * 1024 * 1024;
  747. if (physical_mem_end == 0)
  748. physical_mem_end = _ramend;
  749. memory_setup();
  750. /* Initialize Async memory banks */
  751. bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
  752. bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
  753. bfin_write_EBIU_AMGCTL(AMGCTLVAL);
  754. #ifdef CONFIG_EBIU_MBSCTLVAL
  755. bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
  756. bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
  757. bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
  758. #endif
  759. cclk = get_cclk();
  760. sclk = get_sclk();
  761. if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
  762. panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
  763. #ifdef BF561_FAMILY
  764. if (ANOMALY_05000266) {
  765. bfin_read_IMDMA_D0_IRQ_STATUS();
  766. bfin_read_IMDMA_D1_IRQ_STATUS();
  767. }
  768. #endif
  769. printk(KERN_INFO "Hardware Trace ");
  770. if (bfin_read_TBUFCTL() & 0x1)
  771. printk(KERN_CONT "Active ");
  772. else
  773. printk(KERN_CONT "Off ");
  774. if (bfin_read_TBUFCTL() & 0x2)
  775. printk(KERN_CONT "and Enabled\n");
  776. else
  777. printk(KERN_CONT "and Disabled\n");
  778. printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF);
  779. /* Newer parts mirror SWRST bits in SYSCR */
  780. #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
  781. defined(CONFIG_BF538) || defined(CONFIG_BF539)
  782. _bfin_swrst = bfin_read_SWRST();
  783. #else
  784. /* Clear boot mode field */
  785. _bfin_swrst = bfin_read_SYSCR() & ~0xf;
  786. #endif
  787. #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
  788. bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
  789. #endif
  790. #ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
  791. bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
  792. #endif
  793. #ifdef CONFIG_SMP
  794. if (_bfin_swrst & SWRST_DBL_FAULT_A) {
  795. #else
  796. if (_bfin_swrst & RESET_DOUBLE) {
  797. #endif
  798. printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
  799. #ifdef CONFIG_DEBUG_DOUBLEFAULT
  800. /* We assume the crashing kernel, and the current symbol table match */
  801. printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
  802. (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx);
  803. printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr);
  804. printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr);
  805. #endif
  806. printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
  807. init_retx);
  808. } else if (_bfin_swrst & RESET_WDOG)
  809. printk(KERN_INFO "Recovering from Watchdog event\n");
  810. else if (_bfin_swrst & RESET_SOFTWARE)
  811. printk(KERN_NOTICE "Reset caused by Software reset\n");
  812. printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n");
  813. if (bfin_compiled_revid() == 0xffff)
  814. printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU);
  815. else if (bfin_compiled_revid() == -1)
  816. printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
  817. else
  818. printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
  819. if (likely(CPUID == bfin_cpuid())) {
  820. if (bfin_revid() != bfin_compiled_revid()) {
  821. if (bfin_compiled_revid() == -1)
  822. printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
  823. bfin_revid());
  824. else if (bfin_compiled_revid() != 0xffff) {
  825. printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
  826. bfin_compiled_revid(), bfin_revid());
  827. if (bfin_compiled_revid() > bfin_revid())
  828. panic("Error: you are missing anomaly workarounds for this rev");
  829. }
  830. }
  831. if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
  832. printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
  833. CPU, bfin_revid());
  834. }
  835. /* We can't run on BF548-0.1 due to ANOMALY 05000448 */
  836. if (bfin_cpuid() == 0x27de && bfin_revid() == 1)
  837. panic("You can't run on this processor due to 05000448");
  838. printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
  839. printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
  840. cclk / 1000000, sclk / 1000000);
  841. setup_bootmem_allocator();
  842. paging_init();
  843. /* Copy atomic sequences to their fixed location, and sanity check that
  844. these locations are the ones that we advertise to userspace. */
  845. memcpy((void *)FIXED_CODE_START, &fixed_code_start,
  846. FIXED_CODE_END - FIXED_CODE_START);
  847. BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
  848. != SIGRETURN_STUB - FIXED_CODE_START);
  849. BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
  850. != ATOMIC_XCHG32 - FIXED_CODE_START);
  851. BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
  852. != ATOMIC_CAS32 - FIXED_CODE_START);
  853. BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
  854. != ATOMIC_ADD32 - FIXED_CODE_START);
  855. BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
  856. != ATOMIC_SUB32 - FIXED_CODE_START);
  857. BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
  858. != ATOMIC_IOR32 - FIXED_CODE_START);
  859. BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
  860. != ATOMIC_AND32 - FIXED_CODE_START);
  861. BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
  862. != ATOMIC_XOR32 - FIXED_CODE_START);
  863. BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
  864. != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
  865. #ifdef CONFIG_SMP
  866. platform_init_cpus();
  867. #endif
  868. init_exception_vectors();
  869. bfin_cache_init(); /* Initialize caches for the boot CPU */
  870. }
  871. static int __init topology_init(void)
  872. {
  873. unsigned int cpu;
  874. /* Record CPU-private information for the boot processor. */
  875. bfin_setup_cpudata(0);
  876. for_each_possible_cpu(cpu) {
  877. register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
  878. }
  879. return 0;
  880. }
  881. subsys_initcall(topology_init);
  882. /* Get the input clock frequency */
  883. static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
  884. static u_long get_clkin_hz(void)
  885. {
  886. return cached_clkin_hz;
  887. }
  888. static int __init early_init_clkin_hz(char *buf)
  889. {
  890. cached_clkin_hz = simple_strtoul(buf, NULL, 0);
  891. #ifdef BFIN_KERNEL_CLOCK
  892. if (cached_clkin_hz != CONFIG_CLKIN_HZ)
  893. panic("cannot change clkin_hz when reprogramming clocks");
  894. #endif
  895. return 1;
  896. }
  897. early_param("clkin_hz=", early_init_clkin_hz);
  898. /* Get the voltage input multiplier */
  899. static u_long get_vco(void)
  900. {
  901. static u_long cached_vco;
  902. u_long msel, pll_ctl;
  903. /* The assumption here is that VCO never changes at runtime.
  904. * If, someday, we support that, then we'll have to change this.
  905. */
  906. if (cached_vco)
  907. return cached_vco;
  908. pll_ctl = bfin_read_PLL_CTL();
  909. msel = (pll_ctl >> 9) & 0x3F;
  910. if (0 == msel)
  911. msel = 64;
  912. cached_vco = get_clkin_hz();
  913. cached_vco >>= (1 & pll_ctl); /* DF bit */
  914. cached_vco *= msel;
  915. return cached_vco;
  916. }
  917. /* Get the Core clock */
  918. u_long get_cclk(void)
  919. {
  920. static u_long cached_cclk_pll_div, cached_cclk;
  921. u_long csel, ssel;
  922. if (bfin_read_PLL_STAT() & 0x1)
  923. return get_clkin_hz();
  924. ssel = bfin_read_PLL_DIV();
  925. if (ssel == cached_cclk_pll_div)
  926. return cached_cclk;
  927. else
  928. cached_cclk_pll_div = ssel;
  929. csel = ((ssel >> 4) & 0x03);
  930. ssel &= 0xf;
  931. if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
  932. cached_cclk = get_vco() / ssel;
  933. else
  934. cached_cclk = get_vco() >> csel;
  935. return cached_cclk;
  936. }
  937. EXPORT_SYMBOL(get_cclk);
  938. /* Get the System clock */
  939. u_long get_sclk(void)
  940. {
  941. static u_long cached_sclk;
  942. u_long ssel;
  943. /* The assumption here is that SCLK never changes at runtime.
  944. * If, someday, we support that, then we'll have to change this.
  945. */
  946. if (cached_sclk)
  947. return cached_sclk;
  948. if (bfin_read_PLL_STAT() & 0x1)
  949. return get_clkin_hz();
  950. ssel = bfin_read_PLL_DIV() & 0xf;
  951. if (0 == ssel) {
  952. printk(KERN_WARNING "Invalid System Clock\n");
  953. ssel = 1;
  954. }
  955. cached_sclk = get_vco() / ssel;
  956. return cached_sclk;
  957. }
  958. EXPORT_SYMBOL(get_sclk);
  959. unsigned long sclk_to_usecs(unsigned long sclk)
  960. {
  961. u64 tmp = USEC_PER_SEC * (u64)sclk;
  962. do_div(tmp, get_sclk());
  963. return tmp;
  964. }
  965. EXPORT_SYMBOL(sclk_to_usecs);
  966. unsigned long usecs_to_sclk(unsigned long usecs)
  967. {
  968. u64 tmp = get_sclk() * (u64)usecs;
  969. do_div(tmp, USEC_PER_SEC);
  970. return tmp;
  971. }
  972. EXPORT_SYMBOL(usecs_to_sclk);
  973. /*
  974. * Get CPU information for use by the procfs.
  975. */
  976. static int show_cpuinfo(struct seq_file *m, void *v)
  977. {
  978. char *cpu, *mmu, *fpu, *vendor, *cache;
  979. uint32_t revid;
  980. int cpu_num = *(unsigned int *)v;
  981. u_long sclk, cclk;
  982. u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
  983. struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
  984. cpu = CPU;
  985. mmu = "none";
  986. fpu = "none";
  987. revid = bfin_revid();
  988. sclk = get_sclk();
  989. cclk = get_cclk();
  990. switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
  991. case 0xca:
  992. vendor = "Analog Devices";
  993. break;
  994. default:
  995. vendor = "unknown";
  996. break;
  997. }
  998. seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
  999. if (CPUID == bfin_cpuid())
  1000. seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
  1001. else
  1002. seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
  1003. CPUID, bfin_cpuid());
  1004. seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
  1005. "stepping\t: %d ",
  1006. cpu, cclk/1000000, sclk/1000000,
  1007. #ifdef CONFIG_MPU
  1008. "mpu on",
  1009. #else
  1010. "mpu off",
  1011. #endif
  1012. revid);
  1013. if (bfin_revid() != bfin_compiled_revid()) {
  1014. if (bfin_compiled_revid() == -1)
  1015. seq_printf(m, "(Compiled for Rev none)");
  1016. else if (bfin_compiled_revid() == 0xffff)
  1017. seq_printf(m, "(Compiled for Rev any)");
  1018. else
  1019. seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
  1020. }
  1021. seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
  1022. cclk/1000000, cclk%1000000,
  1023. sclk/1000000, sclk%1000000);
  1024. seq_printf(m, "bogomips\t: %lu.%02lu\n"
  1025. "Calibration\t: %lu loops\n",
  1026. (cpudata->loops_per_jiffy * HZ) / 500000,
  1027. ((cpudata->loops_per_jiffy * HZ) / 5000) % 100,
  1028. (cpudata->loops_per_jiffy * HZ));
  1029. /* Check Cache configutation */
  1030. switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
  1031. case ACACHE_BSRAM:
  1032. cache = "dbank-A/B\t: cache/sram";
  1033. dcache_size = 16;
  1034. dsup_banks = 1;
  1035. break;
  1036. case ACACHE_BCACHE:
  1037. cache = "dbank-A/B\t: cache/cache";
  1038. dcache_size = 32;
  1039. dsup_banks = 2;
  1040. break;
  1041. case ASRAM_BSRAM:
  1042. cache = "dbank-A/B\t: sram/sram";
  1043. dcache_size = 0;
  1044. dsup_banks = 0;
  1045. break;
  1046. default:
  1047. cache = "unknown";
  1048. dcache_size = 0;
  1049. dsup_banks = 0;
  1050. break;
  1051. }
  1052. /* Is it turned on? */
  1053. if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
  1054. dcache_size = 0;
  1055. if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
  1056. icache_size = 0;
  1057. seq_printf(m, "cache size\t: %d KB(L1 icache) "
  1058. "%d KB(L1 dcache) %d KB(L2 cache)\n",
  1059. icache_size, dcache_size, 0);
  1060. seq_printf(m, "%s\n", cache);
  1061. seq_printf(m, "external memory\t: "
  1062. #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
  1063. "cacheable"
  1064. #else
  1065. "uncacheable"
  1066. #endif
  1067. " in instruction cache\n");
  1068. seq_printf(m, "external memory\t: "
  1069. #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
  1070. "cacheable (write-back)"
  1071. #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
  1072. "cacheable (write-through)"
  1073. #else
  1074. "uncacheable"
  1075. #endif
  1076. " in data cache\n");
  1077. if (icache_size)
  1078. seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
  1079. BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
  1080. else
  1081. seq_printf(m, "icache setup\t: off\n");
  1082. seq_printf(m,
  1083. "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
  1084. dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
  1085. BFIN_DLINES);
  1086. #ifdef __ARCH_SYNC_CORE_DCACHE
  1087. seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count);
  1088. #endif
  1089. #ifdef __ARCH_SYNC_CORE_ICACHE
  1090. seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", cpudata->icache_invld_count);
  1091. #endif
  1092. #ifdef CONFIG_BFIN_ICACHE_LOCK
  1093. switch ((cpudata->imemctl >> 3) & WAYALL_L) {
  1094. case WAY0_L:
  1095. seq_printf(m, "Way0 Locked-Down\n");
  1096. break;
  1097. case WAY1_L:
  1098. seq_printf(m, "Way1 Locked-Down\n");
  1099. break;
  1100. case WAY01_L:
  1101. seq_printf(m, "Way0,Way1 Locked-Down\n");
  1102. break;
  1103. case WAY2_L:
  1104. seq_printf(m, "Way2 Locked-Down\n");
  1105. break;
  1106. case WAY02_L:
  1107. seq_printf(m, "Way0,Way2 Locked-Down\n");
  1108. break;
  1109. case WAY12_L:
  1110. seq_printf(m, "Way1,Way2 Locked-Down\n");
  1111. break;
  1112. case WAY012_L:
  1113. seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
  1114. break;
  1115. case WAY3_L:
  1116. seq_printf(m, "Way3 Locked-Down\n");
  1117. break;
  1118. case WAY03_L:
  1119. seq_printf(m, "Way0,Way3 Locked-Down\n");
  1120. break;
  1121. case WAY13_L:
  1122. seq_printf(m, "Way1,Way3 Locked-Down\n");
  1123. break;
  1124. case WAY013_L:
  1125. seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
  1126. break;
  1127. case WAY32_L:
  1128. seq_printf(m, "Way3,Way2 Locked-Down\n");
  1129. break;
  1130. case WAY320_L:
  1131. seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
  1132. break;
  1133. case WAY321_L:
  1134. seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
  1135. break;
  1136. case WAYALL_L:
  1137. seq_printf(m, "All Ways are locked\n");
  1138. break;
  1139. default:
  1140. seq_printf(m, "No Ways are locked\n");
  1141. }
  1142. #endif
  1143. if (cpu_num != num_possible_cpus() - 1)
  1144. return 0;
  1145. if (L2_LENGTH) {
  1146. seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
  1147. seq_printf(m, "L2 SRAM\t\t: "
  1148. #if defined(CONFIG_BFIN_L2_ICACHEABLE)
  1149. "cacheable"
  1150. #else
  1151. "uncacheable"
  1152. #endif
  1153. " in instruction cache\n");
  1154. seq_printf(m, "L2 SRAM\t\t: "
  1155. #if defined(CONFIG_BFIN_L2_WRITEBACK)
  1156. "cacheable (write-back)"
  1157. #elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
  1158. "cacheable (write-through)"
  1159. #else
  1160. "uncacheable"
  1161. #endif
  1162. " in data cache\n");
  1163. }
  1164. seq_printf(m, "board name\t: %s\n", bfin_board_name);
  1165. seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
  1166. physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
  1167. seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n",
  1168. ((int)memory_end - (int)_stext) >> 10,
  1169. _stext,
  1170. (void *)memory_end);
  1171. seq_printf(m, "\n");
  1172. return 0;
  1173. }
  1174. static void *c_start(struct seq_file *m, loff_t *pos)
  1175. {
  1176. if (*pos == 0)
  1177. *pos = first_cpu(cpu_online_map);
  1178. if (*pos >= num_online_cpus())
  1179. return NULL;
  1180. return pos;
  1181. }
  1182. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  1183. {
  1184. *pos = next_cpu(*pos, cpu_online_map);
  1185. return c_start(m, pos);
  1186. }
  1187. static void c_stop(struct seq_file *m, void *v)
  1188. {
  1189. }
  1190. const struct seq_operations cpuinfo_op = {
  1191. .start = c_start,
  1192. .next = c_next,
  1193. .stop = c_stop,
  1194. .show = show_cpuinfo,
  1195. };
  1196. void __init cmdline_init(const char *r0)
  1197. {
  1198. if (r0)
  1199. strncpy(command_line, r0, COMMAND_LINE_SIZE);
  1200. }