init.c 41 KB

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  1. /*
  2. * Copyright (c) 2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <linux/moduleparam.h>
  18. #include <linux/errno.h>
  19. #include <linux/export.h>
  20. #include <linux/of.h>
  21. #include <linux/mmc/sdio_func.h>
  22. #include "core.h"
  23. #include "cfg80211.h"
  24. #include "target.h"
  25. #include "debug.h"
  26. #include "hif-ops.h"
  27. static const struct ath6kl_hw hw_list[] = {
  28. {
  29. .id = AR6003_HW_2_0_VERSION,
  30. .name = "ar6003 hw 2.0",
  31. .dataset_patch_addr = 0x57e884,
  32. .app_load_addr = 0x543180,
  33. .board_ext_data_addr = 0x57e500,
  34. .reserved_ram_size = 6912,
  35. .refclk_hz = 26000000,
  36. .uarttx_pin = 8,
  37. /* hw2.0 needs override address hardcoded */
  38. .app_start_override_addr = 0x944C00,
  39. .fw = {
  40. .dir = AR6003_HW_2_0_FW_DIR,
  41. .otp = AR6003_HW_2_0_OTP_FILE,
  42. .fw = AR6003_HW_2_0_FIRMWARE_FILE,
  43. .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE,
  44. .patch = AR6003_HW_2_0_PATCH_FILE,
  45. },
  46. .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE,
  47. .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE,
  48. },
  49. {
  50. .id = AR6003_HW_2_1_1_VERSION,
  51. .name = "ar6003 hw 2.1.1",
  52. .dataset_patch_addr = 0x57ff74,
  53. .app_load_addr = 0x1234,
  54. .board_ext_data_addr = 0x542330,
  55. .reserved_ram_size = 512,
  56. .refclk_hz = 26000000,
  57. .uarttx_pin = 8,
  58. .testscript_addr = 0x57ef74,
  59. .fw = {
  60. .dir = AR6003_HW_2_1_1_FW_DIR,
  61. .otp = AR6003_HW_2_1_1_OTP_FILE,
  62. .fw = AR6003_HW_2_1_1_FIRMWARE_FILE,
  63. .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE,
  64. .patch = AR6003_HW_2_1_1_PATCH_FILE,
  65. .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE,
  66. .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE,
  67. },
  68. .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE,
  69. .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
  70. },
  71. {
  72. .id = AR6004_HW_1_0_VERSION,
  73. .name = "ar6004 hw 1.0",
  74. .dataset_patch_addr = 0x57e884,
  75. .app_load_addr = 0x1234,
  76. .board_ext_data_addr = 0x437000,
  77. .reserved_ram_size = 19456,
  78. .board_addr = 0x433900,
  79. .refclk_hz = 26000000,
  80. .uarttx_pin = 11,
  81. .fw = {
  82. .dir = AR6004_HW_1_0_FW_DIR,
  83. .fw = AR6004_HW_1_0_FIRMWARE_FILE,
  84. },
  85. .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE,
  86. .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE,
  87. },
  88. {
  89. .id = AR6004_HW_1_1_VERSION,
  90. .name = "ar6004 hw 1.1",
  91. .dataset_patch_addr = 0x57e884,
  92. .app_load_addr = 0x1234,
  93. .board_ext_data_addr = 0x437000,
  94. .reserved_ram_size = 11264,
  95. .board_addr = 0x43d400,
  96. .refclk_hz = 40000000,
  97. .uarttx_pin = 11,
  98. .fw = {
  99. .dir = AR6004_HW_1_1_FW_DIR,
  100. .fw = AR6004_HW_1_1_FIRMWARE_FILE,
  101. },
  102. .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE,
  103. .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE,
  104. },
  105. };
  106. /*
  107. * Include definitions here that can be used to tune the WLAN module
  108. * behavior. Different customers can tune the behavior as per their needs,
  109. * here.
  110. */
  111. /*
  112. * This configuration item enable/disable keepalive support.
  113. * Keepalive support: In the absence of any data traffic to AP, null
  114. * frames will be sent to the AP at periodic interval, to keep the association
  115. * active. This configuration item defines the periodic interval.
  116. * Use value of zero to disable keepalive support
  117. * Default: 60 seconds
  118. */
  119. #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
  120. /*
  121. * This configuration item sets the value of disconnect timeout
  122. * Firmware delays sending the disconnec event to the host for this
  123. * timeout after is gets disconnected from the current AP.
  124. * If the firmware successly roams within the disconnect timeout
  125. * it sends a new connect event
  126. */
  127. #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
  128. #define ATH6KL_DATA_OFFSET 64
  129. struct sk_buff *ath6kl_buf_alloc(int size)
  130. {
  131. struct sk_buff *skb;
  132. u16 reserved;
  133. /* Add chacheline space at front and back of buffer */
  134. reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +
  135. sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES;
  136. skb = dev_alloc_skb(size + reserved);
  137. if (skb)
  138. skb_reserve(skb, reserved - L1_CACHE_BYTES);
  139. return skb;
  140. }
  141. void ath6kl_init_profile_info(struct ath6kl_vif *vif)
  142. {
  143. vif->ssid_len = 0;
  144. memset(vif->ssid, 0, sizeof(vif->ssid));
  145. vif->dot11_auth_mode = OPEN_AUTH;
  146. vif->auth_mode = NONE_AUTH;
  147. vif->prwise_crypto = NONE_CRYPT;
  148. vif->prwise_crypto_len = 0;
  149. vif->grp_crypto = NONE_CRYPT;
  150. vif->grp_crypto_len = 0;
  151. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  152. memset(vif->req_bssid, 0, sizeof(vif->req_bssid));
  153. memset(vif->bssid, 0, sizeof(vif->bssid));
  154. vif->bss_ch = 0;
  155. }
  156. static int ath6kl_set_host_app_area(struct ath6kl *ar)
  157. {
  158. u32 address, data;
  159. struct host_app_area host_app_area;
  160. /* Fetch the address of the host_app_area_s
  161. * instance in the host interest area */
  162. address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
  163. address = TARG_VTOP(ar->target_type, address);
  164. if (ath6kl_diag_read32(ar, address, &data))
  165. return -EIO;
  166. address = TARG_VTOP(ar->target_type, data);
  167. host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION);
  168. if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area,
  169. sizeof(struct host_app_area)))
  170. return -EIO;
  171. return 0;
  172. }
  173. static inline void set_ac2_ep_map(struct ath6kl *ar,
  174. u8 ac,
  175. enum htc_endpoint_id ep)
  176. {
  177. ar->ac2ep_map[ac] = ep;
  178. ar->ep2ac_map[ep] = ac;
  179. }
  180. /* connect to a service */
  181. static int ath6kl_connectservice(struct ath6kl *ar,
  182. struct htc_service_connect_req *con_req,
  183. char *desc)
  184. {
  185. int status;
  186. struct htc_service_connect_resp response;
  187. memset(&response, 0, sizeof(response));
  188. status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response);
  189. if (status) {
  190. ath6kl_err("failed to connect to %s service status:%d\n",
  191. desc, status);
  192. return status;
  193. }
  194. switch (con_req->svc_id) {
  195. case WMI_CONTROL_SVC:
  196. if (test_bit(WMI_ENABLED, &ar->flag))
  197. ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint);
  198. ar->ctrl_ep = response.endpoint;
  199. break;
  200. case WMI_DATA_BE_SVC:
  201. set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint);
  202. break;
  203. case WMI_DATA_BK_SVC:
  204. set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint);
  205. break;
  206. case WMI_DATA_VI_SVC:
  207. set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint);
  208. break;
  209. case WMI_DATA_VO_SVC:
  210. set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint);
  211. break;
  212. default:
  213. ath6kl_err("service id is not mapped %d\n", con_req->svc_id);
  214. return -EINVAL;
  215. }
  216. return 0;
  217. }
  218. static int ath6kl_init_service_ep(struct ath6kl *ar)
  219. {
  220. struct htc_service_connect_req connect;
  221. memset(&connect, 0, sizeof(connect));
  222. /* these fields are the same for all service endpoints */
  223. connect.ep_cb.rx = ath6kl_rx;
  224. connect.ep_cb.rx_refill = ath6kl_rx_refill;
  225. connect.ep_cb.tx_full = ath6kl_tx_queue_full;
  226. /*
  227. * Set the max queue depth so that our ath6kl_tx_queue_full handler
  228. * gets called.
  229. */
  230. connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
  231. connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4;
  232. if (!connect.ep_cb.rx_refill_thresh)
  233. connect.ep_cb.rx_refill_thresh++;
  234. /* connect to control service */
  235. connect.svc_id = WMI_CONTROL_SVC;
  236. if (ath6kl_connectservice(ar, &connect, "WMI CONTROL"))
  237. return -EIO;
  238. connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN;
  239. /*
  240. * Limit the HTC message size on the send path, although e can
  241. * receive A-MSDU frames of 4K, we will only send ethernet-sized
  242. * (802.3) frames on the send path.
  243. */
  244. connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH;
  245. /*
  246. * To reduce the amount of committed memory for larger A_MSDU
  247. * frames, use the recv-alloc threshold mechanism for larger
  248. * packets.
  249. */
  250. connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE;
  251. connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf;
  252. /*
  253. * For the remaining data services set the connection flag to
  254. * reduce dribbling, if configured to do so.
  255. */
  256. connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB;
  257. connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK;
  258. connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF;
  259. connect.svc_id = WMI_DATA_BE_SVC;
  260. if (ath6kl_connectservice(ar, &connect, "WMI DATA BE"))
  261. return -EIO;
  262. /* connect to back-ground map this to WMI LOW_PRI */
  263. connect.svc_id = WMI_DATA_BK_SVC;
  264. if (ath6kl_connectservice(ar, &connect, "WMI DATA BK"))
  265. return -EIO;
  266. /* connect to Video service, map this to to HI PRI */
  267. connect.svc_id = WMI_DATA_VI_SVC;
  268. if (ath6kl_connectservice(ar, &connect, "WMI DATA VI"))
  269. return -EIO;
  270. /*
  271. * Connect to VO service, this is currently not mapped to a WMI
  272. * priority stream due to historical reasons. WMI originally
  273. * defined 3 priorities over 3 mailboxes We can change this when
  274. * WMI is reworked so that priorities are not dependent on
  275. * mailboxes.
  276. */
  277. connect.svc_id = WMI_DATA_VO_SVC;
  278. if (ath6kl_connectservice(ar, &connect, "WMI DATA VO"))
  279. return -EIO;
  280. return 0;
  281. }
  282. void ath6kl_init_control_info(struct ath6kl_vif *vif)
  283. {
  284. ath6kl_init_profile_info(vif);
  285. vif->def_txkey_index = 0;
  286. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  287. vif->ch_hint = 0;
  288. }
  289. /*
  290. * Set HTC/Mbox operational parameters, this can only be called when the
  291. * target is in the BMI phase.
  292. */
  293. static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
  294. u8 htc_ctrl_buf)
  295. {
  296. int status;
  297. u32 blk_size;
  298. blk_size = ar->mbox_info.block_size;
  299. if (htc_ctrl_buf)
  300. blk_size |= ((u32)htc_ctrl_buf) << 16;
  301. /* set the host interest area for the block size */
  302. status = ath6kl_bmi_write(ar,
  303. ath6kl_get_hi_item_addr(ar,
  304. HI_ITEM(hi_mbox_io_block_sz)),
  305. (u8 *)&blk_size,
  306. 4);
  307. if (status) {
  308. ath6kl_err("bmi_write_memory for IO block size failed\n");
  309. goto out;
  310. }
  311. ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
  312. blk_size,
  313. ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
  314. if (mbox_isr_yield_val) {
  315. /* set the host interest area for the mbox ISR yield limit */
  316. status = ath6kl_bmi_write(ar,
  317. ath6kl_get_hi_item_addr(ar,
  318. HI_ITEM(hi_mbox_isr_yield_limit)),
  319. (u8 *)&mbox_isr_yield_val,
  320. 4);
  321. if (status) {
  322. ath6kl_err("bmi_write_memory for yield limit failed\n");
  323. goto out;
  324. }
  325. }
  326. out:
  327. return status;
  328. }
  329. static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
  330. {
  331. int status = 0;
  332. int ret;
  333. /*
  334. * Configure the device for rx dot11 header rules. "0,0" are the
  335. * default values. Required if checksum offload is needed. Set
  336. * RxMetaVersion to 2.
  337. */
  338. if (ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
  339. ar->rx_meta_ver, 0, 0)) {
  340. ath6kl_err("unable to set the rx frame format\n");
  341. status = -EIO;
  342. }
  343. if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN)
  344. if ((ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
  345. IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) {
  346. ath6kl_err("unable to set power save fail event policy\n");
  347. status = -EIO;
  348. }
  349. if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER))
  350. if ((ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
  351. WMI_DONOT_IGNORE_BARKER_IN_ERP)) != 0) {
  352. ath6kl_err("unable to set barker preamble policy\n");
  353. status = -EIO;
  354. }
  355. if (ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
  356. WLAN_CONFIG_KEEP_ALIVE_INTERVAL)) {
  357. ath6kl_err("unable to set keep alive interval\n");
  358. status = -EIO;
  359. }
  360. if (ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
  361. WLAN_CONFIG_DISCONNECT_TIMEOUT)) {
  362. ath6kl_err("unable to set disconnect timeout\n");
  363. status = -EIO;
  364. }
  365. if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST))
  366. if (ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED)) {
  367. ath6kl_err("unable to set txop bursting\n");
  368. status = -EIO;
  369. }
  370. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  371. ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
  372. P2P_FLAG_CAPABILITIES_REQ |
  373. P2P_FLAG_MACADDR_REQ |
  374. P2P_FLAG_HMODEL_REQ);
  375. if (ret) {
  376. ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P "
  377. "capabilities (%d) - assuming P2P not "
  378. "supported\n", ret);
  379. ar->p2p = false;
  380. }
  381. }
  382. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  383. /* Enable Probe Request reporting for P2P */
  384. ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true);
  385. if (ret) {
  386. ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe "
  387. "Request reporting (%d)\n", ret);
  388. }
  389. }
  390. return status;
  391. }
  392. int ath6kl_configure_target(struct ath6kl *ar)
  393. {
  394. u32 param, ram_reserved_size;
  395. u8 fw_iftype, fw_mode = 0, fw_submode = 0;
  396. int i, status;
  397. param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG);
  398. if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar,
  399. HI_ITEM(hi_serial_enable)), (u8 *)&param, 4)) {
  400. ath6kl_err("bmi_write_memory for uart debug failed\n");
  401. return -EIO;
  402. }
  403. /*
  404. * Note: Even though the firmware interface type is
  405. * chosen as BSS_STA for all three interfaces, can
  406. * be configured to IBSS/AP as long as the fw submode
  407. * remains normal mode (0 - AP, STA and IBSS). But
  408. * due to an target assert in firmware only one interface is
  409. * configured for now.
  410. */
  411. fw_iftype = HI_OPTION_FW_MODE_BSS_STA;
  412. for (i = 0; i < ar->vif_max; i++)
  413. fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS);
  414. /*
  415. * By default, submodes :
  416. * vif[0] - AP/STA/IBSS
  417. * vif[1] - "P2P dev"/"P2P GO"/"P2P Client"
  418. * vif[2] - "P2P dev"/"P2P GO"/"P2P Client"
  419. */
  420. for (i = 0; i < ar->max_norm_iface; i++)
  421. fw_submode |= HI_OPTION_FW_SUBMODE_NONE <<
  422. (i * HI_OPTION_FW_SUBMODE_BITS);
  423. for (i = ar->max_norm_iface; i < ar->vif_max; i++)
  424. fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
  425. (i * HI_OPTION_FW_SUBMODE_BITS);
  426. if (ar->p2p && ar->vif_max == 1)
  427. fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
  428. param = HTC_PROTOCOL_VERSION;
  429. if (ath6kl_bmi_write(ar,
  430. ath6kl_get_hi_item_addr(ar,
  431. HI_ITEM(hi_app_host_interest)),
  432. (u8 *)&param, 4) != 0) {
  433. ath6kl_err("bmi_write_memory for htc version failed\n");
  434. return -EIO;
  435. }
  436. /* set the firmware mode to STA/IBSS/AP */
  437. param = 0;
  438. if (ath6kl_bmi_read(ar,
  439. ath6kl_get_hi_item_addr(ar,
  440. HI_ITEM(hi_option_flag)),
  441. (u8 *)&param, 4) != 0) {
  442. ath6kl_err("bmi_read_memory for setting fwmode failed\n");
  443. return -EIO;
  444. }
  445. param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT);
  446. param |= fw_mode << HI_OPTION_FW_MODE_SHIFT;
  447. param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT;
  448. param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  449. param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  450. if (ath6kl_bmi_write(ar,
  451. ath6kl_get_hi_item_addr(ar,
  452. HI_ITEM(hi_option_flag)),
  453. (u8 *)&param,
  454. 4) != 0) {
  455. ath6kl_err("bmi_write_memory for setting fwmode failed\n");
  456. return -EIO;
  457. }
  458. ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
  459. /*
  460. * Hardcode the address use for the extended board data
  461. * Ideally this should be pre-allocate by the OS at boot time
  462. * But since it is a new feature and board data is loaded
  463. * at init time, we have to workaround this from host.
  464. * It is difficult to patch the firmware boot code,
  465. * but possible in theory.
  466. */
  467. param = ar->hw.board_ext_data_addr;
  468. ram_reserved_size = ar->hw.reserved_ram_size;
  469. if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar,
  470. HI_ITEM(hi_board_ext_data)),
  471. (u8 *)&param, 4) != 0) {
  472. ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
  473. return -EIO;
  474. }
  475. if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar,
  476. HI_ITEM(hi_end_ram_reserve_sz)),
  477. (u8 *)&ram_reserved_size, 4) != 0) {
  478. ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
  479. return -EIO;
  480. }
  481. /* set the block size for the target */
  482. if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
  483. /* use default number of control buffers */
  484. return -EIO;
  485. /* Configure GPIO AR600x UART */
  486. param = ar->hw.uarttx_pin;
  487. status = ath6kl_bmi_write(ar,
  488. ath6kl_get_hi_item_addr(ar,
  489. HI_ITEM(hi_dbg_uart_txpin)),
  490. (u8 *)&param, 4);
  491. if (status)
  492. return status;
  493. /* Configure target refclk_hz */
  494. param = ar->hw.refclk_hz;
  495. status = ath6kl_bmi_write(ar,
  496. ath6kl_get_hi_item_addr(ar,
  497. HI_ITEM(hi_refclk_hz)),
  498. (u8 *)&param, 4);
  499. if (status)
  500. return status;
  501. return 0;
  502. }
  503. /* firmware upload */
  504. static int ath6kl_get_fw(struct ath6kl *ar, const char *filename,
  505. u8 **fw, size_t *fw_len)
  506. {
  507. const struct firmware *fw_entry;
  508. int ret;
  509. ret = request_firmware(&fw_entry, filename, ar->dev);
  510. if (ret)
  511. return ret;
  512. *fw_len = fw_entry->size;
  513. *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
  514. if (*fw == NULL)
  515. ret = -ENOMEM;
  516. release_firmware(fw_entry);
  517. return ret;
  518. }
  519. #ifdef CONFIG_OF
  520. /*
  521. * Check the device tree for a board-id and use it to construct
  522. * the pathname to the firmware file. Used (for now) to find a
  523. * fallback to the "bdata.bin" file--typically a symlink to the
  524. * appropriate board-specific file.
  525. */
  526. static bool check_device_tree(struct ath6kl *ar)
  527. {
  528. static const char *board_id_prop = "atheros,board-id";
  529. struct device_node *node;
  530. char board_filename[64];
  531. const char *board_id;
  532. int ret;
  533. for_each_compatible_node(node, NULL, "atheros,ath6kl") {
  534. board_id = of_get_property(node, board_id_prop, NULL);
  535. if (board_id == NULL) {
  536. ath6kl_warn("No \"%s\" property on %s node.\n",
  537. board_id_prop, node->name);
  538. continue;
  539. }
  540. snprintf(board_filename, sizeof(board_filename),
  541. "%s/bdata.%s.bin", ar->hw.fw.dir, board_id);
  542. ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board,
  543. &ar->fw_board_len);
  544. if (ret) {
  545. ath6kl_err("Failed to get DT board file %s: %d\n",
  546. board_filename, ret);
  547. continue;
  548. }
  549. return true;
  550. }
  551. return false;
  552. }
  553. #else
  554. static bool check_device_tree(struct ath6kl *ar)
  555. {
  556. return false;
  557. }
  558. #endif /* CONFIG_OF */
  559. static int ath6kl_fetch_board_file(struct ath6kl *ar)
  560. {
  561. const char *filename;
  562. int ret;
  563. if (ar->fw_board != NULL)
  564. return 0;
  565. if (WARN_ON(ar->hw.fw_board == NULL))
  566. return -EINVAL;
  567. filename = ar->hw.fw_board;
  568. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  569. &ar->fw_board_len);
  570. if (ret == 0) {
  571. /* managed to get proper board file */
  572. return 0;
  573. }
  574. if (check_device_tree(ar)) {
  575. /* got board file from device tree */
  576. return 0;
  577. }
  578. /* there was no proper board file, try to use default instead */
  579. ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n",
  580. filename, ret);
  581. filename = ar->hw.fw_default_board;
  582. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  583. &ar->fw_board_len);
  584. if (ret) {
  585. ath6kl_err("Failed to get default board file %s: %d\n",
  586. filename, ret);
  587. return ret;
  588. }
  589. ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n");
  590. ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n");
  591. return 0;
  592. }
  593. static int ath6kl_fetch_otp_file(struct ath6kl *ar)
  594. {
  595. char filename[100];
  596. int ret;
  597. if (ar->fw_otp != NULL)
  598. return 0;
  599. if (ar->hw.fw.otp == NULL) {
  600. ath6kl_dbg(ATH6KL_DBG_BOOT,
  601. "no OTP file configured for this hw\n");
  602. return 0;
  603. }
  604. snprintf(filename, sizeof(filename), "%s/%s",
  605. ar->hw.fw.dir, ar->hw.fw.otp);
  606. ret = ath6kl_get_fw(ar, filename, &ar->fw_otp,
  607. &ar->fw_otp_len);
  608. if (ret) {
  609. ath6kl_err("Failed to get OTP file %s: %d\n",
  610. filename, ret);
  611. return ret;
  612. }
  613. return 0;
  614. }
  615. static int ath6kl_fetch_testmode_file(struct ath6kl *ar)
  616. {
  617. char filename[100];
  618. int ret;
  619. if (ar->testmode == 0)
  620. return 0;
  621. ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode);
  622. if (ar->testmode == 2) {
  623. if (ar->hw.fw.utf == NULL) {
  624. ath6kl_warn("testmode 2 not supported\n");
  625. return -EOPNOTSUPP;
  626. }
  627. snprintf(filename, sizeof(filename), "%s/%s",
  628. ar->hw.fw.dir, ar->hw.fw.utf);
  629. } else {
  630. if (ar->hw.fw.tcmd == NULL) {
  631. ath6kl_warn("testmode 1 not supported\n");
  632. return -EOPNOTSUPP;
  633. }
  634. snprintf(filename, sizeof(filename), "%s/%s",
  635. ar->hw.fw.dir, ar->hw.fw.tcmd);
  636. }
  637. set_bit(TESTMODE, &ar->flag);
  638. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  639. if (ret) {
  640. ath6kl_err("Failed to get testmode %d firmware file %s: %d\n",
  641. ar->testmode, filename, ret);
  642. return ret;
  643. }
  644. return 0;
  645. }
  646. static int ath6kl_fetch_fw_file(struct ath6kl *ar)
  647. {
  648. char filename[100];
  649. int ret;
  650. if (ar->fw != NULL)
  651. return 0;
  652. /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */
  653. if (WARN_ON(ar->hw.fw.fw == NULL))
  654. return -EINVAL;
  655. snprintf(filename, sizeof(filename), "%s/%s",
  656. ar->hw.fw.dir, ar->hw.fw.fw);
  657. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  658. if (ret) {
  659. ath6kl_err("Failed to get firmware file %s: %d\n",
  660. filename, ret);
  661. return ret;
  662. }
  663. return 0;
  664. }
  665. static int ath6kl_fetch_patch_file(struct ath6kl *ar)
  666. {
  667. char filename[100];
  668. int ret;
  669. if (ar->fw_patch != NULL)
  670. return 0;
  671. if (ar->hw.fw.patch == NULL)
  672. return 0;
  673. snprintf(filename, sizeof(filename), "%s/%s",
  674. ar->hw.fw.dir, ar->hw.fw.patch);
  675. ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
  676. &ar->fw_patch_len);
  677. if (ret) {
  678. ath6kl_err("Failed to get patch file %s: %d\n",
  679. filename, ret);
  680. return ret;
  681. }
  682. return 0;
  683. }
  684. static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
  685. {
  686. char filename[100];
  687. int ret;
  688. if (ar->testmode != 2)
  689. return 0;
  690. if (ar->fw_testscript != NULL)
  691. return 0;
  692. if (ar->hw.fw.testscript == NULL)
  693. return 0;
  694. snprintf(filename, sizeof(filename), "%s/%s",
  695. ar->hw.fw.dir, ar->hw.fw.testscript);
  696. ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
  697. &ar->fw_testscript_len);
  698. if (ret) {
  699. ath6kl_err("Failed to get testscript file %s: %d\n",
  700. filename, ret);
  701. return ret;
  702. }
  703. return 0;
  704. }
  705. static int ath6kl_fetch_fw_api1(struct ath6kl *ar)
  706. {
  707. int ret;
  708. ret = ath6kl_fetch_otp_file(ar);
  709. if (ret)
  710. return ret;
  711. ret = ath6kl_fetch_fw_file(ar);
  712. if (ret)
  713. return ret;
  714. ret = ath6kl_fetch_patch_file(ar);
  715. if (ret)
  716. return ret;
  717. ret = ath6kl_fetch_testscript_file(ar);
  718. if (ret)
  719. return ret;
  720. return 0;
  721. }
  722. static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
  723. {
  724. size_t magic_len, len, ie_len;
  725. const struct firmware *fw;
  726. struct ath6kl_fw_ie *hdr;
  727. char filename[100];
  728. const u8 *data;
  729. int ret, ie_id, i, index, bit;
  730. __le32 *val;
  731. snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name);
  732. ret = request_firmware(&fw, filename, ar->dev);
  733. if (ret)
  734. return ret;
  735. data = fw->data;
  736. len = fw->size;
  737. /* magic also includes the null byte, check that as well */
  738. magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1;
  739. if (len < magic_len) {
  740. ret = -EINVAL;
  741. goto out;
  742. }
  743. if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) {
  744. ret = -EINVAL;
  745. goto out;
  746. }
  747. len -= magic_len;
  748. data += magic_len;
  749. /* loop elements */
  750. while (len > sizeof(struct ath6kl_fw_ie)) {
  751. /* hdr is unaligned! */
  752. hdr = (struct ath6kl_fw_ie *) data;
  753. ie_id = le32_to_cpup(&hdr->id);
  754. ie_len = le32_to_cpup(&hdr->len);
  755. len -= sizeof(*hdr);
  756. data += sizeof(*hdr);
  757. if (len < ie_len) {
  758. ret = -EINVAL;
  759. goto out;
  760. }
  761. switch (ie_id) {
  762. case ATH6KL_FW_IE_OTP_IMAGE:
  763. ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
  764. ie_len);
  765. ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
  766. if (ar->fw_otp == NULL) {
  767. ret = -ENOMEM;
  768. goto out;
  769. }
  770. ar->fw_otp_len = ie_len;
  771. break;
  772. case ATH6KL_FW_IE_FW_IMAGE:
  773. ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
  774. ie_len);
  775. /* in testmode we already might have a fw file */
  776. if (ar->fw != NULL)
  777. break;
  778. ar->fw = kmemdup(data, ie_len, GFP_KERNEL);
  779. if (ar->fw == NULL) {
  780. ret = -ENOMEM;
  781. goto out;
  782. }
  783. ar->fw_len = ie_len;
  784. break;
  785. case ATH6KL_FW_IE_PATCH_IMAGE:
  786. ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
  787. ie_len);
  788. ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
  789. if (ar->fw_patch == NULL) {
  790. ret = -ENOMEM;
  791. goto out;
  792. }
  793. ar->fw_patch_len = ie_len;
  794. break;
  795. case ATH6KL_FW_IE_RESERVED_RAM_SIZE:
  796. val = (__le32 *) data;
  797. ar->hw.reserved_ram_size = le32_to_cpup(val);
  798. ath6kl_dbg(ATH6KL_DBG_BOOT,
  799. "found reserved ram size ie 0x%d\n",
  800. ar->hw.reserved_ram_size);
  801. break;
  802. case ATH6KL_FW_IE_CAPABILITIES:
  803. if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8))
  804. break;
  805. ath6kl_dbg(ATH6KL_DBG_BOOT,
  806. "found firmware capabilities ie (%zd B)\n",
  807. ie_len);
  808. for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
  809. index = i / 8;
  810. bit = i % 8;
  811. if (data[index] & (1 << bit))
  812. __set_bit(i, ar->fw_capabilities);
  813. }
  814. ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "",
  815. ar->fw_capabilities,
  816. sizeof(ar->fw_capabilities));
  817. break;
  818. case ATH6KL_FW_IE_PATCH_ADDR:
  819. if (ie_len != sizeof(*val))
  820. break;
  821. val = (__le32 *) data;
  822. ar->hw.dataset_patch_addr = le32_to_cpup(val);
  823. ath6kl_dbg(ATH6KL_DBG_BOOT,
  824. "found patch address ie 0x%x\n",
  825. ar->hw.dataset_patch_addr);
  826. break;
  827. case ATH6KL_FW_IE_BOARD_ADDR:
  828. if (ie_len != sizeof(*val))
  829. break;
  830. val = (__le32 *) data;
  831. ar->hw.board_addr = le32_to_cpup(val);
  832. ath6kl_dbg(ATH6KL_DBG_BOOT,
  833. "found board address ie 0x%x\n",
  834. ar->hw.board_addr);
  835. break;
  836. case ATH6KL_FW_IE_VIF_MAX:
  837. if (ie_len != sizeof(*val))
  838. break;
  839. val = (__le32 *) data;
  840. ar->vif_max = min_t(unsigned int, le32_to_cpup(val),
  841. ATH6KL_VIF_MAX);
  842. if (ar->vif_max > 1 && !ar->p2p)
  843. ar->max_norm_iface = 2;
  844. ath6kl_dbg(ATH6KL_DBG_BOOT,
  845. "found vif max ie %d\n", ar->vif_max);
  846. break;
  847. default:
  848. ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n",
  849. le32_to_cpup(&hdr->id));
  850. break;
  851. }
  852. len -= ie_len;
  853. data += ie_len;
  854. };
  855. ret = 0;
  856. out:
  857. release_firmware(fw);
  858. return ret;
  859. }
  860. int ath6kl_init_fetch_firmwares(struct ath6kl *ar)
  861. {
  862. int ret;
  863. ret = ath6kl_fetch_board_file(ar);
  864. if (ret)
  865. return ret;
  866. ret = ath6kl_fetch_testmode_file(ar);
  867. if (ret)
  868. return ret;
  869. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE);
  870. if (ret == 0) {
  871. ar->fw_api = 3;
  872. goto out;
  873. }
  874. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE);
  875. if (ret == 0) {
  876. ar->fw_api = 2;
  877. goto out;
  878. }
  879. ret = ath6kl_fetch_fw_api1(ar);
  880. if (ret)
  881. return ret;
  882. ar->fw_api = 1;
  883. out:
  884. ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  885. return 0;
  886. }
  887. static int ath6kl_upload_board_file(struct ath6kl *ar)
  888. {
  889. u32 board_address, board_ext_address, param;
  890. u32 board_data_size, board_ext_data_size;
  891. int ret;
  892. if (WARN_ON(ar->fw_board == NULL))
  893. return -ENOENT;
  894. /*
  895. * Determine where in Target RAM to write Board Data.
  896. * For AR6004, host determine Target RAM address for
  897. * writing board data.
  898. */
  899. if (ar->hw.board_addr != 0) {
  900. board_address = ar->hw.board_addr;
  901. ath6kl_bmi_write(ar,
  902. ath6kl_get_hi_item_addr(ar,
  903. HI_ITEM(hi_board_data)),
  904. (u8 *) &board_address, 4);
  905. } else {
  906. ath6kl_bmi_read(ar,
  907. ath6kl_get_hi_item_addr(ar,
  908. HI_ITEM(hi_board_data)),
  909. (u8 *) &board_address, 4);
  910. }
  911. /* determine where in target ram to write extended board data */
  912. ath6kl_bmi_read(ar,
  913. ath6kl_get_hi_item_addr(ar,
  914. HI_ITEM(hi_board_ext_data)),
  915. (u8 *) &board_ext_address, 4);
  916. if (ar->target_type == TARGET_TYPE_AR6003 &&
  917. board_ext_address == 0) {
  918. ath6kl_err("Failed to get board file target address.\n");
  919. return -EINVAL;
  920. }
  921. switch (ar->target_type) {
  922. case TARGET_TYPE_AR6003:
  923. board_data_size = AR6003_BOARD_DATA_SZ;
  924. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
  925. if (ar->fw_board_len > (board_data_size + board_ext_data_size))
  926. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2;
  927. break;
  928. case TARGET_TYPE_AR6004:
  929. board_data_size = AR6004_BOARD_DATA_SZ;
  930. board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ;
  931. break;
  932. default:
  933. WARN_ON(1);
  934. return -EINVAL;
  935. break;
  936. }
  937. if (board_ext_address &&
  938. ar->fw_board_len == (board_data_size + board_ext_data_size)) {
  939. /* write extended board data */
  940. ath6kl_dbg(ATH6KL_DBG_BOOT,
  941. "writing extended board data to 0x%x (%d B)\n",
  942. board_ext_address, board_ext_data_size);
  943. ret = ath6kl_bmi_write(ar, board_ext_address,
  944. ar->fw_board + board_data_size,
  945. board_ext_data_size);
  946. if (ret) {
  947. ath6kl_err("Failed to write extended board data: %d\n",
  948. ret);
  949. return ret;
  950. }
  951. /* record that extended board data is initialized */
  952. param = (board_ext_data_size << 16) | 1;
  953. ath6kl_bmi_write(ar,
  954. ath6kl_get_hi_item_addr(ar,
  955. HI_ITEM(hi_board_ext_data_config)),
  956. (unsigned char *) &param, 4);
  957. }
  958. if (ar->fw_board_len < board_data_size) {
  959. ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
  960. ret = -EINVAL;
  961. return ret;
  962. }
  963. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n",
  964. board_address, board_data_size);
  965. ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
  966. board_data_size);
  967. if (ret) {
  968. ath6kl_err("Board file bmi write failed: %d\n", ret);
  969. return ret;
  970. }
  971. /* record the fact that Board Data IS initialized */
  972. param = 1;
  973. ath6kl_bmi_write(ar,
  974. ath6kl_get_hi_item_addr(ar,
  975. HI_ITEM(hi_board_data_initialized)),
  976. (u8 *)&param, 4);
  977. return ret;
  978. }
  979. static int ath6kl_upload_otp(struct ath6kl *ar)
  980. {
  981. u32 address, param;
  982. bool from_hw = false;
  983. int ret;
  984. if (ar->fw_otp == NULL)
  985. return 0;
  986. address = ar->hw.app_load_addr;
  987. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address,
  988. ar->fw_otp_len);
  989. ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp,
  990. ar->fw_otp_len);
  991. if (ret) {
  992. ath6kl_err("Failed to upload OTP file: %d\n", ret);
  993. return ret;
  994. }
  995. /* read firmware start address */
  996. ret = ath6kl_bmi_read(ar,
  997. ath6kl_get_hi_item_addr(ar,
  998. HI_ITEM(hi_app_start)),
  999. (u8 *) &address, sizeof(address));
  1000. if (ret) {
  1001. ath6kl_err("Failed to read hi_app_start: %d\n", ret);
  1002. return ret;
  1003. }
  1004. if (ar->hw.app_start_override_addr == 0) {
  1005. ar->hw.app_start_override_addr = address;
  1006. from_hw = true;
  1007. }
  1008. ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n",
  1009. from_hw ? " (from hw)" : "",
  1010. ar->hw.app_start_override_addr);
  1011. /* execute the OTP code */
  1012. ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n",
  1013. ar->hw.app_start_override_addr);
  1014. param = 0;
  1015. ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, &param);
  1016. return ret;
  1017. }
  1018. static int ath6kl_upload_firmware(struct ath6kl *ar)
  1019. {
  1020. u32 address;
  1021. int ret;
  1022. if (WARN_ON(ar->fw == NULL))
  1023. return 0;
  1024. address = ar->hw.app_load_addr;
  1025. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n",
  1026. address, ar->fw_len);
  1027. ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len);
  1028. if (ret) {
  1029. ath6kl_err("Failed to write firmware: %d\n", ret);
  1030. return ret;
  1031. }
  1032. /*
  1033. * Set starting address for firmware
  1034. * Don't need to setup app_start override addr on AR6004
  1035. */
  1036. if (ar->target_type != TARGET_TYPE_AR6004) {
  1037. address = ar->hw.app_start_override_addr;
  1038. ath6kl_bmi_set_app_start(ar, address);
  1039. }
  1040. return ret;
  1041. }
  1042. static int ath6kl_upload_patch(struct ath6kl *ar)
  1043. {
  1044. u32 address, param;
  1045. int ret;
  1046. if (ar->fw_patch == NULL)
  1047. return 0;
  1048. address = ar->hw.dataset_patch_addr;
  1049. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n",
  1050. address, ar->fw_patch_len);
  1051. ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
  1052. if (ret) {
  1053. ath6kl_err("Failed to write patch file: %d\n", ret);
  1054. return ret;
  1055. }
  1056. param = address;
  1057. ath6kl_bmi_write(ar,
  1058. ath6kl_get_hi_item_addr(ar,
  1059. HI_ITEM(hi_dset_list_head)),
  1060. (unsigned char *) &param, 4);
  1061. return 0;
  1062. }
  1063. static int ath6kl_upload_testscript(struct ath6kl *ar)
  1064. {
  1065. u32 address, param;
  1066. int ret;
  1067. if (ar->testmode != 2)
  1068. return 0;
  1069. if (ar->fw_testscript == NULL)
  1070. return 0;
  1071. address = ar->hw.testscript_addr;
  1072. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
  1073. address, ar->fw_testscript_len);
  1074. ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
  1075. ar->fw_testscript_len);
  1076. if (ret) {
  1077. ath6kl_err("Failed to write testscript file: %d\n", ret);
  1078. return ret;
  1079. }
  1080. param = address;
  1081. ath6kl_bmi_write(ar,
  1082. ath6kl_get_hi_item_addr(ar,
  1083. HI_ITEM(hi_ota_testscript)),
  1084. (unsigned char *) &param, 4);
  1085. param = 4096;
  1086. ath6kl_bmi_write(ar,
  1087. ath6kl_get_hi_item_addr(ar,
  1088. HI_ITEM(hi_end_ram_reserve_sz)),
  1089. (unsigned char *) &param, 4);
  1090. param = 1;
  1091. ath6kl_bmi_write(ar,
  1092. ath6kl_get_hi_item_addr(ar,
  1093. HI_ITEM(hi_test_apps_related)),
  1094. (unsigned char *) &param, 4);
  1095. return 0;
  1096. }
  1097. static int ath6kl_init_upload(struct ath6kl *ar)
  1098. {
  1099. u32 param, options, sleep, address;
  1100. int status = 0;
  1101. if (ar->target_type != TARGET_TYPE_AR6003 &&
  1102. ar->target_type != TARGET_TYPE_AR6004)
  1103. return -EINVAL;
  1104. /* temporarily disable system sleep */
  1105. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1106. status = ath6kl_bmi_reg_read(ar, address, &param);
  1107. if (status)
  1108. return status;
  1109. options = param;
  1110. param |= ATH6KL_OPTION_SLEEP_DISABLE;
  1111. status = ath6kl_bmi_reg_write(ar, address, param);
  1112. if (status)
  1113. return status;
  1114. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1115. status = ath6kl_bmi_reg_read(ar, address, &param);
  1116. if (status)
  1117. return status;
  1118. sleep = param;
  1119. param |= SM(SYSTEM_SLEEP_DISABLE, 1);
  1120. status = ath6kl_bmi_reg_write(ar, address, param);
  1121. if (status)
  1122. return status;
  1123. ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
  1124. options, sleep);
  1125. /* program analog PLL register */
  1126. /* no need to control 40/44MHz clock on AR6004 */
  1127. if (ar->target_type != TARGET_TYPE_AR6004) {
  1128. status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
  1129. 0xF9104001);
  1130. if (status)
  1131. return status;
  1132. /* Run at 80/88MHz by default */
  1133. param = SM(CPU_CLOCK_STANDARD, 1);
  1134. address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
  1135. status = ath6kl_bmi_reg_write(ar, address, param);
  1136. if (status)
  1137. return status;
  1138. }
  1139. param = 0;
  1140. address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
  1141. param = SM(LPO_CAL_ENABLE, 1);
  1142. status = ath6kl_bmi_reg_write(ar, address, param);
  1143. if (status)
  1144. return status;
  1145. /* WAR to avoid SDIO CRC err */
  1146. if (ar->version.target_ver == AR6003_HW_2_0_VERSION) {
  1147. ath6kl_err("temporary war to avoid sdio crc error\n");
  1148. param = 0x20;
  1149. address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
  1150. status = ath6kl_bmi_reg_write(ar, address, param);
  1151. if (status)
  1152. return status;
  1153. address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
  1154. status = ath6kl_bmi_reg_write(ar, address, param);
  1155. if (status)
  1156. return status;
  1157. address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
  1158. status = ath6kl_bmi_reg_write(ar, address, param);
  1159. if (status)
  1160. return status;
  1161. address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
  1162. status = ath6kl_bmi_reg_write(ar, address, param);
  1163. if (status)
  1164. return status;
  1165. }
  1166. /* write EEPROM data to Target RAM */
  1167. status = ath6kl_upload_board_file(ar);
  1168. if (status)
  1169. return status;
  1170. /* transfer One time Programmable data */
  1171. status = ath6kl_upload_otp(ar);
  1172. if (status)
  1173. return status;
  1174. /* Download Target firmware */
  1175. status = ath6kl_upload_firmware(ar);
  1176. if (status)
  1177. return status;
  1178. status = ath6kl_upload_patch(ar);
  1179. if (status)
  1180. return status;
  1181. /* Download the test script */
  1182. status = ath6kl_upload_testscript(ar);
  1183. if (status)
  1184. return status;
  1185. /* Restore system sleep */
  1186. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1187. status = ath6kl_bmi_reg_write(ar, address, sleep);
  1188. if (status)
  1189. return status;
  1190. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1191. param = options | 0x20;
  1192. status = ath6kl_bmi_reg_write(ar, address, param);
  1193. if (status)
  1194. return status;
  1195. return status;
  1196. }
  1197. int ath6kl_init_hw_params(struct ath6kl *ar)
  1198. {
  1199. const struct ath6kl_hw *uninitialized_var(hw);
  1200. int i;
  1201. for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
  1202. hw = &hw_list[i];
  1203. if (hw->id == ar->version.target_ver)
  1204. break;
  1205. }
  1206. if (i == ARRAY_SIZE(hw_list)) {
  1207. ath6kl_err("Unsupported hardware version: 0x%x\n",
  1208. ar->version.target_ver);
  1209. return -EINVAL;
  1210. }
  1211. ar->hw = *hw;
  1212. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1213. "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n",
  1214. ar->version.target_ver, ar->target_type,
  1215. ar->hw.dataset_patch_addr, ar->hw.app_load_addr);
  1216. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1217. "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x",
  1218. ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr,
  1219. ar->hw.reserved_ram_size);
  1220. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1221. "refclk_hz %d uarttx_pin %d",
  1222. ar->hw.refclk_hz, ar->hw.uarttx_pin);
  1223. return 0;
  1224. }
  1225. static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type)
  1226. {
  1227. switch (type) {
  1228. case ATH6KL_HIF_TYPE_SDIO:
  1229. return "sdio";
  1230. case ATH6KL_HIF_TYPE_USB:
  1231. return "usb";
  1232. }
  1233. return NULL;
  1234. }
  1235. int ath6kl_init_hw_start(struct ath6kl *ar)
  1236. {
  1237. long timeleft;
  1238. int ret, i;
  1239. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n");
  1240. ret = ath6kl_hif_power_on(ar);
  1241. if (ret)
  1242. return ret;
  1243. ret = ath6kl_configure_target(ar);
  1244. if (ret)
  1245. goto err_power_off;
  1246. ret = ath6kl_init_upload(ar);
  1247. if (ret)
  1248. goto err_power_off;
  1249. /* Do we need to finish the BMI phase */
  1250. /* FIXME: return error from ath6kl_bmi_done() */
  1251. if (ath6kl_bmi_done(ar)) {
  1252. ret = -EIO;
  1253. goto err_power_off;
  1254. }
  1255. /*
  1256. * The reason we have to wait for the target here is that the
  1257. * driver layer has to init BMI in order to set the host block
  1258. * size.
  1259. */
  1260. if (ath6kl_htc_wait_target(ar->htc_target)) {
  1261. ret = -EIO;
  1262. goto err_power_off;
  1263. }
  1264. if (ath6kl_init_service_ep(ar)) {
  1265. ret = -EIO;
  1266. goto err_cleanup_scatter;
  1267. }
  1268. /* setup credit distribution */
  1269. ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info);
  1270. /* start HTC */
  1271. ret = ath6kl_htc_start(ar->htc_target);
  1272. if (ret) {
  1273. /* FIXME: call this */
  1274. ath6kl_cookie_cleanup(ar);
  1275. goto err_cleanup_scatter;
  1276. }
  1277. /* Wait for Wmi event to be ready */
  1278. timeleft = wait_event_interruptible_timeout(ar->event_wq,
  1279. test_bit(WMI_READY,
  1280. &ar->flag),
  1281. WMI_TIMEOUT);
  1282. ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n");
  1283. if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) {
  1284. ath6kl_info("%s %s fw %s api %d%s\n",
  1285. ar->hw.name,
  1286. ath6kl_init_get_hif_name(ar->hif_type),
  1287. ar->wiphy->fw_version,
  1288. ar->fw_api,
  1289. test_bit(TESTMODE, &ar->flag) ? " testmode" : "");
  1290. }
  1291. if (ar->version.abi_ver != ATH6KL_ABI_VERSION) {
  1292. ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n",
  1293. ATH6KL_ABI_VERSION, ar->version.abi_ver);
  1294. ret = -EIO;
  1295. goto err_htc_stop;
  1296. }
  1297. if (!timeleft || signal_pending(current)) {
  1298. ath6kl_err("wmi is not ready or wait was interrupted\n");
  1299. ret = -EIO;
  1300. goto err_htc_stop;
  1301. }
  1302. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__);
  1303. /* communicate the wmi protocol verision to the target */
  1304. /* FIXME: return error */
  1305. if ((ath6kl_set_host_app_area(ar)) != 0)
  1306. ath6kl_err("unable to set the host app area\n");
  1307. for (i = 0; i < ar->vif_max; i++) {
  1308. ret = ath6kl_target_config_wlan_params(ar, i);
  1309. if (ret)
  1310. goto err_htc_stop;
  1311. }
  1312. ar->state = ATH6KL_STATE_ON;
  1313. return 0;
  1314. err_htc_stop:
  1315. ath6kl_htc_stop(ar->htc_target);
  1316. err_cleanup_scatter:
  1317. ath6kl_hif_cleanup_scatter(ar);
  1318. err_power_off:
  1319. ath6kl_hif_power_off(ar);
  1320. return ret;
  1321. }
  1322. int ath6kl_init_hw_stop(struct ath6kl *ar)
  1323. {
  1324. int ret;
  1325. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n");
  1326. ath6kl_htc_stop(ar->htc_target);
  1327. ath6kl_hif_stop(ar);
  1328. ath6kl_bmi_reset(ar);
  1329. ret = ath6kl_hif_power_off(ar);
  1330. if (ret)
  1331. ath6kl_warn("failed to power off hif: %d\n", ret);
  1332. ar->state = ATH6KL_STATE_OFF;
  1333. return 0;
  1334. }
  1335. /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */
  1336. void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready)
  1337. {
  1338. static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  1339. bool discon_issued;
  1340. netif_stop_queue(vif->ndev);
  1341. clear_bit(WLAN_ENABLED, &vif->flags);
  1342. if (wmi_ready) {
  1343. discon_issued = test_bit(CONNECTED, &vif->flags) ||
  1344. test_bit(CONNECT_PEND, &vif->flags);
  1345. ath6kl_disconnect(vif);
  1346. del_timer(&vif->disconnect_timer);
  1347. if (discon_issued)
  1348. ath6kl_disconnect_event(vif, DISCONNECT_CMD,
  1349. (vif->nw_type & AP_NETWORK) ?
  1350. bcast_mac : vif->bssid,
  1351. 0, NULL, 0);
  1352. }
  1353. if (vif->scan_req) {
  1354. cfg80211_scan_done(vif->scan_req, true);
  1355. vif->scan_req = NULL;
  1356. }
  1357. }
  1358. void ath6kl_stop_txrx(struct ath6kl *ar)
  1359. {
  1360. struct ath6kl_vif *vif, *tmp_vif;
  1361. int i;
  1362. set_bit(DESTROY_IN_PROGRESS, &ar->flag);
  1363. if (down_interruptible(&ar->sem)) {
  1364. ath6kl_err("down_interruptible failed\n");
  1365. return;
  1366. }
  1367. for (i = 0; i < AP_MAX_NUM_STA; i++)
  1368. aggr_reset_state(ar->sta_list[i].aggr_conn);
  1369. spin_lock_bh(&ar->list_lock);
  1370. list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) {
  1371. list_del(&vif->list);
  1372. spin_unlock_bh(&ar->list_lock);
  1373. ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag));
  1374. rtnl_lock();
  1375. ath6kl_cfg80211_vif_cleanup(vif);
  1376. rtnl_unlock();
  1377. spin_lock_bh(&ar->list_lock);
  1378. }
  1379. spin_unlock_bh(&ar->list_lock);
  1380. clear_bit(WMI_READY, &ar->flag);
  1381. /*
  1382. * After wmi_shudown all WMI events will be dropped. We
  1383. * need to cleanup the buffers allocated in AP mode and
  1384. * give disconnect notification to stack, which usually
  1385. * happens in the disconnect_event. Simulate the disconnect
  1386. * event by calling the function directly. Sometimes
  1387. * disconnect_event will be received when the debug logs
  1388. * are collected.
  1389. */
  1390. ath6kl_wmi_shutdown(ar->wmi);
  1391. clear_bit(WMI_ENABLED, &ar->flag);
  1392. if (ar->htc_target) {
  1393. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__);
  1394. ath6kl_htc_stop(ar->htc_target);
  1395. }
  1396. /*
  1397. * Try to reset the device if we can. The driver may have been
  1398. * configure NOT to reset the target during a debug session.
  1399. */
  1400. ath6kl_dbg(ATH6KL_DBG_TRC,
  1401. "attempting to reset target on instance destroy\n");
  1402. ath6kl_reset_device(ar, ar->target_type, true, true);
  1403. clear_bit(WLAN_ENABLED, &ar->flag);
  1404. }
  1405. EXPORT_SYMBOL(ath6kl_stop_txrx);