core.c 21 KB

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  1. /*
  2. * Filename: core.c
  3. *
  4. *
  5. * Authors: Joshua Morris <josh.h.morris@us.ibm.com>
  6. * Philip Kelleher <pjk1939@linux.vnet.ibm.com>
  7. *
  8. * (C) Copyright 2013 IBM Corporation
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of the
  13. * License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software Foundation,
  22. * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/init.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/module.h>
  28. #include <linux/pci.h>
  29. #include <linux/reboot.h>
  30. #include <linux/slab.h>
  31. #include <linux/bitops.h>
  32. #include <linux/delay.h>
  33. #include <linux/genhd.h>
  34. #include <linux/idr.h>
  35. #include "rsxx_priv.h"
  36. #include "rsxx_cfg.h"
  37. #define NO_LEGACY 0
  38. #define SYNC_START_TIMEOUT (10 * 60) /* 10 minutes */
  39. MODULE_DESCRIPTION("IBM FlashSystem 70/80 PCIe SSD Device Driver");
  40. MODULE_AUTHOR("Joshua Morris/Philip Kelleher, IBM");
  41. MODULE_LICENSE("GPL");
  42. MODULE_VERSION(DRIVER_VERSION);
  43. static unsigned int force_legacy = NO_LEGACY;
  44. module_param(force_legacy, uint, 0444);
  45. MODULE_PARM_DESC(force_legacy, "Force the use of legacy type PCI interrupts");
  46. static unsigned int sync_start = 1;
  47. module_param(sync_start, uint, 0444);
  48. MODULE_PARM_DESC(sync_start, "On by Default: Driver load will not complete "
  49. "until the card startup has completed.");
  50. static DEFINE_IDA(rsxx_disk_ida);
  51. static DEFINE_SPINLOCK(rsxx_ida_lock);
  52. /*----------------- Interrupt Control & Handling -------------------*/
  53. static void rsxx_mask_interrupts(struct rsxx_cardinfo *card)
  54. {
  55. card->isr_mask = 0;
  56. card->ier_mask = 0;
  57. }
  58. static void __enable_intr(unsigned int *mask, unsigned int intr)
  59. {
  60. *mask |= intr;
  61. }
  62. static void __disable_intr(unsigned int *mask, unsigned int intr)
  63. {
  64. *mask &= ~intr;
  65. }
  66. /*
  67. * NOTE: Disabling the IER will disable the hardware interrupt.
  68. * Disabling the ISR will disable the software handling of the ISR bit.
  69. *
  70. * Enable/Disable interrupt functions assume the card->irq_lock
  71. * is held by the caller.
  72. */
  73. void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr)
  74. {
  75. if (unlikely(card->halt) ||
  76. unlikely(card->eeh_state))
  77. return;
  78. __enable_intr(&card->ier_mask, intr);
  79. iowrite32(card->ier_mask, card->regmap + IER);
  80. }
  81. void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr)
  82. {
  83. if (unlikely(card->eeh_state))
  84. return;
  85. __disable_intr(&card->ier_mask, intr);
  86. iowrite32(card->ier_mask, card->regmap + IER);
  87. }
  88. void rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card,
  89. unsigned int intr)
  90. {
  91. if (unlikely(card->halt) ||
  92. unlikely(card->eeh_state))
  93. return;
  94. __enable_intr(&card->isr_mask, intr);
  95. __enable_intr(&card->ier_mask, intr);
  96. iowrite32(card->ier_mask, card->regmap + IER);
  97. }
  98. void rsxx_disable_ier_and_isr(struct rsxx_cardinfo *card,
  99. unsigned int intr)
  100. {
  101. if (unlikely(card->eeh_state))
  102. return;
  103. __disable_intr(&card->isr_mask, intr);
  104. __disable_intr(&card->ier_mask, intr);
  105. iowrite32(card->ier_mask, card->regmap + IER);
  106. }
  107. static irqreturn_t rsxx_isr(int irq, void *pdata)
  108. {
  109. struct rsxx_cardinfo *card = pdata;
  110. unsigned int isr;
  111. int handled = 0;
  112. int reread_isr;
  113. int i;
  114. spin_lock(&card->irq_lock);
  115. do {
  116. reread_isr = 0;
  117. if (unlikely(card->eeh_state))
  118. break;
  119. isr = ioread32(card->regmap + ISR);
  120. if (isr == 0xffffffff) {
  121. /*
  122. * A few systems seem to have an intermittent issue
  123. * where PCI reads return all Fs, but retrying the read
  124. * a little later will return as expected.
  125. */
  126. dev_info(CARD_TO_DEV(card),
  127. "ISR = 0xFFFFFFFF, retrying later\n");
  128. break;
  129. }
  130. isr &= card->isr_mask;
  131. if (!isr)
  132. break;
  133. for (i = 0; i < card->n_targets; i++) {
  134. if (isr & CR_INTR_DMA(i)) {
  135. if (card->ier_mask & CR_INTR_DMA(i)) {
  136. rsxx_disable_ier(card, CR_INTR_DMA(i));
  137. reread_isr = 1;
  138. }
  139. queue_work(card->ctrl[i].done_wq,
  140. &card->ctrl[i].dma_done_work);
  141. handled++;
  142. }
  143. }
  144. if (isr & CR_INTR_CREG) {
  145. queue_work(card->creg_ctrl.creg_wq,
  146. &card->creg_ctrl.done_work);
  147. handled++;
  148. }
  149. if (isr & CR_INTR_EVENT) {
  150. queue_work(card->event_wq, &card->event_work);
  151. rsxx_disable_ier_and_isr(card, CR_INTR_EVENT);
  152. handled++;
  153. }
  154. } while (reread_isr);
  155. spin_unlock(&card->irq_lock);
  156. return handled ? IRQ_HANDLED : IRQ_NONE;
  157. }
  158. /*----------------- Card Event Handler -------------------*/
  159. static const char * const rsxx_card_state_to_str(unsigned int state)
  160. {
  161. static const char * const state_strings[] = {
  162. "Unknown", "Shutdown", "Starting", "Formatting",
  163. "Uninitialized", "Good", "Shutting Down",
  164. "Fault", "Read Only Fault", "dStroying"
  165. };
  166. return state_strings[ffs(state)];
  167. }
  168. static void card_state_change(struct rsxx_cardinfo *card,
  169. unsigned int new_state)
  170. {
  171. int st;
  172. dev_info(CARD_TO_DEV(card),
  173. "card state change detected.(%s -> %s)\n",
  174. rsxx_card_state_to_str(card->state),
  175. rsxx_card_state_to_str(new_state));
  176. card->state = new_state;
  177. /* Don't attach DMA interfaces if the card has an invalid config */
  178. if (!card->config_valid)
  179. return;
  180. switch (new_state) {
  181. case CARD_STATE_RD_ONLY_FAULT:
  182. dev_crit(CARD_TO_DEV(card),
  183. "Hardware has entered read-only mode!\n");
  184. /*
  185. * Fall through so the DMA devices can be attached and
  186. * the user can attempt to pull off their data.
  187. */
  188. case CARD_STATE_GOOD:
  189. st = rsxx_get_card_size8(card, &card->size8);
  190. if (st)
  191. dev_err(CARD_TO_DEV(card),
  192. "Failed attaching DMA devices\n");
  193. if (card->config_valid)
  194. set_capacity(card->gendisk, card->size8 >> 9);
  195. break;
  196. case CARD_STATE_FAULT:
  197. dev_crit(CARD_TO_DEV(card),
  198. "Hardware Fault reported!\n");
  199. /* Fall through. */
  200. /* Everything else, detach DMA interface if it's attached. */
  201. case CARD_STATE_SHUTDOWN:
  202. case CARD_STATE_STARTING:
  203. case CARD_STATE_FORMATTING:
  204. case CARD_STATE_UNINITIALIZED:
  205. case CARD_STATE_SHUTTING_DOWN:
  206. /*
  207. * dStroy is a term coined by marketing to represent the low level
  208. * secure erase.
  209. */
  210. case CARD_STATE_DSTROYING:
  211. set_capacity(card->gendisk, 0);
  212. break;
  213. }
  214. }
  215. static void card_event_handler(struct work_struct *work)
  216. {
  217. struct rsxx_cardinfo *card;
  218. unsigned int state;
  219. unsigned long flags;
  220. int st;
  221. card = container_of(work, struct rsxx_cardinfo, event_work);
  222. if (unlikely(card->halt))
  223. return;
  224. /*
  225. * Enable the interrupt now to avoid any weird race conditions where a
  226. * state change might occur while rsxx_get_card_state() is
  227. * processing a returned creg cmd.
  228. */
  229. spin_lock_irqsave(&card->irq_lock, flags);
  230. rsxx_enable_ier_and_isr(card, CR_INTR_EVENT);
  231. spin_unlock_irqrestore(&card->irq_lock, flags);
  232. st = rsxx_get_card_state(card, &state);
  233. if (st) {
  234. dev_info(CARD_TO_DEV(card),
  235. "Failed reading state after event.\n");
  236. return;
  237. }
  238. if (card->state != state)
  239. card_state_change(card, state);
  240. if (card->creg_ctrl.creg_stats.stat & CREG_STAT_LOG_PENDING)
  241. rsxx_read_hw_log(card);
  242. }
  243. /*----------------- Card Operations -------------------*/
  244. static int card_shutdown(struct rsxx_cardinfo *card)
  245. {
  246. unsigned int state;
  247. signed long start;
  248. const int timeout = msecs_to_jiffies(120000);
  249. int st;
  250. /* We can't issue a shutdown if the card is in a transition state */
  251. start = jiffies;
  252. do {
  253. st = rsxx_get_card_state(card, &state);
  254. if (st)
  255. return st;
  256. } while (state == CARD_STATE_STARTING &&
  257. (jiffies - start < timeout));
  258. if (state == CARD_STATE_STARTING)
  259. return -ETIMEDOUT;
  260. /* Only issue a shutdown if we need to */
  261. if ((state != CARD_STATE_SHUTTING_DOWN) &&
  262. (state != CARD_STATE_SHUTDOWN)) {
  263. st = rsxx_issue_card_cmd(card, CARD_CMD_SHUTDOWN);
  264. if (st)
  265. return st;
  266. }
  267. start = jiffies;
  268. do {
  269. st = rsxx_get_card_state(card, &state);
  270. if (st)
  271. return st;
  272. } while (state != CARD_STATE_SHUTDOWN &&
  273. (jiffies - start < timeout));
  274. if (state != CARD_STATE_SHUTDOWN)
  275. return -ETIMEDOUT;
  276. return 0;
  277. }
  278. static int rsxx_eeh_frozen(struct pci_dev *dev)
  279. {
  280. struct rsxx_cardinfo *card = pci_get_drvdata(dev);
  281. int i;
  282. int st;
  283. dev_warn(&dev->dev, "IBM FlashSystem PCI: preparing for slot reset.\n");
  284. card->eeh_state = 1;
  285. rsxx_mask_interrupts(card);
  286. /*
  287. * We need to guarantee that the write for eeh_state and masking
  288. * interrupts does not become reordered. This will prevent a possible
  289. * race condition with the EEH code.
  290. */
  291. wmb();
  292. pci_disable_device(dev);
  293. st = rsxx_eeh_save_issued_dmas(card);
  294. if (st)
  295. return st;
  296. rsxx_eeh_save_issued_creg(card);
  297. for (i = 0; i < card->n_targets; i++) {
  298. if (card->ctrl[i].status.buf)
  299. pci_free_consistent(card->dev, STATUS_BUFFER_SIZE8,
  300. card->ctrl[i].status.buf,
  301. card->ctrl[i].status.dma_addr);
  302. if (card->ctrl[i].cmd.buf)
  303. pci_free_consistent(card->dev, COMMAND_BUFFER_SIZE8,
  304. card->ctrl[i].cmd.buf,
  305. card->ctrl[i].cmd.dma_addr);
  306. }
  307. return 0;
  308. }
  309. static void rsxx_eeh_failure(struct pci_dev *dev)
  310. {
  311. struct rsxx_cardinfo *card = pci_get_drvdata(dev);
  312. int i;
  313. int cnt = 0;
  314. dev_err(&dev->dev, "IBM FlashSystem PCI: disabling failed card.\n");
  315. card->eeh_state = 1;
  316. card->halt = 1;
  317. for (i = 0; i < card->n_targets; i++) {
  318. spin_lock_bh(&card->ctrl[i].queue_lock);
  319. cnt = rsxx_cleanup_dma_queue(&card->ctrl[i],
  320. &card->ctrl[i].queue);
  321. spin_unlock_bh(&card->ctrl[i].queue_lock);
  322. cnt += rsxx_dma_cancel(&card->ctrl[i]);
  323. if (cnt)
  324. dev_info(CARD_TO_DEV(card),
  325. "Freed %d queued DMAs on channel %d\n",
  326. cnt, card->ctrl[i].id);
  327. }
  328. }
  329. static int rsxx_eeh_fifo_flush_poll(struct rsxx_cardinfo *card)
  330. {
  331. unsigned int status;
  332. int iter = 0;
  333. /* We need to wait for the hardware to reset */
  334. while (iter++ < 10) {
  335. status = ioread32(card->regmap + PCI_RECONFIG);
  336. if (status & RSXX_FLUSH_BUSY) {
  337. ssleep(1);
  338. continue;
  339. }
  340. if (status & RSXX_FLUSH_TIMEOUT)
  341. dev_warn(CARD_TO_DEV(card), "HW: flash controller timeout\n");
  342. return 0;
  343. }
  344. /* Hardware failed resetting itself. */
  345. return -1;
  346. }
  347. static pci_ers_result_t rsxx_error_detected(struct pci_dev *dev,
  348. enum pci_channel_state error)
  349. {
  350. int st;
  351. if (dev->revision < RSXX_EEH_SUPPORT)
  352. return PCI_ERS_RESULT_NONE;
  353. if (error == pci_channel_io_perm_failure) {
  354. rsxx_eeh_failure(dev);
  355. return PCI_ERS_RESULT_DISCONNECT;
  356. }
  357. st = rsxx_eeh_frozen(dev);
  358. if (st) {
  359. dev_err(&dev->dev, "Slot reset setup failed\n");
  360. rsxx_eeh_failure(dev);
  361. return PCI_ERS_RESULT_DISCONNECT;
  362. }
  363. return PCI_ERS_RESULT_NEED_RESET;
  364. }
  365. static pci_ers_result_t rsxx_slot_reset(struct pci_dev *dev)
  366. {
  367. struct rsxx_cardinfo *card = pci_get_drvdata(dev);
  368. unsigned long flags;
  369. int i;
  370. int st;
  371. dev_warn(&dev->dev,
  372. "IBM FlashSystem PCI: recovering from slot reset.\n");
  373. st = pci_enable_device(dev);
  374. if (st)
  375. goto failed_hw_setup;
  376. pci_set_master(dev);
  377. st = rsxx_eeh_fifo_flush_poll(card);
  378. if (st)
  379. goto failed_hw_setup;
  380. rsxx_dma_queue_reset(card);
  381. for (i = 0; i < card->n_targets; i++) {
  382. st = rsxx_hw_buffers_init(dev, &card->ctrl[i]);
  383. if (st)
  384. goto failed_hw_buffers_init;
  385. }
  386. if (card->config_valid)
  387. rsxx_dma_configure(card);
  388. /* Clears the ISR register from spurious interrupts */
  389. st = ioread32(card->regmap + ISR);
  390. card->eeh_state = 0;
  391. st = rsxx_eeh_remap_dmas(card);
  392. if (st)
  393. goto failed_remap_dmas;
  394. spin_lock_irqsave(&card->irq_lock, flags);
  395. if (card->n_targets & RSXX_MAX_TARGETS)
  396. rsxx_enable_ier_and_isr(card, CR_INTR_ALL_G);
  397. else
  398. rsxx_enable_ier_and_isr(card, CR_INTR_ALL_C);
  399. spin_unlock_irqrestore(&card->irq_lock, flags);
  400. rsxx_kick_creg_queue(card);
  401. for (i = 0; i < card->n_targets; i++) {
  402. spin_lock(&card->ctrl[i].queue_lock);
  403. if (list_empty(&card->ctrl[i].queue)) {
  404. spin_unlock(&card->ctrl[i].queue_lock);
  405. continue;
  406. }
  407. spin_unlock(&card->ctrl[i].queue_lock);
  408. queue_work(card->ctrl[i].issue_wq,
  409. &card->ctrl[i].issue_dma_work);
  410. }
  411. dev_info(&dev->dev, "IBM FlashSystem PCI: recovery complete.\n");
  412. return PCI_ERS_RESULT_RECOVERED;
  413. failed_hw_buffers_init:
  414. failed_remap_dmas:
  415. for (i = 0; i < card->n_targets; i++) {
  416. if (card->ctrl[i].status.buf)
  417. pci_free_consistent(card->dev,
  418. STATUS_BUFFER_SIZE8,
  419. card->ctrl[i].status.buf,
  420. card->ctrl[i].status.dma_addr);
  421. if (card->ctrl[i].cmd.buf)
  422. pci_free_consistent(card->dev,
  423. COMMAND_BUFFER_SIZE8,
  424. card->ctrl[i].cmd.buf,
  425. card->ctrl[i].cmd.dma_addr);
  426. }
  427. failed_hw_setup:
  428. rsxx_eeh_failure(dev);
  429. return PCI_ERS_RESULT_DISCONNECT;
  430. }
  431. /*----------------- Driver Initialization & Setup -------------------*/
  432. /* Returns: 0 if the driver is compatible with the device
  433. -1 if the driver is NOT compatible with the device */
  434. static int rsxx_compatibility_check(struct rsxx_cardinfo *card)
  435. {
  436. unsigned char pci_rev;
  437. pci_read_config_byte(card->dev, PCI_REVISION_ID, &pci_rev);
  438. if (pci_rev > RS70_PCI_REV_SUPPORTED)
  439. return -1;
  440. return 0;
  441. }
  442. static int rsxx_pci_probe(struct pci_dev *dev,
  443. const struct pci_device_id *id)
  444. {
  445. struct rsxx_cardinfo *card;
  446. int st;
  447. unsigned int sync_timeout;
  448. dev_info(&dev->dev, "PCI-Flash SSD discovered\n");
  449. card = kzalloc(sizeof(*card), GFP_KERNEL);
  450. if (!card)
  451. return -ENOMEM;
  452. card->dev = dev;
  453. pci_set_drvdata(dev, card);
  454. do {
  455. if (!ida_pre_get(&rsxx_disk_ida, GFP_KERNEL)) {
  456. st = -ENOMEM;
  457. goto failed_ida_get;
  458. }
  459. spin_lock(&rsxx_ida_lock);
  460. st = ida_get_new(&rsxx_disk_ida, &card->disk_id);
  461. spin_unlock(&rsxx_ida_lock);
  462. } while (st == -EAGAIN);
  463. if (st)
  464. goto failed_ida_get;
  465. st = pci_enable_device(dev);
  466. if (st)
  467. goto failed_enable;
  468. pci_set_master(dev);
  469. pci_set_dma_max_seg_size(dev, RSXX_HW_BLK_SIZE);
  470. st = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
  471. if (st) {
  472. dev_err(CARD_TO_DEV(card),
  473. "No usable DMA configuration,aborting\n");
  474. goto failed_dma_mask;
  475. }
  476. st = pci_request_regions(dev, DRIVER_NAME);
  477. if (st) {
  478. dev_err(CARD_TO_DEV(card),
  479. "Failed to request memory region\n");
  480. goto failed_request_regions;
  481. }
  482. if (pci_resource_len(dev, 0) == 0) {
  483. dev_err(CARD_TO_DEV(card), "BAR0 has length 0!\n");
  484. st = -ENOMEM;
  485. goto failed_iomap;
  486. }
  487. card->regmap = pci_iomap(dev, 0, 0);
  488. if (!card->regmap) {
  489. dev_err(CARD_TO_DEV(card), "Failed to map BAR0\n");
  490. st = -ENOMEM;
  491. goto failed_iomap;
  492. }
  493. spin_lock_init(&card->irq_lock);
  494. card->halt = 0;
  495. card->eeh_state = 0;
  496. spin_lock_irq(&card->irq_lock);
  497. rsxx_disable_ier_and_isr(card, CR_INTR_ALL);
  498. spin_unlock_irq(&card->irq_lock);
  499. if (!force_legacy) {
  500. st = pci_enable_msi(dev);
  501. if (st)
  502. dev_warn(CARD_TO_DEV(card),
  503. "Failed to enable MSI\n");
  504. }
  505. st = request_irq(dev->irq, rsxx_isr, IRQF_DISABLED | IRQF_SHARED,
  506. DRIVER_NAME, card);
  507. if (st) {
  508. dev_err(CARD_TO_DEV(card),
  509. "Failed requesting IRQ%d\n", dev->irq);
  510. goto failed_irq;
  511. }
  512. /************* Setup Processor Command Interface *************/
  513. st = rsxx_creg_setup(card);
  514. if (st) {
  515. dev_err(CARD_TO_DEV(card), "Failed to setup creg interface.\n");
  516. goto failed_creg_setup;
  517. }
  518. spin_lock_irq(&card->irq_lock);
  519. rsxx_enable_ier_and_isr(card, CR_INTR_CREG);
  520. spin_unlock_irq(&card->irq_lock);
  521. st = rsxx_compatibility_check(card);
  522. if (st) {
  523. dev_warn(CARD_TO_DEV(card),
  524. "Incompatible driver detected. Please update the driver.\n");
  525. st = -EINVAL;
  526. goto failed_compatiblity_check;
  527. }
  528. /************* Load Card Config *************/
  529. st = rsxx_load_config(card);
  530. if (st)
  531. dev_err(CARD_TO_DEV(card),
  532. "Failed loading card config\n");
  533. /************* Setup DMA Engine *************/
  534. st = rsxx_get_num_targets(card, &card->n_targets);
  535. if (st)
  536. dev_info(CARD_TO_DEV(card),
  537. "Failed reading the number of DMA targets\n");
  538. card->ctrl = kzalloc(card->n_targets * sizeof(*card->ctrl), GFP_KERNEL);
  539. if (!card->ctrl) {
  540. st = -ENOMEM;
  541. goto failed_dma_setup;
  542. }
  543. st = rsxx_dma_setup(card);
  544. if (st) {
  545. dev_info(CARD_TO_DEV(card),
  546. "Failed to setup DMA engine\n");
  547. goto failed_dma_setup;
  548. }
  549. /************* Setup Card Event Handler *************/
  550. card->event_wq = create_singlethread_workqueue(DRIVER_NAME"_event");
  551. if (!card->event_wq) {
  552. dev_err(CARD_TO_DEV(card), "Failed card event setup.\n");
  553. goto failed_event_handler;
  554. }
  555. INIT_WORK(&card->event_work, card_event_handler);
  556. st = rsxx_setup_dev(card);
  557. if (st)
  558. goto failed_create_dev;
  559. rsxx_get_card_state(card, &card->state);
  560. dev_info(CARD_TO_DEV(card),
  561. "card state: %s\n",
  562. rsxx_card_state_to_str(card->state));
  563. /*
  564. * Now that the DMA Engine and devices have been setup,
  565. * we can enable the event interrupt(it kicks off actions in
  566. * those layers so we couldn't enable it right away.)
  567. */
  568. spin_lock_irq(&card->irq_lock);
  569. rsxx_enable_ier_and_isr(card, CR_INTR_EVENT);
  570. spin_unlock_irq(&card->irq_lock);
  571. if (card->state == CARD_STATE_SHUTDOWN) {
  572. st = rsxx_issue_card_cmd(card, CARD_CMD_STARTUP);
  573. if (st)
  574. dev_crit(CARD_TO_DEV(card),
  575. "Failed issuing card startup\n");
  576. if (sync_start) {
  577. sync_timeout = SYNC_START_TIMEOUT;
  578. dev_info(CARD_TO_DEV(card),
  579. "Waiting for card to startup\n");
  580. do {
  581. ssleep(1);
  582. sync_timeout--;
  583. rsxx_get_card_state(card, &card->state);
  584. } while (sync_timeout &&
  585. (card->state == CARD_STATE_STARTING));
  586. if (card->state == CARD_STATE_STARTING) {
  587. dev_warn(CARD_TO_DEV(card),
  588. "Card startup timed out\n");
  589. card->size8 = 0;
  590. } else {
  591. dev_info(CARD_TO_DEV(card),
  592. "card state: %s\n",
  593. rsxx_card_state_to_str(card->state));
  594. st = rsxx_get_card_size8(card, &card->size8);
  595. if (st)
  596. card->size8 = 0;
  597. }
  598. }
  599. } else if (card->state == CARD_STATE_GOOD ||
  600. card->state == CARD_STATE_RD_ONLY_FAULT) {
  601. st = rsxx_get_card_size8(card, &card->size8);
  602. if (st)
  603. card->size8 = 0;
  604. }
  605. rsxx_attach_dev(card);
  606. return 0;
  607. failed_create_dev:
  608. destroy_workqueue(card->event_wq);
  609. card->event_wq = NULL;
  610. failed_event_handler:
  611. rsxx_dma_destroy(card);
  612. failed_dma_setup:
  613. failed_compatiblity_check:
  614. destroy_workqueue(card->creg_ctrl.creg_wq);
  615. card->creg_ctrl.creg_wq = NULL;
  616. failed_creg_setup:
  617. spin_lock_irq(&card->irq_lock);
  618. rsxx_disable_ier_and_isr(card, CR_INTR_ALL);
  619. spin_unlock_irq(&card->irq_lock);
  620. free_irq(dev->irq, card);
  621. if (!force_legacy)
  622. pci_disable_msi(dev);
  623. failed_irq:
  624. pci_iounmap(dev, card->regmap);
  625. failed_iomap:
  626. pci_release_regions(dev);
  627. failed_request_regions:
  628. failed_dma_mask:
  629. pci_disable_device(dev);
  630. failed_enable:
  631. spin_lock(&rsxx_ida_lock);
  632. ida_remove(&rsxx_disk_ida, card->disk_id);
  633. spin_unlock(&rsxx_ida_lock);
  634. failed_ida_get:
  635. kfree(card);
  636. return st;
  637. }
  638. static void rsxx_pci_remove(struct pci_dev *dev)
  639. {
  640. struct rsxx_cardinfo *card = pci_get_drvdata(dev);
  641. unsigned long flags;
  642. int st;
  643. int i;
  644. if (!card)
  645. return;
  646. dev_info(CARD_TO_DEV(card),
  647. "Removing PCI-Flash SSD.\n");
  648. rsxx_detach_dev(card);
  649. for (i = 0; i < card->n_targets; i++) {
  650. spin_lock_irqsave(&card->irq_lock, flags);
  651. rsxx_disable_ier_and_isr(card, CR_INTR_DMA(i));
  652. spin_unlock_irqrestore(&card->irq_lock, flags);
  653. }
  654. st = card_shutdown(card);
  655. if (st)
  656. dev_crit(CARD_TO_DEV(card), "Shutdown failed!\n");
  657. /* Sync outstanding event handlers. */
  658. spin_lock_irqsave(&card->irq_lock, flags);
  659. rsxx_disable_ier_and_isr(card, CR_INTR_EVENT);
  660. spin_unlock_irqrestore(&card->irq_lock, flags);
  661. cancel_work_sync(&card->event_work);
  662. rsxx_destroy_dev(card);
  663. rsxx_dma_destroy(card);
  664. spin_lock_irqsave(&card->irq_lock, flags);
  665. rsxx_disable_ier_and_isr(card, CR_INTR_ALL);
  666. spin_unlock_irqrestore(&card->irq_lock, flags);
  667. /* Prevent work_structs from re-queuing themselves. */
  668. card->halt = 1;
  669. free_irq(dev->irq, card);
  670. if (!force_legacy)
  671. pci_disable_msi(dev);
  672. rsxx_creg_destroy(card);
  673. pci_iounmap(dev, card->regmap);
  674. pci_disable_device(dev);
  675. pci_release_regions(dev);
  676. kfree(card);
  677. }
  678. static int rsxx_pci_suspend(struct pci_dev *dev, pm_message_t state)
  679. {
  680. /* We don't support suspend at this time. */
  681. return -ENOSYS;
  682. }
  683. static void rsxx_pci_shutdown(struct pci_dev *dev)
  684. {
  685. struct rsxx_cardinfo *card = pci_get_drvdata(dev);
  686. unsigned long flags;
  687. int i;
  688. if (!card)
  689. return;
  690. dev_info(CARD_TO_DEV(card), "Shutting down PCI-Flash SSD.\n");
  691. rsxx_detach_dev(card);
  692. for (i = 0; i < card->n_targets; i++) {
  693. spin_lock_irqsave(&card->irq_lock, flags);
  694. rsxx_disable_ier_and_isr(card, CR_INTR_DMA(i));
  695. spin_unlock_irqrestore(&card->irq_lock, flags);
  696. }
  697. card_shutdown(card);
  698. }
  699. static const struct pci_error_handlers rsxx_err_handler = {
  700. .error_detected = rsxx_error_detected,
  701. .slot_reset = rsxx_slot_reset,
  702. };
  703. static DEFINE_PCI_DEVICE_TABLE(rsxx_pci_ids) = {
  704. {PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_FS70_FLASH)},
  705. {PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_FS80_FLASH)},
  706. {0,},
  707. };
  708. MODULE_DEVICE_TABLE(pci, rsxx_pci_ids);
  709. static struct pci_driver rsxx_pci_driver = {
  710. .name = DRIVER_NAME,
  711. .id_table = rsxx_pci_ids,
  712. .probe = rsxx_pci_probe,
  713. .remove = rsxx_pci_remove,
  714. .suspend = rsxx_pci_suspend,
  715. .shutdown = rsxx_pci_shutdown,
  716. .err_handler = &rsxx_err_handler,
  717. };
  718. static int __init rsxx_core_init(void)
  719. {
  720. int st;
  721. st = rsxx_dev_init();
  722. if (st)
  723. return st;
  724. st = rsxx_dma_init();
  725. if (st)
  726. goto dma_init_failed;
  727. st = rsxx_creg_init();
  728. if (st)
  729. goto creg_init_failed;
  730. return pci_register_driver(&rsxx_pci_driver);
  731. creg_init_failed:
  732. rsxx_dma_cleanup();
  733. dma_init_failed:
  734. rsxx_dev_cleanup();
  735. return st;
  736. }
  737. static void __exit rsxx_core_cleanup(void)
  738. {
  739. pci_unregister_driver(&rsxx_pci_driver);
  740. rsxx_creg_cleanup();
  741. rsxx_dma_cleanup();
  742. rsxx_dev_cleanup();
  743. }
  744. module_init(rsxx_core_init);
  745. module_exit(rsxx_core_cleanup);