tg3.c 415 KB

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  1. /*
  2. * tg3.c: Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. * Copyright (C) 2005-2011 Broadcom Corporation.
  8. *
  9. * Firmware is:
  10. * Derived from proprietary unpublished source code,
  11. * Copyright (C) 2000-2003 Broadcom Corporation.
  12. *
  13. * Permission is hereby granted for the distribution of this firmware
  14. * data in hexadecimal or equivalent format, provided this copyright
  15. * notice is accompanying it.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/stringify.h>
  20. #include <linux/kernel.h>
  21. #include <linux/types.h>
  22. #include <linux/compiler.h>
  23. #include <linux/slab.h>
  24. #include <linux/delay.h>
  25. #include <linux/in.h>
  26. #include <linux/init.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/ioport.h>
  29. #include <linux/pci.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/skbuff.h>
  33. #include <linux/ethtool.h>
  34. #include <linux/mdio.h>
  35. #include <linux/mii.h>
  36. #include <linux/phy.h>
  37. #include <linux/brcmphy.h>
  38. #include <linux/if_vlan.h>
  39. #include <linux/ip.h>
  40. #include <linux/tcp.h>
  41. #include <linux/workqueue.h>
  42. #include <linux/prefetch.h>
  43. #include <linux/dma-mapping.h>
  44. #include <linux/firmware.h>
  45. #include <net/checksum.h>
  46. #include <net/ip.h>
  47. #include <asm/system.h>
  48. #include <linux/io.h>
  49. #include <asm/byteorder.h>
  50. #include <linux/uaccess.h>
  51. #ifdef CONFIG_SPARC
  52. #include <asm/idprom.h>
  53. #include <asm/prom.h>
  54. #endif
  55. #define BAR_0 0
  56. #define BAR_2 2
  57. #include "tg3.h"
  58. /* Functions & macros to verify TG3_FLAGS types */
  59. static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
  60. {
  61. return test_bit(flag, bits);
  62. }
  63. static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
  64. {
  65. set_bit(flag, bits);
  66. }
  67. static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
  68. {
  69. clear_bit(flag, bits);
  70. }
  71. #define tg3_flag(tp, flag) \
  72. _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
  73. #define tg3_flag_set(tp, flag) \
  74. _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
  75. #define tg3_flag_clear(tp, flag) \
  76. _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
  77. #define DRV_MODULE_NAME "tg3"
  78. #define TG3_MAJ_NUM 3
  79. #define TG3_MIN_NUM 121
  80. #define DRV_MODULE_VERSION \
  81. __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  82. #define DRV_MODULE_RELDATE "November 2, 2011"
  83. #define RESET_KIND_SHUTDOWN 0
  84. #define RESET_KIND_INIT 1
  85. #define RESET_KIND_SUSPEND 2
  86. #define TG3_DEF_RX_MODE 0
  87. #define TG3_DEF_TX_MODE 0
  88. #define TG3_DEF_MSG_ENABLE \
  89. (NETIF_MSG_DRV | \
  90. NETIF_MSG_PROBE | \
  91. NETIF_MSG_LINK | \
  92. NETIF_MSG_TIMER | \
  93. NETIF_MSG_IFDOWN | \
  94. NETIF_MSG_IFUP | \
  95. NETIF_MSG_RX_ERR | \
  96. NETIF_MSG_TX_ERR)
  97. #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
  98. /* length of time before we decide the hardware is borked,
  99. * and dev->tx_timeout() should be called to fix the problem
  100. */
  101. #define TG3_TX_TIMEOUT (5 * HZ)
  102. /* hardware minimum and maximum for a single frame's data payload */
  103. #define TG3_MIN_MTU 60
  104. #define TG3_MAX_MTU(tp) \
  105. (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
  106. /* These numbers seem to be hard coded in the NIC firmware somehow.
  107. * You can't change the ring sizes, but you can change where you place
  108. * them in the NIC onboard memory.
  109. */
  110. #define TG3_RX_STD_RING_SIZE(tp) \
  111. (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
  112. TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
  113. #define TG3_DEF_RX_RING_PENDING 200
  114. #define TG3_RX_JMB_RING_SIZE(tp) \
  115. (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
  116. TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
  117. #define TG3_DEF_RX_JUMBO_RING_PENDING 100
  118. #define TG3_RSS_INDIR_TBL_SIZE 128
  119. /* Do not place this n-ring entries value into the tp struct itself,
  120. * we really want to expose these constants to GCC so that modulo et
  121. * al. operations are done with shifts and masks instead of with
  122. * hw multiply/modulo instructions. Another solution would be to
  123. * replace things like '% foo' with '& (foo - 1)'.
  124. */
  125. #define TG3_TX_RING_SIZE 512
  126. #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
  127. #define TG3_RX_STD_RING_BYTES(tp) \
  128. (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
  129. #define TG3_RX_JMB_RING_BYTES(tp) \
  130. (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
  131. #define TG3_RX_RCB_RING_BYTES(tp) \
  132. (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
  133. #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
  134. TG3_TX_RING_SIZE)
  135. #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
  136. #define TG3_DMA_BYTE_ENAB 64
  137. #define TG3_RX_STD_DMA_SZ 1536
  138. #define TG3_RX_JMB_DMA_SZ 9046
  139. #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
  140. #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
  141. #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
  142. #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
  143. (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
  144. #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
  145. (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
  146. /* Due to a hardware bug, the 5701 can only DMA to memory addresses
  147. * that are at least dword aligned when used in PCIX mode. The driver
  148. * works around this bug by double copying the packet. This workaround
  149. * is built into the normal double copy length check for efficiency.
  150. *
  151. * However, the double copy is only necessary on those architectures
  152. * where unaligned memory accesses are inefficient. For those architectures
  153. * where unaligned memory accesses incur little penalty, we can reintegrate
  154. * the 5701 in the normal rx path. Doing so saves a device structure
  155. * dereference by hardcoding the double copy threshold in place.
  156. */
  157. #define TG3_RX_COPY_THRESHOLD 256
  158. #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
  159. #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
  160. #else
  161. #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
  162. #endif
  163. #if (NET_IP_ALIGN != 0)
  164. #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
  165. #else
  166. #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
  167. #endif
  168. /* minimum number of free TX descriptors required to wake up TX process */
  169. #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
  170. #define TG3_TX_BD_DMA_MAX 4096
  171. #define TG3_RAW_IP_ALIGN 2
  172. #define TG3_FW_UPDATE_TIMEOUT_SEC 5
  173. #define FIRMWARE_TG3 "tigon/tg3.bin"
  174. #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
  175. #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
  176. static char version[] __devinitdata =
  177. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
  178. MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
  179. MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
  180. MODULE_LICENSE("GPL");
  181. MODULE_VERSION(DRV_MODULE_VERSION);
  182. MODULE_FIRMWARE(FIRMWARE_TG3);
  183. MODULE_FIRMWARE(FIRMWARE_TG3TSO);
  184. MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
  185. static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
  186. module_param(tg3_debug, int, 0);
  187. MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
  188. static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
  189. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
  190. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
  191. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
  192. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
  193. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
  194. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
  195. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
  196. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
  197. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
  198. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
  199. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
  200. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
  201. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
  202. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
  203. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
  204. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
  205. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
  206. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
  207. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
  208. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
  209. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
  210. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
  211. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  212. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  213. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  214. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  215. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
  216. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
  217. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
  218. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
  219. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
  220. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
  221. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
  222. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
  223. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
  224. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
  225. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
  226. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
  227. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
  228. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
  229. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
  230. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
  231. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
  232. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
  233. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
  234. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
  235. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
  236. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
  237. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
  238. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
  239. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
  240. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
  241. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
  242. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
  243. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
  244. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
  245. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
  246. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
  247. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
  248. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
  249. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
  250. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
  251. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
  252. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
  253. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
  254. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
  255. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
  256. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
  257. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
  258. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
  259. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
  260. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
  261. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
  262. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
  263. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
  264. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
  265. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
  266. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
  267. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
  268. {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
  269. {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
  270. {}
  271. };
  272. MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
  273. static const struct {
  274. const char string[ETH_GSTRING_LEN];
  275. } ethtool_stats_keys[] = {
  276. { "rx_octets" },
  277. { "rx_fragments" },
  278. { "rx_ucast_packets" },
  279. { "rx_mcast_packets" },
  280. { "rx_bcast_packets" },
  281. { "rx_fcs_errors" },
  282. { "rx_align_errors" },
  283. { "rx_xon_pause_rcvd" },
  284. { "rx_xoff_pause_rcvd" },
  285. { "rx_mac_ctrl_rcvd" },
  286. { "rx_xoff_entered" },
  287. { "rx_frame_too_long_errors" },
  288. { "rx_jabbers" },
  289. { "rx_undersize_packets" },
  290. { "rx_in_length_errors" },
  291. { "rx_out_length_errors" },
  292. { "rx_64_or_less_octet_packets" },
  293. { "rx_65_to_127_octet_packets" },
  294. { "rx_128_to_255_octet_packets" },
  295. { "rx_256_to_511_octet_packets" },
  296. { "rx_512_to_1023_octet_packets" },
  297. { "rx_1024_to_1522_octet_packets" },
  298. { "rx_1523_to_2047_octet_packets" },
  299. { "rx_2048_to_4095_octet_packets" },
  300. { "rx_4096_to_8191_octet_packets" },
  301. { "rx_8192_to_9022_octet_packets" },
  302. { "tx_octets" },
  303. { "tx_collisions" },
  304. { "tx_xon_sent" },
  305. { "tx_xoff_sent" },
  306. { "tx_flow_control" },
  307. { "tx_mac_errors" },
  308. { "tx_single_collisions" },
  309. { "tx_mult_collisions" },
  310. { "tx_deferred" },
  311. { "tx_excessive_collisions" },
  312. { "tx_late_collisions" },
  313. { "tx_collide_2times" },
  314. { "tx_collide_3times" },
  315. { "tx_collide_4times" },
  316. { "tx_collide_5times" },
  317. { "tx_collide_6times" },
  318. { "tx_collide_7times" },
  319. { "tx_collide_8times" },
  320. { "tx_collide_9times" },
  321. { "tx_collide_10times" },
  322. { "tx_collide_11times" },
  323. { "tx_collide_12times" },
  324. { "tx_collide_13times" },
  325. { "tx_collide_14times" },
  326. { "tx_collide_15times" },
  327. { "tx_ucast_packets" },
  328. { "tx_mcast_packets" },
  329. { "tx_bcast_packets" },
  330. { "tx_carrier_sense_errors" },
  331. { "tx_discards" },
  332. { "tx_errors" },
  333. { "dma_writeq_full" },
  334. { "dma_write_prioq_full" },
  335. { "rxbds_empty" },
  336. { "rx_discards" },
  337. { "rx_errors" },
  338. { "rx_threshold_hit" },
  339. { "dma_readq_full" },
  340. { "dma_read_prioq_full" },
  341. { "tx_comp_queue_full" },
  342. { "ring_set_send_prod_index" },
  343. { "ring_status_update" },
  344. { "nic_irqs" },
  345. { "nic_avoided_irqs" },
  346. { "nic_tx_threshold_hit" },
  347. { "mbuf_lwm_thresh_hit" },
  348. };
  349. #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
  350. static const struct {
  351. const char string[ETH_GSTRING_LEN];
  352. } ethtool_test_keys[] = {
  353. { "nvram test (online) " },
  354. { "link test (online) " },
  355. { "register test (offline)" },
  356. { "memory test (offline)" },
  357. { "mac loopback test (offline)" },
  358. { "phy loopback test (offline)" },
  359. { "ext loopback test (offline)" },
  360. { "interrupt test (offline)" },
  361. };
  362. #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
  363. static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
  364. {
  365. writel(val, tp->regs + off);
  366. }
  367. static u32 tg3_read32(struct tg3 *tp, u32 off)
  368. {
  369. return readl(tp->regs + off);
  370. }
  371. static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
  372. {
  373. writel(val, tp->aperegs + off);
  374. }
  375. static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
  376. {
  377. return readl(tp->aperegs + off);
  378. }
  379. static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
  380. {
  381. unsigned long flags;
  382. spin_lock_irqsave(&tp->indirect_lock, flags);
  383. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  384. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  385. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  386. }
  387. static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
  388. {
  389. writel(val, tp->regs + off);
  390. readl(tp->regs + off);
  391. }
  392. static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
  393. {
  394. unsigned long flags;
  395. u32 val;
  396. spin_lock_irqsave(&tp->indirect_lock, flags);
  397. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  398. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  399. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  400. return val;
  401. }
  402. static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
  403. {
  404. unsigned long flags;
  405. if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
  406. pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
  407. TG3_64BIT_REG_LOW, val);
  408. return;
  409. }
  410. if (off == TG3_RX_STD_PROD_IDX_REG) {
  411. pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
  412. TG3_64BIT_REG_LOW, val);
  413. return;
  414. }
  415. spin_lock_irqsave(&tp->indirect_lock, flags);
  416. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  417. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  418. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  419. /* In indirect mode when disabling interrupts, we also need
  420. * to clear the interrupt bit in the GRC local ctrl register.
  421. */
  422. if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
  423. (val == 0x1)) {
  424. pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
  425. tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
  426. }
  427. }
  428. static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
  429. {
  430. unsigned long flags;
  431. u32 val;
  432. spin_lock_irqsave(&tp->indirect_lock, flags);
  433. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  434. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  435. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  436. return val;
  437. }
  438. /* usec_wait specifies the wait time in usec when writing to certain registers
  439. * where it is unsafe to read back the register without some delay.
  440. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
  441. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
  442. */
  443. static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
  444. {
  445. if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
  446. /* Non-posted methods */
  447. tp->write32(tp, off, val);
  448. else {
  449. /* Posted method */
  450. tg3_write32(tp, off, val);
  451. if (usec_wait)
  452. udelay(usec_wait);
  453. tp->read32(tp, off);
  454. }
  455. /* Wait again after the read for the posted method to guarantee that
  456. * the wait time is met.
  457. */
  458. if (usec_wait)
  459. udelay(usec_wait);
  460. }
  461. static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  462. {
  463. tp->write32_mbox(tp, off, val);
  464. if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
  465. tp->read32_mbox(tp, off);
  466. }
  467. static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
  468. {
  469. void __iomem *mbox = tp->regs + off;
  470. writel(val, mbox);
  471. if (tg3_flag(tp, TXD_MBOX_HWBUG))
  472. writel(val, mbox);
  473. if (tg3_flag(tp, MBOX_WRITE_REORDER))
  474. readl(mbox);
  475. }
  476. static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
  477. {
  478. return readl(tp->regs + off + GRCMBOX_BASE);
  479. }
  480. static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
  481. {
  482. writel(val, tp->regs + off + GRCMBOX_BASE);
  483. }
  484. #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
  485. #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
  486. #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
  487. #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
  488. #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
  489. #define tw32(reg, val) tp->write32(tp, reg, val)
  490. #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
  491. #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
  492. #define tr32(reg) tp->read32(tp, reg)
  493. static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
  494. {
  495. unsigned long flags;
  496. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
  497. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
  498. return;
  499. spin_lock_irqsave(&tp->indirect_lock, flags);
  500. if (tg3_flag(tp, SRAM_USE_CONFIG)) {
  501. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  502. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  503. /* Always leave this as zero. */
  504. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  505. } else {
  506. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  507. tw32_f(TG3PCI_MEM_WIN_DATA, val);
  508. /* Always leave this as zero. */
  509. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  510. }
  511. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  512. }
  513. static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
  514. {
  515. unsigned long flags;
  516. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
  517. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
  518. *val = 0;
  519. return;
  520. }
  521. spin_lock_irqsave(&tp->indirect_lock, flags);
  522. if (tg3_flag(tp, SRAM_USE_CONFIG)) {
  523. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  524. pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  525. /* Always leave this as zero. */
  526. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  527. } else {
  528. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  529. *val = tr32(TG3PCI_MEM_WIN_DATA);
  530. /* Always leave this as zero. */
  531. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  532. }
  533. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  534. }
  535. static void tg3_ape_lock_init(struct tg3 *tp)
  536. {
  537. int i;
  538. u32 regbase, bit;
  539. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  540. regbase = TG3_APE_LOCK_GRANT;
  541. else
  542. regbase = TG3_APE_PER_LOCK_GRANT;
  543. /* Make sure the driver hasn't any stale locks. */
  544. for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
  545. switch (i) {
  546. case TG3_APE_LOCK_PHY0:
  547. case TG3_APE_LOCK_PHY1:
  548. case TG3_APE_LOCK_PHY2:
  549. case TG3_APE_LOCK_PHY3:
  550. bit = APE_LOCK_GRANT_DRIVER;
  551. break;
  552. default:
  553. if (!tp->pci_fn)
  554. bit = APE_LOCK_GRANT_DRIVER;
  555. else
  556. bit = 1 << tp->pci_fn;
  557. }
  558. tg3_ape_write32(tp, regbase + 4 * i, bit);
  559. }
  560. }
  561. static int tg3_ape_lock(struct tg3 *tp, int locknum)
  562. {
  563. int i, off;
  564. int ret = 0;
  565. u32 status, req, gnt, bit;
  566. if (!tg3_flag(tp, ENABLE_APE))
  567. return 0;
  568. switch (locknum) {
  569. case TG3_APE_LOCK_GPIO:
  570. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  571. return 0;
  572. case TG3_APE_LOCK_GRC:
  573. case TG3_APE_LOCK_MEM:
  574. if (!tp->pci_fn)
  575. bit = APE_LOCK_REQ_DRIVER;
  576. else
  577. bit = 1 << tp->pci_fn;
  578. break;
  579. default:
  580. return -EINVAL;
  581. }
  582. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
  583. req = TG3_APE_LOCK_REQ;
  584. gnt = TG3_APE_LOCK_GRANT;
  585. } else {
  586. req = TG3_APE_PER_LOCK_REQ;
  587. gnt = TG3_APE_PER_LOCK_GRANT;
  588. }
  589. off = 4 * locknum;
  590. tg3_ape_write32(tp, req + off, bit);
  591. /* Wait for up to 1 millisecond to acquire lock. */
  592. for (i = 0; i < 100; i++) {
  593. status = tg3_ape_read32(tp, gnt + off);
  594. if (status == bit)
  595. break;
  596. udelay(10);
  597. }
  598. if (status != bit) {
  599. /* Revoke the lock request. */
  600. tg3_ape_write32(tp, gnt + off, bit);
  601. ret = -EBUSY;
  602. }
  603. return ret;
  604. }
  605. static void tg3_ape_unlock(struct tg3 *tp, int locknum)
  606. {
  607. u32 gnt, bit;
  608. if (!tg3_flag(tp, ENABLE_APE))
  609. return;
  610. switch (locknum) {
  611. case TG3_APE_LOCK_GPIO:
  612. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  613. return;
  614. case TG3_APE_LOCK_GRC:
  615. case TG3_APE_LOCK_MEM:
  616. if (!tp->pci_fn)
  617. bit = APE_LOCK_GRANT_DRIVER;
  618. else
  619. bit = 1 << tp->pci_fn;
  620. break;
  621. default:
  622. return;
  623. }
  624. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  625. gnt = TG3_APE_LOCK_GRANT;
  626. else
  627. gnt = TG3_APE_PER_LOCK_GRANT;
  628. tg3_ape_write32(tp, gnt + 4 * locknum, bit);
  629. }
  630. static void tg3_ape_send_event(struct tg3 *tp, u32 event)
  631. {
  632. int i;
  633. u32 apedata;
  634. /* NCSI does not support APE events */
  635. if (tg3_flag(tp, APE_HAS_NCSI))
  636. return;
  637. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  638. if (apedata != APE_SEG_SIG_MAGIC)
  639. return;
  640. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  641. if (!(apedata & APE_FW_STATUS_READY))
  642. return;
  643. /* Wait for up to 1 millisecond for APE to service previous event. */
  644. for (i = 0; i < 10; i++) {
  645. if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
  646. return;
  647. apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
  648. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  649. tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
  650. event | APE_EVENT_STATUS_EVENT_PENDING);
  651. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  652. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  653. break;
  654. udelay(100);
  655. }
  656. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  657. tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
  658. }
  659. static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
  660. {
  661. u32 event;
  662. u32 apedata;
  663. if (!tg3_flag(tp, ENABLE_APE))
  664. return;
  665. switch (kind) {
  666. case RESET_KIND_INIT:
  667. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
  668. APE_HOST_SEG_SIG_MAGIC);
  669. tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
  670. APE_HOST_SEG_LEN_MAGIC);
  671. apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
  672. tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
  673. tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
  674. APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
  675. tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
  676. APE_HOST_BEHAV_NO_PHYLOCK);
  677. tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
  678. TG3_APE_HOST_DRVR_STATE_START);
  679. event = APE_EVENT_STATUS_STATE_START;
  680. break;
  681. case RESET_KIND_SHUTDOWN:
  682. /* With the interface we are currently using,
  683. * APE does not track driver state. Wiping
  684. * out the HOST SEGMENT SIGNATURE forces
  685. * the APE to assume OS absent status.
  686. */
  687. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
  688. if (device_may_wakeup(&tp->pdev->dev) &&
  689. tg3_flag(tp, WOL_ENABLE)) {
  690. tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
  691. TG3_APE_HOST_WOL_SPEED_AUTO);
  692. apedata = TG3_APE_HOST_DRVR_STATE_WOL;
  693. } else
  694. apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
  695. tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
  696. event = APE_EVENT_STATUS_STATE_UNLOAD;
  697. break;
  698. case RESET_KIND_SUSPEND:
  699. event = APE_EVENT_STATUS_STATE_SUSPEND;
  700. break;
  701. default:
  702. return;
  703. }
  704. event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
  705. tg3_ape_send_event(tp, event);
  706. }
  707. static void tg3_disable_ints(struct tg3 *tp)
  708. {
  709. int i;
  710. tw32(TG3PCI_MISC_HOST_CTRL,
  711. (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
  712. for (i = 0; i < tp->irq_max; i++)
  713. tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
  714. }
  715. static void tg3_enable_ints(struct tg3 *tp)
  716. {
  717. int i;
  718. tp->irq_sync = 0;
  719. wmb();
  720. tw32(TG3PCI_MISC_HOST_CTRL,
  721. (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
  722. tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
  723. for (i = 0; i < tp->irq_cnt; i++) {
  724. struct tg3_napi *tnapi = &tp->napi[i];
  725. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  726. if (tg3_flag(tp, 1SHOT_MSI))
  727. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  728. tp->coal_now |= tnapi->coal_now;
  729. }
  730. /* Force an initial interrupt */
  731. if (!tg3_flag(tp, TAGGED_STATUS) &&
  732. (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
  733. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  734. else
  735. tw32(HOSTCC_MODE, tp->coal_now);
  736. tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
  737. }
  738. static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
  739. {
  740. struct tg3 *tp = tnapi->tp;
  741. struct tg3_hw_status *sblk = tnapi->hw_status;
  742. unsigned int work_exists = 0;
  743. /* check for phy events */
  744. if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
  745. if (sblk->status & SD_STATUS_LINK_CHG)
  746. work_exists = 1;
  747. }
  748. /* check for RX/TX work to do */
  749. if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
  750. *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
  751. work_exists = 1;
  752. return work_exists;
  753. }
  754. /* tg3_int_reenable
  755. * similar to tg3_enable_ints, but it accurately determines whether there
  756. * is new work pending and can return without flushing the PIO write
  757. * which reenables interrupts
  758. */
  759. static void tg3_int_reenable(struct tg3_napi *tnapi)
  760. {
  761. struct tg3 *tp = tnapi->tp;
  762. tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
  763. mmiowb();
  764. /* When doing tagged status, this work check is unnecessary.
  765. * The last_tag we write above tells the chip which piece of
  766. * work we've completed.
  767. */
  768. if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
  769. tw32(HOSTCC_MODE, tp->coalesce_mode |
  770. HOSTCC_MODE_ENABLE | tnapi->coal_now);
  771. }
  772. static void tg3_switch_clocks(struct tg3 *tp)
  773. {
  774. u32 clock_ctrl;
  775. u32 orig_clock_ctrl;
  776. if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
  777. return;
  778. clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
  779. orig_clock_ctrl = clock_ctrl;
  780. clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
  781. CLOCK_CTRL_CLKRUN_OENABLE |
  782. 0x1f);
  783. tp->pci_clock_ctrl = clock_ctrl;
  784. if (tg3_flag(tp, 5705_PLUS)) {
  785. if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
  786. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  787. clock_ctrl | CLOCK_CTRL_625_CORE, 40);
  788. }
  789. } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
  790. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  791. clock_ctrl |
  792. (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
  793. 40);
  794. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  795. clock_ctrl | (CLOCK_CTRL_ALTCLK),
  796. 40);
  797. }
  798. tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
  799. }
  800. #define PHY_BUSY_LOOPS 5000
  801. static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  802. {
  803. u32 frame_val;
  804. unsigned int loops;
  805. int ret;
  806. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  807. tw32_f(MAC_MI_MODE,
  808. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  809. udelay(80);
  810. }
  811. *val = 0x0;
  812. frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  813. MI_COM_PHY_ADDR_MASK);
  814. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  815. MI_COM_REG_ADDR_MASK);
  816. frame_val |= (MI_COM_CMD_READ | MI_COM_START);
  817. tw32_f(MAC_MI_COM, frame_val);
  818. loops = PHY_BUSY_LOOPS;
  819. while (loops != 0) {
  820. udelay(10);
  821. frame_val = tr32(MAC_MI_COM);
  822. if ((frame_val & MI_COM_BUSY) == 0) {
  823. udelay(5);
  824. frame_val = tr32(MAC_MI_COM);
  825. break;
  826. }
  827. loops -= 1;
  828. }
  829. ret = -EBUSY;
  830. if (loops != 0) {
  831. *val = frame_val & MI_COM_DATA_MASK;
  832. ret = 0;
  833. }
  834. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  835. tw32_f(MAC_MI_MODE, tp->mi_mode);
  836. udelay(80);
  837. }
  838. return ret;
  839. }
  840. static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  841. {
  842. u32 frame_val;
  843. unsigned int loops;
  844. int ret;
  845. if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  846. (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
  847. return 0;
  848. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  849. tw32_f(MAC_MI_MODE,
  850. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  851. udelay(80);
  852. }
  853. frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  854. MI_COM_PHY_ADDR_MASK);
  855. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  856. MI_COM_REG_ADDR_MASK);
  857. frame_val |= (val & MI_COM_DATA_MASK);
  858. frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
  859. tw32_f(MAC_MI_COM, frame_val);
  860. loops = PHY_BUSY_LOOPS;
  861. while (loops != 0) {
  862. udelay(10);
  863. frame_val = tr32(MAC_MI_COM);
  864. if ((frame_val & MI_COM_BUSY) == 0) {
  865. udelay(5);
  866. frame_val = tr32(MAC_MI_COM);
  867. break;
  868. }
  869. loops -= 1;
  870. }
  871. ret = -EBUSY;
  872. if (loops != 0)
  873. ret = 0;
  874. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  875. tw32_f(MAC_MI_MODE, tp->mi_mode);
  876. udelay(80);
  877. }
  878. return ret;
  879. }
  880. static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
  881. {
  882. int err;
  883. err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
  884. if (err)
  885. goto done;
  886. err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
  887. if (err)
  888. goto done;
  889. err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
  890. MII_TG3_MMD_CTRL_DATA_NOINC | devad);
  891. if (err)
  892. goto done;
  893. err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
  894. done:
  895. return err;
  896. }
  897. static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
  898. {
  899. int err;
  900. err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
  901. if (err)
  902. goto done;
  903. err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
  904. if (err)
  905. goto done;
  906. err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
  907. MII_TG3_MMD_CTRL_DATA_NOINC | devad);
  908. if (err)
  909. goto done;
  910. err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
  911. done:
  912. return err;
  913. }
  914. static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
  915. {
  916. int err;
  917. err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
  918. if (!err)
  919. err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
  920. return err;
  921. }
  922. static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
  923. {
  924. int err;
  925. err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
  926. if (!err)
  927. err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
  928. return err;
  929. }
  930. static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
  931. {
  932. int err;
  933. err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
  934. (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
  935. MII_TG3_AUXCTL_SHDWSEL_MISC);
  936. if (!err)
  937. err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
  938. return err;
  939. }
  940. static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
  941. {
  942. if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
  943. set |= MII_TG3_AUXCTL_MISC_WREN;
  944. return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
  945. }
  946. #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
  947. tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
  948. MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
  949. MII_TG3_AUXCTL_ACTL_TX_6DB)
  950. #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
  951. tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
  952. MII_TG3_AUXCTL_ACTL_TX_6DB);
  953. static int tg3_bmcr_reset(struct tg3 *tp)
  954. {
  955. u32 phy_control;
  956. int limit, err;
  957. /* OK, reset it, and poll the BMCR_RESET bit until it
  958. * clears or we time out.
  959. */
  960. phy_control = BMCR_RESET;
  961. err = tg3_writephy(tp, MII_BMCR, phy_control);
  962. if (err != 0)
  963. return -EBUSY;
  964. limit = 5000;
  965. while (limit--) {
  966. err = tg3_readphy(tp, MII_BMCR, &phy_control);
  967. if (err != 0)
  968. return -EBUSY;
  969. if ((phy_control & BMCR_RESET) == 0) {
  970. udelay(40);
  971. break;
  972. }
  973. udelay(10);
  974. }
  975. if (limit < 0)
  976. return -EBUSY;
  977. return 0;
  978. }
  979. static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
  980. {
  981. struct tg3 *tp = bp->priv;
  982. u32 val;
  983. spin_lock_bh(&tp->lock);
  984. if (tg3_readphy(tp, reg, &val))
  985. val = -EIO;
  986. spin_unlock_bh(&tp->lock);
  987. return val;
  988. }
  989. static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
  990. {
  991. struct tg3 *tp = bp->priv;
  992. u32 ret = 0;
  993. spin_lock_bh(&tp->lock);
  994. if (tg3_writephy(tp, reg, val))
  995. ret = -EIO;
  996. spin_unlock_bh(&tp->lock);
  997. return ret;
  998. }
  999. static int tg3_mdio_reset(struct mii_bus *bp)
  1000. {
  1001. return 0;
  1002. }
  1003. static void tg3_mdio_config_5785(struct tg3 *tp)
  1004. {
  1005. u32 val;
  1006. struct phy_device *phydev;
  1007. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1008. switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
  1009. case PHY_ID_BCM50610:
  1010. case PHY_ID_BCM50610M:
  1011. val = MAC_PHYCFG2_50610_LED_MODES;
  1012. break;
  1013. case PHY_ID_BCMAC131:
  1014. val = MAC_PHYCFG2_AC131_LED_MODES;
  1015. break;
  1016. case PHY_ID_RTL8211C:
  1017. val = MAC_PHYCFG2_RTL8211C_LED_MODES;
  1018. break;
  1019. case PHY_ID_RTL8201E:
  1020. val = MAC_PHYCFG2_RTL8201E_LED_MODES;
  1021. break;
  1022. default:
  1023. return;
  1024. }
  1025. if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
  1026. tw32(MAC_PHYCFG2, val);
  1027. val = tr32(MAC_PHYCFG1);
  1028. val &= ~(MAC_PHYCFG1_RGMII_INT |
  1029. MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
  1030. val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
  1031. tw32(MAC_PHYCFG1, val);
  1032. return;
  1033. }
  1034. if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
  1035. val |= MAC_PHYCFG2_EMODE_MASK_MASK |
  1036. MAC_PHYCFG2_FMODE_MASK_MASK |
  1037. MAC_PHYCFG2_GMODE_MASK_MASK |
  1038. MAC_PHYCFG2_ACT_MASK_MASK |
  1039. MAC_PHYCFG2_QUAL_MASK_MASK |
  1040. MAC_PHYCFG2_INBAND_ENABLE;
  1041. tw32(MAC_PHYCFG2, val);
  1042. val = tr32(MAC_PHYCFG1);
  1043. val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
  1044. MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
  1045. if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
  1046. if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
  1047. val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
  1048. if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
  1049. val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
  1050. }
  1051. val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
  1052. MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
  1053. tw32(MAC_PHYCFG1, val);
  1054. val = tr32(MAC_EXT_RGMII_MODE);
  1055. val &= ~(MAC_RGMII_MODE_RX_INT_B |
  1056. MAC_RGMII_MODE_RX_QUALITY |
  1057. MAC_RGMII_MODE_RX_ACTIVITY |
  1058. MAC_RGMII_MODE_RX_ENG_DET |
  1059. MAC_RGMII_MODE_TX_ENABLE |
  1060. MAC_RGMII_MODE_TX_LOWPWR |
  1061. MAC_RGMII_MODE_TX_RESET);
  1062. if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
  1063. if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
  1064. val |= MAC_RGMII_MODE_RX_INT_B |
  1065. MAC_RGMII_MODE_RX_QUALITY |
  1066. MAC_RGMII_MODE_RX_ACTIVITY |
  1067. MAC_RGMII_MODE_RX_ENG_DET;
  1068. if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
  1069. val |= MAC_RGMII_MODE_TX_ENABLE |
  1070. MAC_RGMII_MODE_TX_LOWPWR |
  1071. MAC_RGMII_MODE_TX_RESET;
  1072. }
  1073. tw32(MAC_EXT_RGMII_MODE, val);
  1074. }
  1075. static void tg3_mdio_start(struct tg3 *tp)
  1076. {
  1077. tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
  1078. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1079. udelay(80);
  1080. if (tg3_flag(tp, MDIOBUS_INITED) &&
  1081. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  1082. tg3_mdio_config_5785(tp);
  1083. }
  1084. static int tg3_mdio_init(struct tg3 *tp)
  1085. {
  1086. int i;
  1087. u32 reg;
  1088. struct phy_device *phydev;
  1089. if (tg3_flag(tp, 5717_PLUS)) {
  1090. u32 is_serdes;
  1091. tp->phy_addr = tp->pci_fn + 1;
  1092. if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
  1093. is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
  1094. else
  1095. is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
  1096. TG3_CPMU_PHY_STRAP_IS_SERDES;
  1097. if (is_serdes)
  1098. tp->phy_addr += 7;
  1099. } else
  1100. tp->phy_addr = TG3_PHY_MII_ADDR;
  1101. tg3_mdio_start(tp);
  1102. if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
  1103. return 0;
  1104. tp->mdio_bus = mdiobus_alloc();
  1105. if (tp->mdio_bus == NULL)
  1106. return -ENOMEM;
  1107. tp->mdio_bus->name = "tg3 mdio bus";
  1108. snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
  1109. (tp->pdev->bus->number << 8) | tp->pdev->devfn);
  1110. tp->mdio_bus->priv = tp;
  1111. tp->mdio_bus->parent = &tp->pdev->dev;
  1112. tp->mdio_bus->read = &tg3_mdio_read;
  1113. tp->mdio_bus->write = &tg3_mdio_write;
  1114. tp->mdio_bus->reset = &tg3_mdio_reset;
  1115. tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
  1116. tp->mdio_bus->irq = &tp->mdio_irq[0];
  1117. for (i = 0; i < PHY_MAX_ADDR; i++)
  1118. tp->mdio_bus->irq[i] = PHY_POLL;
  1119. /* The bus registration will look for all the PHYs on the mdio bus.
  1120. * Unfortunately, it does not ensure the PHY is powered up before
  1121. * accessing the PHY ID registers. A chip reset is the
  1122. * quickest way to bring the device back to an operational state..
  1123. */
  1124. if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
  1125. tg3_bmcr_reset(tp);
  1126. i = mdiobus_register(tp->mdio_bus);
  1127. if (i) {
  1128. dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
  1129. mdiobus_free(tp->mdio_bus);
  1130. return i;
  1131. }
  1132. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1133. if (!phydev || !phydev->drv) {
  1134. dev_warn(&tp->pdev->dev, "No PHY devices\n");
  1135. mdiobus_unregister(tp->mdio_bus);
  1136. mdiobus_free(tp->mdio_bus);
  1137. return -ENODEV;
  1138. }
  1139. switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
  1140. case PHY_ID_BCM57780:
  1141. phydev->interface = PHY_INTERFACE_MODE_GMII;
  1142. phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
  1143. break;
  1144. case PHY_ID_BCM50610:
  1145. case PHY_ID_BCM50610M:
  1146. phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
  1147. PHY_BRCM_RX_REFCLK_UNUSED |
  1148. PHY_BRCM_DIS_TXCRXC_NOENRGY |
  1149. PHY_BRCM_AUTO_PWRDWN_ENABLE;
  1150. if (tg3_flag(tp, RGMII_INBAND_DISABLE))
  1151. phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
  1152. if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
  1153. phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
  1154. if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
  1155. phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
  1156. /* fallthru */
  1157. case PHY_ID_RTL8211C:
  1158. phydev->interface = PHY_INTERFACE_MODE_RGMII;
  1159. break;
  1160. case PHY_ID_RTL8201E:
  1161. case PHY_ID_BCMAC131:
  1162. phydev->interface = PHY_INTERFACE_MODE_MII;
  1163. phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
  1164. tp->phy_flags |= TG3_PHYFLG_IS_FET;
  1165. break;
  1166. }
  1167. tg3_flag_set(tp, MDIOBUS_INITED);
  1168. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  1169. tg3_mdio_config_5785(tp);
  1170. return 0;
  1171. }
  1172. static void tg3_mdio_fini(struct tg3 *tp)
  1173. {
  1174. if (tg3_flag(tp, MDIOBUS_INITED)) {
  1175. tg3_flag_clear(tp, MDIOBUS_INITED);
  1176. mdiobus_unregister(tp->mdio_bus);
  1177. mdiobus_free(tp->mdio_bus);
  1178. }
  1179. }
  1180. /* tp->lock is held. */
  1181. static inline void tg3_generate_fw_event(struct tg3 *tp)
  1182. {
  1183. u32 val;
  1184. val = tr32(GRC_RX_CPU_EVENT);
  1185. val |= GRC_RX_CPU_DRIVER_EVENT;
  1186. tw32_f(GRC_RX_CPU_EVENT, val);
  1187. tp->last_event_jiffies = jiffies;
  1188. }
  1189. #define TG3_FW_EVENT_TIMEOUT_USEC 2500
  1190. /* tp->lock is held. */
  1191. static void tg3_wait_for_event_ack(struct tg3 *tp)
  1192. {
  1193. int i;
  1194. unsigned int delay_cnt;
  1195. long time_remain;
  1196. /* If enough time has passed, no wait is necessary. */
  1197. time_remain = (long)(tp->last_event_jiffies + 1 +
  1198. usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
  1199. (long)jiffies;
  1200. if (time_remain < 0)
  1201. return;
  1202. /* Check if we can shorten the wait time. */
  1203. delay_cnt = jiffies_to_usecs(time_remain);
  1204. if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
  1205. delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
  1206. delay_cnt = (delay_cnt >> 3) + 1;
  1207. for (i = 0; i < delay_cnt; i++) {
  1208. if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
  1209. break;
  1210. udelay(8);
  1211. }
  1212. }
  1213. /* tp->lock is held. */
  1214. static void tg3_ump_link_report(struct tg3 *tp)
  1215. {
  1216. u32 reg;
  1217. u32 val;
  1218. if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
  1219. return;
  1220. tg3_wait_for_event_ack(tp);
  1221. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
  1222. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
  1223. val = 0;
  1224. if (!tg3_readphy(tp, MII_BMCR, &reg))
  1225. val = reg << 16;
  1226. if (!tg3_readphy(tp, MII_BMSR, &reg))
  1227. val |= (reg & 0xffff);
  1228. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
  1229. val = 0;
  1230. if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
  1231. val = reg << 16;
  1232. if (!tg3_readphy(tp, MII_LPA, &reg))
  1233. val |= (reg & 0xffff);
  1234. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
  1235. val = 0;
  1236. if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
  1237. if (!tg3_readphy(tp, MII_CTRL1000, &reg))
  1238. val = reg << 16;
  1239. if (!tg3_readphy(tp, MII_STAT1000, &reg))
  1240. val |= (reg & 0xffff);
  1241. }
  1242. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
  1243. if (!tg3_readphy(tp, MII_PHYADDR, &reg))
  1244. val = reg << 16;
  1245. else
  1246. val = 0;
  1247. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
  1248. tg3_generate_fw_event(tp);
  1249. }
  1250. /* tp->lock is held. */
  1251. static void tg3_stop_fw(struct tg3 *tp)
  1252. {
  1253. if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
  1254. /* Wait for RX cpu to ACK the previous event. */
  1255. tg3_wait_for_event_ack(tp);
  1256. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
  1257. tg3_generate_fw_event(tp);
  1258. /* Wait for RX cpu to ACK this event. */
  1259. tg3_wait_for_event_ack(tp);
  1260. }
  1261. }
  1262. /* tp->lock is held. */
  1263. static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
  1264. {
  1265. tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
  1266. NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  1267. if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
  1268. switch (kind) {
  1269. case RESET_KIND_INIT:
  1270. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1271. DRV_STATE_START);
  1272. break;
  1273. case RESET_KIND_SHUTDOWN:
  1274. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1275. DRV_STATE_UNLOAD);
  1276. break;
  1277. case RESET_KIND_SUSPEND:
  1278. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1279. DRV_STATE_SUSPEND);
  1280. break;
  1281. default:
  1282. break;
  1283. }
  1284. }
  1285. if (kind == RESET_KIND_INIT ||
  1286. kind == RESET_KIND_SUSPEND)
  1287. tg3_ape_driver_state_change(tp, kind);
  1288. }
  1289. /* tp->lock is held. */
  1290. static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
  1291. {
  1292. if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
  1293. switch (kind) {
  1294. case RESET_KIND_INIT:
  1295. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1296. DRV_STATE_START_DONE);
  1297. break;
  1298. case RESET_KIND_SHUTDOWN:
  1299. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1300. DRV_STATE_UNLOAD_DONE);
  1301. break;
  1302. default:
  1303. break;
  1304. }
  1305. }
  1306. if (kind == RESET_KIND_SHUTDOWN)
  1307. tg3_ape_driver_state_change(tp, kind);
  1308. }
  1309. /* tp->lock is held. */
  1310. static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
  1311. {
  1312. if (tg3_flag(tp, ENABLE_ASF)) {
  1313. switch (kind) {
  1314. case RESET_KIND_INIT:
  1315. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1316. DRV_STATE_START);
  1317. break;
  1318. case RESET_KIND_SHUTDOWN:
  1319. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1320. DRV_STATE_UNLOAD);
  1321. break;
  1322. case RESET_KIND_SUSPEND:
  1323. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1324. DRV_STATE_SUSPEND);
  1325. break;
  1326. default:
  1327. break;
  1328. }
  1329. }
  1330. }
  1331. static int tg3_poll_fw(struct tg3 *tp)
  1332. {
  1333. int i;
  1334. u32 val;
  1335. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1336. /* Wait up to 20ms for init done. */
  1337. for (i = 0; i < 200; i++) {
  1338. if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
  1339. return 0;
  1340. udelay(100);
  1341. }
  1342. return -ENODEV;
  1343. }
  1344. /* Wait for firmware initialization to complete. */
  1345. for (i = 0; i < 100000; i++) {
  1346. tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  1347. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  1348. break;
  1349. udelay(10);
  1350. }
  1351. /* Chip might not be fitted with firmware. Some Sun onboard
  1352. * parts are configured like that. So don't signal the timeout
  1353. * of the above loop as an error, but do report the lack of
  1354. * running firmware once.
  1355. */
  1356. if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
  1357. tg3_flag_set(tp, NO_FWARE_REPORTED);
  1358. netdev_info(tp->dev, "No firmware running\n");
  1359. }
  1360. if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
  1361. /* The 57765 A0 needs a little more
  1362. * time to do some important work.
  1363. */
  1364. mdelay(10);
  1365. }
  1366. return 0;
  1367. }
  1368. static void tg3_link_report(struct tg3 *tp)
  1369. {
  1370. if (!netif_carrier_ok(tp->dev)) {
  1371. netif_info(tp, link, tp->dev, "Link is down\n");
  1372. tg3_ump_link_report(tp);
  1373. } else if (netif_msg_link(tp)) {
  1374. netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
  1375. (tp->link_config.active_speed == SPEED_1000 ?
  1376. 1000 :
  1377. (tp->link_config.active_speed == SPEED_100 ?
  1378. 100 : 10)),
  1379. (tp->link_config.active_duplex == DUPLEX_FULL ?
  1380. "full" : "half"));
  1381. netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
  1382. (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
  1383. "on" : "off",
  1384. (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
  1385. "on" : "off");
  1386. if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
  1387. netdev_info(tp->dev, "EEE is %s\n",
  1388. tp->setlpicnt ? "enabled" : "disabled");
  1389. tg3_ump_link_report(tp);
  1390. }
  1391. }
  1392. static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
  1393. {
  1394. u16 miireg;
  1395. if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
  1396. miireg = ADVERTISE_PAUSE_CAP;
  1397. else if (flow_ctrl & FLOW_CTRL_TX)
  1398. miireg = ADVERTISE_PAUSE_ASYM;
  1399. else if (flow_ctrl & FLOW_CTRL_RX)
  1400. miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1401. else
  1402. miireg = 0;
  1403. return miireg;
  1404. }
  1405. static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
  1406. {
  1407. u16 miireg;
  1408. if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
  1409. miireg = ADVERTISE_1000XPAUSE;
  1410. else if (flow_ctrl & FLOW_CTRL_TX)
  1411. miireg = ADVERTISE_1000XPSE_ASYM;
  1412. else if (flow_ctrl & FLOW_CTRL_RX)
  1413. miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  1414. else
  1415. miireg = 0;
  1416. return miireg;
  1417. }
  1418. static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
  1419. {
  1420. u8 cap = 0;
  1421. if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
  1422. cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
  1423. } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
  1424. if (lcladv & ADVERTISE_1000XPAUSE)
  1425. cap = FLOW_CTRL_RX;
  1426. if (rmtadv & ADVERTISE_1000XPAUSE)
  1427. cap = FLOW_CTRL_TX;
  1428. }
  1429. return cap;
  1430. }
  1431. static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
  1432. {
  1433. u8 autoneg;
  1434. u8 flowctrl = 0;
  1435. u32 old_rx_mode = tp->rx_mode;
  1436. u32 old_tx_mode = tp->tx_mode;
  1437. if (tg3_flag(tp, USE_PHYLIB))
  1438. autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
  1439. else
  1440. autoneg = tp->link_config.autoneg;
  1441. if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
  1442. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  1443. flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
  1444. else
  1445. flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  1446. } else
  1447. flowctrl = tp->link_config.flowctrl;
  1448. tp->link_config.active_flowctrl = flowctrl;
  1449. if (flowctrl & FLOW_CTRL_RX)
  1450. tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
  1451. else
  1452. tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
  1453. if (old_rx_mode != tp->rx_mode)
  1454. tw32_f(MAC_RX_MODE, tp->rx_mode);
  1455. if (flowctrl & FLOW_CTRL_TX)
  1456. tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
  1457. else
  1458. tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
  1459. if (old_tx_mode != tp->tx_mode)
  1460. tw32_f(MAC_TX_MODE, tp->tx_mode);
  1461. }
  1462. static void tg3_adjust_link(struct net_device *dev)
  1463. {
  1464. u8 oldflowctrl, linkmesg = 0;
  1465. u32 mac_mode, lcl_adv, rmt_adv;
  1466. struct tg3 *tp = netdev_priv(dev);
  1467. struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1468. spin_lock_bh(&tp->lock);
  1469. mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
  1470. MAC_MODE_HALF_DUPLEX);
  1471. oldflowctrl = tp->link_config.active_flowctrl;
  1472. if (phydev->link) {
  1473. lcl_adv = 0;
  1474. rmt_adv = 0;
  1475. if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
  1476. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1477. else if (phydev->speed == SPEED_1000 ||
  1478. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
  1479. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1480. else
  1481. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1482. if (phydev->duplex == DUPLEX_HALF)
  1483. mac_mode |= MAC_MODE_HALF_DUPLEX;
  1484. else {
  1485. lcl_adv = tg3_advert_flowctrl_1000T(
  1486. tp->link_config.flowctrl);
  1487. if (phydev->pause)
  1488. rmt_adv = LPA_PAUSE_CAP;
  1489. if (phydev->asym_pause)
  1490. rmt_adv |= LPA_PAUSE_ASYM;
  1491. }
  1492. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  1493. } else
  1494. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1495. if (mac_mode != tp->mac_mode) {
  1496. tp->mac_mode = mac_mode;
  1497. tw32_f(MAC_MODE, tp->mac_mode);
  1498. udelay(40);
  1499. }
  1500. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
  1501. if (phydev->speed == SPEED_10)
  1502. tw32(MAC_MI_STAT,
  1503. MAC_MI_STAT_10MBPS_MODE |
  1504. MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  1505. else
  1506. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  1507. }
  1508. if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
  1509. tw32(MAC_TX_LENGTHS,
  1510. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1511. (6 << TX_LENGTHS_IPG_SHIFT) |
  1512. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1513. else
  1514. tw32(MAC_TX_LENGTHS,
  1515. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1516. (6 << TX_LENGTHS_IPG_SHIFT) |
  1517. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1518. if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
  1519. (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
  1520. phydev->speed != tp->link_config.active_speed ||
  1521. phydev->duplex != tp->link_config.active_duplex ||
  1522. oldflowctrl != tp->link_config.active_flowctrl)
  1523. linkmesg = 1;
  1524. tp->link_config.active_speed = phydev->speed;
  1525. tp->link_config.active_duplex = phydev->duplex;
  1526. spin_unlock_bh(&tp->lock);
  1527. if (linkmesg)
  1528. tg3_link_report(tp);
  1529. }
  1530. static int tg3_phy_init(struct tg3 *tp)
  1531. {
  1532. struct phy_device *phydev;
  1533. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
  1534. return 0;
  1535. /* Bring the PHY back to a known state. */
  1536. tg3_bmcr_reset(tp);
  1537. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1538. /* Attach the MAC to the PHY. */
  1539. phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
  1540. phydev->dev_flags, phydev->interface);
  1541. if (IS_ERR(phydev)) {
  1542. dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
  1543. return PTR_ERR(phydev);
  1544. }
  1545. /* Mask with MAC supported features. */
  1546. switch (phydev->interface) {
  1547. case PHY_INTERFACE_MODE_GMII:
  1548. case PHY_INTERFACE_MODE_RGMII:
  1549. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  1550. phydev->supported &= (PHY_GBIT_FEATURES |
  1551. SUPPORTED_Pause |
  1552. SUPPORTED_Asym_Pause);
  1553. break;
  1554. }
  1555. /* fallthru */
  1556. case PHY_INTERFACE_MODE_MII:
  1557. phydev->supported &= (PHY_BASIC_FEATURES |
  1558. SUPPORTED_Pause |
  1559. SUPPORTED_Asym_Pause);
  1560. break;
  1561. default:
  1562. phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1563. return -EINVAL;
  1564. }
  1565. tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
  1566. phydev->advertising = phydev->supported;
  1567. return 0;
  1568. }
  1569. static void tg3_phy_start(struct tg3 *tp)
  1570. {
  1571. struct phy_device *phydev;
  1572. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  1573. return;
  1574. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1575. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
  1576. tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
  1577. phydev->speed = tp->link_config.orig_speed;
  1578. phydev->duplex = tp->link_config.orig_duplex;
  1579. phydev->autoneg = tp->link_config.orig_autoneg;
  1580. phydev->advertising = tp->link_config.orig_advertising;
  1581. }
  1582. phy_start(phydev);
  1583. phy_start_aneg(phydev);
  1584. }
  1585. static void tg3_phy_stop(struct tg3 *tp)
  1586. {
  1587. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  1588. return;
  1589. phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1590. }
  1591. static void tg3_phy_fini(struct tg3 *tp)
  1592. {
  1593. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  1594. phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1595. tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
  1596. }
  1597. }
  1598. static int tg3_phy_set_extloopbk(struct tg3 *tp)
  1599. {
  1600. int err;
  1601. u32 val;
  1602. if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  1603. return 0;
  1604. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  1605. /* Cannot do read-modify-write on 5401 */
  1606. err = tg3_phy_auxctl_write(tp,
  1607. MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
  1608. MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
  1609. 0x4c20);
  1610. goto done;
  1611. }
  1612. err = tg3_phy_auxctl_read(tp,
  1613. MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
  1614. if (err)
  1615. return err;
  1616. val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
  1617. err = tg3_phy_auxctl_write(tp,
  1618. MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
  1619. done:
  1620. return err;
  1621. }
  1622. static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
  1623. {
  1624. u32 phytest;
  1625. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
  1626. u32 phy;
  1627. tg3_writephy(tp, MII_TG3_FET_TEST,
  1628. phytest | MII_TG3_FET_SHADOW_EN);
  1629. if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
  1630. if (enable)
  1631. phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
  1632. else
  1633. phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
  1634. tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
  1635. }
  1636. tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
  1637. }
  1638. }
  1639. static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
  1640. {
  1641. u32 reg;
  1642. if (!tg3_flag(tp, 5705_PLUS) ||
  1643. (tg3_flag(tp, 5717_PLUS) &&
  1644. (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
  1645. return;
  1646. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  1647. tg3_phy_fet_toggle_apd(tp, enable);
  1648. return;
  1649. }
  1650. reg = MII_TG3_MISC_SHDW_WREN |
  1651. MII_TG3_MISC_SHDW_SCR5_SEL |
  1652. MII_TG3_MISC_SHDW_SCR5_LPED |
  1653. MII_TG3_MISC_SHDW_SCR5_DLPTLM |
  1654. MII_TG3_MISC_SHDW_SCR5_SDTL |
  1655. MII_TG3_MISC_SHDW_SCR5_C125OE;
  1656. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
  1657. reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
  1658. tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
  1659. reg = MII_TG3_MISC_SHDW_WREN |
  1660. MII_TG3_MISC_SHDW_APD_SEL |
  1661. MII_TG3_MISC_SHDW_APD_WKTM_84MS;
  1662. if (enable)
  1663. reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
  1664. tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
  1665. }
  1666. static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
  1667. {
  1668. u32 phy;
  1669. if (!tg3_flag(tp, 5705_PLUS) ||
  1670. (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  1671. return;
  1672. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  1673. u32 ephy;
  1674. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
  1675. u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
  1676. tg3_writephy(tp, MII_TG3_FET_TEST,
  1677. ephy | MII_TG3_FET_SHADOW_EN);
  1678. if (!tg3_readphy(tp, reg, &phy)) {
  1679. if (enable)
  1680. phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
  1681. else
  1682. phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
  1683. tg3_writephy(tp, reg, phy);
  1684. }
  1685. tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
  1686. }
  1687. } else {
  1688. int ret;
  1689. ret = tg3_phy_auxctl_read(tp,
  1690. MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
  1691. if (!ret) {
  1692. if (enable)
  1693. phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1694. else
  1695. phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1696. tg3_phy_auxctl_write(tp,
  1697. MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
  1698. }
  1699. }
  1700. }
  1701. static void tg3_phy_set_wirespeed(struct tg3 *tp)
  1702. {
  1703. int ret;
  1704. u32 val;
  1705. if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
  1706. return;
  1707. ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
  1708. if (!ret)
  1709. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
  1710. val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
  1711. }
  1712. static void tg3_phy_apply_otp(struct tg3 *tp)
  1713. {
  1714. u32 otp, phy;
  1715. if (!tp->phy_otp)
  1716. return;
  1717. otp = tp->phy_otp;
  1718. if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
  1719. return;
  1720. phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
  1721. phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
  1722. tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
  1723. phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
  1724. ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
  1725. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
  1726. phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
  1727. phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
  1728. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
  1729. phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
  1730. tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
  1731. phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
  1732. tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
  1733. phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
  1734. ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
  1735. tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
  1736. TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
  1737. }
  1738. static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
  1739. {
  1740. u32 val;
  1741. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
  1742. return;
  1743. tp->setlpicnt = 0;
  1744. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  1745. current_link_up == 1 &&
  1746. tp->link_config.active_duplex == DUPLEX_FULL &&
  1747. (tp->link_config.active_speed == SPEED_100 ||
  1748. tp->link_config.active_speed == SPEED_1000)) {
  1749. u32 eeectl;
  1750. if (tp->link_config.active_speed == SPEED_1000)
  1751. eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
  1752. else
  1753. eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
  1754. tw32(TG3_CPMU_EEE_CTRL, eeectl);
  1755. tg3_phy_cl45_read(tp, MDIO_MMD_AN,
  1756. TG3_CL45_D7_EEERES_STAT, &val);
  1757. if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
  1758. val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
  1759. tp->setlpicnt = 2;
  1760. }
  1761. if (!tp->setlpicnt) {
  1762. if (current_link_up == 1 &&
  1763. !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
  1764. tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
  1765. TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
  1766. }
  1767. val = tr32(TG3_CPMU_EEE_MODE);
  1768. tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
  1769. }
  1770. }
  1771. static void tg3_phy_eee_enable(struct tg3 *tp)
  1772. {
  1773. u32 val;
  1774. if (tp->link_config.active_speed == SPEED_1000 &&
  1775. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  1776. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  1777. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
  1778. !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
  1779. val = MII_TG3_DSP_TAP26_ALNOKO |
  1780. MII_TG3_DSP_TAP26_RMRXSTO;
  1781. tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
  1782. TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
  1783. }
  1784. val = tr32(TG3_CPMU_EEE_MODE);
  1785. tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
  1786. }
  1787. static int tg3_wait_macro_done(struct tg3 *tp)
  1788. {
  1789. int limit = 100;
  1790. while (limit--) {
  1791. u32 tmp32;
  1792. if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
  1793. if ((tmp32 & 0x1000) == 0)
  1794. break;
  1795. }
  1796. }
  1797. if (limit < 0)
  1798. return -EBUSY;
  1799. return 0;
  1800. }
  1801. static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
  1802. {
  1803. static const u32 test_pat[4][6] = {
  1804. { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
  1805. { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
  1806. { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
  1807. { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
  1808. };
  1809. int chan;
  1810. for (chan = 0; chan < 4; chan++) {
  1811. int i;
  1812. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1813. (chan * 0x2000) | 0x0200);
  1814. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
  1815. for (i = 0; i < 6; i++)
  1816. tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
  1817. test_pat[chan][i]);
  1818. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
  1819. if (tg3_wait_macro_done(tp)) {
  1820. *resetp = 1;
  1821. return -EBUSY;
  1822. }
  1823. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1824. (chan * 0x2000) | 0x0200);
  1825. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
  1826. if (tg3_wait_macro_done(tp)) {
  1827. *resetp = 1;
  1828. return -EBUSY;
  1829. }
  1830. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
  1831. if (tg3_wait_macro_done(tp)) {
  1832. *resetp = 1;
  1833. return -EBUSY;
  1834. }
  1835. for (i = 0; i < 6; i += 2) {
  1836. u32 low, high;
  1837. if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
  1838. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
  1839. tg3_wait_macro_done(tp)) {
  1840. *resetp = 1;
  1841. return -EBUSY;
  1842. }
  1843. low &= 0x7fff;
  1844. high &= 0x000f;
  1845. if (low != test_pat[chan][i] ||
  1846. high != test_pat[chan][i+1]) {
  1847. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
  1848. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
  1849. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
  1850. return -EBUSY;
  1851. }
  1852. }
  1853. }
  1854. return 0;
  1855. }
  1856. static int tg3_phy_reset_chanpat(struct tg3 *tp)
  1857. {
  1858. int chan;
  1859. for (chan = 0; chan < 4; chan++) {
  1860. int i;
  1861. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1862. (chan * 0x2000) | 0x0200);
  1863. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
  1864. for (i = 0; i < 6; i++)
  1865. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
  1866. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
  1867. if (tg3_wait_macro_done(tp))
  1868. return -EBUSY;
  1869. }
  1870. return 0;
  1871. }
  1872. static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
  1873. {
  1874. u32 reg32, phy9_orig;
  1875. int retries, do_phy_reset, err;
  1876. retries = 10;
  1877. do_phy_reset = 1;
  1878. do {
  1879. if (do_phy_reset) {
  1880. err = tg3_bmcr_reset(tp);
  1881. if (err)
  1882. return err;
  1883. do_phy_reset = 0;
  1884. }
  1885. /* Disable transmitter and interrupt. */
  1886. if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
  1887. continue;
  1888. reg32 |= 0x3000;
  1889. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  1890. /* Set full-duplex, 1000 mbps. */
  1891. tg3_writephy(tp, MII_BMCR,
  1892. BMCR_FULLDPLX | BMCR_SPEED1000);
  1893. /* Set to master mode. */
  1894. if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
  1895. continue;
  1896. tg3_writephy(tp, MII_CTRL1000,
  1897. CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
  1898. err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
  1899. if (err)
  1900. return err;
  1901. /* Block the PHY control access. */
  1902. tg3_phydsp_write(tp, 0x8005, 0x0800);
  1903. err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
  1904. if (!err)
  1905. break;
  1906. } while (--retries);
  1907. err = tg3_phy_reset_chanpat(tp);
  1908. if (err)
  1909. return err;
  1910. tg3_phydsp_write(tp, 0x8005, 0x0000);
  1911. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
  1912. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
  1913. TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
  1914. tg3_writephy(tp, MII_CTRL1000, phy9_orig);
  1915. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
  1916. reg32 &= ~0x3000;
  1917. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  1918. } else if (!err)
  1919. err = -EBUSY;
  1920. return err;
  1921. }
  1922. /* This will reset the tigon3 PHY if there is no valid
  1923. * link unless the FORCE argument is non-zero.
  1924. */
  1925. static int tg3_phy_reset(struct tg3 *tp)
  1926. {
  1927. u32 val, cpmuctrl;
  1928. int err;
  1929. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1930. val = tr32(GRC_MISC_CFG);
  1931. tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
  1932. udelay(40);
  1933. }
  1934. err = tg3_readphy(tp, MII_BMSR, &val);
  1935. err |= tg3_readphy(tp, MII_BMSR, &val);
  1936. if (err != 0)
  1937. return -EBUSY;
  1938. if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
  1939. netif_carrier_off(tp->dev);
  1940. tg3_link_report(tp);
  1941. }
  1942. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  1943. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1944. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  1945. err = tg3_phy_reset_5703_4_5(tp);
  1946. if (err)
  1947. return err;
  1948. goto out;
  1949. }
  1950. cpmuctrl = 0;
  1951. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  1952. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
  1953. cpmuctrl = tr32(TG3_CPMU_CTRL);
  1954. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
  1955. tw32(TG3_CPMU_CTRL,
  1956. cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
  1957. }
  1958. err = tg3_bmcr_reset(tp);
  1959. if (err)
  1960. return err;
  1961. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
  1962. val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
  1963. tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
  1964. tw32(TG3_CPMU_CTRL, cpmuctrl);
  1965. }
  1966. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
  1967. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
  1968. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  1969. if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
  1970. CPMU_LSPD_1000MB_MACCLK_12_5) {
  1971. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  1972. udelay(40);
  1973. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  1974. }
  1975. }
  1976. if (tg3_flag(tp, 5717_PLUS) &&
  1977. (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
  1978. return 0;
  1979. tg3_phy_apply_otp(tp);
  1980. if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
  1981. tg3_phy_toggle_apd(tp, true);
  1982. else
  1983. tg3_phy_toggle_apd(tp, false);
  1984. out:
  1985. if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
  1986. !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
  1987. tg3_phydsp_write(tp, 0x201f, 0x2aaa);
  1988. tg3_phydsp_write(tp, 0x000a, 0x0323);
  1989. TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
  1990. }
  1991. if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
  1992. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  1993. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  1994. }
  1995. if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
  1996. if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
  1997. tg3_phydsp_write(tp, 0x000a, 0x310b);
  1998. tg3_phydsp_write(tp, 0x201f, 0x9506);
  1999. tg3_phydsp_write(tp, 0x401f, 0x14e2);
  2000. TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
  2001. }
  2002. } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
  2003. if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
  2004. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  2005. if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
  2006. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
  2007. tg3_writephy(tp, MII_TG3_TEST1,
  2008. MII_TG3_TEST1_TRIM_EN | 0x4);
  2009. } else
  2010. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
  2011. TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
  2012. }
  2013. }
  2014. /* Set Extended packet length bit (bit 14) on all chips that */
  2015. /* support jumbo frames */
  2016. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  2017. /* Cannot do read-modify-write on 5401 */
  2018. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
  2019. } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
  2020. /* Set bit 14 with read-modify-write to preserve other bits */
  2021. err = tg3_phy_auxctl_read(tp,
  2022. MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
  2023. if (!err)
  2024. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
  2025. val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
  2026. }
  2027. /* Set phy register 0x10 bit 0 to high fifo elasticity to support
  2028. * jumbo frames transmission.
  2029. */
  2030. if (tg3_flag(tp, JUMBO_CAPABLE)) {
  2031. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
  2032. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  2033. val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
  2034. }
  2035. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  2036. /* adjust output voltage */
  2037. tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
  2038. }
  2039. tg3_phy_toggle_automdix(tp, 1);
  2040. tg3_phy_set_wirespeed(tp);
  2041. return 0;
  2042. }
  2043. #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
  2044. #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
  2045. #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
  2046. TG3_GPIO_MSG_NEED_VAUX)
  2047. #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
  2048. ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
  2049. (TG3_GPIO_MSG_DRVR_PRES << 4) | \
  2050. (TG3_GPIO_MSG_DRVR_PRES << 8) | \
  2051. (TG3_GPIO_MSG_DRVR_PRES << 12))
  2052. #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
  2053. ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
  2054. (TG3_GPIO_MSG_NEED_VAUX << 4) | \
  2055. (TG3_GPIO_MSG_NEED_VAUX << 8) | \
  2056. (TG3_GPIO_MSG_NEED_VAUX << 12))
  2057. static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
  2058. {
  2059. u32 status, shift;
  2060. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  2061. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
  2062. status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
  2063. else
  2064. status = tr32(TG3_CPMU_DRV_STATUS);
  2065. shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
  2066. status &= ~(TG3_GPIO_MSG_MASK << shift);
  2067. status |= (newstat << shift);
  2068. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  2069. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
  2070. tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
  2071. else
  2072. tw32(TG3_CPMU_DRV_STATUS, status);
  2073. return status >> TG3_APE_GPIO_MSG_SHIFT;
  2074. }
  2075. static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
  2076. {
  2077. if (!tg3_flag(tp, IS_NIC))
  2078. return 0;
  2079. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  2080. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  2081. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
  2082. if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
  2083. return -EIO;
  2084. tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
  2085. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
  2086. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2087. tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
  2088. } else {
  2089. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
  2090. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2091. }
  2092. return 0;
  2093. }
  2094. static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
  2095. {
  2096. u32 grc_local_ctrl;
  2097. if (!tg3_flag(tp, IS_NIC) ||
  2098. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2099. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
  2100. return;
  2101. grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
  2102. tw32_wait_f(GRC_LOCAL_CTRL,
  2103. grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
  2104. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2105. tw32_wait_f(GRC_LOCAL_CTRL,
  2106. grc_local_ctrl,
  2107. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2108. tw32_wait_f(GRC_LOCAL_CTRL,
  2109. grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
  2110. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2111. }
  2112. static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
  2113. {
  2114. if (!tg3_flag(tp, IS_NIC))
  2115. return;
  2116. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2117. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  2118. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  2119. (GRC_LCLCTRL_GPIO_OE0 |
  2120. GRC_LCLCTRL_GPIO_OE1 |
  2121. GRC_LCLCTRL_GPIO_OE2 |
  2122. GRC_LCLCTRL_GPIO_OUTPUT0 |
  2123. GRC_LCLCTRL_GPIO_OUTPUT1),
  2124. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2125. } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  2126. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
  2127. /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
  2128. u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
  2129. GRC_LCLCTRL_GPIO_OE1 |
  2130. GRC_LCLCTRL_GPIO_OE2 |
  2131. GRC_LCLCTRL_GPIO_OUTPUT0 |
  2132. GRC_LCLCTRL_GPIO_OUTPUT1 |
  2133. tp->grc_local_ctrl;
  2134. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
  2135. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2136. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
  2137. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
  2138. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2139. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
  2140. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
  2141. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2142. } else {
  2143. u32 no_gpio2;
  2144. u32 grc_local_ctrl = 0;
  2145. /* Workaround to prevent overdrawing Amps. */
  2146. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  2147. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  2148. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  2149. grc_local_ctrl,
  2150. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2151. }
  2152. /* On 5753 and variants, GPIO2 cannot be used. */
  2153. no_gpio2 = tp->nic_sram_data_cfg &
  2154. NIC_SRAM_DATA_CFG_NO_GPIO2;
  2155. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  2156. GRC_LCLCTRL_GPIO_OE1 |
  2157. GRC_LCLCTRL_GPIO_OE2 |
  2158. GRC_LCLCTRL_GPIO_OUTPUT1 |
  2159. GRC_LCLCTRL_GPIO_OUTPUT2;
  2160. if (no_gpio2) {
  2161. grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
  2162. GRC_LCLCTRL_GPIO_OUTPUT2);
  2163. }
  2164. tw32_wait_f(GRC_LOCAL_CTRL,
  2165. tp->grc_local_ctrl | grc_local_ctrl,
  2166. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2167. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
  2168. tw32_wait_f(GRC_LOCAL_CTRL,
  2169. tp->grc_local_ctrl | grc_local_ctrl,
  2170. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2171. if (!no_gpio2) {
  2172. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
  2173. tw32_wait_f(GRC_LOCAL_CTRL,
  2174. tp->grc_local_ctrl | grc_local_ctrl,
  2175. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2176. }
  2177. }
  2178. }
  2179. static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
  2180. {
  2181. u32 msg = 0;
  2182. /* Serialize power state transitions */
  2183. if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
  2184. return;
  2185. if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
  2186. msg = TG3_GPIO_MSG_NEED_VAUX;
  2187. msg = tg3_set_function_status(tp, msg);
  2188. if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
  2189. goto done;
  2190. if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
  2191. tg3_pwrsrc_switch_to_vaux(tp);
  2192. else
  2193. tg3_pwrsrc_die_with_vmain(tp);
  2194. done:
  2195. tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
  2196. }
  2197. static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
  2198. {
  2199. bool need_vaux = false;
  2200. /* The GPIOs do something completely different on 57765. */
  2201. if (!tg3_flag(tp, IS_NIC) ||
  2202. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  2203. return;
  2204. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  2205. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  2206. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
  2207. tg3_frob_aux_power_5717(tp, include_wol ?
  2208. tg3_flag(tp, WOL_ENABLE) != 0 : 0);
  2209. return;
  2210. }
  2211. if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
  2212. struct net_device *dev_peer;
  2213. dev_peer = pci_get_drvdata(tp->pdev_peer);
  2214. /* remove_one() may have been run on the peer. */
  2215. if (dev_peer) {
  2216. struct tg3 *tp_peer = netdev_priv(dev_peer);
  2217. if (tg3_flag(tp_peer, INIT_COMPLETE))
  2218. return;
  2219. if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
  2220. tg3_flag(tp_peer, ENABLE_ASF))
  2221. need_vaux = true;
  2222. }
  2223. }
  2224. if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
  2225. tg3_flag(tp, ENABLE_ASF))
  2226. need_vaux = true;
  2227. if (need_vaux)
  2228. tg3_pwrsrc_switch_to_vaux(tp);
  2229. else
  2230. tg3_pwrsrc_die_with_vmain(tp);
  2231. }
  2232. static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
  2233. {
  2234. if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
  2235. return 1;
  2236. else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
  2237. if (speed != SPEED_10)
  2238. return 1;
  2239. } else if (speed == SPEED_10)
  2240. return 1;
  2241. return 0;
  2242. }
  2243. static int tg3_setup_phy(struct tg3 *, int);
  2244. static int tg3_halt_cpu(struct tg3 *, u32);
  2245. static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
  2246. {
  2247. u32 val;
  2248. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  2249. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  2250. u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
  2251. u32 serdes_cfg = tr32(MAC_SERDES_CFG);
  2252. sg_dig_ctrl |=
  2253. SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
  2254. tw32(SG_DIG_CTRL, sg_dig_ctrl);
  2255. tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
  2256. }
  2257. return;
  2258. }
  2259. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  2260. tg3_bmcr_reset(tp);
  2261. val = tr32(GRC_MISC_CFG);
  2262. tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
  2263. udelay(40);
  2264. return;
  2265. } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  2266. u32 phytest;
  2267. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
  2268. u32 phy;
  2269. tg3_writephy(tp, MII_ADVERTISE, 0);
  2270. tg3_writephy(tp, MII_BMCR,
  2271. BMCR_ANENABLE | BMCR_ANRESTART);
  2272. tg3_writephy(tp, MII_TG3_FET_TEST,
  2273. phytest | MII_TG3_FET_SHADOW_EN);
  2274. if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
  2275. phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
  2276. tg3_writephy(tp,
  2277. MII_TG3_FET_SHDW_AUXMODE4,
  2278. phy);
  2279. }
  2280. tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
  2281. }
  2282. return;
  2283. } else if (do_low_power) {
  2284. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  2285. MII_TG3_EXT_CTRL_FORCE_LED_OFF);
  2286. val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
  2287. MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
  2288. MII_TG3_AUXCTL_PCTL_VREG_11V;
  2289. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
  2290. }
  2291. /* The PHY should not be powered down on some chips because
  2292. * of bugs.
  2293. */
  2294. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2295. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  2296. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
  2297. (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
  2298. return;
  2299. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
  2300. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
  2301. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  2302. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  2303. val |= CPMU_LSPD_1000MB_MACCLK_12_5;
  2304. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  2305. }
  2306. tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
  2307. }
  2308. /* tp->lock is held. */
  2309. static int tg3_nvram_lock(struct tg3 *tp)
  2310. {
  2311. if (tg3_flag(tp, NVRAM)) {
  2312. int i;
  2313. if (tp->nvram_lock_cnt == 0) {
  2314. tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  2315. for (i = 0; i < 8000; i++) {
  2316. if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  2317. break;
  2318. udelay(20);
  2319. }
  2320. if (i == 8000) {
  2321. tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
  2322. return -ENODEV;
  2323. }
  2324. }
  2325. tp->nvram_lock_cnt++;
  2326. }
  2327. return 0;
  2328. }
  2329. /* tp->lock is held. */
  2330. static void tg3_nvram_unlock(struct tg3 *tp)
  2331. {
  2332. if (tg3_flag(tp, NVRAM)) {
  2333. if (tp->nvram_lock_cnt > 0)
  2334. tp->nvram_lock_cnt--;
  2335. if (tp->nvram_lock_cnt == 0)
  2336. tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
  2337. }
  2338. }
  2339. /* tp->lock is held. */
  2340. static void tg3_enable_nvram_access(struct tg3 *tp)
  2341. {
  2342. if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
  2343. u32 nvaccess = tr32(NVRAM_ACCESS);
  2344. tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
  2345. }
  2346. }
  2347. /* tp->lock is held. */
  2348. static void tg3_disable_nvram_access(struct tg3 *tp)
  2349. {
  2350. if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
  2351. u32 nvaccess = tr32(NVRAM_ACCESS);
  2352. tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
  2353. }
  2354. }
  2355. static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
  2356. u32 offset, u32 *val)
  2357. {
  2358. u32 tmp;
  2359. int i;
  2360. if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
  2361. return -EINVAL;
  2362. tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
  2363. EEPROM_ADDR_DEVID_MASK |
  2364. EEPROM_ADDR_READ);
  2365. tw32(GRC_EEPROM_ADDR,
  2366. tmp |
  2367. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  2368. ((offset << EEPROM_ADDR_ADDR_SHIFT) &
  2369. EEPROM_ADDR_ADDR_MASK) |
  2370. EEPROM_ADDR_READ | EEPROM_ADDR_START);
  2371. for (i = 0; i < 1000; i++) {
  2372. tmp = tr32(GRC_EEPROM_ADDR);
  2373. if (tmp & EEPROM_ADDR_COMPLETE)
  2374. break;
  2375. msleep(1);
  2376. }
  2377. if (!(tmp & EEPROM_ADDR_COMPLETE))
  2378. return -EBUSY;
  2379. tmp = tr32(GRC_EEPROM_DATA);
  2380. /*
  2381. * The data will always be opposite the native endian
  2382. * format. Perform a blind byteswap to compensate.
  2383. */
  2384. *val = swab32(tmp);
  2385. return 0;
  2386. }
  2387. #define NVRAM_CMD_TIMEOUT 10000
  2388. static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
  2389. {
  2390. int i;
  2391. tw32(NVRAM_CMD, nvram_cmd);
  2392. for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
  2393. udelay(10);
  2394. if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
  2395. udelay(10);
  2396. break;
  2397. }
  2398. }
  2399. if (i == NVRAM_CMD_TIMEOUT)
  2400. return -EBUSY;
  2401. return 0;
  2402. }
  2403. static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
  2404. {
  2405. if (tg3_flag(tp, NVRAM) &&
  2406. tg3_flag(tp, NVRAM_BUFFERED) &&
  2407. tg3_flag(tp, FLASH) &&
  2408. !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
  2409. (tp->nvram_jedecnum == JEDEC_ATMEL))
  2410. addr = ((addr / tp->nvram_pagesize) <<
  2411. ATMEL_AT45DB0X1B_PAGE_POS) +
  2412. (addr % tp->nvram_pagesize);
  2413. return addr;
  2414. }
  2415. static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
  2416. {
  2417. if (tg3_flag(tp, NVRAM) &&
  2418. tg3_flag(tp, NVRAM_BUFFERED) &&
  2419. tg3_flag(tp, FLASH) &&
  2420. !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
  2421. (tp->nvram_jedecnum == JEDEC_ATMEL))
  2422. addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
  2423. tp->nvram_pagesize) +
  2424. (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
  2425. return addr;
  2426. }
  2427. /* NOTE: Data read in from NVRAM is byteswapped according to
  2428. * the byteswapping settings for all other register accesses.
  2429. * tg3 devices are BE devices, so on a BE machine, the data
  2430. * returned will be exactly as it is seen in NVRAM. On a LE
  2431. * machine, the 32-bit value will be byteswapped.
  2432. */
  2433. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
  2434. {
  2435. int ret;
  2436. if (!tg3_flag(tp, NVRAM))
  2437. return tg3_nvram_read_using_eeprom(tp, offset, val);
  2438. offset = tg3_nvram_phys_addr(tp, offset);
  2439. if (offset > NVRAM_ADDR_MSK)
  2440. return -EINVAL;
  2441. ret = tg3_nvram_lock(tp);
  2442. if (ret)
  2443. return ret;
  2444. tg3_enable_nvram_access(tp);
  2445. tw32(NVRAM_ADDR, offset);
  2446. ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
  2447. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
  2448. if (ret == 0)
  2449. *val = tr32(NVRAM_RDDATA);
  2450. tg3_disable_nvram_access(tp);
  2451. tg3_nvram_unlock(tp);
  2452. return ret;
  2453. }
  2454. /* Ensures NVRAM data is in bytestream format. */
  2455. static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
  2456. {
  2457. u32 v;
  2458. int res = tg3_nvram_read(tp, offset, &v);
  2459. if (!res)
  2460. *val = cpu_to_be32(v);
  2461. return res;
  2462. }
  2463. #define RX_CPU_SCRATCH_BASE 0x30000
  2464. #define RX_CPU_SCRATCH_SIZE 0x04000
  2465. #define TX_CPU_SCRATCH_BASE 0x34000
  2466. #define TX_CPU_SCRATCH_SIZE 0x04000
  2467. /* tp->lock is held. */
  2468. static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
  2469. {
  2470. int i;
  2471. BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
  2472. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  2473. u32 val = tr32(GRC_VCPU_EXT_CTRL);
  2474. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
  2475. return 0;
  2476. }
  2477. if (offset == RX_CPU_BASE) {
  2478. for (i = 0; i < 10000; i++) {
  2479. tw32(offset + CPU_STATE, 0xffffffff);
  2480. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  2481. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  2482. break;
  2483. }
  2484. tw32(offset + CPU_STATE, 0xffffffff);
  2485. tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
  2486. udelay(10);
  2487. } else {
  2488. for (i = 0; i < 10000; i++) {
  2489. tw32(offset + CPU_STATE, 0xffffffff);
  2490. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  2491. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  2492. break;
  2493. }
  2494. }
  2495. if (i >= 10000) {
  2496. netdev_err(tp->dev, "%s timed out, %s CPU\n",
  2497. __func__, offset == RX_CPU_BASE ? "RX" : "TX");
  2498. return -ENODEV;
  2499. }
  2500. /* Clear firmware's nvram arbitration. */
  2501. if (tg3_flag(tp, NVRAM))
  2502. tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
  2503. return 0;
  2504. }
  2505. struct fw_info {
  2506. unsigned int fw_base;
  2507. unsigned int fw_len;
  2508. const __be32 *fw_data;
  2509. };
  2510. /* tp->lock is held. */
  2511. static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
  2512. u32 cpu_scratch_base, int cpu_scratch_size,
  2513. struct fw_info *info)
  2514. {
  2515. int err, lock_err, i;
  2516. void (*write_op)(struct tg3 *, u32, u32);
  2517. if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
  2518. netdev_err(tp->dev,
  2519. "%s: Trying to load TX cpu firmware which is 5705\n",
  2520. __func__);
  2521. return -EINVAL;
  2522. }
  2523. if (tg3_flag(tp, 5705_PLUS))
  2524. write_op = tg3_write_mem;
  2525. else
  2526. write_op = tg3_write_indirect_reg32;
  2527. /* It is possible that bootcode is still loading at this point.
  2528. * Get the nvram lock first before halting the cpu.
  2529. */
  2530. lock_err = tg3_nvram_lock(tp);
  2531. err = tg3_halt_cpu(tp, cpu_base);
  2532. if (!lock_err)
  2533. tg3_nvram_unlock(tp);
  2534. if (err)
  2535. goto out;
  2536. for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  2537. write_op(tp, cpu_scratch_base + i, 0);
  2538. tw32(cpu_base + CPU_STATE, 0xffffffff);
  2539. tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
  2540. for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
  2541. write_op(tp, (cpu_scratch_base +
  2542. (info->fw_base & 0xffff) +
  2543. (i * sizeof(u32))),
  2544. be32_to_cpu(info->fw_data[i]));
  2545. err = 0;
  2546. out:
  2547. return err;
  2548. }
  2549. /* tp->lock is held. */
  2550. static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
  2551. {
  2552. struct fw_info info;
  2553. const __be32 *fw_data;
  2554. int err, i;
  2555. fw_data = (void *)tp->fw->data;
  2556. /* Firmware blob starts with version numbers, followed by
  2557. start address and length. We are setting complete length.
  2558. length = end_address_of_bss - start_address_of_text.
  2559. Remainder is the blob to be loaded contiguously
  2560. from start address. */
  2561. info.fw_base = be32_to_cpu(fw_data[1]);
  2562. info.fw_len = tp->fw->size - 12;
  2563. info.fw_data = &fw_data[3];
  2564. err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
  2565. RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
  2566. &info);
  2567. if (err)
  2568. return err;
  2569. err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  2570. TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  2571. &info);
  2572. if (err)
  2573. return err;
  2574. /* Now startup only the RX cpu. */
  2575. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  2576. tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
  2577. for (i = 0; i < 5; i++) {
  2578. if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
  2579. break;
  2580. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  2581. tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
  2582. tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
  2583. udelay(1000);
  2584. }
  2585. if (i >= 5) {
  2586. netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
  2587. "should be %08x\n", __func__,
  2588. tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
  2589. return -ENODEV;
  2590. }
  2591. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  2592. tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
  2593. return 0;
  2594. }
  2595. /* tp->lock is held. */
  2596. static int tg3_load_tso_firmware(struct tg3 *tp)
  2597. {
  2598. struct fw_info info;
  2599. const __be32 *fw_data;
  2600. unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  2601. int err, i;
  2602. if (tg3_flag(tp, HW_TSO_1) ||
  2603. tg3_flag(tp, HW_TSO_2) ||
  2604. tg3_flag(tp, HW_TSO_3))
  2605. return 0;
  2606. fw_data = (void *)tp->fw->data;
  2607. /* Firmware blob starts with version numbers, followed by
  2608. start address and length. We are setting complete length.
  2609. length = end_address_of_bss - start_address_of_text.
  2610. Remainder is the blob to be loaded contiguously
  2611. from start address. */
  2612. info.fw_base = be32_to_cpu(fw_data[1]);
  2613. cpu_scratch_size = tp->fw_len;
  2614. info.fw_len = tp->fw->size - 12;
  2615. info.fw_data = &fw_data[3];
  2616. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  2617. cpu_base = RX_CPU_BASE;
  2618. cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
  2619. } else {
  2620. cpu_base = TX_CPU_BASE;
  2621. cpu_scratch_base = TX_CPU_SCRATCH_BASE;
  2622. cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
  2623. }
  2624. err = tg3_load_firmware_cpu(tp, cpu_base,
  2625. cpu_scratch_base, cpu_scratch_size,
  2626. &info);
  2627. if (err)
  2628. return err;
  2629. /* Now startup the cpu. */
  2630. tw32(cpu_base + CPU_STATE, 0xffffffff);
  2631. tw32_f(cpu_base + CPU_PC, info.fw_base);
  2632. for (i = 0; i < 5; i++) {
  2633. if (tr32(cpu_base + CPU_PC) == info.fw_base)
  2634. break;
  2635. tw32(cpu_base + CPU_STATE, 0xffffffff);
  2636. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  2637. tw32_f(cpu_base + CPU_PC, info.fw_base);
  2638. udelay(1000);
  2639. }
  2640. if (i >= 5) {
  2641. netdev_err(tp->dev,
  2642. "%s fails to set CPU PC, is %08x should be %08x\n",
  2643. __func__, tr32(cpu_base + CPU_PC), info.fw_base);
  2644. return -ENODEV;
  2645. }
  2646. tw32(cpu_base + CPU_STATE, 0xffffffff);
  2647. tw32_f(cpu_base + CPU_MODE, 0x00000000);
  2648. return 0;
  2649. }
  2650. /* tp->lock is held. */
  2651. static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
  2652. {
  2653. u32 addr_high, addr_low;
  2654. int i;
  2655. addr_high = ((tp->dev->dev_addr[0] << 8) |
  2656. tp->dev->dev_addr[1]);
  2657. addr_low = ((tp->dev->dev_addr[2] << 24) |
  2658. (tp->dev->dev_addr[3] << 16) |
  2659. (tp->dev->dev_addr[4] << 8) |
  2660. (tp->dev->dev_addr[5] << 0));
  2661. for (i = 0; i < 4; i++) {
  2662. if (i == 1 && skip_mac_1)
  2663. continue;
  2664. tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
  2665. tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  2666. }
  2667. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  2668. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  2669. for (i = 0; i < 12; i++) {
  2670. tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
  2671. tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
  2672. }
  2673. }
  2674. addr_high = (tp->dev->dev_addr[0] +
  2675. tp->dev->dev_addr[1] +
  2676. tp->dev->dev_addr[2] +
  2677. tp->dev->dev_addr[3] +
  2678. tp->dev->dev_addr[4] +
  2679. tp->dev->dev_addr[5]) &
  2680. TX_BACKOFF_SEED_MASK;
  2681. tw32(MAC_TX_BACKOFF_SEED, addr_high);
  2682. }
  2683. static void tg3_enable_register_access(struct tg3 *tp)
  2684. {
  2685. /*
  2686. * Make sure register accesses (indirect or otherwise) will function
  2687. * correctly.
  2688. */
  2689. pci_write_config_dword(tp->pdev,
  2690. TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
  2691. }
  2692. static int tg3_power_up(struct tg3 *tp)
  2693. {
  2694. int err;
  2695. tg3_enable_register_access(tp);
  2696. err = pci_set_power_state(tp->pdev, PCI_D0);
  2697. if (!err) {
  2698. /* Switch out of Vaux if it is a NIC */
  2699. tg3_pwrsrc_switch_to_vmain(tp);
  2700. } else {
  2701. netdev_err(tp->dev, "Transition to D0 failed\n");
  2702. }
  2703. return err;
  2704. }
  2705. static int tg3_power_down_prepare(struct tg3 *tp)
  2706. {
  2707. u32 misc_host_ctrl;
  2708. bool device_should_wake, do_low_power;
  2709. tg3_enable_register_access(tp);
  2710. /* Restore the CLKREQ setting. */
  2711. if (tg3_flag(tp, CLKREQ_BUG)) {
  2712. u16 lnkctl;
  2713. pci_read_config_word(tp->pdev,
  2714. pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
  2715. &lnkctl);
  2716. lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
  2717. pci_write_config_word(tp->pdev,
  2718. pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
  2719. lnkctl);
  2720. }
  2721. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  2722. tw32(TG3PCI_MISC_HOST_CTRL,
  2723. misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
  2724. device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
  2725. tg3_flag(tp, WOL_ENABLE);
  2726. if (tg3_flag(tp, USE_PHYLIB)) {
  2727. do_low_power = false;
  2728. if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
  2729. !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  2730. struct phy_device *phydev;
  2731. u32 phyid, advertising;
  2732. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  2733. tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
  2734. tp->link_config.orig_speed = phydev->speed;
  2735. tp->link_config.orig_duplex = phydev->duplex;
  2736. tp->link_config.orig_autoneg = phydev->autoneg;
  2737. tp->link_config.orig_advertising = phydev->advertising;
  2738. advertising = ADVERTISED_TP |
  2739. ADVERTISED_Pause |
  2740. ADVERTISED_Autoneg |
  2741. ADVERTISED_10baseT_Half;
  2742. if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
  2743. if (tg3_flag(tp, WOL_SPEED_100MB))
  2744. advertising |=
  2745. ADVERTISED_100baseT_Half |
  2746. ADVERTISED_100baseT_Full |
  2747. ADVERTISED_10baseT_Full;
  2748. else
  2749. advertising |= ADVERTISED_10baseT_Full;
  2750. }
  2751. phydev->advertising = advertising;
  2752. phy_start_aneg(phydev);
  2753. phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
  2754. if (phyid != PHY_ID_BCMAC131) {
  2755. phyid &= PHY_BCM_OUI_MASK;
  2756. if (phyid == PHY_BCM_OUI_1 ||
  2757. phyid == PHY_BCM_OUI_2 ||
  2758. phyid == PHY_BCM_OUI_3)
  2759. do_low_power = true;
  2760. }
  2761. }
  2762. } else {
  2763. do_low_power = true;
  2764. if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  2765. tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
  2766. tp->link_config.orig_speed = tp->link_config.speed;
  2767. tp->link_config.orig_duplex = tp->link_config.duplex;
  2768. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  2769. }
  2770. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  2771. tp->link_config.speed = SPEED_10;
  2772. tp->link_config.duplex = DUPLEX_HALF;
  2773. tp->link_config.autoneg = AUTONEG_ENABLE;
  2774. tg3_setup_phy(tp, 0);
  2775. }
  2776. }
  2777. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  2778. u32 val;
  2779. val = tr32(GRC_VCPU_EXT_CTRL);
  2780. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
  2781. } else if (!tg3_flag(tp, ENABLE_ASF)) {
  2782. int i;
  2783. u32 val;
  2784. for (i = 0; i < 200; i++) {
  2785. tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
  2786. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  2787. break;
  2788. msleep(1);
  2789. }
  2790. }
  2791. if (tg3_flag(tp, WOL_CAP))
  2792. tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
  2793. WOL_DRV_STATE_SHUTDOWN |
  2794. WOL_DRV_WOL |
  2795. WOL_SET_MAGIC_PKT);
  2796. if (device_should_wake) {
  2797. u32 mac_mode;
  2798. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  2799. if (do_low_power &&
  2800. !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  2801. tg3_phy_auxctl_write(tp,
  2802. MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
  2803. MII_TG3_AUXCTL_PCTL_WOL_EN |
  2804. MII_TG3_AUXCTL_PCTL_100TX_LPWR |
  2805. MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
  2806. udelay(40);
  2807. }
  2808. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  2809. mac_mode = MAC_MODE_PORT_MODE_GMII;
  2810. else
  2811. mac_mode = MAC_MODE_PORT_MODE_MII;
  2812. mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
  2813. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  2814. ASIC_REV_5700) {
  2815. u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
  2816. SPEED_100 : SPEED_10;
  2817. if (tg3_5700_link_polarity(tp, speed))
  2818. mac_mode |= MAC_MODE_LINK_POLARITY;
  2819. else
  2820. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  2821. }
  2822. } else {
  2823. mac_mode = MAC_MODE_PORT_MODE_TBI;
  2824. }
  2825. if (!tg3_flag(tp, 5750_PLUS))
  2826. tw32(MAC_LED_CTRL, tp->led_ctrl);
  2827. mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
  2828. if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
  2829. (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
  2830. mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
  2831. if (tg3_flag(tp, ENABLE_APE))
  2832. mac_mode |= MAC_MODE_APE_TX_EN |
  2833. MAC_MODE_APE_RX_EN |
  2834. MAC_MODE_TDE_ENABLE;
  2835. tw32_f(MAC_MODE, mac_mode);
  2836. udelay(100);
  2837. tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
  2838. udelay(10);
  2839. }
  2840. if (!tg3_flag(tp, WOL_SPEED_100MB) &&
  2841. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2842. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  2843. u32 base_val;
  2844. base_val = tp->pci_clock_ctrl;
  2845. base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
  2846. CLOCK_CTRL_TXCLK_DISABLE);
  2847. tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
  2848. CLOCK_CTRL_PWRDOWN_PLL133, 40);
  2849. } else if (tg3_flag(tp, 5780_CLASS) ||
  2850. tg3_flag(tp, CPMU_PRESENT) ||
  2851. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  2852. /* do nothing */
  2853. } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
  2854. u32 newbits1, newbits2;
  2855. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2856. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  2857. newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
  2858. CLOCK_CTRL_TXCLK_DISABLE |
  2859. CLOCK_CTRL_ALTCLK);
  2860. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  2861. } else if (tg3_flag(tp, 5705_PLUS)) {
  2862. newbits1 = CLOCK_CTRL_625_CORE;
  2863. newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
  2864. } else {
  2865. newbits1 = CLOCK_CTRL_ALTCLK;
  2866. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  2867. }
  2868. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
  2869. 40);
  2870. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
  2871. 40);
  2872. if (!tg3_flag(tp, 5705_PLUS)) {
  2873. u32 newbits3;
  2874. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2875. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  2876. newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
  2877. CLOCK_CTRL_TXCLK_DISABLE |
  2878. CLOCK_CTRL_44MHZ_CORE);
  2879. } else {
  2880. newbits3 = CLOCK_CTRL_44MHZ_CORE;
  2881. }
  2882. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  2883. tp->pci_clock_ctrl | newbits3, 40);
  2884. }
  2885. }
  2886. if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
  2887. tg3_power_down_phy(tp, do_low_power);
  2888. tg3_frob_aux_power(tp, true);
  2889. /* Workaround for unstable PLL clock */
  2890. if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  2891. (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
  2892. u32 val = tr32(0x7d00);
  2893. val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  2894. tw32(0x7d00, val);
  2895. if (!tg3_flag(tp, ENABLE_ASF)) {
  2896. int err;
  2897. err = tg3_nvram_lock(tp);
  2898. tg3_halt_cpu(tp, RX_CPU_BASE);
  2899. if (!err)
  2900. tg3_nvram_unlock(tp);
  2901. }
  2902. }
  2903. tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
  2904. return 0;
  2905. }
  2906. static void tg3_power_down(struct tg3 *tp)
  2907. {
  2908. tg3_power_down_prepare(tp);
  2909. pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
  2910. pci_set_power_state(tp->pdev, PCI_D3hot);
  2911. }
  2912. static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
  2913. {
  2914. switch (val & MII_TG3_AUX_STAT_SPDMASK) {
  2915. case MII_TG3_AUX_STAT_10HALF:
  2916. *speed = SPEED_10;
  2917. *duplex = DUPLEX_HALF;
  2918. break;
  2919. case MII_TG3_AUX_STAT_10FULL:
  2920. *speed = SPEED_10;
  2921. *duplex = DUPLEX_FULL;
  2922. break;
  2923. case MII_TG3_AUX_STAT_100HALF:
  2924. *speed = SPEED_100;
  2925. *duplex = DUPLEX_HALF;
  2926. break;
  2927. case MII_TG3_AUX_STAT_100FULL:
  2928. *speed = SPEED_100;
  2929. *duplex = DUPLEX_FULL;
  2930. break;
  2931. case MII_TG3_AUX_STAT_1000HALF:
  2932. *speed = SPEED_1000;
  2933. *duplex = DUPLEX_HALF;
  2934. break;
  2935. case MII_TG3_AUX_STAT_1000FULL:
  2936. *speed = SPEED_1000;
  2937. *duplex = DUPLEX_FULL;
  2938. break;
  2939. default:
  2940. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  2941. *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
  2942. SPEED_10;
  2943. *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
  2944. DUPLEX_HALF;
  2945. break;
  2946. }
  2947. *speed = SPEED_INVALID;
  2948. *duplex = DUPLEX_INVALID;
  2949. break;
  2950. }
  2951. }
  2952. static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
  2953. {
  2954. int err = 0;
  2955. u32 val, new_adv;
  2956. new_adv = ADVERTISE_CSMA;
  2957. new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
  2958. new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
  2959. err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2960. if (err)
  2961. goto done;
  2962. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  2963. goto done;
  2964. new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
  2965. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  2966. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  2967. new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
  2968. err = tg3_writephy(tp, MII_CTRL1000, new_adv);
  2969. if (err)
  2970. goto done;
  2971. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
  2972. goto done;
  2973. tw32(TG3_CPMU_EEE_MODE,
  2974. tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
  2975. err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
  2976. if (!err) {
  2977. u32 err2;
  2978. val = 0;
  2979. /* Advertise 100-BaseTX EEE ability */
  2980. if (advertise & ADVERTISED_100baseT_Full)
  2981. val |= MDIO_AN_EEE_ADV_100TX;
  2982. /* Advertise 1000-BaseT EEE ability */
  2983. if (advertise & ADVERTISED_1000baseT_Full)
  2984. val |= MDIO_AN_EEE_ADV_1000T;
  2985. err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  2986. if (err)
  2987. val = 0;
  2988. switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
  2989. case ASIC_REV_5717:
  2990. case ASIC_REV_57765:
  2991. case ASIC_REV_5719:
  2992. /* If we advertised any eee advertisements above... */
  2993. if (val)
  2994. val = MII_TG3_DSP_TAP26_ALNOKO |
  2995. MII_TG3_DSP_TAP26_RMRXSTO |
  2996. MII_TG3_DSP_TAP26_OPCSINPT;
  2997. tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
  2998. /* Fall through */
  2999. case ASIC_REV_5720:
  3000. if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
  3001. tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
  3002. MII_TG3_DSP_CH34TP2_HIBW01);
  3003. }
  3004. err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
  3005. if (!err)
  3006. err = err2;
  3007. }
  3008. done:
  3009. return err;
  3010. }
  3011. static void tg3_phy_copper_begin(struct tg3 *tp)
  3012. {
  3013. u32 new_adv;
  3014. int i;
  3015. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
  3016. new_adv = ADVERTISED_10baseT_Half |
  3017. ADVERTISED_10baseT_Full;
  3018. if (tg3_flag(tp, WOL_SPEED_100MB))
  3019. new_adv |= ADVERTISED_100baseT_Half |
  3020. ADVERTISED_100baseT_Full;
  3021. tg3_phy_autoneg_cfg(tp, new_adv,
  3022. FLOW_CTRL_TX | FLOW_CTRL_RX);
  3023. } else if (tp->link_config.speed == SPEED_INVALID) {
  3024. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  3025. tp->link_config.advertising &=
  3026. ~(ADVERTISED_1000baseT_Half |
  3027. ADVERTISED_1000baseT_Full);
  3028. tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
  3029. tp->link_config.flowctrl);
  3030. } else {
  3031. /* Asking for a specific link mode. */
  3032. if (tp->link_config.speed == SPEED_1000) {
  3033. if (tp->link_config.duplex == DUPLEX_FULL)
  3034. new_adv = ADVERTISED_1000baseT_Full;
  3035. else
  3036. new_adv = ADVERTISED_1000baseT_Half;
  3037. } else if (tp->link_config.speed == SPEED_100) {
  3038. if (tp->link_config.duplex == DUPLEX_FULL)
  3039. new_adv = ADVERTISED_100baseT_Full;
  3040. else
  3041. new_adv = ADVERTISED_100baseT_Half;
  3042. } else {
  3043. if (tp->link_config.duplex == DUPLEX_FULL)
  3044. new_adv = ADVERTISED_10baseT_Full;
  3045. else
  3046. new_adv = ADVERTISED_10baseT_Half;
  3047. }
  3048. tg3_phy_autoneg_cfg(tp, new_adv,
  3049. tp->link_config.flowctrl);
  3050. }
  3051. if (tp->link_config.autoneg == AUTONEG_DISABLE &&
  3052. tp->link_config.speed != SPEED_INVALID) {
  3053. u32 bmcr, orig_bmcr;
  3054. tp->link_config.active_speed = tp->link_config.speed;
  3055. tp->link_config.active_duplex = tp->link_config.duplex;
  3056. bmcr = 0;
  3057. switch (tp->link_config.speed) {
  3058. default:
  3059. case SPEED_10:
  3060. break;
  3061. case SPEED_100:
  3062. bmcr |= BMCR_SPEED100;
  3063. break;
  3064. case SPEED_1000:
  3065. bmcr |= BMCR_SPEED1000;
  3066. break;
  3067. }
  3068. if (tp->link_config.duplex == DUPLEX_FULL)
  3069. bmcr |= BMCR_FULLDPLX;
  3070. if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
  3071. (bmcr != orig_bmcr)) {
  3072. tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
  3073. for (i = 0; i < 1500; i++) {
  3074. u32 tmp;
  3075. udelay(10);
  3076. if (tg3_readphy(tp, MII_BMSR, &tmp) ||
  3077. tg3_readphy(tp, MII_BMSR, &tmp))
  3078. continue;
  3079. if (!(tmp & BMSR_LSTATUS)) {
  3080. udelay(40);
  3081. break;
  3082. }
  3083. }
  3084. tg3_writephy(tp, MII_BMCR, bmcr);
  3085. udelay(40);
  3086. }
  3087. } else {
  3088. tg3_writephy(tp, MII_BMCR,
  3089. BMCR_ANENABLE | BMCR_ANRESTART);
  3090. }
  3091. }
  3092. static int tg3_init_5401phy_dsp(struct tg3 *tp)
  3093. {
  3094. int err;
  3095. /* Turn off tap power management. */
  3096. /* Set Extended packet length bit */
  3097. err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
  3098. err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
  3099. err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
  3100. err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
  3101. err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
  3102. err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
  3103. udelay(40);
  3104. return err;
  3105. }
  3106. static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
  3107. {
  3108. u32 adv_reg, all_mask = 0;
  3109. all_mask = ethtool_adv_to_mii_adv_t(mask) & ADVERTISE_ALL;
  3110. if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
  3111. return 0;
  3112. if ((adv_reg & ADVERTISE_ALL) != all_mask)
  3113. return 0;
  3114. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3115. u32 tg3_ctrl;
  3116. all_mask = ethtool_adv_to_mii_ctrl1000_t(mask);
  3117. if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
  3118. return 0;
  3119. tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
  3120. if (tg3_ctrl != all_mask)
  3121. return 0;
  3122. }
  3123. return 1;
  3124. }
  3125. static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
  3126. {
  3127. u32 curadv, reqadv;
  3128. if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
  3129. return 1;
  3130. curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  3131. reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  3132. if (tp->link_config.active_duplex == DUPLEX_FULL) {
  3133. if (curadv != reqadv)
  3134. return 0;
  3135. if (tg3_flag(tp, PAUSE_AUTONEG))
  3136. tg3_readphy(tp, MII_LPA, rmtadv);
  3137. } else {
  3138. /* Reprogram the advertisement register, even if it
  3139. * does not affect the current link. If the link
  3140. * gets renegotiated in the future, we can save an
  3141. * additional renegotiation cycle by advertising
  3142. * it correctly in the first place.
  3143. */
  3144. if (curadv != reqadv) {
  3145. *lcladv &= ~(ADVERTISE_PAUSE_CAP |
  3146. ADVERTISE_PAUSE_ASYM);
  3147. tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
  3148. }
  3149. }
  3150. return 1;
  3151. }
  3152. static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
  3153. {
  3154. int current_link_up;
  3155. u32 bmsr, val;
  3156. u32 lcl_adv, rmt_adv;
  3157. u16 current_speed;
  3158. u8 current_duplex;
  3159. int i, err;
  3160. tw32(MAC_EVENT, 0);
  3161. tw32_f(MAC_STATUS,
  3162. (MAC_STATUS_SYNC_CHANGED |
  3163. MAC_STATUS_CFG_CHANGED |
  3164. MAC_STATUS_MI_COMPLETION |
  3165. MAC_STATUS_LNKSTATE_CHANGED));
  3166. udelay(40);
  3167. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  3168. tw32_f(MAC_MI_MODE,
  3169. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  3170. udelay(80);
  3171. }
  3172. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
  3173. /* Some third-party PHYs need to be reset on link going
  3174. * down.
  3175. */
  3176. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  3177. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  3178. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  3179. netif_carrier_ok(tp->dev)) {
  3180. tg3_readphy(tp, MII_BMSR, &bmsr);
  3181. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  3182. !(bmsr & BMSR_LSTATUS))
  3183. force_reset = 1;
  3184. }
  3185. if (force_reset)
  3186. tg3_phy_reset(tp);
  3187. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  3188. tg3_readphy(tp, MII_BMSR, &bmsr);
  3189. if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
  3190. !tg3_flag(tp, INIT_COMPLETE))
  3191. bmsr = 0;
  3192. if (!(bmsr & BMSR_LSTATUS)) {
  3193. err = tg3_init_5401phy_dsp(tp);
  3194. if (err)
  3195. return err;
  3196. tg3_readphy(tp, MII_BMSR, &bmsr);
  3197. for (i = 0; i < 1000; i++) {
  3198. udelay(10);
  3199. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  3200. (bmsr & BMSR_LSTATUS)) {
  3201. udelay(40);
  3202. break;
  3203. }
  3204. }
  3205. if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
  3206. TG3_PHY_REV_BCM5401_B0 &&
  3207. !(bmsr & BMSR_LSTATUS) &&
  3208. tp->link_config.active_speed == SPEED_1000) {
  3209. err = tg3_phy_reset(tp);
  3210. if (!err)
  3211. err = tg3_init_5401phy_dsp(tp);
  3212. if (err)
  3213. return err;
  3214. }
  3215. }
  3216. } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  3217. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
  3218. /* 5701 {A0,B0} CRC bug workaround */
  3219. tg3_writephy(tp, 0x15, 0x0a75);
  3220. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
  3221. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  3222. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
  3223. }
  3224. /* Clear pending interrupts... */
  3225. tg3_readphy(tp, MII_TG3_ISTAT, &val);
  3226. tg3_readphy(tp, MII_TG3_ISTAT, &val);
  3227. if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
  3228. tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
  3229. else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
  3230. tg3_writephy(tp, MII_TG3_IMASK, ~0);
  3231. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  3232. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  3233. if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
  3234. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  3235. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  3236. else
  3237. tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
  3238. }
  3239. current_link_up = 0;
  3240. current_speed = SPEED_INVALID;
  3241. current_duplex = DUPLEX_INVALID;
  3242. if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
  3243. err = tg3_phy_auxctl_read(tp,
  3244. MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
  3245. &val);
  3246. if (!err && !(val & (1 << 10))) {
  3247. tg3_phy_auxctl_write(tp,
  3248. MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
  3249. val | (1 << 10));
  3250. goto relink;
  3251. }
  3252. }
  3253. bmsr = 0;
  3254. for (i = 0; i < 100; i++) {
  3255. tg3_readphy(tp, MII_BMSR, &bmsr);
  3256. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  3257. (bmsr & BMSR_LSTATUS))
  3258. break;
  3259. udelay(40);
  3260. }
  3261. if (bmsr & BMSR_LSTATUS) {
  3262. u32 aux_stat, bmcr;
  3263. tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
  3264. for (i = 0; i < 2000; i++) {
  3265. udelay(10);
  3266. if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
  3267. aux_stat)
  3268. break;
  3269. }
  3270. tg3_aux_stat_to_speed_duplex(tp, aux_stat,
  3271. &current_speed,
  3272. &current_duplex);
  3273. bmcr = 0;
  3274. for (i = 0; i < 200; i++) {
  3275. tg3_readphy(tp, MII_BMCR, &bmcr);
  3276. if (tg3_readphy(tp, MII_BMCR, &bmcr))
  3277. continue;
  3278. if (bmcr && bmcr != 0x7fff)
  3279. break;
  3280. udelay(10);
  3281. }
  3282. lcl_adv = 0;
  3283. rmt_adv = 0;
  3284. tp->link_config.active_speed = current_speed;
  3285. tp->link_config.active_duplex = current_duplex;
  3286. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  3287. if ((bmcr & BMCR_ANENABLE) &&
  3288. tg3_copper_is_advertising_all(tp,
  3289. tp->link_config.advertising)) {
  3290. if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
  3291. &rmt_adv))
  3292. current_link_up = 1;
  3293. }
  3294. } else {
  3295. if (!(bmcr & BMCR_ANENABLE) &&
  3296. tp->link_config.speed == current_speed &&
  3297. tp->link_config.duplex == current_duplex &&
  3298. tp->link_config.flowctrl ==
  3299. tp->link_config.active_flowctrl) {
  3300. current_link_up = 1;
  3301. }
  3302. }
  3303. if (current_link_up == 1 &&
  3304. tp->link_config.active_duplex == DUPLEX_FULL)
  3305. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  3306. }
  3307. relink:
  3308. if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  3309. tg3_phy_copper_begin(tp);
  3310. tg3_readphy(tp, MII_BMSR, &bmsr);
  3311. if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
  3312. (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
  3313. current_link_up = 1;
  3314. }
  3315. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  3316. if (current_link_up == 1) {
  3317. if (tp->link_config.active_speed == SPEED_100 ||
  3318. tp->link_config.active_speed == SPEED_10)
  3319. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  3320. else
  3321. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  3322. } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  3323. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  3324. else
  3325. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  3326. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  3327. if (tp->link_config.active_duplex == DUPLEX_HALF)
  3328. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  3329. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  3330. if (current_link_up == 1 &&
  3331. tg3_5700_link_polarity(tp, tp->link_config.active_speed))
  3332. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  3333. else
  3334. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  3335. }
  3336. /* ??? Without this setting Netgear GA302T PHY does not
  3337. * ??? send/receive packets...
  3338. */
  3339. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
  3340. tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
  3341. tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
  3342. tw32_f(MAC_MI_MODE, tp->mi_mode);
  3343. udelay(80);
  3344. }
  3345. tw32_f(MAC_MODE, tp->mac_mode);
  3346. udelay(40);
  3347. tg3_phy_eee_adjust(tp, current_link_up);
  3348. if (tg3_flag(tp, USE_LINKCHG_REG)) {
  3349. /* Polled via timer. */
  3350. tw32_f(MAC_EVENT, 0);
  3351. } else {
  3352. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  3353. }
  3354. udelay(40);
  3355. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
  3356. current_link_up == 1 &&
  3357. tp->link_config.active_speed == SPEED_1000 &&
  3358. (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
  3359. udelay(120);
  3360. tw32_f(MAC_STATUS,
  3361. (MAC_STATUS_SYNC_CHANGED |
  3362. MAC_STATUS_CFG_CHANGED));
  3363. udelay(40);
  3364. tg3_write_mem(tp,
  3365. NIC_SRAM_FIRMWARE_MBOX,
  3366. NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
  3367. }
  3368. /* Prevent send BD corruption. */
  3369. if (tg3_flag(tp, CLKREQ_BUG)) {
  3370. u16 oldlnkctl, newlnkctl;
  3371. pci_read_config_word(tp->pdev,
  3372. pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
  3373. &oldlnkctl);
  3374. if (tp->link_config.active_speed == SPEED_100 ||
  3375. tp->link_config.active_speed == SPEED_10)
  3376. newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
  3377. else
  3378. newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
  3379. if (newlnkctl != oldlnkctl)
  3380. pci_write_config_word(tp->pdev,
  3381. pci_pcie_cap(tp->pdev) +
  3382. PCI_EXP_LNKCTL, newlnkctl);
  3383. }
  3384. if (current_link_up != netif_carrier_ok(tp->dev)) {
  3385. if (current_link_up)
  3386. netif_carrier_on(tp->dev);
  3387. else
  3388. netif_carrier_off(tp->dev);
  3389. tg3_link_report(tp);
  3390. }
  3391. return 0;
  3392. }
  3393. struct tg3_fiber_aneginfo {
  3394. int state;
  3395. #define ANEG_STATE_UNKNOWN 0
  3396. #define ANEG_STATE_AN_ENABLE 1
  3397. #define ANEG_STATE_RESTART_INIT 2
  3398. #define ANEG_STATE_RESTART 3
  3399. #define ANEG_STATE_DISABLE_LINK_OK 4
  3400. #define ANEG_STATE_ABILITY_DETECT_INIT 5
  3401. #define ANEG_STATE_ABILITY_DETECT 6
  3402. #define ANEG_STATE_ACK_DETECT_INIT 7
  3403. #define ANEG_STATE_ACK_DETECT 8
  3404. #define ANEG_STATE_COMPLETE_ACK_INIT 9
  3405. #define ANEG_STATE_COMPLETE_ACK 10
  3406. #define ANEG_STATE_IDLE_DETECT_INIT 11
  3407. #define ANEG_STATE_IDLE_DETECT 12
  3408. #define ANEG_STATE_LINK_OK 13
  3409. #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
  3410. #define ANEG_STATE_NEXT_PAGE_WAIT 15
  3411. u32 flags;
  3412. #define MR_AN_ENABLE 0x00000001
  3413. #define MR_RESTART_AN 0x00000002
  3414. #define MR_AN_COMPLETE 0x00000004
  3415. #define MR_PAGE_RX 0x00000008
  3416. #define MR_NP_LOADED 0x00000010
  3417. #define MR_TOGGLE_TX 0x00000020
  3418. #define MR_LP_ADV_FULL_DUPLEX 0x00000040
  3419. #define MR_LP_ADV_HALF_DUPLEX 0x00000080
  3420. #define MR_LP_ADV_SYM_PAUSE 0x00000100
  3421. #define MR_LP_ADV_ASYM_PAUSE 0x00000200
  3422. #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
  3423. #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
  3424. #define MR_LP_ADV_NEXT_PAGE 0x00001000
  3425. #define MR_TOGGLE_RX 0x00002000
  3426. #define MR_NP_RX 0x00004000
  3427. #define MR_LINK_OK 0x80000000
  3428. unsigned long link_time, cur_time;
  3429. u32 ability_match_cfg;
  3430. int ability_match_count;
  3431. char ability_match, idle_match, ack_match;
  3432. u32 txconfig, rxconfig;
  3433. #define ANEG_CFG_NP 0x00000080
  3434. #define ANEG_CFG_ACK 0x00000040
  3435. #define ANEG_CFG_RF2 0x00000020
  3436. #define ANEG_CFG_RF1 0x00000010
  3437. #define ANEG_CFG_PS2 0x00000001
  3438. #define ANEG_CFG_PS1 0x00008000
  3439. #define ANEG_CFG_HD 0x00004000
  3440. #define ANEG_CFG_FD 0x00002000
  3441. #define ANEG_CFG_INVAL 0x00001f06
  3442. };
  3443. #define ANEG_OK 0
  3444. #define ANEG_DONE 1
  3445. #define ANEG_TIMER_ENAB 2
  3446. #define ANEG_FAILED -1
  3447. #define ANEG_STATE_SETTLE_TIME 10000
  3448. static int tg3_fiber_aneg_smachine(struct tg3 *tp,
  3449. struct tg3_fiber_aneginfo *ap)
  3450. {
  3451. u16 flowctrl;
  3452. unsigned long delta;
  3453. u32 rx_cfg_reg;
  3454. int ret;
  3455. if (ap->state == ANEG_STATE_UNKNOWN) {
  3456. ap->rxconfig = 0;
  3457. ap->link_time = 0;
  3458. ap->cur_time = 0;
  3459. ap->ability_match_cfg = 0;
  3460. ap->ability_match_count = 0;
  3461. ap->ability_match = 0;
  3462. ap->idle_match = 0;
  3463. ap->ack_match = 0;
  3464. }
  3465. ap->cur_time++;
  3466. if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
  3467. rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
  3468. if (rx_cfg_reg != ap->ability_match_cfg) {
  3469. ap->ability_match_cfg = rx_cfg_reg;
  3470. ap->ability_match = 0;
  3471. ap->ability_match_count = 0;
  3472. } else {
  3473. if (++ap->ability_match_count > 1) {
  3474. ap->ability_match = 1;
  3475. ap->ability_match_cfg = rx_cfg_reg;
  3476. }
  3477. }
  3478. if (rx_cfg_reg & ANEG_CFG_ACK)
  3479. ap->ack_match = 1;
  3480. else
  3481. ap->ack_match = 0;
  3482. ap->idle_match = 0;
  3483. } else {
  3484. ap->idle_match = 1;
  3485. ap->ability_match_cfg = 0;
  3486. ap->ability_match_count = 0;
  3487. ap->ability_match = 0;
  3488. ap->ack_match = 0;
  3489. rx_cfg_reg = 0;
  3490. }
  3491. ap->rxconfig = rx_cfg_reg;
  3492. ret = ANEG_OK;
  3493. switch (ap->state) {
  3494. case ANEG_STATE_UNKNOWN:
  3495. if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
  3496. ap->state = ANEG_STATE_AN_ENABLE;
  3497. /* fallthru */
  3498. case ANEG_STATE_AN_ENABLE:
  3499. ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
  3500. if (ap->flags & MR_AN_ENABLE) {
  3501. ap->link_time = 0;
  3502. ap->cur_time = 0;
  3503. ap->ability_match_cfg = 0;
  3504. ap->ability_match_count = 0;
  3505. ap->ability_match = 0;
  3506. ap->idle_match = 0;
  3507. ap->ack_match = 0;
  3508. ap->state = ANEG_STATE_RESTART_INIT;
  3509. } else {
  3510. ap->state = ANEG_STATE_DISABLE_LINK_OK;
  3511. }
  3512. break;
  3513. case ANEG_STATE_RESTART_INIT:
  3514. ap->link_time = ap->cur_time;
  3515. ap->flags &= ~(MR_NP_LOADED);
  3516. ap->txconfig = 0;
  3517. tw32(MAC_TX_AUTO_NEG, 0);
  3518. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  3519. tw32_f(MAC_MODE, tp->mac_mode);
  3520. udelay(40);
  3521. ret = ANEG_TIMER_ENAB;
  3522. ap->state = ANEG_STATE_RESTART;
  3523. /* fallthru */
  3524. case ANEG_STATE_RESTART:
  3525. delta = ap->cur_time - ap->link_time;
  3526. if (delta > ANEG_STATE_SETTLE_TIME)
  3527. ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
  3528. else
  3529. ret = ANEG_TIMER_ENAB;
  3530. break;
  3531. case ANEG_STATE_DISABLE_LINK_OK:
  3532. ret = ANEG_DONE;
  3533. break;
  3534. case ANEG_STATE_ABILITY_DETECT_INIT:
  3535. ap->flags &= ~(MR_TOGGLE_TX);
  3536. ap->txconfig = ANEG_CFG_FD;
  3537. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  3538. if (flowctrl & ADVERTISE_1000XPAUSE)
  3539. ap->txconfig |= ANEG_CFG_PS1;
  3540. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  3541. ap->txconfig |= ANEG_CFG_PS2;
  3542. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  3543. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  3544. tw32_f(MAC_MODE, tp->mac_mode);
  3545. udelay(40);
  3546. ap->state = ANEG_STATE_ABILITY_DETECT;
  3547. break;
  3548. case ANEG_STATE_ABILITY_DETECT:
  3549. if (ap->ability_match != 0 && ap->rxconfig != 0)
  3550. ap->state = ANEG_STATE_ACK_DETECT_INIT;
  3551. break;
  3552. case ANEG_STATE_ACK_DETECT_INIT:
  3553. ap->txconfig |= ANEG_CFG_ACK;
  3554. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  3555. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  3556. tw32_f(MAC_MODE, tp->mac_mode);
  3557. udelay(40);
  3558. ap->state = ANEG_STATE_ACK_DETECT;
  3559. /* fallthru */
  3560. case ANEG_STATE_ACK_DETECT:
  3561. if (ap->ack_match != 0) {
  3562. if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
  3563. (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
  3564. ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
  3565. } else {
  3566. ap->state = ANEG_STATE_AN_ENABLE;
  3567. }
  3568. } else if (ap->ability_match != 0 &&
  3569. ap->rxconfig == 0) {
  3570. ap->state = ANEG_STATE_AN_ENABLE;
  3571. }
  3572. break;
  3573. case ANEG_STATE_COMPLETE_ACK_INIT:
  3574. if (ap->rxconfig & ANEG_CFG_INVAL) {
  3575. ret = ANEG_FAILED;
  3576. break;
  3577. }
  3578. ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
  3579. MR_LP_ADV_HALF_DUPLEX |
  3580. MR_LP_ADV_SYM_PAUSE |
  3581. MR_LP_ADV_ASYM_PAUSE |
  3582. MR_LP_ADV_REMOTE_FAULT1 |
  3583. MR_LP_ADV_REMOTE_FAULT2 |
  3584. MR_LP_ADV_NEXT_PAGE |
  3585. MR_TOGGLE_RX |
  3586. MR_NP_RX);
  3587. if (ap->rxconfig & ANEG_CFG_FD)
  3588. ap->flags |= MR_LP_ADV_FULL_DUPLEX;
  3589. if (ap->rxconfig & ANEG_CFG_HD)
  3590. ap->flags |= MR_LP_ADV_HALF_DUPLEX;
  3591. if (ap->rxconfig & ANEG_CFG_PS1)
  3592. ap->flags |= MR_LP_ADV_SYM_PAUSE;
  3593. if (ap->rxconfig & ANEG_CFG_PS2)
  3594. ap->flags |= MR_LP_ADV_ASYM_PAUSE;
  3595. if (ap->rxconfig & ANEG_CFG_RF1)
  3596. ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
  3597. if (ap->rxconfig & ANEG_CFG_RF2)
  3598. ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
  3599. if (ap->rxconfig & ANEG_CFG_NP)
  3600. ap->flags |= MR_LP_ADV_NEXT_PAGE;
  3601. ap->link_time = ap->cur_time;
  3602. ap->flags ^= (MR_TOGGLE_TX);
  3603. if (ap->rxconfig & 0x0008)
  3604. ap->flags |= MR_TOGGLE_RX;
  3605. if (ap->rxconfig & ANEG_CFG_NP)
  3606. ap->flags |= MR_NP_RX;
  3607. ap->flags |= MR_PAGE_RX;
  3608. ap->state = ANEG_STATE_COMPLETE_ACK;
  3609. ret = ANEG_TIMER_ENAB;
  3610. break;
  3611. case ANEG_STATE_COMPLETE_ACK:
  3612. if (ap->ability_match != 0 &&
  3613. ap->rxconfig == 0) {
  3614. ap->state = ANEG_STATE_AN_ENABLE;
  3615. break;
  3616. }
  3617. delta = ap->cur_time - ap->link_time;
  3618. if (delta > ANEG_STATE_SETTLE_TIME) {
  3619. if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
  3620. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  3621. } else {
  3622. if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
  3623. !(ap->flags & MR_NP_RX)) {
  3624. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  3625. } else {
  3626. ret = ANEG_FAILED;
  3627. }
  3628. }
  3629. }
  3630. break;
  3631. case ANEG_STATE_IDLE_DETECT_INIT:
  3632. ap->link_time = ap->cur_time;
  3633. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  3634. tw32_f(MAC_MODE, tp->mac_mode);
  3635. udelay(40);
  3636. ap->state = ANEG_STATE_IDLE_DETECT;
  3637. ret = ANEG_TIMER_ENAB;
  3638. break;
  3639. case ANEG_STATE_IDLE_DETECT:
  3640. if (ap->ability_match != 0 &&
  3641. ap->rxconfig == 0) {
  3642. ap->state = ANEG_STATE_AN_ENABLE;
  3643. break;
  3644. }
  3645. delta = ap->cur_time - ap->link_time;
  3646. if (delta > ANEG_STATE_SETTLE_TIME) {
  3647. /* XXX another gem from the Broadcom driver :( */
  3648. ap->state = ANEG_STATE_LINK_OK;
  3649. }
  3650. break;
  3651. case ANEG_STATE_LINK_OK:
  3652. ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
  3653. ret = ANEG_DONE;
  3654. break;
  3655. case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
  3656. /* ??? unimplemented */
  3657. break;
  3658. case ANEG_STATE_NEXT_PAGE_WAIT:
  3659. /* ??? unimplemented */
  3660. break;
  3661. default:
  3662. ret = ANEG_FAILED;
  3663. break;
  3664. }
  3665. return ret;
  3666. }
  3667. static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
  3668. {
  3669. int res = 0;
  3670. struct tg3_fiber_aneginfo aninfo;
  3671. int status = ANEG_FAILED;
  3672. unsigned int tick;
  3673. u32 tmp;
  3674. tw32_f(MAC_TX_AUTO_NEG, 0);
  3675. tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  3676. tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
  3677. udelay(40);
  3678. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
  3679. udelay(40);
  3680. memset(&aninfo, 0, sizeof(aninfo));
  3681. aninfo.flags |= MR_AN_ENABLE;
  3682. aninfo.state = ANEG_STATE_UNKNOWN;
  3683. aninfo.cur_time = 0;
  3684. tick = 0;
  3685. while (++tick < 195000) {
  3686. status = tg3_fiber_aneg_smachine(tp, &aninfo);
  3687. if (status == ANEG_DONE || status == ANEG_FAILED)
  3688. break;
  3689. udelay(1);
  3690. }
  3691. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  3692. tw32_f(MAC_MODE, tp->mac_mode);
  3693. udelay(40);
  3694. *txflags = aninfo.txconfig;
  3695. *rxflags = aninfo.flags;
  3696. if (status == ANEG_DONE &&
  3697. (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
  3698. MR_LP_ADV_FULL_DUPLEX)))
  3699. res = 1;
  3700. return res;
  3701. }
  3702. static void tg3_init_bcm8002(struct tg3 *tp)
  3703. {
  3704. u32 mac_status = tr32(MAC_STATUS);
  3705. int i;
  3706. /* Reset when initting first time or we have a link. */
  3707. if (tg3_flag(tp, INIT_COMPLETE) &&
  3708. !(mac_status & MAC_STATUS_PCS_SYNCED))
  3709. return;
  3710. /* Set PLL lock range. */
  3711. tg3_writephy(tp, 0x16, 0x8007);
  3712. /* SW reset */
  3713. tg3_writephy(tp, MII_BMCR, BMCR_RESET);
  3714. /* Wait for reset to complete. */
  3715. /* XXX schedule_timeout() ... */
  3716. for (i = 0; i < 500; i++)
  3717. udelay(10);
  3718. /* Config mode; select PMA/Ch 1 regs. */
  3719. tg3_writephy(tp, 0x10, 0x8411);
  3720. /* Enable auto-lock and comdet, select txclk for tx. */
  3721. tg3_writephy(tp, 0x11, 0x0a10);
  3722. tg3_writephy(tp, 0x18, 0x00a0);
  3723. tg3_writephy(tp, 0x16, 0x41ff);
  3724. /* Assert and deassert POR. */
  3725. tg3_writephy(tp, 0x13, 0x0400);
  3726. udelay(40);
  3727. tg3_writephy(tp, 0x13, 0x0000);
  3728. tg3_writephy(tp, 0x11, 0x0a50);
  3729. udelay(40);
  3730. tg3_writephy(tp, 0x11, 0x0a10);
  3731. /* Wait for signal to stabilize */
  3732. /* XXX schedule_timeout() ... */
  3733. for (i = 0; i < 15000; i++)
  3734. udelay(10);
  3735. /* Deselect the channel register so we can read the PHYID
  3736. * later.
  3737. */
  3738. tg3_writephy(tp, 0x10, 0x8011);
  3739. }
  3740. static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
  3741. {
  3742. u16 flowctrl;
  3743. u32 sg_dig_ctrl, sg_dig_status;
  3744. u32 serdes_cfg, expected_sg_dig_ctrl;
  3745. int workaround, port_a;
  3746. int current_link_up;
  3747. serdes_cfg = 0;
  3748. expected_sg_dig_ctrl = 0;
  3749. workaround = 0;
  3750. port_a = 1;
  3751. current_link_up = 0;
  3752. if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
  3753. tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
  3754. workaround = 1;
  3755. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  3756. port_a = 0;
  3757. /* preserve bits 0-11,13,14 for signal pre-emphasis */
  3758. /* preserve bits 20-23 for voltage regulator */
  3759. serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
  3760. }
  3761. sg_dig_ctrl = tr32(SG_DIG_CTRL);
  3762. if (tp->link_config.autoneg != AUTONEG_ENABLE) {
  3763. if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
  3764. if (workaround) {
  3765. u32 val = serdes_cfg;
  3766. if (port_a)
  3767. val |= 0xc010000;
  3768. else
  3769. val |= 0x4010000;
  3770. tw32_f(MAC_SERDES_CFG, val);
  3771. }
  3772. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  3773. }
  3774. if (mac_status & MAC_STATUS_PCS_SYNCED) {
  3775. tg3_setup_flow_control(tp, 0, 0);
  3776. current_link_up = 1;
  3777. }
  3778. goto out;
  3779. }
  3780. /* Want auto-negotiation. */
  3781. expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
  3782. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  3783. if (flowctrl & ADVERTISE_1000XPAUSE)
  3784. expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
  3785. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  3786. expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
  3787. if (sg_dig_ctrl != expected_sg_dig_ctrl) {
  3788. if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
  3789. tp->serdes_counter &&
  3790. ((mac_status & (MAC_STATUS_PCS_SYNCED |
  3791. MAC_STATUS_RCVD_CFG)) ==
  3792. MAC_STATUS_PCS_SYNCED)) {
  3793. tp->serdes_counter--;
  3794. current_link_up = 1;
  3795. goto out;
  3796. }
  3797. restart_autoneg:
  3798. if (workaround)
  3799. tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
  3800. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
  3801. udelay(5);
  3802. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
  3803. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  3804. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3805. } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
  3806. MAC_STATUS_SIGNAL_DET)) {
  3807. sg_dig_status = tr32(SG_DIG_STATUS);
  3808. mac_status = tr32(MAC_STATUS);
  3809. if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
  3810. (mac_status & MAC_STATUS_PCS_SYNCED)) {
  3811. u32 local_adv = 0, remote_adv = 0;
  3812. if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
  3813. local_adv |= ADVERTISE_1000XPAUSE;
  3814. if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
  3815. local_adv |= ADVERTISE_1000XPSE_ASYM;
  3816. if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
  3817. remote_adv |= LPA_1000XPAUSE;
  3818. if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
  3819. remote_adv |= LPA_1000XPAUSE_ASYM;
  3820. tg3_setup_flow_control(tp, local_adv, remote_adv);
  3821. current_link_up = 1;
  3822. tp->serdes_counter = 0;
  3823. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3824. } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
  3825. if (tp->serdes_counter)
  3826. tp->serdes_counter--;
  3827. else {
  3828. if (workaround) {
  3829. u32 val = serdes_cfg;
  3830. if (port_a)
  3831. val |= 0xc010000;
  3832. else
  3833. val |= 0x4010000;
  3834. tw32_f(MAC_SERDES_CFG, val);
  3835. }
  3836. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  3837. udelay(40);
  3838. /* Link parallel detection - link is up */
  3839. /* only if we have PCS_SYNC and not */
  3840. /* receiving config code words */
  3841. mac_status = tr32(MAC_STATUS);
  3842. if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
  3843. !(mac_status & MAC_STATUS_RCVD_CFG)) {
  3844. tg3_setup_flow_control(tp, 0, 0);
  3845. current_link_up = 1;
  3846. tp->phy_flags |=
  3847. TG3_PHYFLG_PARALLEL_DETECT;
  3848. tp->serdes_counter =
  3849. SERDES_PARALLEL_DET_TIMEOUT;
  3850. } else
  3851. goto restart_autoneg;
  3852. }
  3853. }
  3854. } else {
  3855. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  3856. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3857. }
  3858. out:
  3859. return current_link_up;
  3860. }
  3861. static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
  3862. {
  3863. int current_link_up = 0;
  3864. if (!(mac_status & MAC_STATUS_PCS_SYNCED))
  3865. goto out;
  3866. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  3867. u32 txflags, rxflags;
  3868. int i;
  3869. if (fiber_autoneg(tp, &txflags, &rxflags)) {
  3870. u32 local_adv = 0, remote_adv = 0;
  3871. if (txflags & ANEG_CFG_PS1)
  3872. local_adv |= ADVERTISE_1000XPAUSE;
  3873. if (txflags & ANEG_CFG_PS2)
  3874. local_adv |= ADVERTISE_1000XPSE_ASYM;
  3875. if (rxflags & MR_LP_ADV_SYM_PAUSE)
  3876. remote_adv |= LPA_1000XPAUSE;
  3877. if (rxflags & MR_LP_ADV_ASYM_PAUSE)
  3878. remote_adv |= LPA_1000XPAUSE_ASYM;
  3879. tg3_setup_flow_control(tp, local_adv, remote_adv);
  3880. current_link_up = 1;
  3881. }
  3882. for (i = 0; i < 30; i++) {
  3883. udelay(20);
  3884. tw32_f(MAC_STATUS,
  3885. (MAC_STATUS_SYNC_CHANGED |
  3886. MAC_STATUS_CFG_CHANGED));
  3887. udelay(40);
  3888. if ((tr32(MAC_STATUS) &
  3889. (MAC_STATUS_SYNC_CHANGED |
  3890. MAC_STATUS_CFG_CHANGED)) == 0)
  3891. break;
  3892. }
  3893. mac_status = tr32(MAC_STATUS);
  3894. if (current_link_up == 0 &&
  3895. (mac_status & MAC_STATUS_PCS_SYNCED) &&
  3896. !(mac_status & MAC_STATUS_RCVD_CFG))
  3897. current_link_up = 1;
  3898. } else {
  3899. tg3_setup_flow_control(tp, 0, 0);
  3900. /* Forcing 1000FD link up. */
  3901. current_link_up = 1;
  3902. tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
  3903. udelay(40);
  3904. tw32_f(MAC_MODE, tp->mac_mode);
  3905. udelay(40);
  3906. }
  3907. out:
  3908. return current_link_up;
  3909. }
  3910. static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
  3911. {
  3912. u32 orig_pause_cfg;
  3913. u16 orig_active_speed;
  3914. u8 orig_active_duplex;
  3915. u32 mac_status;
  3916. int current_link_up;
  3917. int i;
  3918. orig_pause_cfg = tp->link_config.active_flowctrl;
  3919. orig_active_speed = tp->link_config.active_speed;
  3920. orig_active_duplex = tp->link_config.active_duplex;
  3921. if (!tg3_flag(tp, HW_AUTONEG) &&
  3922. netif_carrier_ok(tp->dev) &&
  3923. tg3_flag(tp, INIT_COMPLETE)) {
  3924. mac_status = tr32(MAC_STATUS);
  3925. mac_status &= (MAC_STATUS_PCS_SYNCED |
  3926. MAC_STATUS_SIGNAL_DET |
  3927. MAC_STATUS_CFG_CHANGED |
  3928. MAC_STATUS_RCVD_CFG);
  3929. if (mac_status == (MAC_STATUS_PCS_SYNCED |
  3930. MAC_STATUS_SIGNAL_DET)) {
  3931. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  3932. MAC_STATUS_CFG_CHANGED));
  3933. return 0;
  3934. }
  3935. }
  3936. tw32_f(MAC_TX_AUTO_NEG, 0);
  3937. tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  3938. tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
  3939. tw32_f(MAC_MODE, tp->mac_mode);
  3940. udelay(40);
  3941. if (tp->phy_id == TG3_PHY_ID_BCM8002)
  3942. tg3_init_bcm8002(tp);
  3943. /* Enable link change event even when serdes polling. */
  3944. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  3945. udelay(40);
  3946. current_link_up = 0;
  3947. mac_status = tr32(MAC_STATUS);
  3948. if (tg3_flag(tp, HW_AUTONEG))
  3949. current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
  3950. else
  3951. current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
  3952. tp->napi[0].hw_status->status =
  3953. (SD_STATUS_UPDATED |
  3954. (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
  3955. for (i = 0; i < 100; i++) {
  3956. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  3957. MAC_STATUS_CFG_CHANGED));
  3958. udelay(5);
  3959. if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
  3960. MAC_STATUS_CFG_CHANGED |
  3961. MAC_STATUS_LNKSTATE_CHANGED)) == 0)
  3962. break;
  3963. }
  3964. mac_status = tr32(MAC_STATUS);
  3965. if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
  3966. current_link_up = 0;
  3967. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  3968. tp->serdes_counter == 0) {
  3969. tw32_f(MAC_MODE, (tp->mac_mode |
  3970. MAC_MODE_SEND_CONFIGS));
  3971. udelay(1);
  3972. tw32_f(MAC_MODE, tp->mac_mode);
  3973. }
  3974. }
  3975. if (current_link_up == 1) {
  3976. tp->link_config.active_speed = SPEED_1000;
  3977. tp->link_config.active_duplex = DUPLEX_FULL;
  3978. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  3979. LED_CTRL_LNKLED_OVERRIDE |
  3980. LED_CTRL_1000MBPS_ON));
  3981. } else {
  3982. tp->link_config.active_speed = SPEED_INVALID;
  3983. tp->link_config.active_duplex = DUPLEX_INVALID;
  3984. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  3985. LED_CTRL_LNKLED_OVERRIDE |
  3986. LED_CTRL_TRAFFIC_OVERRIDE));
  3987. }
  3988. if (current_link_up != netif_carrier_ok(tp->dev)) {
  3989. if (current_link_up)
  3990. netif_carrier_on(tp->dev);
  3991. else
  3992. netif_carrier_off(tp->dev);
  3993. tg3_link_report(tp);
  3994. } else {
  3995. u32 now_pause_cfg = tp->link_config.active_flowctrl;
  3996. if (orig_pause_cfg != now_pause_cfg ||
  3997. orig_active_speed != tp->link_config.active_speed ||
  3998. orig_active_duplex != tp->link_config.active_duplex)
  3999. tg3_link_report(tp);
  4000. }
  4001. return 0;
  4002. }
  4003. static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
  4004. {
  4005. int current_link_up, err = 0;
  4006. u32 bmsr, bmcr;
  4007. u16 current_speed;
  4008. u8 current_duplex;
  4009. u32 local_adv, remote_adv;
  4010. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  4011. tw32_f(MAC_MODE, tp->mac_mode);
  4012. udelay(40);
  4013. tw32(MAC_EVENT, 0);
  4014. tw32_f(MAC_STATUS,
  4015. (MAC_STATUS_SYNC_CHANGED |
  4016. MAC_STATUS_CFG_CHANGED |
  4017. MAC_STATUS_MI_COMPLETION |
  4018. MAC_STATUS_LNKSTATE_CHANGED));
  4019. udelay(40);
  4020. if (force_reset)
  4021. tg3_phy_reset(tp);
  4022. current_link_up = 0;
  4023. current_speed = SPEED_INVALID;
  4024. current_duplex = DUPLEX_INVALID;
  4025. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4026. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4027. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  4028. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  4029. bmsr |= BMSR_LSTATUS;
  4030. else
  4031. bmsr &= ~BMSR_LSTATUS;
  4032. }
  4033. err |= tg3_readphy(tp, MII_BMCR, &bmcr);
  4034. if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
  4035. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
  4036. /* do nothing, just check for link up at the end */
  4037. } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  4038. u32 adv, newadv;
  4039. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  4040. newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
  4041. ADVERTISE_1000XPAUSE |
  4042. ADVERTISE_1000XPSE_ASYM |
  4043. ADVERTISE_SLCT);
  4044. newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  4045. newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
  4046. if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
  4047. tg3_writephy(tp, MII_ADVERTISE, newadv);
  4048. bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
  4049. tg3_writephy(tp, MII_BMCR, bmcr);
  4050. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4051. tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
  4052. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4053. return err;
  4054. }
  4055. } else {
  4056. u32 new_bmcr;
  4057. bmcr &= ~BMCR_SPEED1000;
  4058. new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
  4059. if (tp->link_config.duplex == DUPLEX_FULL)
  4060. new_bmcr |= BMCR_FULLDPLX;
  4061. if (new_bmcr != bmcr) {
  4062. /* BMCR_SPEED1000 is a reserved bit that needs
  4063. * to be set on write.
  4064. */
  4065. new_bmcr |= BMCR_SPEED1000;
  4066. /* Force a linkdown */
  4067. if (netif_carrier_ok(tp->dev)) {
  4068. u32 adv;
  4069. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  4070. adv &= ~(ADVERTISE_1000XFULL |
  4071. ADVERTISE_1000XHALF |
  4072. ADVERTISE_SLCT);
  4073. tg3_writephy(tp, MII_ADVERTISE, adv);
  4074. tg3_writephy(tp, MII_BMCR, bmcr |
  4075. BMCR_ANRESTART |
  4076. BMCR_ANENABLE);
  4077. udelay(10);
  4078. netif_carrier_off(tp->dev);
  4079. }
  4080. tg3_writephy(tp, MII_BMCR, new_bmcr);
  4081. bmcr = new_bmcr;
  4082. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4083. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4084. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  4085. ASIC_REV_5714) {
  4086. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  4087. bmsr |= BMSR_LSTATUS;
  4088. else
  4089. bmsr &= ~BMSR_LSTATUS;
  4090. }
  4091. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4092. }
  4093. }
  4094. if (bmsr & BMSR_LSTATUS) {
  4095. current_speed = SPEED_1000;
  4096. current_link_up = 1;
  4097. if (bmcr & BMCR_FULLDPLX)
  4098. current_duplex = DUPLEX_FULL;
  4099. else
  4100. current_duplex = DUPLEX_HALF;
  4101. local_adv = 0;
  4102. remote_adv = 0;
  4103. if (bmcr & BMCR_ANENABLE) {
  4104. u32 common;
  4105. err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
  4106. err |= tg3_readphy(tp, MII_LPA, &remote_adv);
  4107. common = local_adv & remote_adv;
  4108. if (common & (ADVERTISE_1000XHALF |
  4109. ADVERTISE_1000XFULL)) {
  4110. if (common & ADVERTISE_1000XFULL)
  4111. current_duplex = DUPLEX_FULL;
  4112. else
  4113. current_duplex = DUPLEX_HALF;
  4114. } else if (!tg3_flag(tp, 5780_CLASS)) {
  4115. /* Link is up via parallel detect */
  4116. } else {
  4117. current_link_up = 0;
  4118. }
  4119. }
  4120. }
  4121. if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
  4122. tg3_setup_flow_control(tp, local_adv, remote_adv);
  4123. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  4124. if (tp->link_config.active_duplex == DUPLEX_HALF)
  4125. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  4126. tw32_f(MAC_MODE, tp->mac_mode);
  4127. udelay(40);
  4128. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4129. tp->link_config.active_speed = current_speed;
  4130. tp->link_config.active_duplex = current_duplex;
  4131. if (current_link_up != netif_carrier_ok(tp->dev)) {
  4132. if (current_link_up)
  4133. netif_carrier_on(tp->dev);
  4134. else {
  4135. netif_carrier_off(tp->dev);
  4136. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4137. }
  4138. tg3_link_report(tp);
  4139. }
  4140. return err;
  4141. }
  4142. static void tg3_serdes_parallel_detect(struct tg3 *tp)
  4143. {
  4144. if (tp->serdes_counter) {
  4145. /* Give autoneg time to complete. */
  4146. tp->serdes_counter--;
  4147. return;
  4148. }
  4149. if (!netif_carrier_ok(tp->dev) &&
  4150. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  4151. u32 bmcr;
  4152. tg3_readphy(tp, MII_BMCR, &bmcr);
  4153. if (bmcr & BMCR_ANENABLE) {
  4154. u32 phy1, phy2;
  4155. /* Select shadow register 0x1f */
  4156. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
  4157. tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
  4158. /* Select expansion interrupt status register */
  4159. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  4160. MII_TG3_DSP_EXP1_INT_STAT);
  4161. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  4162. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  4163. if ((phy1 & 0x10) && !(phy2 & 0x20)) {
  4164. /* We have signal detect and not receiving
  4165. * config code words, link is up by parallel
  4166. * detection.
  4167. */
  4168. bmcr &= ~BMCR_ANENABLE;
  4169. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  4170. tg3_writephy(tp, MII_BMCR, bmcr);
  4171. tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
  4172. }
  4173. }
  4174. } else if (netif_carrier_ok(tp->dev) &&
  4175. (tp->link_config.autoneg == AUTONEG_ENABLE) &&
  4176. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
  4177. u32 phy2;
  4178. /* Select expansion interrupt status register */
  4179. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  4180. MII_TG3_DSP_EXP1_INT_STAT);
  4181. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  4182. if (phy2 & 0x20) {
  4183. u32 bmcr;
  4184. /* Config code words received, turn on autoneg. */
  4185. tg3_readphy(tp, MII_BMCR, &bmcr);
  4186. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
  4187. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4188. }
  4189. }
  4190. }
  4191. static int tg3_setup_phy(struct tg3 *tp, int force_reset)
  4192. {
  4193. u32 val;
  4194. int err;
  4195. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  4196. err = tg3_setup_fiber_phy(tp, force_reset);
  4197. else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  4198. err = tg3_setup_fiber_mii_phy(tp, force_reset);
  4199. else
  4200. err = tg3_setup_copper_phy(tp, force_reset);
  4201. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
  4202. u32 scale;
  4203. val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
  4204. if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
  4205. scale = 65;
  4206. else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
  4207. scale = 6;
  4208. else
  4209. scale = 12;
  4210. val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
  4211. val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
  4212. tw32(GRC_MISC_CFG, val);
  4213. }
  4214. val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  4215. (6 << TX_LENGTHS_IPG_SHIFT);
  4216. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
  4217. val |= tr32(MAC_TX_LENGTHS) &
  4218. (TX_LENGTHS_JMB_FRM_LEN_MSK |
  4219. TX_LENGTHS_CNT_DWN_VAL_MSK);
  4220. if (tp->link_config.active_speed == SPEED_1000 &&
  4221. tp->link_config.active_duplex == DUPLEX_HALF)
  4222. tw32(MAC_TX_LENGTHS, val |
  4223. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
  4224. else
  4225. tw32(MAC_TX_LENGTHS, val |
  4226. (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
  4227. if (!tg3_flag(tp, 5705_PLUS)) {
  4228. if (netif_carrier_ok(tp->dev)) {
  4229. tw32(HOSTCC_STAT_COAL_TICKS,
  4230. tp->coal.stats_block_coalesce_usecs);
  4231. } else {
  4232. tw32(HOSTCC_STAT_COAL_TICKS, 0);
  4233. }
  4234. }
  4235. if (tg3_flag(tp, ASPM_WORKAROUND)) {
  4236. val = tr32(PCIE_PWR_MGMT_THRESH);
  4237. if (!netif_carrier_ok(tp->dev))
  4238. val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
  4239. tp->pwrmgmt_thresh;
  4240. else
  4241. val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
  4242. tw32(PCIE_PWR_MGMT_THRESH, val);
  4243. }
  4244. return err;
  4245. }
  4246. static inline int tg3_irq_sync(struct tg3 *tp)
  4247. {
  4248. return tp->irq_sync;
  4249. }
  4250. static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
  4251. {
  4252. int i;
  4253. dst = (u32 *)((u8 *)dst + off);
  4254. for (i = 0; i < len; i += sizeof(u32))
  4255. *dst++ = tr32(off + i);
  4256. }
  4257. static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
  4258. {
  4259. tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
  4260. tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
  4261. tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
  4262. tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
  4263. tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
  4264. tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
  4265. tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
  4266. tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
  4267. tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
  4268. tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
  4269. tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
  4270. tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
  4271. tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
  4272. tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
  4273. tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
  4274. tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
  4275. tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
  4276. tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
  4277. tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
  4278. if (tg3_flag(tp, SUPPORT_MSIX))
  4279. tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
  4280. tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
  4281. tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
  4282. tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
  4283. tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
  4284. tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
  4285. tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
  4286. tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
  4287. tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
  4288. if (!tg3_flag(tp, 5705_PLUS)) {
  4289. tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
  4290. tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
  4291. tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
  4292. }
  4293. tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
  4294. tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
  4295. tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
  4296. tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
  4297. tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
  4298. if (tg3_flag(tp, NVRAM))
  4299. tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
  4300. }
  4301. static void tg3_dump_state(struct tg3 *tp)
  4302. {
  4303. int i;
  4304. u32 *regs;
  4305. regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
  4306. if (!regs) {
  4307. netdev_err(tp->dev, "Failed allocating register dump buffer\n");
  4308. return;
  4309. }
  4310. if (tg3_flag(tp, PCI_EXPRESS)) {
  4311. /* Read up to but not including private PCI registers */
  4312. for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
  4313. regs[i / sizeof(u32)] = tr32(i);
  4314. } else
  4315. tg3_dump_legacy_regs(tp, regs);
  4316. for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
  4317. if (!regs[i + 0] && !regs[i + 1] &&
  4318. !regs[i + 2] && !regs[i + 3])
  4319. continue;
  4320. netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
  4321. i * 4,
  4322. regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
  4323. }
  4324. kfree(regs);
  4325. for (i = 0; i < tp->irq_cnt; i++) {
  4326. struct tg3_napi *tnapi = &tp->napi[i];
  4327. /* SW status block */
  4328. netdev_err(tp->dev,
  4329. "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
  4330. i,
  4331. tnapi->hw_status->status,
  4332. tnapi->hw_status->status_tag,
  4333. tnapi->hw_status->rx_jumbo_consumer,
  4334. tnapi->hw_status->rx_consumer,
  4335. tnapi->hw_status->rx_mini_consumer,
  4336. tnapi->hw_status->idx[0].rx_producer,
  4337. tnapi->hw_status->idx[0].tx_consumer);
  4338. netdev_err(tp->dev,
  4339. "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
  4340. i,
  4341. tnapi->last_tag, tnapi->last_irq_tag,
  4342. tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
  4343. tnapi->rx_rcb_ptr,
  4344. tnapi->prodring.rx_std_prod_idx,
  4345. tnapi->prodring.rx_std_cons_idx,
  4346. tnapi->prodring.rx_jmb_prod_idx,
  4347. tnapi->prodring.rx_jmb_cons_idx);
  4348. }
  4349. }
  4350. /* This is called whenever we suspect that the system chipset is re-
  4351. * ordering the sequence of MMIO to the tx send mailbox. The symptom
  4352. * is bogus tx completions. We try to recover by setting the
  4353. * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
  4354. * in the workqueue.
  4355. */
  4356. static void tg3_tx_recover(struct tg3 *tp)
  4357. {
  4358. BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
  4359. tp->write32_tx_mbox == tg3_write_indirect_mbox);
  4360. netdev_warn(tp->dev,
  4361. "The system may be re-ordering memory-mapped I/O "
  4362. "cycles to the network device, attempting to recover. "
  4363. "Please report the problem to the driver maintainer "
  4364. "and include system chipset information.\n");
  4365. spin_lock(&tp->lock);
  4366. tg3_flag_set(tp, TX_RECOVERY_PENDING);
  4367. spin_unlock(&tp->lock);
  4368. }
  4369. static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
  4370. {
  4371. /* Tell compiler to fetch tx indices from memory. */
  4372. barrier();
  4373. return tnapi->tx_pending -
  4374. ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
  4375. }
  4376. /* Tigon3 never reports partial packet sends. So we do not
  4377. * need special logic to handle SKBs that have not had all
  4378. * of their frags sent yet, like SunGEM does.
  4379. */
  4380. static void tg3_tx(struct tg3_napi *tnapi)
  4381. {
  4382. struct tg3 *tp = tnapi->tp;
  4383. u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
  4384. u32 sw_idx = tnapi->tx_cons;
  4385. struct netdev_queue *txq;
  4386. int index = tnapi - tp->napi;
  4387. if (tg3_flag(tp, ENABLE_TSS))
  4388. index--;
  4389. txq = netdev_get_tx_queue(tp->dev, index);
  4390. while (sw_idx != hw_idx) {
  4391. struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
  4392. struct sk_buff *skb = ri->skb;
  4393. int i, tx_bug = 0;
  4394. if (unlikely(skb == NULL)) {
  4395. tg3_tx_recover(tp);
  4396. return;
  4397. }
  4398. pci_unmap_single(tp->pdev,
  4399. dma_unmap_addr(ri, mapping),
  4400. skb_headlen(skb),
  4401. PCI_DMA_TODEVICE);
  4402. ri->skb = NULL;
  4403. while (ri->fragmented) {
  4404. ri->fragmented = false;
  4405. sw_idx = NEXT_TX(sw_idx);
  4406. ri = &tnapi->tx_buffers[sw_idx];
  4407. }
  4408. sw_idx = NEXT_TX(sw_idx);
  4409. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  4410. ri = &tnapi->tx_buffers[sw_idx];
  4411. if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
  4412. tx_bug = 1;
  4413. pci_unmap_page(tp->pdev,
  4414. dma_unmap_addr(ri, mapping),
  4415. skb_frag_size(&skb_shinfo(skb)->frags[i]),
  4416. PCI_DMA_TODEVICE);
  4417. while (ri->fragmented) {
  4418. ri->fragmented = false;
  4419. sw_idx = NEXT_TX(sw_idx);
  4420. ri = &tnapi->tx_buffers[sw_idx];
  4421. }
  4422. sw_idx = NEXT_TX(sw_idx);
  4423. }
  4424. dev_kfree_skb(skb);
  4425. if (unlikely(tx_bug)) {
  4426. tg3_tx_recover(tp);
  4427. return;
  4428. }
  4429. }
  4430. tnapi->tx_cons = sw_idx;
  4431. /* Need to make the tx_cons update visible to tg3_start_xmit()
  4432. * before checking for netif_queue_stopped(). Without the
  4433. * memory barrier, there is a small possibility that tg3_start_xmit()
  4434. * will miss it and cause the queue to be stopped forever.
  4435. */
  4436. smp_mb();
  4437. if (unlikely(netif_tx_queue_stopped(txq) &&
  4438. (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
  4439. __netif_tx_lock(txq, smp_processor_id());
  4440. if (netif_tx_queue_stopped(txq) &&
  4441. (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
  4442. netif_tx_wake_queue(txq);
  4443. __netif_tx_unlock(txq);
  4444. }
  4445. }
  4446. static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
  4447. {
  4448. if (!ri->data)
  4449. return;
  4450. pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
  4451. map_sz, PCI_DMA_FROMDEVICE);
  4452. kfree(ri->data);
  4453. ri->data = NULL;
  4454. }
  4455. /* Returns size of skb allocated or < 0 on error.
  4456. *
  4457. * We only need to fill in the address because the other members
  4458. * of the RX descriptor are invariant, see tg3_init_rings.
  4459. *
  4460. * Note the purposeful assymetry of cpu vs. chip accesses. For
  4461. * posting buffers we only dirty the first cache line of the RX
  4462. * descriptor (containing the address). Whereas for the RX status
  4463. * buffers the cpu only reads the last cacheline of the RX descriptor
  4464. * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
  4465. */
  4466. static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
  4467. u32 opaque_key, u32 dest_idx_unmasked)
  4468. {
  4469. struct tg3_rx_buffer_desc *desc;
  4470. struct ring_info *map;
  4471. u8 *data;
  4472. dma_addr_t mapping;
  4473. int skb_size, data_size, dest_idx;
  4474. switch (opaque_key) {
  4475. case RXD_OPAQUE_RING_STD:
  4476. dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
  4477. desc = &tpr->rx_std[dest_idx];
  4478. map = &tpr->rx_std_buffers[dest_idx];
  4479. data_size = tp->rx_pkt_map_sz;
  4480. break;
  4481. case RXD_OPAQUE_RING_JUMBO:
  4482. dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
  4483. desc = &tpr->rx_jmb[dest_idx].std;
  4484. map = &tpr->rx_jmb_buffers[dest_idx];
  4485. data_size = TG3_RX_JMB_MAP_SZ;
  4486. break;
  4487. default:
  4488. return -EINVAL;
  4489. }
  4490. /* Do not overwrite any of the map or rp information
  4491. * until we are sure we can commit to a new buffer.
  4492. *
  4493. * Callers depend upon this behavior and assume that
  4494. * we leave everything unchanged if we fail.
  4495. */
  4496. skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
  4497. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  4498. data = kmalloc(skb_size, GFP_ATOMIC);
  4499. if (!data)
  4500. return -ENOMEM;
  4501. mapping = pci_map_single(tp->pdev,
  4502. data + TG3_RX_OFFSET(tp),
  4503. data_size,
  4504. PCI_DMA_FROMDEVICE);
  4505. if (pci_dma_mapping_error(tp->pdev, mapping)) {
  4506. kfree(data);
  4507. return -EIO;
  4508. }
  4509. map->data = data;
  4510. dma_unmap_addr_set(map, mapping, mapping);
  4511. desc->addr_hi = ((u64)mapping >> 32);
  4512. desc->addr_lo = ((u64)mapping & 0xffffffff);
  4513. return data_size;
  4514. }
  4515. /* We only need to move over in the address because the other
  4516. * members of the RX descriptor are invariant. See notes above
  4517. * tg3_alloc_rx_data for full details.
  4518. */
  4519. static void tg3_recycle_rx(struct tg3_napi *tnapi,
  4520. struct tg3_rx_prodring_set *dpr,
  4521. u32 opaque_key, int src_idx,
  4522. u32 dest_idx_unmasked)
  4523. {
  4524. struct tg3 *tp = tnapi->tp;
  4525. struct tg3_rx_buffer_desc *src_desc, *dest_desc;
  4526. struct ring_info *src_map, *dest_map;
  4527. struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
  4528. int dest_idx;
  4529. switch (opaque_key) {
  4530. case RXD_OPAQUE_RING_STD:
  4531. dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
  4532. dest_desc = &dpr->rx_std[dest_idx];
  4533. dest_map = &dpr->rx_std_buffers[dest_idx];
  4534. src_desc = &spr->rx_std[src_idx];
  4535. src_map = &spr->rx_std_buffers[src_idx];
  4536. break;
  4537. case RXD_OPAQUE_RING_JUMBO:
  4538. dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
  4539. dest_desc = &dpr->rx_jmb[dest_idx].std;
  4540. dest_map = &dpr->rx_jmb_buffers[dest_idx];
  4541. src_desc = &spr->rx_jmb[src_idx].std;
  4542. src_map = &spr->rx_jmb_buffers[src_idx];
  4543. break;
  4544. default:
  4545. return;
  4546. }
  4547. dest_map->data = src_map->data;
  4548. dma_unmap_addr_set(dest_map, mapping,
  4549. dma_unmap_addr(src_map, mapping));
  4550. dest_desc->addr_hi = src_desc->addr_hi;
  4551. dest_desc->addr_lo = src_desc->addr_lo;
  4552. /* Ensure that the update to the skb happens after the physical
  4553. * addresses have been transferred to the new BD location.
  4554. */
  4555. smp_wmb();
  4556. src_map->data = NULL;
  4557. }
  4558. /* The RX ring scheme is composed of multiple rings which post fresh
  4559. * buffers to the chip, and one special ring the chip uses to report
  4560. * status back to the host.
  4561. *
  4562. * The special ring reports the status of received packets to the
  4563. * host. The chip does not write into the original descriptor the
  4564. * RX buffer was obtained from. The chip simply takes the original
  4565. * descriptor as provided by the host, updates the status and length
  4566. * field, then writes this into the next status ring entry.
  4567. *
  4568. * Each ring the host uses to post buffers to the chip is described
  4569. * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
  4570. * it is first placed into the on-chip ram. When the packet's length
  4571. * is known, it walks down the TG3_BDINFO entries to select the ring.
  4572. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
  4573. * which is within the range of the new packet's length is chosen.
  4574. *
  4575. * The "separate ring for rx status" scheme may sound queer, but it makes
  4576. * sense from a cache coherency perspective. If only the host writes
  4577. * to the buffer post rings, and only the chip writes to the rx status
  4578. * rings, then cache lines never move beyond shared-modified state.
  4579. * If both the host and chip were to write into the same ring, cache line
  4580. * eviction could occur since both entities want it in an exclusive state.
  4581. */
  4582. static int tg3_rx(struct tg3_napi *tnapi, int budget)
  4583. {
  4584. struct tg3 *tp = tnapi->tp;
  4585. u32 work_mask, rx_std_posted = 0;
  4586. u32 std_prod_idx, jmb_prod_idx;
  4587. u32 sw_idx = tnapi->rx_rcb_ptr;
  4588. u16 hw_idx;
  4589. int received;
  4590. struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
  4591. hw_idx = *(tnapi->rx_rcb_prod_idx);
  4592. /*
  4593. * We need to order the read of hw_idx and the read of
  4594. * the opaque cookie.
  4595. */
  4596. rmb();
  4597. work_mask = 0;
  4598. received = 0;
  4599. std_prod_idx = tpr->rx_std_prod_idx;
  4600. jmb_prod_idx = tpr->rx_jmb_prod_idx;
  4601. while (sw_idx != hw_idx && budget > 0) {
  4602. struct ring_info *ri;
  4603. struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
  4604. unsigned int len;
  4605. struct sk_buff *skb;
  4606. dma_addr_t dma_addr;
  4607. u32 opaque_key, desc_idx, *post_ptr;
  4608. u8 *data;
  4609. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  4610. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  4611. if (opaque_key == RXD_OPAQUE_RING_STD) {
  4612. ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
  4613. dma_addr = dma_unmap_addr(ri, mapping);
  4614. data = ri->data;
  4615. post_ptr = &std_prod_idx;
  4616. rx_std_posted++;
  4617. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  4618. ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
  4619. dma_addr = dma_unmap_addr(ri, mapping);
  4620. data = ri->data;
  4621. post_ptr = &jmb_prod_idx;
  4622. } else
  4623. goto next_pkt_nopost;
  4624. work_mask |= opaque_key;
  4625. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  4626. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
  4627. drop_it:
  4628. tg3_recycle_rx(tnapi, tpr, opaque_key,
  4629. desc_idx, *post_ptr);
  4630. drop_it_no_recycle:
  4631. /* Other statistics kept track of by card. */
  4632. tp->rx_dropped++;
  4633. goto next_pkt;
  4634. }
  4635. prefetch(data + TG3_RX_OFFSET(tp));
  4636. len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
  4637. ETH_FCS_LEN;
  4638. if (len > TG3_RX_COPY_THRESH(tp)) {
  4639. int skb_size;
  4640. skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
  4641. *post_ptr);
  4642. if (skb_size < 0)
  4643. goto drop_it;
  4644. pci_unmap_single(tp->pdev, dma_addr, skb_size,
  4645. PCI_DMA_FROMDEVICE);
  4646. skb = build_skb(data);
  4647. if (!skb) {
  4648. kfree(data);
  4649. goto drop_it_no_recycle;
  4650. }
  4651. skb_reserve(skb, TG3_RX_OFFSET(tp));
  4652. /* Ensure that the update to the data happens
  4653. * after the usage of the old DMA mapping.
  4654. */
  4655. smp_wmb();
  4656. ri->data = NULL;
  4657. } else {
  4658. tg3_recycle_rx(tnapi, tpr, opaque_key,
  4659. desc_idx, *post_ptr);
  4660. skb = netdev_alloc_skb(tp->dev,
  4661. len + TG3_RAW_IP_ALIGN);
  4662. if (skb == NULL)
  4663. goto drop_it_no_recycle;
  4664. skb_reserve(skb, TG3_RAW_IP_ALIGN);
  4665. pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  4666. memcpy(skb->data,
  4667. data + TG3_RX_OFFSET(tp),
  4668. len);
  4669. pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  4670. }
  4671. skb_put(skb, len);
  4672. if ((tp->dev->features & NETIF_F_RXCSUM) &&
  4673. (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  4674. (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  4675. >> RXD_TCPCSUM_SHIFT) == 0xffff))
  4676. skb->ip_summed = CHECKSUM_UNNECESSARY;
  4677. else
  4678. skb_checksum_none_assert(skb);
  4679. skb->protocol = eth_type_trans(skb, tp->dev);
  4680. if (len > (tp->dev->mtu + ETH_HLEN) &&
  4681. skb->protocol != htons(ETH_P_8021Q)) {
  4682. dev_kfree_skb(skb);
  4683. goto drop_it_no_recycle;
  4684. }
  4685. if (desc->type_flags & RXD_FLAG_VLAN &&
  4686. !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
  4687. __vlan_hwaccel_put_tag(skb,
  4688. desc->err_vlan & RXD_VLAN_MASK);
  4689. napi_gro_receive(&tnapi->napi, skb);
  4690. received++;
  4691. budget--;
  4692. next_pkt:
  4693. (*post_ptr)++;
  4694. if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
  4695. tpr->rx_std_prod_idx = std_prod_idx &
  4696. tp->rx_std_ring_mask;
  4697. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  4698. tpr->rx_std_prod_idx);
  4699. work_mask &= ~RXD_OPAQUE_RING_STD;
  4700. rx_std_posted = 0;
  4701. }
  4702. next_pkt_nopost:
  4703. sw_idx++;
  4704. sw_idx &= tp->rx_ret_ring_mask;
  4705. /* Refresh hw_idx to see if there is new work */
  4706. if (sw_idx == hw_idx) {
  4707. hw_idx = *(tnapi->rx_rcb_prod_idx);
  4708. rmb();
  4709. }
  4710. }
  4711. /* ACK the status ring. */
  4712. tnapi->rx_rcb_ptr = sw_idx;
  4713. tw32_rx_mbox(tnapi->consmbox, sw_idx);
  4714. /* Refill RX ring(s). */
  4715. if (!tg3_flag(tp, ENABLE_RSS)) {
  4716. if (work_mask & RXD_OPAQUE_RING_STD) {
  4717. tpr->rx_std_prod_idx = std_prod_idx &
  4718. tp->rx_std_ring_mask;
  4719. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  4720. tpr->rx_std_prod_idx);
  4721. }
  4722. if (work_mask & RXD_OPAQUE_RING_JUMBO) {
  4723. tpr->rx_jmb_prod_idx = jmb_prod_idx &
  4724. tp->rx_jmb_ring_mask;
  4725. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
  4726. tpr->rx_jmb_prod_idx);
  4727. }
  4728. mmiowb();
  4729. } else if (work_mask) {
  4730. /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
  4731. * updated before the producer indices can be updated.
  4732. */
  4733. smp_wmb();
  4734. tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
  4735. tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
  4736. if (tnapi != &tp->napi[1])
  4737. napi_schedule(&tp->napi[1].napi);
  4738. }
  4739. return received;
  4740. }
  4741. static void tg3_poll_link(struct tg3 *tp)
  4742. {
  4743. /* handle link change and other phy events */
  4744. if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
  4745. struct tg3_hw_status *sblk = tp->napi[0].hw_status;
  4746. if (sblk->status & SD_STATUS_LINK_CHG) {
  4747. sblk->status = SD_STATUS_UPDATED |
  4748. (sblk->status & ~SD_STATUS_LINK_CHG);
  4749. spin_lock(&tp->lock);
  4750. if (tg3_flag(tp, USE_PHYLIB)) {
  4751. tw32_f(MAC_STATUS,
  4752. (MAC_STATUS_SYNC_CHANGED |
  4753. MAC_STATUS_CFG_CHANGED |
  4754. MAC_STATUS_MI_COMPLETION |
  4755. MAC_STATUS_LNKSTATE_CHANGED));
  4756. udelay(40);
  4757. } else
  4758. tg3_setup_phy(tp, 0);
  4759. spin_unlock(&tp->lock);
  4760. }
  4761. }
  4762. }
  4763. static int tg3_rx_prodring_xfer(struct tg3 *tp,
  4764. struct tg3_rx_prodring_set *dpr,
  4765. struct tg3_rx_prodring_set *spr)
  4766. {
  4767. u32 si, di, cpycnt, src_prod_idx;
  4768. int i, err = 0;
  4769. while (1) {
  4770. src_prod_idx = spr->rx_std_prod_idx;
  4771. /* Make sure updates to the rx_std_buffers[] entries and the
  4772. * standard producer index are seen in the correct order.
  4773. */
  4774. smp_rmb();
  4775. if (spr->rx_std_cons_idx == src_prod_idx)
  4776. break;
  4777. if (spr->rx_std_cons_idx < src_prod_idx)
  4778. cpycnt = src_prod_idx - spr->rx_std_cons_idx;
  4779. else
  4780. cpycnt = tp->rx_std_ring_mask + 1 -
  4781. spr->rx_std_cons_idx;
  4782. cpycnt = min(cpycnt,
  4783. tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
  4784. si = spr->rx_std_cons_idx;
  4785. di = dpr->rx_std_prod_idx;
  4786. for (i = di; i < di + cpycnt; i++) {
  4787. if (dpr->rx_std_buffers[i].data) {
  4788. cpycnt = i - di;
  4789. err = -ENOSPC;
  4790. break;
  4791. }
  4792. }
  4793. if (!cpycnt)
  4794. break;
  4795. /* Ensure that updates to the rx_std_buffers ring and the
  4796. * shadowed hardware producer ring from tg3_recycle_skb() are
  4797. * ordered correctly WRT the skb check above.
  4798. */
  4799. smp_rmb();
  4800. memcpy(&dpr->rx_std_buffers[di],
  4801. &spr->rx_std_buffers[si],
  4802. cpycnt * sizeof(struct ring_info));
  4803. for (i = 0; i < cpycnt; i++, di++, si++) {
  4804. struct tg3_rx_buffer_desc *sbd, *dbd;
  4805. sbd = &spr->rx_std[si];
  4806. dbd = &dpr->rx_std[di];
  4807. dbd->addr_hi = sbd->addr_hi;
  4808. dbd->addr_lo = sbd->addr_lo;
  4809. }
  4810. spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
  4811. tp->rx_std_ring_mask;
  4812. dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
  4813. tp->rx_std_ring_mask;
  4814. }
  4815. while (1) {
  4816. src_prod_idx = spr->rx_jmb_prod_idx;
  4817. /* Make sure updates to the rx_jmb_buffers[] entries and
  4818. * the jumbo producer index are seen in the correct order.
  4819. */
  4820. smp_rmb();
  4821. if (spr->rx_jmb_cons_idx == src_prod_idx)
  4822. break;
  4823. if (spr->rx_jmb_cons_idx < src_prod_idx)
  4824. cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
  4825. else
  4826. cpycnt = tp->rx_jmb_ring_mask + 1 -
  4827. spr->rx_jmb_cons_idx;
  4828. cpycnt = min(cpycnt,
  4829. tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
  4830. si = spr->rx_jmb_cons_idx;
  4831. di = dpr->rx_jmb_prod_idx;
  4832. for (i = di; i < di + cpycnt; i++) {
  4833. if (dpr->rx_jmb_buffers[i].data) {
  4834. cpycnt = i - di;
  4835. err = -ENOSPC;
  4836. break;
  4837. }
  4838. }
  4839. if (!cpycnt)
  4840. break;
  4841. /* Ensure that updates to the rx_jmb_buffers ring and the
  4842. * shadowed hardware producer ring from tg3_recycle_skb() are
  4843. * ordered correctly WRT the skb check above.
  4844. */
  4845. smp_rmb();
  4846. memcpy(&dpr->rx_jmb_buffers[di],
  4847. &spr->rx_jmb_buffers[si],
  4848. cpycnt * sizeof(struct ring_info));
  4849. for (i = 0; i < cpycnt; i++, di++, si++) {
  4850. struct tg3_rx_buffer_desc *sbd, *dbd;
  4851. sbd = &spr->rx_jmb[si].std;
  4852. dbd = &dpr->rx_jmb[di].std;
  4853. dbd->addr_hi = sbd->addr_hi;
  4854. dbd->addr_lo = sbd->addr_lo;
  4855. }
  4856. spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
  4857. tp->rx_jmb_ring_mask;
  4858. dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
  4859. tp->rx_jmb_ring_mask;
  4860. }
  4861. return err;
  4862. }
  4863. static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
  4864. {
  4865. struct tg3 *tp = tnapi->tp;
  4866. /* run TX completion thread */
  4867. if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
  4868. tg3_tx(tnapi);
  4869. if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
  4870. return work_done;
  4871. }
  4872. /* run RX thread, within the bounds set by NAPI.
  4873. * All RX "locking" is done by ensuring outside
  4874. * code synchronizes with tg3->napi.poll()
  4875. */
  4876. if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
  4877. work_done += tg3_rx(tnapi, budget - work_done);
  4878. if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
  4879. struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
  4880. int i, err = 0;
  4881. u32 std_prod_idx = dpr->rx_std_prod_idx;
  4882. u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
  4883. for (i = 1; i < tp->irq_cnt; i++)
  4884. err |= tg3_rx_prodring_xfer(tp, dpr,
  4885. &tp->napi[i].prodring);
  4886. wmb();
  4887. if (std_prod_idx != dpr->rx_std_prod_idx)
  4888. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  4889. dpr->rx_std_prod_idx);
  4890. if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
  4891. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
  4892. dpr->rx_jmb_prod_idx);
  4893. mmiowb();
  4894. if (err)
  4895. tw32_f(HOSTCC_MODE, tp->coal_now);
  4896. }
  4897. return work_done;
  4898. }
  4899. static inline void tg3_reset_task_schedule(struct tg3 *tp)
  4900. {
  4901. if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
  4902. schedule_work(&tp->reset_task);
  4903. }
  4904. static inline void tg3_reset_task_cancel(struct tg3 *tp)
  4905. {
  4906. cancel_work_sync(&tp->reset_task);
  4907. tg3_flag_clear(tp, RESET_TASK_PENDING);
  4908. }
  4909. static int tg3_poll_msix(struct napi_struct *napi, int budget)
  4910. {
  4911. struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
  4912. struct tg3 *tp = tnapi->tp;
  4913. int work_done = 0;
  4914. struct tg3_hw_status *sblk = tnapi->hw_status;
  4915. while (1) {
  4916. work_done = tg3_poll_work(tnapi, work_done, budget);
  4917. if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
  4918. goto tx_recovery;
  4919. if (unlikely(work_done >= budget))
  4920. break;
  4921. /* tp->last_tag is used in tg3_int_reenable() below
  4922. * to tell the hw how much work has been processed,
  4923. * so we must read it before checking for more work.
  4924. */
  4925. tnapi->last_tag = sblk->status_tag;
  4926. tnapi->last_irq_tag = tnapi->last_tag;
  4927. rmb();
  4928. /* check for RX/TX work to do */
  4929. if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
  4930. *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
  4931. napi_complete(napi);
  4932. /* Reenable interrupts. */
  4933. tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
  4934. mmiowb();
  4935. break;
  4936. }
  4937. }
  4938. return work_done;
  4939. tx_recovery:
  4940. /* work_done is guaranteed to be less than budget. */
  4941. napi_complete(napi);
  4942. tg3_reset_task_schedule(tp);
  4943. return work_done;
  4944. }
  4945. static void tg3_process_error(struct tg3 *tp)
  4946. {
  4947. u32 val;
  4948. bool real_error = false;
  4949. if (tg3_flag(tp, ERROR_PROCESSED))
  4950. return;
  4951. /* Check Flow Attention register */
  4952. val = tr32(HOSTCC_FLOW_ATTN);
  4953. if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
  4954. netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
  4955. real_error = true;
  4956. }
  4957. if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
  4958. netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
  4959. real_error = true;
  4960. }
  4961. if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
  4962. netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
  4963. real_error = true;
  4964. }
  4965. if (!real_error)
  4966. return;
  4967. tg3_dump_state(tp);
  4968. tg3_flag_set(tp, ERROR_PROCESSED);
  4969. tg3_reset_task_schedule(tp);
  4970. }
  4971. static int tg3_poll(struct napi_struct *napi, int budget)
  4972. {
  4973. struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
  4974. struct tg3 *tp = tnapi->tp;
  4975. int work_done = 0;
  4976. struct tg3_hw_status *sblk = tnapi->hw_status;
  4977. while (1) {
  4978. if (sblk->status & SD_STATUS_ERROR)
  4979. tg3_process_error(tp);
  4980. tg3_poll_link(tp);
  4981. work_done = tg3_poll_work(tnapi, work_done, budget);
  4982. if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
  4983. goto tx_recovery;
  4984. if (unlikely(work_done >= budget))
  4985. break;
  4986. if (tg3_flag(tp, TAGGED_STATUS)) {
  4987. /* tp->last_tag is used in tg3_int_reenable() below
  4988. * to tell the hw how much work has been processed,
  4989. * so we must read it before checking for more work.
  4990. */
  4991. tnapi->last_tag = sblk->status_tag;
  4992. tnapi->last_irq_tag = tnapi->last_tag;
  4993. rmb();
  4994. } else
  4995. sblk->status &= ~SD_STATUS_UPDATED;
  4996. if (likely(!tg3_has_work(tnapi))) {
  4997. napi_complete(napi);
  4998. tg3_int_reenable(tnapi);
  4999. break;
  5000. }
  5001. }
  5002. return work_done;
  5003. tx_recovery:
  5004. /* work_done is guaranteed to be less than budget. */
  5005. napi_complete(napi);
  5006. tg3_reset_task_schedule(tp);
  5007. return work_done;
  5008. }
  5009. static void tg3_napi_disable(struct tg3 *tp)
  5010. {
  5011. int i;
  5012. for (i = tp->irq_cnt - 1; i >= 0; i--)
  5013. napi_disable(&tp->napi[i].napi);
  5014. }
  5015. static void tg3_napi_enable(struct tg3 *tp)
  5016. {
  5017. int i;
  5018. for (i = 0; i < tp->irq_cnt; i++)
  5019. napi_enable(&tp->napi[i].napi);
  5020. }
  5021. static void tg3_napi_init(struct tg3 *tp)
  5022. {
  5023. int i;
  5024. netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
  5025. for (i = 1; i < tp->irq_cnt; i++)
  5026. netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
  5027. }
  5028. static void tg3_napi_fini(struct tg3 *tp)
  5029. {
  5030. int i;
  5031. for (i = 0; i < tp->irq_cnt; i++)
  5032. netif_napi_del(&tp->napi[i].napi);
  5033. }
  5034. static inline void tg3_netif_stop(struct tg3 *tp)
  5035. {
  5036. tp->dev->trans_start = jiffies; /* prevent tx timeout */
  5037. tg3_napi_disable(tp);
  5038. netif_tx_disable(tp->dev);
  5039. }
  5040. static inline void tg3_netif_start(struct tg3 *tp)
  5041. {
  5042. /* NOTE: unconditional netif_tx_wake_all_queues is only
  5043. * appropriate so long as all callers are assured to
  5044. * have free tx slots (such as after tg3_init_hw)
  5045. */
  5046. netif_tx_wake_all_queues(tp->dev);
  5047. tg3_napi_enable(tp);
  5048. tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
  5049. tg3_enable_ints(tp);
  5050. }
  5051. static void tg3_irq_quiesce(struct tg3 *tp)
  5052. {
  5053. int i;
  5054. BUG_ON(tp->irq_sync);
  5055. tp->irq_sync = 1;
  5056. smp_mb();
  5057. for (i = 0; i < tp->irq_cnt; i++)
  5058. synchronize_irq(tp->napi[i].irq_vec);
  5059. }
  5060. /* Fully shutdown all tg3 driver activity elsewhere in the system.
  5061. * If irq_sync is non-zero, then the IRQ handler must be synchronized
  5062. * with as well. Most of the time, this is not necessary except when
  5063. * shutting down the device.
  5064. */
  5065. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
  5066. {
  5067. spin_lock_bh(&tp->lock);
  5068. if (irq_sync)
  5069. tg3_irq_quiesce(tp);
  5070. }
  5071. static inline void tg3_full_unlock(struct tg3 *tp)
  5072. {
  5073. spin_unlock_bh(&tp->lock);
  5074. }
  5075. /* One-shot MSI handler - Chip automatically disables interrupt
  5076. * after sending MSI so driver doesn't have to do it.
  5077. */
  5078. static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
  5079. {
  5080. struct tg3_napi *tnapi = dev_id;
  5081. struct tg3 *tp = tnapi->tp;
  5082. prefetch(tnapi->hw_status);
  5083. if (tnapi->rx_rcb)
  5084. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  5085. if (likely(!tg3_irq_sync(tp)))
  5086. napi_schedule(&tnapi->napi);
  5087. return IRQ_HANDLED;
  5088. }
  5089. /* MSI ISR - No need to check for interrupt sharing and no need to
  5090. * flush status block and interrupt mailbox. PCI ordering rules
  5091. * guarantee that MSI will arrive after the status block.
  5092. */
  5093. static irqreturn_t tg3_msi(int irq, void *dev_id)
  5094. {
  5095. struct tg3_napi *tnapi = dev_id;
  5096. struct tg3 *tp = tnapi->tp;
  5097. prefetch(tnapi->hw_status);
  5098. if (tnapi->rx_rcb)
  5099. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  5100. /*
  5101. * Writing any value to intr-mbox-0 clears PCI INTA# and
  5102. * chip-internal interrupt pending events.
  5103. * Writing non-zero to intr-mbox-0 additional tells the
  5104. * NIC to stop sending us irqs, engaging "in-intr-handler"
  5105. * event coalescing.
  5106. */
  5107. tw32_mailbox(tnapi->int_mbox, 0x00000001);
  5108. if (likely(!tg3_irq_sync(tp)))
  5109. napi_schedule(&tnapi->napi);
  5110. return IRQ_RETVAL(1);
  5111. }
  5112. static irqreturn_t tg3_interrupt(int irq, void *dev_id)
  5113. {
  5114. struct tg3_napi *tnapi = dev_id;
  5115. struct tg3 *tp = tnapi->tp;
  5116. struct tg3_hw_status *sblk = tnapi->hw_status;
  5117. unsigned int handled = 1;
  5118. /* In INTx mode, it is possible for the interrupt to arrive at
  5119. * the CPU before the status block posted prior to the interrupt.
  5120. * Reading the PCI State register will confirm whether the
  5121. * interrupt is ours and will flush the status block.
  5122. */
  5123. if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
  5124. if (tg3_flag(tp, CHIP_RESETTING) ||
  5125. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  5126. handled = 0;
  5127. goto out;
  5128. }
  5129. }
  5130. /*
  5131. * Writing any value to intr-mbox-0 clears PCI INTA# and
  5132. * chip-internal interrupt pending events.
  5133. * Writing non-zero to intr-mbox-0 additional tells the
  5134. * NIC to stop sending us irqs, engaging "in-intr-handler"
  5135. * event coalescing.
  5136. *
  5137. * Flush the mailbox to de-assert the IRQ immediately to prevent
  5138. * spurious interrupts. The flush impacts performance but
  5139. * excessive spurious interrupts can be worse in some cases.
  5140. */
  5141. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  5142. if (tg3_irq_sync(tp))
  5143. goto out;
  5144. sblk->status &= ~SD_STATUS_UPDATED;
  5145. if (likely(tg3_has_work(tnapi))) {
  5146. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  5147. napi_schedule(&tnapi->napi);
  5148. } else {
  5149. /* No work, shared interrupt perhaps? re-enable
  5150. * interrupts, and flush that PCI write
  5151. */
  5152. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  5153. 0x00000000);
  5154. }
  5155. out:
  5156. return IRQ_RETVAL(handled);
  5157. }
  5158. static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
  5159. {
  5160. struct tg3_napi *tnapi = dev_id;
  5161. struct tg3 *tp = tnapi->tp;
  5162. struct tg3_hw_status *sblk = tnapi->hw_status;
  5163. unsigned int handled = 1;
  5164. /* In INTx mode, it is possible for the interrupt to arrive at
  5165. * the CPU before the status block posted prior to the interrupt.
  5166. * Reading the PCI State register will confirm whether the
  5167. * interrupt is ours and will flush the status block.
  5168. */
  5169. if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
  5170. if (tg3_flag(tp, CHIP_RESETTING) ||
  5171. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  5172. handled = 0;
  5173. goto out;
  5174. }
  5175. }
  5176. /*
  5177. * writing any value to intr-mbox-0 clears PCI INTA# and
  5178. * chip-internal interrupt pending events.
  5179. * writing non-zero to intr-mbox-0 additional tells the
  5180. * NIC to stop sending us irqs, engaging "in-intr-handler"
  5181. * event coalescing.
  5182. *
  5183. * Flush the mailbox to de-assert the IRQ immediately to prevent
  5184. * spurious interrupts. The flush impacts performance but
  5185. * excessive spurious interrupts can be worse in some cases.
  5186. */
  5187. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  5188. /*
  5189. * In a shared interrupt configuration, sometimes other devices'
  5190. * interrupts will scream. We record the current status tag here
  5191. * so that the above check can report that the screaming interrupts
  5192. * are unhandled. Eventually they will be silenced.
  5193. */
  5194. tnapi->last_irq_tag = sblk->status_tag;
  5195. if (tg3_irq_sync(tp))
  5196. goto out;
  5197. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  5198. napi_schedule(&tnapi->napi);
  5199. out:
  5200. return IRQ_RETVAL(handled);
  5201. }
  5202. /* ISR for interrupt test */
  5203. static irqreturn_t tg3_test_isr(int irq, void *dev_id)
  5204. {
  5205. struct tg3_napi *tnapi = dev_id;
  5206. struct tg3 *tp = tnapi->tp;
  5207. struct tg3_hw_status *sblk = tnapi->hw_status;
  5208. if ((sblk->status & SD_STATUS_UPDATED) ||
  5209. !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  5210. tg3_disable_ints(tp);
  5211. return IRQ_RETVAL(1);
  5212. }
  5213. return IRQ_RETVAL(0);
  5214. }
  5215. static int tg3_init_hw(struct tg3 *, int);
  5216. static int tg3_halt(struct tg3 *, int, int);
  5217. /* Restart hardware after configuration changes, self-test, etc.
  5218. * Invoked with tp->lock held.
  5219. */
  5220. static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
  5221. __releases(tp->lock)
  5222. __acquires(tp->lock)
  5223. {
  5224. int err;
  5225. err = tg3_init_hw(tp, reset_phy);
  5226. if (err) {
  5227. netdev_err(tp->dev,
  5228. "Failed to re-initialize device, aborting\n");
  5229. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  5230. tg3_full_unlock(tp);
  5231. del_timer_sync(&tp->timer);
  5232. tp->irq_sync = 0;
  5233. tg3_napi_enable(tp);
  5234. dev_close(tp->dev);
  5235. tg3_full_lock(tp, 0);
  5236. }
  5237. return err;
  5238. }
  5239. #ifdef CONFIG_NET_POLL_CONTROLLER
  5240. static void tg3_poll_controller(struct net_device *dev)
  5241. {
  5242. int i;
  5243. struct tg3 *tp = netdev_priv(dev);
  5244. for (i = 0; i < tp->irq_cnt; i++)
  5245. tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
  5246. }
  5247. #endif
  5248. static void tg3_reset_task(struct work_struct *work)
  5249. {
  5250. struct tg3 *tp = container_of(work, struct tg3, reset_task);
  5251. int err;
  5252. tg3_full_lock(tp, 0);
  5253. if (!netif_running(tp->dev)) {
  5254. tg3_flag_clear(tp, RESET_TASK_PENDING);
  5255. tg3_full_unlock(tp);
  5256. return;
  5257. }
  5258. tg3_full_unlock(tp);
  5259. tg3_phy_stop(tp);
  5260. tg3_netif_stop(tp);
  5261. tg3_full_lock(tp, 1);
  5262. if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
  5263. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  5264. tp->write32_rx_mbox = tg3_write_flush_reg32;
  5265. tg3_flag_set(tp, MBOX_WRITE_REORDER);
  5266. tg3_flag_clear(tp, TX_RECOVERY_PENDING);
  5267. }
  5268. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  5269. err = tg3_init_hw(tp, 1);
  5270. if (err)
  5271. goto out;
  5272. tg3_netif_start(tp);
  5273. out:
  5274. tg3_full_unlock(tp);
  5275. if (!err)
  5276. tg3_phy_start(tp);
  5277. tg3_flag_clear(tp, RESET_TASK_PENDING);
  5278. }
  5279. static void tg3_tx_timeout(struct net_device *dev)
  5280. {
  5281. struct tg3 *tp = netdev_priv(dev);
  5282. if (netif_msg_tx_err(tp)) {
  5283. netdev_err(dev, "transmit timed out, resetting\n");
  5284. tg3_dump_state(tp);
  5285. }
  5286. tg3_reset_task_schedule(tp);
  5287. }
  5288. /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
  5289. static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
  5290. {
  5291. u32 base = (u32) mapping & 0xffffffff;
  5292. return (base > 0xffffdcc0) && (base + len + 8 < base);
  5293. }
  5294. /* Test for DMA addresses > 40-bit */
  5295. static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  5296. int len)
  5297. {
  5298. #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
  5299. if (tg3_flag(tp, 40BIT_DMA_BUG))
  5300. return ((u64) mapping + len) > DMA_BIT_MASK(40);
  5301. return 0;
  5302. #else
  5303. return 0;
  5304. #endif
  5305. }
  5306. static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
  5307. dma_addr_t mapping, u32 len, u32 flags,
  5308. u32 mss, u32 vlan)
  5309. {
  5310. txbd->addr_hi = ((u64) mapping >> 32);
  5311. txbd->addr_lo = ((u64) mapping & 0xffffffff);
  5312. txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
  5313. txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
  5314. }
  5315. static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
  5316. dma_addr_t map, u32 len, u32 flags,
  5317. u32 mss, u32 vlan)
  5318. {
  5319. struct tg3 *tp = tnapi->tp;
  5320. bool hwbug = false;
  5321. if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
  5322. hwbug = 1;
  5323. if (tg3_4g_overflow_test(map, len))
  5324. hwbug = 1;
  5325. if (tg3_40bit_overflow_test(tp, map, len))
  5326. hwbug = 1;
  5327. if (tg3_flag(tp, 4K_FIFO_LIMIT)) {
  5328. u32 prvidx = *entry;
  5329. u32 tmp_flag = flags & ~TXD_FLAG_END;
  5330. while (len > TG3_TX_BD_DMA_MAX && *budget) {
  5331. u32 frag_len = TG3_TX_BD_DMA_MAX;
  5332. len -= TG3_TX_BD_DMA_MAX;
  5333. /* Avoid the 8byte DMA problem */
  5334. if (len <= 8) {
  5335. len += TG3_TX_BD_DMA_MAX / 2;
  5336. frag_len = TG3_TX_BD_DMA_MAX / 2;
  5337. }
  5338. tnapi->tx_buffers[*entry].fragmented = true;
  5339. tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
  5340. frag_len, tmp_flag, mss, vlan);
  5341. *budget -= 1;
  5342. prvidx = *entry;
  5343. *entry = NEXT_TX(*entry);
  5344. map += frag_len;
  5345. }
  5346. if (len) {
  5347. if (*budget) {
  5348. tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
  5349. len, flags, mss, vlan);
  5350. *budget -= 1;
  5351. *entry = NEXT_TX(*entry);
  5352. } else {
  5353. hwbug = 1;
  5354. tnapi->tx_buffers[prvidx].fragmented = false;
  5355. }
  5356. }
  5357. } else {
  5358. tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
  5359. len, flags, mss, vlan);
  5360. *entry = NEXT_TX(*entry);
  5361. }
  5362. return hwbug;
  5363. }
  5364. static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
  5365. {
  5366. int i;
  5367. struct sk_buff *skb;
  5368. struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
  5369. skb = txb->skb;
  5370. txb->skb = NULL;
  5371. pci_unmap_single(tnapi->tp->pdev,
  5372. dma_unmap_addr(txb, mapping),
  5373. skb_headlen(skb),
  5374. PCI_DMA_TODEVICE);
  5375. while (txb->fragmented) {
  5376. txb->fragmented = false;
  5377. entry = NEXT_TX(entry);
  5378. txb = &tnapi->tx_buffers[entry];
  5379. }
  5380. for (i = 0; i <= last; i++) {
  5381. const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  5382. entry = NEXT_TX(entry);
  5383. txb = &tnapi->tx_buffers[entry];
  5384. pci_unmap_page(tnapi->tp->pdev,
  5385. dma_unmap_addr(txb, mapping),
  5386. skb_frag_size(frag), PCI_DMA_TODEVICE);
  5387. while (txb->fragmented) {
  5388. txb->fragmented = false;
  5389. entry = NEXT_TX(entry);
  5390. txb = &tnapi->tx_buffers[entry];
  5391. }
  5392. }
  5393. }
  5394. /* Workaround 4GB and 40-bit hardware DMA bugs. */
  5395. static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
  5396. struct sk_buff **pskb,
  5397. u32 *entry, u32 *budget,
  5398. u32 base_flags, u32 mss, u32 vlan)
  5399. {
  5400. struct tg3 *tp = tnapi->tp;
  5401. struct sk_buff *new_skb, *skb = *pskb;
  5402. dma_addr_t new_addr = 0;
  5403. int ret = 0;
  5404. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  5405. new_skb = skb_copy(skb, GFP_ATOMIC);
  5406. else {
  5407. int more_headroom = 4 - ((unsigned long)skb->data & 3);
  5408. new_skb = skb_copy_expand(skb,
  5409. skb_headroom(skb) + more_headroom,
  5410. skb_tailroom(skb), GFP_ATOMIC);
  5411. }
  5412. if (!new_skb) {
  5413. ret = -1;
  5414. } else {
  5415. /* New SKB is guaranteed to be linear. */
  5416. new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
  5417. PCI_DMA_TODEVICE);
  5418. /* Make sure the mapping succeeded */
  5419. if (pci_dma_mapping_error(tp->pdev, new_addr)) {
  5420. dev_kfree_skb(new_skb);
  5421. ret = -1;
  5422. } else {
  5423. u32 save_entry = *entry;
  5424. base_flags |= TXD_FLAG_END;
  5425. tnapi->tx_buffers[*entry].skb = new_skb;
  5426. dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
  5427. mapping, new_addr);
  5428. if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
  5429. new_skb->len, base_flags,
  5430. mss, vlan)) {
  5431. tg3_tx_skb_unmap(tnapi, save_entry, -1);
  5432. dev_kfree_skb(new_skb);
  5433. ret = -1;
  5434. }
  5435. }
  5436. }
  5437. dev_kfree_skb(skb);
  5438. *pskb = new_skb;
  5439. return ret;
  5440. }
  5441. static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
  5442. /* Use GSO to workaround a rare TSO bug that may be triggered when the
  5443. * TSO header is greater than 80 bytes.
  5444. */
  5445. static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
  5446. {
  5447. struct sk_buff *segs, *nskb;
  5448. u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
  5449. /* Estimate the number of fragments in the worst case */
  5450. if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
  5451. netif_stop_queue(tp->dev);
  5452. /* netif_tx_stop_queue() must be done before checking
  5453. * checking tx index in tg3_tx_avail() below, because in
  5454. * tg3_tx(), we update tx index before checking for
  5455. * netif_tx_queue_stopped().
  5456. */
  5457. smp_mb();
  5458. if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
  5459. return NETDEV_TX_BUSY;
  5460. netif_wake_queue(tp->dev);
  5461. }
  5462. segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
  5463. if (IS_ERR(segs))
  5464. goto tg3_tso_bug_end;
  5465. do {
  5466. nskb = segs;
  5467. segs = segs->next;
  5468. nskb->next = NULL;
  5469. tg3_start_xmit(nskb, tp->dev);
  5470. } while (segs);
  5471. tg3_tso_bug_end:
  5472. dev_kfree_skb(skb);
  5473. return NETDEV_TX_OK;
  5474. }
  5475. /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
  5476. * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
  5477. */
  5478. static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
  5479. {
  5480. struct tg3 *tp = netdev_priv(dev);
  5481. u32 len, entry, base_flags, mss, vlan = 0;
  5482. u32 budget;
  5483. int i = -1, would_hit_hwbug;
  5484. dma_addr_t mapping;
  5485. struct tg3_napi *tnapi;
  5486. struct netdev_queue *txq;
  5487. unsigned int last;
  5488. txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
  5489. tnapi = &tp->napi[skb_get_queue_mapping(skb)];
  5490. if (tg3_flag(tp, ENABLE_TSS))
  5491. tnapi++;
  5492. budget = tg3_tx_avail(tnapi);
  5493. /* We are running in BH disabled context with netif_tx_lock
  5494. * and TX reclaim runs via tp->napi.poll inside of a software
  5495. * interrupt. Furthermore, IRQ processing runs lockless so we have
  5496. * no IRQ context deadlocks to worry about either. Rejoice!
  5497. */
  5498. if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
  5499. if (!netif_tx_queue_stopped(txq)) {
  5500. netif_tx_stop_queue(txq);
  5501. /* This is a hard error, log it. */
  5502. netdev_err(dev,
  5503. "BUG! Tx Ring full when queue awake!\n");
  5504. }
  5505. return NETDEV_TX_BUSY;
  5506. }
  5507. entry = tnapi->tx_prod;
  5508. base_flags = 0;
  5509. if (skb->ip_summed == CHECKSUM_PARTIAL)
  5510. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  5511. mss = skb_shinfo(skb)->gso_size;
  5512. if (mss) {
  5513. struct iphdr *iph;
  5514. u32 tcp_opt_len, hdr_len;
  5515. if (skb_header_cloned(skb) &&
  5516. pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
  5517. goto drop;
  5518. iph = ip_hdr(skb);
  5519. tcp_opt_len = tcp_optlen(skb);
  5520. if (skb_is_gso_v6(skb)) {
  5521. hdr_len = skb_headlen(skb) - ETH_HLEN;
  5522. } else {
  5523. u32 ip_tcp_len;
  5524. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  5525. hdr_len = ip_tcp_len + tcp_opt_len;
  5526. iph->check = 0;
  5527. iph->tot_len = htons(mss + hdr_len);
  5528. }
  5529. if (unlikely((ETH_HLEN + hdr_len) > 80) &&
  5530. tg3_flag(tp, TSO_BUG))
  5531. return tg3_tso_bug(tp, skb);
  5532. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  5533. TXD_FLAG_CPU_POST_DMA);
  5534. if (tg3_flag(tp, HW_TSO_1) ||
  5535. tg3_flag(tp, HW_TSO_2) ||
  5536. tg3_flag(tp, HW_TSO_3)) {
  5537. tcp_hdr(skb)->check = 0;
  5538. base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
  5539. } else
  5540. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  5541. iph->daddr, 0,
  5542. IPPROTO_TCP,
  5543. 0);
  5544. if (tg3_flag(tp, HW_TSO_3)) {
  5545. mss |= (hdr_len & 0xc) << 12;
  5546. if (hdr_len & 0x10)
  5547. base_flags |= 0x00000010;
  5548. base_flags |= (hdr_len & 0x3e0) << 5;
  5549. } else if (tg3_flag(tp, HW_TSO_2))
  5550. mss |= hdr_len << 9;
  5551. else if (tg3_flag(tp, HW_TSO_1) ||
  5552. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  5553. if (tcp_opt_len || iph->ihl > 5) {
  5554. int tsflags;
  5555. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  5556. mss |= (tsflags << 11);
  5557. }
  5558. } else {
  5559. if (tcp_opt_len || iph->ihl > 5) {
  5560. int tsflags;
  5561. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  5562. base_flags |= tsflags << 12;
  5563. }
  5564. }
  5565. }
  5566. if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
  5567. !mss && skb->len > VLAN_ETH_FRAME_LEN)
  5568. base_flags |= TXD_FLAG_JMB_PKT;
  5569. if (vlan_tx_tag_present(skb)) {
  5570. base_flags |= TXD_FLAG_VLAN;
  5571. vlan = vlan_tx_tag_get(skb);
  5572. }
  5573. len = skb_headlen(skb);
  5574. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  5575. if (pci_dma_mapping_error(tp->pdev, mapping))
  5576. goto drop;
  5577. tnapi->tx_buffers[entry].skb = skb;
  5578. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
  5579. would_hit_hwbug = 0;
  5580. if (tg3_flag(tp, 5701_DMA_BUG))
  5581. would_hit_hwbug = 1;
  5582. if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
  5583. ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
  5584. mss, vlan)) {
  5585. would_hit_hwbug = 1;
  5586. /* Now loop through additional data fragments, and queue them. */
  5587. } else if (skb_shinfo(skb)->nr_frags > 0) {
  5588. u32 tmp_mss = mss;
  5589. if (!tg3_flag(tp, HW_TSO_1) &&
  5590. !tg3_flag(tp, HW_TSO_2) &&
  5591. !tg3_flag(tp, HW_TSO_3))
  5592. tmp_mss = 0;
  5593. last = skb_shinfo(skb)->nr_frags - 1;
  5594. for (i = 0; i <= last; i++) {
  5595. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  5596. len = skb_frag_size(frag);
  5597. mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
  5598. len, DMA_TO_DEVICE);
  5599. tnapi->tx_buffers[entry].skb = NULL;
  5600. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
  5601. mapping);
  5602. if (dma_mapping_error(&tp->pdev->dev, mapping))
  5603. goto dma_error;
  5604. if (!budget ||
  5605. tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
  5606. len, base_flags |
  5607. ((i == last) ? TXD_FLAG_END : 0),
  5608. tmp_mss, vlan)) {
  5609. would_hit_hwbug = 1;
  5610. break;
  5611. }
  5612. }
  5613. }
  5614. if (would_hit_hwbug) {
  5615. tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
  5616. /* If the workaround fails due to memory/mapping
  5617. * failure, silently drop this packet.
  5618. */
  5619. entry = tnapi->tx_prod;
  5620. budget = tg3_tx_avail(tnapi);
  5621. if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
  5622. base_flags, mss, vlan))
  5623. goto drop_nofree;
  5624. }
  5625. skb_tx_timestamp(skb);
  5626. /* Packets are ready, update Tx producer idx local and on card. */
  5627. tw32_tx_mbox(tnapi->prodmbox, entry);
  5628. tnapi->tx_prod = entry;
  5629. if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
  5630. netif_tx_stop_queue(txq);
  5631. /* netif_tx_stop_queue() must be done before checking
  5632. * checking tx index in tg3_tx_avail() below, because in
  5633. * tg3_tx(), we update tx index before checking for
  5634. * netif_tx_queue_stopped().
  5635. */
  5636. smp_mb();
  5637. if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
  5638. netif_tx_wake_queue(txq);
  5639. }
  5640. mmiowb();
  5641. return NETDEV_TX_OK;
  5642. dma_error:
  5643. tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
  5644. tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
  5645. drop:
  5646. dev_kfree_skb(skb);
  5647. drop_nofree:
  5648. tp->tx_dropped++;
  5649. return NETDEV_TX_OK;
  5650. }
  5651. static void tg3_mac_loopback(struct tg3 *tp, bool enable)
  5652. {
  5653. if (enable) {
  5654. tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
  5655. MAC_MODE_PORT_MODE_MASK);
  5656. tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
  5657. if (!tg3_flag(tp, 5705_PLUS))
  5658. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  5659. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  5660. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  5661. else
  5662. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  5663. } else {
  5664. tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
  5665. if (tg3_flag(tp, 5705_PLUS) ||
  5666. (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
  5667. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  5668. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  5669. }
  5670. tw32(MAC_MODE, tp->mac_mode);
  5671. udelay(40);
  5672. }
  5673. static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
  5674. {
  5675. u32 val, bmcr, mac_mode, ptest = 0;
  5676. tg3_phy_toggle_apd(tp, false);
  5677. tg3_phy_toggle_automdix(tp, 0);
  5678. if (extlpbk && tg3_phy_set_extloopbk(tp))
  5679. return -EIO;
  5680. bmcr = BMCR_FULLDPLX;
  5681. switch (speed) {
  5682. case SPEED_10:
  5683. break;
  5684. case SPEED_100:
  5685. bmcr |= BMCR_SPEED100;
  5686. break;
  5687. case SPEED_1000:
  5688. default:
  5689. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  5690. speed = SPEED_100;
  5691. bmcr |= BMCR_SPEED100;
  5692. } else {
  5693. speed = SPEED_1000;
  5694. bmcr |= BMCR_SPEED1000;
  5695. }
  5696. }
  5697. if (extlpbk) {
  5698. if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  5699. tg3_readphy(tp, MII_CTRL1000, &val);
  5700. val |= CTL1000_AS_MASTER |
  5701. CTL1000_ENABLE_MASTER;
  5702. tg3_writephy(tp, MII_CTRL1000, val);
  5703. } else {
  5704. ptest = MII_TG3_FET_PTEST_TRIM_SEL |
  5705. MII_TG3_FET_PTEST_TRIM_2;
  5706. tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
  5707. }
  5708. } else
  5709. bmcr |= BMCR_LOOPBACK;
  5710. tg3_writephy(tp, MII_BMCR, bmcr);
  5711. /* The write needs to be flushed for the FETs */
  5712. if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  5713. tg3_readphy(tp, MII_BMCR, &bmcr);
  5714. udelay(40);
  5715. if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  5716. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
  5717. tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
  5718. MII_TG3_FET_PTEST_FRC_TX_LINK |
  5719. MII_TG3_FET_PTEST_FRC_TX_LOCK);
  5720. /* The write needs to be flushed for the AC131 */
  5721. tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
  5722. }
  5723. /* Reset to prevent losing 1st rx packet intermittently */
  5724. if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  5725. tg3_flag(tp, 5780_CLASS)) {
  5726. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  5727. udelay(10);
  5728. tw32_f(MAC_RX_MODE, tp->rx_mode);
  5729. }
  5730. mac_mode = tp->mac_mode &
  5731. ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  5732. if (speed == SPEED_1000)
  5733. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  5734. else
  5735. mac_mode |= MAC_MODE_PORT_MODE_MII;
  5736. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  5737. u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
  5738. if (masked_phy_id == TG3_PHY_ID_BCM5401)
  5739. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  5740. else if (masked_phy_id == TG3_PHY_ID_BCM5411)
  5741. mac_mode |= MAC_MODE_LINK_POLARITY;
  5742. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  5743. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  5744. }
  5745. tw32(MAC_MODE, mac_mode);
  5746. udelay(40);
  5747. return 0;
  5748. }
  5749. static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
  5750. {
  5751. struct tg3 *tp = netdev_priv(dev);
  5752. if (features & NETIF_F_LOOPBACK) {
  5753. if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
  5754. return;
  5755. spin_lock_bh(&tp->lock);
  5756. tg3_mac_loopback(tp, true);
  5757. netif_carrier_on(tp->dev);
  5758. spin_unlock_bh(&tp->lock);
  5759. netdev_info(dev, "Internal MAC loopback mode enabled.\n");
  5760. } else {
  5761. if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
  5762. return;
  5763. spin_lock_bh(&tp->lock);
  5764. tg3_mac_loopback(tp, false);
  5765. /* Force link status check */
  5766. tg3_setup_phy(tp, 1);
  5767. spin_unlock_bh(&tp->lock);
  5768. netdev_info(dev, "Internal MAC loopback mode disabled.\n");
  5769. }
  5770. }
  5771. static netdev_features_t tg3_fix_features(struct net_device *dev,
  5772. netdev_features_t features)
  5773. {
  5774. struct tg3 *tp = netdev_priv(dev);
  5775. if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
  5776. features &= ~NETIF_F_ALL_TSO;
  5777. return features;
  5778. }
  5779. static int tg3_set_features(struct net_device *dev, netdev_features_t features)
  5780. {
  5781. netdev_features_t changed = dev->features ^ features;
  5782. if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
  5783. tg3_set_loopback(dev, features);
  5784. return 0;
  5785. }
  5786. static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
  5787. int new_mtu)
  5788. {
  5789. dev->mtu = new_mtu;
  5790. if (new_mtu > ETH_DATA_LEN) {
  5791. if (tg3_flag(tp, 5780_CLASS)) {
  5792. netdev_update_features(dev);
  5793. tg3_flag_clear(tp, TSO_CAPABLE);
  5794. } else {
  5795. tg3_flag_set(tp, JUMBO_RING_ENABLE);
  5796. }
  5797. } else {
  5798. if (tg3_flag(tp, 5780_CLASS)) {
  5799. tg3_flag_set(tp, TSO_CAPABLE);
  5800. netdev_update_features(dev);
  5801. }
  5802. tg3_flag_clear(tp, JUMBO_RING_ENABLE);
  5803. }
  5804. }
  5805. static int tg3_change_mtu(struct net_device *dev, int new_mtu)
  5806. {
  5807. struct tg3 *tp = netdev_priv(dev);
  5808. int err;
  5809. if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
  5810. return -EINVAL;
  5811. if (!netif_running(dev)) {
  5812. /* We'll just catch it later when the
  5813. * device is up'd.
  5814. */
  5815. tg3_set_mtu(dev, tp, new_mtu);
  5816. return 0;
  5817. }
  5818. tg3_phy_stop(tp);
  5819. tg3_netif_stop(tp);
  5820. tg3_full_lock(tp, 1);
  5821. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  5822. tg3_set_mtu(dev, tp, new_mtu);
  5823. err = tg3_restart_hw(tp, 0);
  5824. if (!err)
  5825. tg3_netif_start(tp);
  5826. tg3_full_unlock(tp);
  5827. if (!err)
  5828. tg3_phy_start(tp);
  5829. return err;
  5830. }
  5831. static void tg3_rx_prodring_free(struct tg3 *tp,
  5832. struct tg3_rx_prodring_set *tpr)
  5833. {
  5834. int i;
  5835. if (tpr != &tp->napi[0].prodring) {
  5836. for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
  5837. i = (i + 1) & tp->rx_std_ring_mask)
  5838. tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
  5839. tp->rx_pkt_map_sz);
  5840. if (tg3_flag(tp, JUMBO_CAPABLE)) {
  5841. for (i = tpr->rx_jmb_cons_idx;
  5842. i != tpr->rx_jmb_prod_idx;
  5843. i = (i + 1) & tp->rx_jmb_ring_mask) {
  5844. tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
  5845. TG3_RX_JMB_MAP_SZ);
  5846. }
  5847. }
  5848. return;
  5849. }
  5850. for (i = 0; i <= tp->rx_std_ring_mask; i++)
  5851. tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
  5852. tp->rx_pkt_map_sz);
  5853. if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
  5854. for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
  5855. tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
  5856. TG3_RX_JMB_MAP_SZ);
  5857. }
  5858. }
  5859. /* Initialize rx rings for packet processing.
  5860. *
  5861. * The chip has been shut down and the driver detached from
  5862. * the networking, so no interrupts or new tx packets will
  5863. * end up in the driver. tp->{tx,}lock are held and thus
  5864. * we may not sleep.
  5865. */
  5866. static int tg3_rx_prodring_alloc(struct tg3 *tp,
  5867. struct tg3_rx_prodring_set *tpr)
  5868. {
  5869. u32 i, rx_pkt_dma_sz;
  5870. tpr->rx_std_cons_idx = 0;
  5871. tpr->rx_std_prod_idx = 0;
  5872. tpr->rx_jmb_cons_idx = 0;
  5873. tpr->rx_jmb_prod_idx = 0;
  5874. if (tpr != &tp->napi[0].prodring) {
  5875. memset(&tpr->rx_std_buffers[0], 0,
  5876. TG3_RX_STD_BUFF_RING_SIZE(tp));
  5877. if (tpr->rx_jmb_buffers)
  5878. memset(&tpr->rx_jmb_buffers[0], 0,
  5879. TG3_RX_JMB_BUFF_RING_SIZE(tp));
  5880. goto done;
  5881. }
  5882. /* Zero out all descriptors. */
  5883. memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
  5884. rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
  5885. if (tg3_flag(tp, 5780_CLASS) &&
  5886. tp->dev->mtu > ETH_DATA_LEN)
  5887. rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
  5888. tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
  5889. /* Initialize invariants of the rings, we only set this
  5890. * stuff once. This works because the card does not
  5891. * write into the rx buffer posting rings.
  5892. */
  5893. for (i = 0; i <= tp->rx_std_ring_mask; i++) {
  5894. struct tg3_rx_buffer_desc *rxd;
  5895. rxd = &tpr->rx_std[i];
  5896. rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
  5897. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
  5898. rxd->opaque = (RXD_OPAQUE_RING_STD |
  5899. (i << RXD_OPAQUE_INDEX_SHIFT));
  5900. }
  5901. /* Now allocate fresh SKBs for each rx ring. */
  5902. for (i = 0; i < tp->rx_pending; i++) {
  5903. if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
  5904. netdev_warn(tp->dev,
  5905. "Using a smaller RX standard ring. Only "
  5906. "%d out of %d buffers were allocated "
  5907. "successfully\n", i, tp->rx_pending);
  5908. if (i == 0)
  5909. goto initfail;
  5910. tp->rx_pending = i;
  5911. break;
  5912. }
  5913. }
  5914. if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
  5915. goto done;
  5916. memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
  5917. if (!tg3_flag(tp, JUMBO_RING_ENABLE))
  5918. goto done;
  5919. for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
  5920. struct tg3_rx_buffer_desc *rxd;
  5921. rxd = &tpr->rx_jmb[i].std;
  5922. rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
  5923. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
  5924. RXD_FLAG_JUMBO;
  5925. rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
  5926. (i << RXD_OPAQUE_INDEX_SHIFT));
  5927. }
  5928. for (i = 0; i < tp->rx_jumbo_pending; i++) {
  5929. if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
  5930. netdev_warn(tp->dev,
  5931. "Using a smaller RX jumbo ring. Only %d "
  5932. "out of %d buffers were allocated "
  5933. "successfully\n", i, tp->rx_jumbo_pending);
  5934. if (i == 0)
  5935. goto initfail;
  5936. tp->rx_jumbo_pending = i;
  5937. break;
  5938. }
  5939. }
  5940. done:
  5941. return 0;
  5942. initfail:
  5943. tg3_rx_prodring_free(tp, tpr);
  5944. return -ENOMEM;
  5945. }
  5946. static void tg3_rx_prodring_fini(struct tg3 *tp,
  5947. struct tg3_rx_prodring_set *tpr)
  5948. {
  5949. kfree(tpr->rx_std_buffers);
  5950. tpr->rx_std_buffers = NULL;
  5951. kfree(tpr->rx_jmb_buffers);
  5952. tpr->rx_jmb_buffers = NULL;
  5953. if (tpr->rx_std) {
  5954. dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
  5955. tpr->rx_std, tpr->rx_std_mapping);
  5956. tpr->rx_std = NULL;
  5957. }
  5958. if (tpr->rx_jmb) {
  5959. dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
  5960. tpr->rx_jmb, tpr->rx_jmb_mapping);
  5961. tpr->rx_jmb = NULL;
  5962. }
  5963. }
  5964. static int tg3_rx_prodring_init(struct tg3 *tp,
  5965. struct tg3_rx_prodring_set *tpr)
  5966. {
  5967. tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
  5968. GFP_KERNEL);
  5969. if (!tpr->rx_std_buffers)
  5970. return -ENOMEM;
  5971. tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
  5972. TG3_RX_STD_RING_BYTES(tp),
  5973. &tpr->rx_std_mapping,
  5974. GFP_KERNEL);
  5975. if (!tpr->rx_std)
  5976. goto err_out;
  5977. if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
  5978. tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
  5979. GFP_KERNEL);
  5980. if (!tpr->rx_jmb_buffers)
  5981. goto err_out;
  5982. tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
  5983. TG3_RX_JMB_RING_BYTES(tp),
  5984. &tpr->rx_jmb_mapping,
  5985. GFP_KERNEL);
  5986. if (!tpr->rx_jmb)
  5987. goto err_out;
  5988. }
  5989. return 0;
  5990. err_out:
  5991. tg3_rx_prodring_fini(tp, tpr);
  5992. return -ENOMEM;
  5993. }
  5994. /* Free up pending packets in all rx/tx rings.
  5995. *
  5996. * The chip has been shut down and the driver detached from
  5997. * the networking, so no interrupts or new tx packets will
  5998. * end up in the driver. tp->{tx,}lock is not held and we are not
  5999. * in an interrupt context and thus may sleep.
  6000. */
  6001. static void tg3_free_rings(struct tg3 *tp)
  6002. {
  6003. int i, j;
  6004. for (j = 0; j < tp->irq_cnt; j++) {
  6005. struct tg3_napi *tnapi = &tp->napi[j];
  6006. tg3_rx_prodring_free(tp, &tnapi->prodring);
  6007. if (!tnapi->tx_buffers)
  6008. continue;
  6009. for (i = 0; i < TG3_TX_RING_SIZE; i++) {
  6010. struct sk_buff *skb = tnapi->tx_buffers[i].skb;
  6011. if (!skb)
  6012. continue;
  6013. tg3_tx_skb_unmap(tnapi, i,
  6014. skb_shinfo(skb)->nr_frags - 1);
  6015. dev_kfree_skb_any(skb);
  6016. }
  6017. }
  6018. }
  6019. /* Initialize tx/rx rings for packet processing.
  6020. *
  6021. * The chip has been shut down and the driver detached from
  6022. * the networking, so no interrupts or new tx packets will
  6023. * end up in the driver. tp->{tx,}lock are held and thus
  6024. * we may not sleep.
  6025. */
  6026. static int tg3_init_rings(struct tg3 *tp)
  6027. {
  6028. int i;
  6029. /* Free up all the SKBs. */
  6030. tg3_free_rings(tp);
  6031. for (i = 0; i < tp->irq_cnt; i++) {
  6032. struct tg3_napi *tnapi = &tp->napi[i];
  6033. tnapi->last_tag = 0;
  6034. tnapi->last_irq_tag = 0;
  6035. tnapi->hw_status->status = 0;
  6036. tnapi->hw_status->status_tag = 0;
  6037. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6038. tnapi->tx_prod = 0;
  6039. tnapi->tx_cons = 0;
  6040. if (tnapi->tx_ring)
  6041. memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
  6042. tnapi->rx_rcb_ptr = 0;
  6043. if (tnapi->rx_rcb)
  6044. memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  6045. if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
  6046. tg3_free_rings(tp);
  6047. return -ENOMEM;
  6048. }
  6049. }
  6050. return 0;
  6051. }
  6052. /*
  6053. * Must not be invoked with interrupt sources disabled and
  6054. * the hardware shutdown down.
  6055. */
  6056. static void tg3_free_consistent(struct tg3 *tp)
  6057. {
  6058. int i;
  6059. for (i = 0; i < tp->irq_cnt; i++) {
  6060. struct tg3_napi *tnapi = &tp->napi[i];
  6061. if (tnapi->tx_ring) {
  6062. dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
  6063. tnapi->tx_ring, tnapi->tx_desc_mapping);
  6064. tnapi->tx_ring = NULL;
  6065. }
  6066. kfree(tnapi->tx_buffers);
  6067. tnapi->tx_buffers = NULL;
  6068. if (tnapi->rx_rcb) {
  6069. dma_free_coherent(&tp->pdev->dev,
  6070. TG3_RX_RCB_RING_BYTES(tp),
  6071. tnapi->rx_rcb,
  6072. tnapi->rx_rcb_mapping);
  6073. tnapi->rx_rcb = NULL;
  6074. }
  6075. tg3_rx_prodring_fini(tp, &tnapi->prodring);
  6076. if (tnapi->hw_status) {
  6077. dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
  6078. tnapi->hw_status,
  6079. tnapi->status_mapping);
  6080. tnapi->hw_status = NULL;
  6081. }
  6082. }
  6083. if (tp->hw_stats) {
  6084. dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
  6085. tp->hw_stats, tp->stats_mapping);
  6086. tp->hw_stats = NULL;
  6087. }
  6088. }
  6089. /*
  6090. * Must not be invoked with interrupt sources disabled and
  6091. * the hardware shutdown down. Can sleep.
  6092. */
  6093. static int tg3_alloc_consistent(struct tg3 *tp)
  6094. {
  6095. int i;
  6096. tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
  6097. sizeof(struct tg3_hw_stats),
  6098. &tp->stats_mapping,
  6099. GFP_KERNEL);
  6100. if (!tp->hw_stats)
  6101. goto err_out;
  6102. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  6103. for (i = 0; i < tp->irq_cnt; i++) {
  6104. struct tg3_napi *tnapi = &tp->napi[i];
  6105. struct tg3_hw_status *sblk;
  6106. tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
  6107. TG3_HW_STATUS_SIZE,
  6108. &tnapi->status_mapping,
  6109. GFP_KERNEL);
  6110. if (!tnapi->hw_status)
  6111. goto err_out;
  6112. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6113. sblk = tnapi->hw_status;
  6114. if (tg3_rx_prodring_init(tp, &tnapi->prodring))
  6115. goto err_out;
  6116. /* If multivector TSS is enabled, vector 0 does not handle
  6117. * tx interrupts. Don't allocate any resources for it.
  6118. */
  6119. if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
  6120. (i && tg3_flag(tp, ENABLE_TSS))) {
  6121. tnapi->tx_buffers = kzalloc(
  6122. sizeof(struct tg3_tx_ring_info) *
  6123. TG3_TX_RING_SIZE, GFP_KERNEL);
  6124. if (!tnapi->tx_buffers)
  6125. goto err_out;
  6126. tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
  6127. TG3_TX_RING_BYTES,
  6128. &tnapi->tx_desc_mapping,
  6129. GFP_KERNEL);
  6130. if (!tnapi->tx_ring)
  6131. goto err_out;
  6132. }
  6133. /*
  6134. * When RSS is enabled, the status block format changes
  6135. * slightly. The "rx_jumbo_consumer", "reserved",
  6136. * and "rx_mini_consumer" members get mapped to the
  6137. * other three rx return ring producer indexes.
  6138. */
  6139. switch (i) {
  6140. default:
  6141. tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
  6142. break;
  6143. case 2:
  6144. tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
  6145. break;
  6146. case 3:
  6147. tnapi->rx_rcb_prod_idx = &sblk->reserved;
  6148. break;
  6149. case 4:
  6150. tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
  6151. break;
  6152. }
  6153. /*
  6154. * If multivector RSS is enabled, vector 0 does not handle
  6155. * rx or tx interrupts. Don't allocate any resources for it.
  6156. */
  6157. if (!i && tg3_flag(tp, ENABLE_RSS))
  6158. continue;
  6159. tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
  6160. TG3_RX_RCB_RING_BYTES(tp),
  6161. &tnapi->rx_rcb_mapping,
  6162. GFP_KERNEL);
  6163. if (!tnapi->rx_rcb)
  6164. goto err_out;
  6165. memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  6166. }
  6167. return 0;
  6168. err_out:
  6169. tg3_free_consistent(tp);
  6170. return -ENOMEM;
  6171. }
  6172. #define MAX_WAIT_CNT 1000
  6173. /* To stop a block, clear the enable bit and poll till it
  6174. * clears. tp->lock is held.
  6175. */
  6176. static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
  6177. {
  6178. unsigned int i;
  6179. u32 val;
  6180. if (tg3_flag(tp, 5705_PLUS)) {
  6181. switch (ofs) {
  6182. case RCVLSC_MODE:
  6183. case DMAC_MODE:
  6184. case MBFREE_MODE:
  6185. case BUFMGR_MODE:
  6186. case MEMARB_MODE:
  6187. /* We can't enable/disable these bits of the
  6188. * 5705/5750, just say success.
  6189. */
  6190. return 0;
  6191. default:
  6192. break;
  6193. }
  6194. }
  6195. val = tr32(ofs);
  6196. val &= ~enable_bit;
  6197. tw32_f(ofs, val);
  6198. for (i = 0; i < MAX_WAIT_CNT; i++) {
  6199. udelay(100);
  6200. val = tr32(ofs);
  6201. if ((val & enable_bit) == 0)
  6202. break;
  6203. }
  6204. if (i == MAX_WAIT_CNT && !silent) {
  6205. dev_err(&tp->pdev->dev,
  6206. "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
  6207. ofs, enable_bit);
  6208. return -ENODEV;
  6209. }
  6210. return 0;
  6211. }
  6212. /* tp->lock is held. */
  6213. static int tg3_abort_hw(struct tg3 *tp, int silent)
  6214. {
  6215. int i, err;
  6216. tg3_disable_ints(tp);
  6217. tp->rx_mode &= ~RX_MODE_ENABLE;
  6218. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6219. udelay(10);
  6220. err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
  6221. err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
  6222. err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
  6223. err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
  6224. err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
  6225. err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
  6226. err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
  6227. err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
  6228. err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
  6229. err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
  6230. err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
  6231. err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
  6232. err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
  6233. tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  6234. tw32_f(MAC_MODE, tp->mac_mode);
  6235. udelay(40);
  6236. tp->tx_mode &= ~TX_MODE_ENABLE;
  6237. tw32_f(MAC_TX_MODE, tp->tx_mode);
  6238. for (i = 0; i < MAX_WAIT_CNT; i++) {
  6239. udelay(100);
  6240. if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
  6241. break;
  6242. }
  6243. if (i >= MAX_WAIT_CNT) {
  6244. dev_err(&tp->pdev->dev,
  6245. "%s timed out, TX_MODE_ENABLE will not clear "
  6246. "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
  6247. err |= -ENODEV;
  6248. }
  6249. err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
  6250. err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
  6251. err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
  6252. tw32(FTQ_RESET, 0xffffffff);
  6253. tw32(FTQ_RESET, 0x00000000);
  6254. err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
  6255. err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
  6256. for (i = 0; i < tp->irq_cnt; i++) {
  6257. struct tg3_napi *tnapi = &tp->napi[i];
  6258. if (tnapi->hw_status)
  6259. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6260. }
  6261. if (tp->hw_stats)
  6262. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  6263. return err;
  6264. }
  6265. /* Save PCI command register before chip reset */
  6266. static void tg3_save_pci_state(struct tg3 *tp)
  6267. {
  6268. pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
  6269. }
  6270. /* Restore PCI state after chip reset */
  6271. static void tg3_restore_pci_state(struct tg3 *tp)
  6272. {
  6273. u32 val;
  6274. /* Re-enable indirect register accesses. */
  6275. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  6276. tp->misc_host_ctrl);
  6277. /* Set MAX PCI retry to zero. */
  6278. val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
  6279. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  6280. tg3_flag(tp, PCIX_MODE))
  6281. val |= PCISTATE_RETRY_SAME_DMA;
  6282. /* Allow reads and writes to the APE register and memory space. */
  6283. if (tg3_flag(tp, ENABLE_APE))
  6284. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  6285. PCISTATE_ALLOW_APE_SHMEM_WR |
  6286. PCISTATE_ALLOW_APE_PSPACE_WR;
  6287. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
  6288. pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
  6289. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
  6290. if (tg3_flag(tp, PCI_EXPRESS))
  6291. pcie_set_readrq(tp->pdev, tp->pcie_readrq);
  6292. else {
  6293. pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  6294. tp->pci_cacheline_sz);
  6295. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  6296. tp->pci_lat_timer);
  6297. }
  6298. }
  6299. /* Make sure PCI-X relaxed ordering bit is clear. */
  6300. if (tg3_flag(tp, PCIX_MODE)) {
  6301. u16 pcix_cmd;
  6302. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  6303. &pcix_cmd);
  6304. pcix_cmd &= ~PCI_X_CMD_ERO;
  6305. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  6306. pcix_cmd);
  6307. }
  6308. if (tg3_flag(tp, 5780_CLASS)) {
  6309. /* Chip reset on 5780 will reset MSI enable bit,
  6310. * so need to restore it.
  6311. */
  6312. if (tg3_flag(tp, USING_MSI)) {
  6313. u16 ctrl;
  6314. pci_read_config_word(tp->pdev,
  6315. tp->msi_cap + PCI_MSI_FLAGS,
  6316. &ctrl);
  6317. pci_write_config_word(tp->pdev,
  6318. tp->msi_cap + PCI_MSI_FLAGS,
  6319. ctrl | PCI_MSI_FLAGS_ENABLE);
  6320. val = tr32(MSGINT_MODE);
  6321. tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
  6322. }
  6323. }
  6324. }
  6325. /* tp->lock is held. */
  6326. static int tg3_chip_reset(struct tg3 *tp)
  6327. {
  6328. u32 val;
  6329. void (*write_op)(struct tg3 *, u32, u32);
  6330. int i, err;
  6331. tg3_nvram_lock(tp);
  6332. tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
  6333. /* No matching tg3_nvram_unlock() after this because
  6334. * chip reset below will undo the nvram lock.
  6335. */
  6336. tp->nvram_lock_cnt = 0;
  6337. /* GRC_MISC_CFG core clock reset will clear the memory
  6338. * enable bit in PCI register 4 and the MSI enable bit
  6339. * on some chips, so we save relevant registers here.
  6340. */
  6341. tg3_save_pci_state(tp);
  6342. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  6343. tg3_flag(tp, 5755_PLUS))
  6344. tw32(GRC_FASTBOOT_PC, 0);
  6345. /*
  6346. * We must avoid the readl() that normally takes place.
  6347. * It locks machines, causes machine checks, and other
  6348. * fun things. So, temporarily disable the 5701
  6349. * hardware workaround, while we do the reset.
  6350. */
  6351. write_op = tp->write32;
  6352. if (write_op == tg3_write_flush_reg32)
  6353. tp->write32 = tg3_write32;
  6354. /* Prevent the irq handler from reading or writing PCI registers
  6355. * during chip reset when the memory enable bit in the PCI command
  6356. * register may be cleared. The chip does not generate interrupt
  6357. * at this time, but the irq handler may still be called due to irq
  6358. * sharing or irqpoll.
  6359. */
  6360. tg3_flag_set(tp, CHIP_RESETTING);
  6361. for (i = 0; i < tp->irq_cnt; i++) {
  6362. struct tg3_napi *tnapi = &tp->napi[i];
  6363. if (tnapi->hw_status) {
  6364. tnapi->hw_status->status = 0;
  6365. tnapi->hw_status->status_tag = 0;
  6366. }
  6367. tnapi->last_tag = 0;
  6368. tnapi->last_irq_tag = 0;
  6369. }
  6370. smp_mb();
  6371. for (i = 0; i < tp->irq_cnt; i++)
  6372. synchronize_irq(tp->napi[i].irq_vec);
  6373. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
  6374. val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
  6375. tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
  6376. }
  6377. /* do the reset */
  6378. val = GRC_MISC_CFG_CORECLK_RESET;
  6379. if (tg3_flag(tp, PCI_EXPRESS)) {
  6380. /* Force PCIe 1.0a mode */
  6381. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
  6382. !tg3_flag(tp, 57765_PLUS) &&
  6383. tr32(TG3_PCIE_PHY_TSTCTL) ==
  6384. (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
  6385. tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
  6386. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  6387. tw32(GRC_MISC_CFG, (1 << 29));
  6388. val |= (1 << 29);
  6389. }
  6390. }
  6391. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  6392. tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
  6393. tw32(GRC_VCPU_EXT_CTRL,
  6394. tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
  6395. }
  6396. /* Manage gphy power for all CPMU absent PCIe devices. */
  6397. if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
  6398. val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  6399. tw32(GRC_MISC_CFG, val);
  6400. /* restore 5701 hardware bug workaround write method */
  6401. tp->write32 = write_op;
  6402. /* Unfortunately, we have to delay before the PCI read back.
  6403. * Some 575X chips even will not respond to a PCI cfg access
  6404. * when the reset command is given to the chip.
  6405. *
  6406. * How do these hardware designers expect things to work
  6407. * properly if the PCI write is posted for a long period
  6408. * of time? It is always necessary to have some method by
  6409. * which a register read back can occur to push the write
  6410. * out which does the reset.
  6411. *
  6412. * For most tg3 variants the trick below was working.
  6413. * Ho hum...
  6414. */
  6415. udelay(120);
  6416. /* Flush PCI posted writes. The normal MMIO registers
  6417. * are inaccessible at this time so this is the only
  6418. * way to make this reliably (actually, this is no longer
  6419. * the case, see above). I tried to use indirect
  6420. * register read/write but this upset some 5701 variants.
  6421. */
  6422. pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
  6423. udelay(120);
  6424. if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
  6425. u16 val16;
  6426. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
  6427. int i;
  6428. u32 cfg_val;
  6429. /* Wait for link training to complete. */
  6430. for (i = 0; i < 5000; i++)
  6431. udelay(100);
  6432. pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
  6433. pci_write_config_dword(tp->pdev, 0xc4,
  6434. cfg_val | (1 << 15));
  6435. }
  6436. /* Clear the "no snoop" and "relaxed ordering" bits. */
  6437. pci_read_config_word(tp->pdev,
  6438. pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
  6439. &val16);
  6440. val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
  6441. PCI_EXP_DEVCTL_NOSNOOP_EN);
  6442. /*
  6443. * Older PCIe devices only support the 128 byte
  6444. * MPS setting. Enforce the restriction.
  6445. */
  6446. if (!tg3_flag(tp, CPMU_PRESENT))
  6447. val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
  6448. pci_write_config_word(tp->pdev,
  6449. pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
  6450. val16);
  6451. pcie_set_readrq(tp->pdev, tp->pcie_readrq);
  6452. /* Clear error status */
  6453. pci_write_config_word(tp->pdev,
  6454. pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
  6455. PCI_EXP_DEVSTA_CED |
  6456. PCI_EXP_DEVSTA_NFED |
  6457. PCI_EXP_DEVSTA_FED |
  6458. PCI_EXP_DEVSTA_URD);
  6459. }
  6460. tg3_restore_pci_state(tp);
  6461. tg3_flag_clear(tp, CHIP_RESETTING);
  6462. tg3_flag_clear(tp, ERROR_PROCESSED);
  6463. val = 0;
  6464. if (tg3_flag(tp, 5780_CLASS))
  6465. val = tr32(MEMARB_MODE);
  6466. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  6467. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
  6468. tg3_stop_fw(tp);
  6469. tw32(0x5000, 0x400);
  6470. }
  6471. tw32(GRC_MODE, tp->grc_mode);
  6472. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
  6473. val = tr32(0xc4);
  6474. tw32(0xc4, val | (1 << 15));
  6475. }
  6476. if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
  6477. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  6478. tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
  6479. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
  6480. tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
  6481. tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  6482. }
  6483. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  6484. tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
  6485. val = tp->mac_mode;
  6486. } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
  6487. tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
  6488. val = tp->mac_mode;
  6489. } else
  6490. val = 0;
  6491. tw32_f(MAC_MODE, val);
  6492. udelay(40);
  6493. tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
  6494. err = tg3_poll_fw(tp);
  6495. if (err)
  6496. return err;
  6497. tg3_mdio_start(tp);
  6498. if (tg3_flag(tp, PCI_EXPRESS) &&
  6499. tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
  6500. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
  6501. !tg3_flag(tp, 57765_PLUS)) {
  6502. val = tr32(0x7c00);
  6503. tw32(0x7c00, val | (1 << 25));
  6504. }
  6505. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
  6506. val = tr32(TG3_CPMU_CLCK_ORIDE);
  6507. tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
  6508. }
  6509. /* Reprobe ASF enable state. */
  6510. tg3_flag_clear(tp, ENABLE_ASF);
  6511. tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
  6512. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  6513. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  6514. u32 nic_cfg;
  6515. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  6516. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  6517. tg3_flag_set(tp, ENABLE_ASF);
  6518. tp->last_event_jiffies = jiffies;
  6519. if (tg3_flag(tp, 5750_PLUS))
  6520. tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
  6521. }
  6522. }
  6523. return 0;
  6524. }
  6525. /* tp->lock is held. */
  6526. static int tg3_halt(struct tg3 *tp, int kind, int silent)
  6527. {
  6528. int err;
  6529. tg3_stop_fw(tp);
  6530. tg3_write_sig_pre_reset(tp, kind);
  6531. tg3_abort_hw(tp, silent);
  6532. err = tg3_chip_reset(tp);
  6533. __tg3_set_mac_addr(tp, 0);
  6534. tg3_write_sig_legacy(tp, kind);
  6535. tg3_write_sig_post_reset(tp, kind);
  6536. if (err)
  6537. return err;
  6538. return 0;
  6539. }
  6540. static int tg3_set_mac_addr(struct net_device *dev, void *p)
  6541. {
  6542. struct tg3 *tp = netdev_priv(dev);
  6543. struct sockaddr *addr = p;
  6544. int err = 0, skip_mac_1 = 0;
  6545. if (!is_valid_ether_addr(addr->sa_data))
  6546. return -EINVAL;
  6547. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  6548. if (!netif_running(dev))
  6549. return 0;
  6550. if (tg3_flag(tp, ENABLE_ASF)) {
  6551. u32 addr0_high, addr0_low, addr1_high, addr1_low;
  6552. addr0_high = tr32(MAC_ADDR_0_HIGH);
  6553. addr0_low = tr32(MAC_ADDR_0_LOW);
  6554. addr1_high = tr32(MAC_ADDR_1_HIGH);
  6555. addr1_low = tr32(MAC_ADDR_1_LOW);
  6556. /* Skip MAC addr 1 if ASF is using it. */
  6557. if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
  6558. !(addr1_high == 0 && addr1_low == 0))
  6559. skip_mac_1 = 1;
  6560. }
  6561. spin_lock_bh(&tp->lock);
  6562. __tg3_set_mac_addr(tp, skip_mac_1);
  6563. spin_unlock_bh(&tp->lock);
  6564. return err;
  6565. }
  6566. /* tp->lock is held. */
  6567. static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
  6568. dma_addr_t mapping, u32 maxlen_flags,
  6569. u32 nic_addr)
  6570. {
  6571. tg3_write_mem(tp,
  6572. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6573. ((u64) mapping >> 32));
  6574. tg3_write_mem(tp,
  6575. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
  6576. ((u64) mapping & 0xffffffff));
  6577. tg3_write_mem(tp,
  6578. (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
  6579. maxlen_flags);
  6580. if (!tg3_flag(tp, 5705_PLUS))
  6581. tg3_write_mem(tp,
  6582. (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
  6583. nic_addr);
  6584. }
  6585. static void __tg3_set_rx_mode(struct net_device *);
  6586. static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
  6587. {
  6588. int i;
  6589. if (!tg3_flag(tp, ENABLE_TSS)) {
  6590. tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
  6591. tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
  6592. tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
  6593. } else {
  6594. tw32(HOSTCC_TXCOL_TICKS, 0);
  6595. tw32(HOSTCC_TXMAX_FRAMES, 0);
  6596. tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
  6597. }
  6598. if (!tg3_flag(tp, ENABLE_RSS)) {
  6599. tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
  6600. tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
  6601. tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
  6602. } else {
  6603. tw32(HOSTCC_RXCOL_TICKS, 0);
  6604. tw32(HOSTCC_RXMAX_FRAMES, 0);
  6605. tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
  6606. }
  6607. if (!tg3_flag(tp, 5705_PLUS)) {
  6608. u32 val = ec->stats_block_coalesce_usecs;
  6609. tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
  6610. tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
  6611. if (!netif_carrier_ok(tp->dev))
  6612. val = 0;
  6613. tw32(HOSTCC_STAT_COAL_TICKS, val);
  6614. }
  6615. for (i = 0; i < tp->irq_cnt - 1; i++) {
  6616. u32 reg;
  6617. reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
  6618. tw32(reg, ec->rx_coalesce_usecs);
  6619. reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
  6620. tw32(reg, ec->rx_max_coalesced_frames);
  6621. reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
  6622. tw32(reg, ec->rx_max_coalesced_frames_irq);
  6623. if (tg3_flag(tp, ENABLE_TSS)) {
  6624. reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
  6625. tw32(reg, ec->tx_coalesce_usecs);
  6626. reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
  6627. tw32(reg, ec->tx_max_coalesced_frames);
  6628. reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
  6629. tw32(reg, ec->tx_max_coalesced_frames_irq);
  6630. }
  6631. }
  6632. for (; i < tp->irq_max - 1; i++) {
  6633. tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
  6634. tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
  6635. tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
  6636. if (tg3_flag(tp, ENABLE_TSS)) {
  6637. tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
  6638. tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
  6639. tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
  6640. }
  6641. }
  6642. }
  6643. /* tp->lock is held. */
  6644. static void tg3_rings_reset(struct tg3 *tp)
  6645. {
  6646. int i;
  6647. u32 stblk, txrcb, rxrcb, limit;
  6648. struct tg3_napi *tnapi = &tp->napi[0];
  6649. /* Disable all transmit rings but the first. */
  6650. if (!tg3_flag(tp, 5705_PLUS))
  6651. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
  6652. else if (tg3_flag(tp, 5717_PLUS))
  6653. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
  6654. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  6655. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
  6656. else
  6657. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
  6658. for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
  6659. txrcb < limit; txrcb += TG3_BDINFO_SIZE)
  6660. tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
  6661. BDINFO_FLAGS_DISABLED);
  6662. /* Disable all receive return rings but the first. */
  6663. if (tg3_flag(tp, 5717_PLUS))
  6664. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
  6665. else if (!tg3_flag(tp, 5705_PLUS))
  6666. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
  6667. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  6668. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  6669. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
  6670. else
  6671. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
  6672. for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
  6673. rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
  6674. tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
  6675. BDINFO_FLAGS_DISABLED);
  6676. /* Disable interrupts */
  6677. tw32_mailbox_f(tp->napi[0].int_mbox, 1);
  6678. tp->napi[0].chk_msi_cnt = 0;
  6679. tp->napi[0].last_rx_cons = 0;
  6680. tp->napi[0].last_tx_cons = 0;
  6681. /* Zero mailbox registers. */
  6682. if (tg3_flag(tp, SUPPORT_MSIX)) {
  6683. for (i = 1; i < tp->irq_max; i++) {
  6684. tp->napi[i].tx_prod = 0;
  6685. tp->napi[i].tx_cons = 0;
  6686. if (tg3_flag(tp, ENABLE_TSS))
  6687. tw32_mailbox(tp->napi[i].prodmbox, 0);
  6688. tw32_rx_mbox(tp->napi[i].consmbox, 0);
  6689. tw32_mailbox_f(tp->napi[i].int_mbox, 1);
  6690. tp->napi[i].chk_msi_cnt = 0;
  6691. tp->napi[i].last_rx_cons = 0;
  6692. tp->napi[i].last_tx_cons = 0;
  6693. }
  6694. if (!tg3_flag(tp, ENABLE_TSS))
  6695. tw32_mailbox(tp->napi[0].prodmbox, 0);
  6696. } else {
  6697. tp->napi[0].tx_prod = 0;
  6698. tp->napi[0].tx_cons = 0;
  6699. tw32_mailbox(tp->napi[0].prodmbox, 0);
  6700. tw32_rx_mbox(tp->napi[0].consmbox, 0);
  6701. }
  6702. /* Make sure the NIC-based send BD rings are disabled. */
  6703. if (!tg3_flag(tp, 5705_PLUS)) {
  6704. u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
  6705. for (i = 0; i < 16; i++)
  6706. tw32_tx_mbox(mbox + i * 8, 0);
  6707. }
  6708. txrcb = NIC_SRAM_SEND_RCB;
  6709. rxrcb = NIC_SRAM_RCV_RET_RCB;
  6710. /* Clear status block in ram. */
  6711. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6712. /* Set status block DMA address */
  6713. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6714. ((u64) tnapi->status_mapping >> 32));
  6715. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  6716. ((u64) tnapi->status_mapping & 0xffffffff));
  6717. if (tnapi->tx_ring) {
  6718. tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
  6719. (TG3_TX_RING_SIZE <<
  6720. BDINFO_FLAGS_MAXLEN_SHIFT),
  6721. NIC_SRAM_TX_BUFFER_DESC);
  6722. txrcb += TG3_BDINFO_SIZE;
  6723. }
  6724. if (tnapi->rx_rcb) {
  6725. tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
  6726. (tp->rx_ret_ring_mask + 1) <<
  6727. BDINFO_FLAGS_MAXLEN_SHIFT, 0);
  6728. rxrcb += TG3_BDINFO_SIZE;
  6729. }
  6730. stblk = HOSTCC_STATBLCK_RING1;
  6731. for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
  6732. u64 mapping = (u64)tnapi->status_mapping;
  6733. tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
  6734. tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
  6735. /* Clear status block in ram. */
  6736. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6737. if (tnapi->tx_ring) {
  6738. tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
  6739. (TG3_TX_RING_SIZE <<
  6740. BDINFO_FLAGS_MAXLEN_SHIFT),
  6741. NIC_SRAM_TX_BUFFER_DESC);
  6742. txrcb += TG3_BDINFO_SIZE;
  6743. }
  6744. tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
  6745. ((tp->rx_ret_ring_mask + 1) <<
  6746. BDINFO_FLAGS_MAXLEN_SHIFT), 0);
  6747. stblk += 8;
  6748. rxrcb += TG3_BDINFO_SIZE;
  6749. }
  6750. }
  6751. static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
  6752. {
  6753. u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
  6754. if (!tg3_flag(tp, 5750_PLUS) ||
  6755. tg3_flag(tp, 5780_CLASS) ||
  6756. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  6757. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  6758. tg3_flag(tp, 57765_PLUS))
  6759. bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
  6760. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  6761. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
  6762. bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
  6763. else
  6764. bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
  6765. nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
  6766. host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
  6767. val = min(nic_rep_thresh, host_rep_thresh);
  6768. tw32(RCVBDI_STD_THRESH, val);
  6769. if (tg3_flag(tp, 57765_PLUS))
  6770. tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
  6771. if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
  6772. return;
  6773. bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
  6774. host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
  6775. val = min(bdcache_maxcnt / 2, host_rep_thresh);
  6776. tw32(RCVBDI_JUMBO_THRESH, val);
  6777. if (tg3_flag(tp, 57765_PLUS))
  6778. tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
  6779. }
  6780. /* tp->lock is held. */
  6781. static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
  6782. {
  6783. u32 val, rdmac_mode;
  6784. int i, err, limit;
  6785. struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
  6786. tg3_disable_ints(tp);
  6787. tg3_stop_fw(tp);
  6788. tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
  6789. if (tg3_flag(tp, INIT_COMPLETE))
  6790. tg3_abort_hw(tp, 1);
  6791. /* Enable MAC control of LPI */
  6792. if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
  6793. tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
  6794. TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
  6795. TG3_CPMU_EEE_LNKIDL_UART_IDL);
  6796. tw32_f(TG3_CPMU_EEE_CTRL,
  6797. TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
  6798. val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
  6799. TG3_CPMU_EEEMD_LPI_IN_TX |
  6800. TG3_CPMU_EEEMD_LPI_IN_RX |
  6801. TG3_CPMU_EEEMD_EEE_ENABLE;
  6802. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
  6803. val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
  6804. if (tg3_flag(tp, ENABLE_APE))
  6805. val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
  6806. tw32_f(TG3_CPMU_EEE_MODE, val);
  6807. tw32_f(TG3_CPMU_EEE_DBTMR1,
  6808. TG3_CPMU_DBTMR1_PCIEXIT_2047US |
  6809. TG3_CPMU_DBTMR1_LNKIDLE_2047US);
  6810. tw32_f(TG3_CPMU_EEE_DBTMR2,
  6811. TG3_CPMU_DBTMR2_APE_TX_2047US |
  6812. TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
  6813. }
  6814. if (reset_phy)
  6815. tg3_phy_reset(tp);
  6816. err = tg3_chip_reset(tp);
  6817. if (err)
  6818. return err;
  6819. tg3_write_sig_legacy(tp, RESET_KIND_INIT);
  6820. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
  6821. val = tr32(TG3_CPMU_CTRL);
  6822. val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
  6823. tw32(TG3_CPMU_CTRL, val);
  6824. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  6825. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  6826. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  6827. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  6828. val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
  6829. val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
  6830. val |= CPMU_LNK_AWARE_MACCLK_6_25;
  6831. tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
  6832. val = tr32(TG3_CPMU_HST_ACC);
  6833. val &= ~CPMU_HST_ACC_MACCLK_MASK;
  6834. val |= CPMU_HST_ACC_MACCLK_6_25;
  6835. tw32(TG3_CPMU_HST_ACC, val);
  6836. }
  6837. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
  6838. val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
  6839. val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
  6840. PCIE_PWR_MGMT_L1_THRESH_4MS;
  6841. tw32(PCIE_PWR_MGMT_THRESH, val);
  6842. val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
  6843. tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
  6844. tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
  6845. val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
  6846. tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
  6847. }
  6848. if (tg3_flag(tp, L1PLLPD_EN)) {
  6849. u32 grc_mode = tr32(GRC_MODE);
  6850. /* Access the lower 1K of PL PCIE block registers. */
  6851. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  6852. tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
  6853. val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
  6854. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
  6855. val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
  6856. tw32(GRC_MODE, grc_mode);
  6857. }
  6858. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
  6859. if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
  6860. u32 grc_mode = tr32(GRC_MODE);
  6861. /* Access the lower 1K of PL PCIE block registers. */
  6862. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  6863. tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
  6864. val = tr32(TG3_PCIE_TLDLPL_PORT +
  6865. TG3_PCIE_PL_LO_PHYCTL5);
  6866. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
  6867. val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
  6868. tw32(GRC_MODE, grc_mode);
  6869. }
  6870. if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
  6871. u32 grc_mode = tr32(GRC_MODE);
  6872. /* Access the lower 1K of DL PCIE block registers. */
  6873. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  6874. tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
  6875. val = tr32(TG3_PCIE_TLDLPL_PORT +
  6876. TG3_PCIE_DL_LO_FTSMAX);
  6877. val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
  6878. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
  6879. val | TG3_PCIE_DL_LO_FTSMAX_VAL);
  6880. tw32(GRC_MODE, grc_mode);
  6881. }
  6882. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  6883. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  6884. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  6885. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  6886. }
  6887. /* This works around an issue with Athlon chipsets on
  6888. * B3 tigon3 silicon. This bit has no effect on any
  6889. * other revision. But do not set this on PCI Express
  6890. * chips and don't even touch the clocks if the CPMU is present.
  6891. */
  6892. if (!tg3_flag(tp, CPMU_PRESENT)) {
  6893. if (!tg3_flag(tp, PCI_EXPRESS))
  6894. tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  6895. tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  6896. }
  6897. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  6898. tg3_flag(tp, PCIX_MODE)) {
  6899. val = tr32(TG3PCI_PCISTATE);
  6900. val |= PCISTATE_RETRY_SAME_DMA;
  6901. tw32(TG3PCI_PCISTATE, val);
  6902. }
  6903. if (tg3_flag(tp, ENABLE_APE)) {
  6904. /* Allow reads and writes to the
  6905. * APE register and memory space.
  6906. */
  6907. val = tr32(TG3PCI_PCISTATE);
  6908. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  6909. PCISTATE_ALLOW_APE_SHMEM_WR |
  6910. PCISTATE_ALLOW_APE_PSPACE_WR;
  6911. tw32(TG3PCI_PCISTATE, val);
  6912. }
  6913. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
  6914. /* Enable some hw fixes. */
  6915. val = tr32(TG3PCI_MSI_DATA);
  6916. val |= (1 << 26) | (1 << 28) | (1 << 29);
  6917. tw32(TG3PCI_MSI_DATA, val);
  6918. }
  6919. /* Descriptor ring init may make accesses to the
  6920. * NIC SRAM area to setup the TX descriptors, so we
  6921. * can only do this after the hardware has been
  6922. * successfully reset.
  6923. */
  6924. err = tg3_init_rings(tp);
  6925. if (err)
  6926. return err;
  6927. if (tg3_flag(tp, 57765_PLUS)) {
  6928. val = tr32(TG3PCI_DMA_RW_CTRL) &
  6929. ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
  6930. if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
  6931. val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
  6932. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
  6933. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
  6934. val |= DMA_RWCTRL_TAGGED_STAT_WA;
  6935. tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
  6936. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
  6937. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
  6938. /* This value is determined during the probe time DMA
  6939. * engine test, tg3_test_dma.
  6940. */
  6941. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  6942. }
  6943. tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
  6944. GRC_MODE_4X_NIC_SEND_RINGS |
  6945. GRC_MODE_NO_TX_PHDR_CSUM |
  6946. GRC_MODE_NO_RX_PHDR_CSUM);
  6947. tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
  6948. /* Pseudo-header checksum is done by hardware logic and not
  6949. * the offload processers, so make the chip do the pseudo-
  6950. * header checksums on receive. For transmit it is more
  6951. * convenient to do the pseudo-header checksum in software
  6952. * as Linux does that on transmit for us in all cases.
  6953. */
  6954. tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
  6955. tw32(GRC_MODE,
  6956. tp->grc_mode |
  6957. (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
  6958. /* Setup the timer prescalar register. Clock is always 66Mhz. */
  6959. val = tr32(GRC_MISC_CFG);
  6960. val &= ~0xff;
  6961. val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
  6962. tw32(GRC_MISC_CFG, val);
  6963. /* Initialize MBUF/DESC pool. */
  6964. if (tg3_flag(tp, 5750_PLUS)) {
  6965. /* Do nothing. */
  6966. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  6967. tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  6968. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  6969. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  6970. else
  6971. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  6972. tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  6973. tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  6974. } else if (tg3_flag(tp, TSO_CAPABLE)) {
  6975. int fw_len;
  6976. fw_len = tp->fw_len;
  6977. fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
  6978. tw32(BUFMGR_MB_POOL_ADDR,
  6979. NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
  6980. tw32(BUFMGR_MB_POOL_SIZE,
  6981. NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
  6982. }
  6983. if (tp->dev->mtu <= ETH_DATA_LEN) {
  6984. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  6985. tp->bufmgr_config.mbuf_read_dma_low_water);
  6986. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  6987. tp->bufmgr_config.mbuf_mac_rx_low_water);
  6988. tw32(BUFMGR_MB_HIGH_WATER,
  6989. tp->bufmgr_config.mbuf_high_water);
  6990. } else {
  6991. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  6992. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
  6993. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  6994. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
  6995. tw32(BUFMGR_MB_HIGH_WATER,
  6996. tp->bufmgr_config.mbuf_high_water_jumbo);
  6997. }
  6998. tw32(BUFMGR_DMA_LOW_WATER,
  6999. tp->bufmgr_config.dma_low_water);
  7000. tw32(BUFMGR_DMA_HIGH_WATER,
  7001. tp->bufmgr_config.dma_high_water);
  7002. val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
  7003. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
  7004. val |= BUFMGR_MODE_NO_TX_UNDERRUN;
  7005. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  7006. tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
  7007. tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
  7008. val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
  7009. tw32(BUFMGR_MODE, val);
  7010. for (i = 0; i < 2000; i++) {
  7011. if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
  7012. break;
  7013. udelay(10);
  7014. }
  7015. if (i >= 2000) {
  7016. netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
  7017. return -ENODEV;
  7018. }
  7019. if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
  7020. tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
  7021. tg3_setup_rxbd_thresholds(tp);
  7022. /* Initialize TG3_BDINFO's at:
  7023. * RCVDBDI_STD_BD: standard eth size rx ring
  7024. * RCVDBDI_JUMBO_BD: jumbo frame rx ring
  7025. * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
  7026. *
  7027. * like so:
  7028. * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
  7029. * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
  7030. * ring attribute flags
  7031. * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
  7032. *
  7033. * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
  7034. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
  7035. *
  7036. * The size of each ring is fixed in the firmware, but the location is
  7037. * configurable.
  7038. */
  7039. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  7040. ((u64) tpr->rx_std_mapping >> 32));
  7041. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  7042. ((u64) tpr->rx_std_mapping & 0xffffffff));
  7043. if (!tg3_flag(tp, 5717_PLUS))
  7044. tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  7045. NIC_SRAM_RX_BUFFER_DESC);
  7046. /* Disable the mini ring */
  7047. if (!tg3_flag(tp, 5705_PLUS))
  7048. tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  7049. BDINFO_FLAGS_DISABLED);
  7050. /* Program the jumbo buffer descriptor ring control
  7051. * blocks on those devices that have them.
  7052. */
  7053. if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
  7054. (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
  7055. if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
  7056. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  7057. ((u64) tpr->rx_jmb_mapping >> 32));
  7058. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  7059. ((u64) tpr->rx_jmb_mapping & 0xffffffff));
  7060. val = TG3_RX_JMB_RING_SIZE(tp) <<
  7061. BDINFO_FLAGS_MAXLEN_SHIFT;
  7062. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  7063. val | BDINFO_FLAGS_USE_EXT_RECV);
  7064. if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
  7065. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  7066. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  7067. NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  7068. } else {
  7069. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  7070. BDINFO_FLAGS_DISABLED);
  7071. }
  7072. if (tg3_flag(tp, 57765_PLUS)) {
  7073. val = TG3_RX_STD_RING_SIZE(tp);
  7074. val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
  7075. val |= (TG3_RX_STD_DMA_SZ << 2);
  7076. } else
  7077. val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
  7078. } else
  7079. val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
  7080. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
  7081. tpr->rx_std_prod_idx = tp->rx_pending;
  7082. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
  7083. tpr->rx_jmb_prod_idx =
  7084. tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
  7085. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
  7086. tg3_rings_reset(tp);
  7087. /* Initialize MAC address and backoff seed. */
  7088. __tg3_set_mac_addr(tp, 0);
  7089. /* MTU + ethernet header + FCS + optional VLAN tag */
  7090. tw32(MAC_RX_MTU_SIZE,
  7091. tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  7092. /* The slot time is changed by tg3_setup_phy if we
  7093. * run at gigabit with half duplex.
  7094. */
  7095. val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  7096. (6 << TX_LENGTHS_IPG_SHIFT) |
  7097. (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
  7098. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
  7099. val |= tr32(MAC_TX_LENGTHS) &
  7100. (TX_LENGTHS_JMB_FRM_LEN_MSK |
  7101. TX_LENGTHS_CNT_DWN_VAL_MSK);
  7102. tw32(MAC_TX_LENGTHS, val);
  7103. /* Receive rules. */
  7104. tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  7105. tw32(RCVLPC_CONFIG, 0x0181);
  7106. /* Calculate RDMAC_MODE setting early, we need it to determine
  7107. * the RCVLPC_STATE_ENABLE mask.
  7108. */
  7109. rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  7110. RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  7111. RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  7112. RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  7113. RDMAC_MODE_LNGREAD_ENAB);
  7114. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
  7115. rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
  7116. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  7117. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  7118. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  7119. rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
  7120. RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
  7121. RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
  7122. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  7123. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
  7124. if (tg3_flag(tp, TSO_CAPABLE) &&
  7125. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  7126. rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
  7127. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  7128. !tg3_flag(tp, IS_5788)) {
  7129. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  7130. }
  7131. }
  7132. if (tg3_flag(tp, PCI_EXPRESS))
  7133. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  7134. if (tg3_flag(tp, HW_TSO_1) ||
  7135. tg3_flag(tp, HW_TSO_2) ||
  7136. tg3_flag(tp, HW_TSO_3))
  7137. rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
  7138. if (tg3_flag(tp, 57765_PLUS) ||
  7139. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  7140. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  7141. rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
  7142. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
  7143. rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
  7144. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  7145. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  7146. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  7147. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  7148. tg3_flag(tp, 57765_PLUS)) {
  7149. val = tr32(TG3_RDMA_RSRVCTRL_REG);
  7150. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  7151. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
  7152. val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
  7153. TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
  7154. TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
  7155. val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
  7156. TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
  7157. TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
  7158. }
  7159. tw32(TG3_RDMA_RSRVCTRL_REG,
  7160. val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
  7161. }
  7162. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  7163. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
  7164. val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
  7165. tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
  7166. TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
  7167. TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
  7168. }
  7169. /* Receive/send statistics. */
  7170. if (tg3_flag(tp, 5750_PLUS)) {
  7171. val = tr32(RCVLPC_STATS_ENABLE);
  7172. val &= ~RCVLPC_STATSENAB_DACK_FIX;
  7173. tw32(RCVLPC_STATS_ENABLE, val);
  7174. } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
  7175. tg3_flag(tp, TSO_CAPABLE)) {
  7176. val = tr32(RCVLPC_STATS_ENABLE);
  7177. val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
  7178. tw32(RCVLPC_STATS_ENABLE, val);
  7179. } else {
  7180. tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  7181. }
  7182. tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  7183. tw32(SNDDATAI_STATSENAB, 0xffffff);
  7184. tw32(SNDDATAI_STATSCTRL,
  7185. (SNDDATAI_SCTRL_ENABLE |
  7186. SNDDATAI_SCTRL_FASTUPD));
  7187. /* Setup host coalescing engine. */
  7188. tw32(HOSTCC_MODE, 0);
  7189. for (i = 0; i < 2000; i++) {
  7190. if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
  7191. break;
  7192. udelay(10);
  7193. }
  7194. __tg3_set_coalesce(tp, &tp->coal);
  7195. if (!tg3_flag(tp, 5705_PLUS)) {
  7196. /* Status/statistics block address. See tg3_timer,
  7197. * the tg3_periodic_fetch_stats call there, and
  7198. * tg3_get_stats to see how this works for 5705/5750 chips.
  7199. */
  7200. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  7201. ((u64) tp->stats_mapping >> 32));
  7202. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  7203. ((u64) tp->stats_mapping & 0xffffffff));
  7204. tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  7205. tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  7206. /* Clear statistics and status block memory areas */
  7207. for (i = NIC_SRAM_STATS_BLK;
  7208. i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  7209. i += sizeof(u32)) {
  7210. tg3_write_mem(tp, i, 0);
  7211. udelay(40);
  7212. }
  7213. }
  7214. tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  7215. tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  7216. tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  7217. if (!tg3_flag(tp, 5705_PLUS))
  7218. tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  7219. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
  7220. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  7221. /* reset to prevent losing 1st rx packet intermittently */
  7222. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  7223. udelay(10);
  7224. }
  7225. tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  7226. MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
  7227. MAC_MODE_FHDE_ENABLE;
  7228. if (tg3_flag(tp, ENABLE_APE))
  7229. tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  7230. if (!tg3_flag(tp, 5705_PLUS) &&
  7231. !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  7232. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
  7233. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  7234. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
  7235. udelay(40);
  7236. /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
  7237. * If TG3_FLAG_IS_NIC is zero, we should read the
  7238. * register to preserve the GPIO settings for LOMs. The GPIOs,
  7239. * whether used as inputs or outputs, are set by boot code after
  7240. * reset.
  7241. */
  7242. if (!tg3_flag(tp, IS_NIC)) {
  7243. u32 gpio_mask;
  7244. gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
  7245. GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
  7246. GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
  7247. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  7248. gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
  7249. GRC_LCLCTRL_GPIO_OUTPUT3;
  7250. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  7251. gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
  7252. tp->grc_local_ctrl &= ~gpio_mask;
  7253. tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
  7254. /* GPIO1 must be driven high for eeprom write protect */
  7255. if (tg3_flag(tp, EEPROM_WRITE_PROT))
  7256. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  7257. GRC_LCLCTRL_GPIO_OUTPUT1);
  7258. }
  7259. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  7260. udelay(100);
  7261. if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
  7262. val = tr32(MSGINT_MODE);
  7263. val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
  7264. if (!tg3_flag(tp, 1SHOT_MSI))
  7265. val |= MSGINT_MODE_ONE_SHOT_DISABLE;
  7266. tw32(MSGINT_MODE, val);
  7267. }
  7268. if (!tg3_flag(tp, 5705_PLUS)) {
  7269. tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
  7270. udelay(40);
  7271. }
  7272. val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  7273. WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  7274. WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  7275. WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  7276. WDMAC_MODE_LNGREAD_ENAB);
  7277. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  7278. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
  7279. if (tg3_flag(tp, TSO_CAPABLE) &&
  7280. (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
  7281. tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
  7282. /* nothing */
  7283. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  7284. !tg3_flag(tp, IS_5788)) {
  7285. val |= WDMAC_MODE_RX_ACCEL;
  7286. }
  7287. }
  7288. /* Enable host coalescing bug fix */
  7289. if (tg3_flag(tp, 5755_PLUS))
  7290. val |= WDMAC_MODE_STATUS_TAG_FIX;
  7291. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  7292. val |= WDMAC_MODE_BURST_ALL_DATA;
  7293. tw32_f(WDMAC_MODE, val);
  7294. udelay(40);
  7295. if (tg3_flag(tp, PCIX_MODE)) {
  7296. u16 pcix_cmd;
  7297. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  7298. &pcix_cmd);
  7299. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
  7300. pcix_cmd &= ~PCI_X_CMD_MAX_READ;
  7301. pcix_cmd |= PCI_X_CMD_READ_2K;
  7302. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  7303. pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
  7304. pcix_cmd |= PCI_X_CMD_READ_2K;
  7305. }
  7306. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  7307. pcix_cmd);
  7308. }
  7309. tw32_f(RDMAC_MODE, rdmac_mode);
  7310. udelay(40);
  7311. tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  7312. if (!tg3_flag(tp, 5705_PLUS))
  7313. tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  7314. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  7315. tw32(SNDDATAC_MODE,
  7316. SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
  7317. else
  7318. tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  7319. tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  7320. tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  7321. val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
  7322. if (tg3_flag(tp, LRG_PROD_RING_CAP))
  7323. val |= RCVDBDI_MODE_LRG_RING_SZ;
  7324. tw32(RCVDBDI_MODE, val);
  7325. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  7326. if (tg3_flag(tp, HW_TSO_1) ||
  7327. tg3_flag(tp, HW_TSO_2) ||
  7328. tg3_flag(tp, HW_TSO_3))
  7329. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
  7330. val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
  7331. if (tg3_flag(tp, ENABLE_TSS))
  7332. val |= SNDBDI_MODE_MULTI_TXQ_EN;
  7333. tw32(SNDBDI_MODE, val);
  7334. tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
  7335. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
  7336. err = tg3_load_5701_a0_firmware_fix(tp);
  7337. if (err)
  7338. return err;
  7339. }
  7340. if (tg3_flag(tp, TSO_CAPABLE)) {
  7341. err = tg3_load_tso_firmware(tp);
  7342. if (err)
  7343. return err;
  7344. }
  7345. tp->tx_mode = TX_MODE_ENABLE;
  7346. if (tg3_flag(tp, 5755_PLUS) ||
  7347. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  7348. tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
  7349. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
  7350. val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
  7351. tp->tx_mode &= ~val;
  7352. tp->tx_mode |= tr32(MAC_TX_MODE) & val;
  7353. }
  7354. tw32_f(MAC_TX_MODE, tp->tx_mode);
  7355. udelay(100);
  7356. if (tg3_flag(tp, ENABLE_RSS)) {
  7357. int i = 0;
  7358. u32 reg = MAC_RSS_INDIR_TBL_0;
  7359. if (tp->irq_cnt == 2) {
  7360. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i += 8) {
  7361. tw32(reg, 0x0);
  7362. reg += 4;
  7363. }
  7364. } else {
  7365. u32 val;
  7366. while (i < TG3_RSS_INDIR_TBL_SIZE) {
  7367. val = i % (tp->irq_cnt - 1);
  7368. i++;
  7369. for (; i % 8; i++) {
  7370. val <<= 4;
  7371. val |= (i % (tp->irq_cnt - 1));
  7372. }
  7373. tw32(reg, val);
  7374. reg += 4;
  7375. }
  7376. }
  7377. /* Setup the "secret" hash key. */
  7378. tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
  7379. tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
  7380. tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
  7381. tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
  7382. tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
  7383. tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
  7384. tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
  7385. tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
  7386. tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
  7387. tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
  7388. }
  7389. tp->rx_mode = RX_MODE_ENABLE;
  7390. if (tg3_flag(tp, 5755_PLUS))
  7391. tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
  7392. if (tg3_flag(tp, ENABLE_RSS))
  7393. tp->rx_mode |= RX_MODE_RSS_ENABLE |
  7394. RX_MODE_RSS_ITBL_HASH_BITS_7 |
  7395. RX_MODE_RSS_IPV6_HASH_EN |
  7396. RX_MODE_RSS_TCP_IPV6_HASH_EN |
  7397. RX_MODE_RSS_IPV4_HASH_EN |
  7398. RX_MODE_RSS_TCP_IPV4_HASH_EN;
  7399. tw32_f(MAC_RX_MODE, tp->rx_mode);
  7400. udelay(10);
  7401. tw32(MAC_LED_CTRL, tp->led_ctrl);
  7402. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  7403. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  7404. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  7405. udelay(10);
  7406. }
  7407. tw32_f(MAC_RX_MODE, tp->rx_mode);
  7408. udelay(10);
  7409. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  7410. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
  7411. !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
  7412. /* Set drive transmission level to 1.2V */
  7413. /* only if the signal pre-emphasis bit is not set */
  7414. val = tr32(MAC_SERDES_CFG);
  7415. val &= 0xfffff000;
  7416. val |= 0x880;
  7417. tw32(MAC_SERDES_CFG, val);
  7418. }
  7419. if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
  7420. tw32(MAC_SERDES_CFG, 0x616000);
  7421. }
  7422. /* Prevent chip from dropping frames when flow control
  7423. * is enabled.
  7424. */
  7425. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  7426. val = 1;
  7427. else
  7428. val = 2;
  7429. tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
  7430. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
  7431. (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  7432. /* Use hardware link auto-negotiation */
  7433. tg3_flag_set(tp, HW_AUTONEG);
  7434. }
  7435. if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  7436. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  7437. u32 tmp;
  7438. tmp = tr32(SERDES_RX_CTRL);
  7439. tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
  7440. tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
  7441. tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
  7442. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  7443. }
  7444. if (!tg3_flag(tp, USE_PHYLIB)) {
  7445. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
  7446. tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
  7447. tp->link_config.speed = tp->link_config.orig_speed;
  7448. tp->link_config.duplex = tp->link_config.orig_duplex;
  7449. tp->link_config.autoneg = tp->link_config.orig_autoneg;
  7450. }
  7451. err = tg3_setup_phy(tp, 0);
  7452. if (err)
  7453. return err;
  7454. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  7455. !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  7456. u32 tmp;
  7457. /* Clear CRC stats. */
  7458. if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
  7459. tg3_writephy(tp, MII_TG3_TEST1,
  7460. tmp | MII_TG3_TEST1_CRC_EN);
  7461. tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
  7462. }
  7463. }
  7464. }
  7465. __tg3_set_rx_mode(tp->dev);
  7466. /* Initialize receive rules. */
  7467. tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
  7468. tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  7469. tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
  7470. tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  7471. if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
  7472. limit = 8;
  7473. else
  7474. limit = 16;
  7475. if (tg3_flag(tp, ENABLE_ASF))
  7476. limit -= 4;
  7477. switch (limit) {
  7478. case 16:
  7479. tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
  7480. case 15:
  7481. tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
  7482. case 14:
  7483. tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
  7484. case 13:
  7485. tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
  7486. case 12:
  7487. tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
  7488. case 11:
  7489. tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
  7490. case 10:
  7491. tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
  7492. case 9:
  7493. tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
  7494. case 8:
  7495. tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
  7496. case 7:
  7497. tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
  7498. case 6:
  7499. tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
  7500. case 5:
  7501. tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
  7502. case 4:
  7503. /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
  7504. case 3:
  7505. /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
  7506. case 2:
  7507. case 1:
  7508. default:
  7509. break;
  7510. }
  7511. if (tg3_flag(tp, ENABLE_APE))
  7512. /* Write our heartbeat update interval to APE. */
  7513. tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
  7514. APE_HOST_HEARTBEAT_INT_DISABLE);
  7515. tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
  7516. return 0;
  7517. }
  7518. /* Called at device open time to get the chip ready for
  7519. * packet processing. Invoked with tp->lock held.
  7520. */
  7521. static int tg3_init_hw(struct tg3 *tp, int reset_phy)
  7522. {
  7523. tg3_switch_clocks(tp);
  7524. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  7525. return tg3_reset_hw(tp, reset_phy);
  7526. }
  7527. #define TG3_STAT_ADD32(PSTAT, REG) \
  7528. do { u32 __val = tr32(REG); \
  7529. (PSTAT)->low += __val; \
  7530. if ((PSTAT)->low < __val) \
  7531. (PSTAT)->high += 1; \
  7532. } while (0)
  7533. static void tg3_periodic_fetch_stats(struct tg3 *tp)
  7534. {
  7535. struct tg3_hw_stats *sp = tp->hw_stats;
  7536. if (!netif_carrier_ok(tp->dev))
  7537. return;
  7538. TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
  7539. TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
  7540. TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
  7541. TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
  7542. TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
  7543. TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
  7544. TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
  7545. TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
  7546. TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
  7547. TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
  7548. TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
  7549. TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
  7550. TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
  7551. TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
  7552. TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
  7553. TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
  7554. TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
  7555. TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
  7556. TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
  7557. TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
  7558. TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
  7559. TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
  7560. TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
  7561. TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
  7562. TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
  7563. TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
  7564. TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
  7565. TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
  7566. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
  7567. tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
  7568. tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
  7569. TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
  7570. } else {
  7571. u32 val = tr32(HOSTCC_FLOW_ATTN);
  7572. val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
  7573. if (val) {
  7574. tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
  7575. sp->rx_discards.low += val;
  7576. if (sp->rx_discards.low < val)
  7577. sp->rx_discards.high += 1;
  7578. }
  7579. sp->mbuf_lwm_thresh_hit = sp->rx_discards;
  7580. }
  7581. TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
  7582. }
  7583. static void tg3_chk_missed_msi(struct tg3 *tp)
  7584. {
  7585. u32 i;
  7586. for (i = 0; i < tp->irq_cnt; i++) {
  7587. struct tg3_napi *tnapi = &tp->napi[i];
  7588. if (tg3_has_work(tnapi)) {
  7589. if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
  7590. tnapi->last_tx_cons == tnapi->tx_cons) {
  7591. if (tnapi->chk_msi_cnt < 1) {
  7592. tnapi->chk_msi_cnt++;
  7593. return;
  7594. }
  7595. tg3_msi(0, tnapi);
  7596. }
  7597. }
  7598. tnapi->chk_msi_cnt = 0;
  7599. tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
  7600. tnapi->last_tx_cons = tnapi->tx_cons;
  7601. }
  7602. }
  7603. static void tg3_timer(unsigned long __opaque)
  7604. {
  7605. struct tg3 *tp = (struct tg3 *) __opaque;
  7606. if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
  7607. goto restart_timer;
  7608. spin_lock(&tp->lock);
  7609. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  7610. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  7611. tg3_chk_missed_msi(tp);
  7612. if (!tg3_flag(tp, TAGGED_STATUS)) {
  7613. /* All of this garbage is because when using non-tagged
  7614. * IRQ status the mailbox/status_block protocol the chip
  7615. * uses with the cpu is race prone.
  7616. */
  7617. if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
  7618. tw32(GRC_LOCAL_CTRL,
  7619. tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  7620. } else {
  7621. tw32(HOSTCC_MODE, tp->coalesce_mode |
  7622. HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
  7623. }
  7624. if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  7625. spin_unlock(&tp->lock);
  7626. tg3_reset_task_schedule(tp);
  7627. goto restart_timer;
  7628. }
  7629. }
  7630. /* This part only runs once per second. */
  7631. if (!--tp->timer_counter) {
  7632. if (tg3_flag(tp, 5705_PLUS))
  7633. tg3_periodic_fetch_stats(tp);
  7634. if (tp->setlpicnt && !--tp->setlpicnt)
  7635. tg3_phy_eee_enable(tp);
  7636. if (tg3_flag(tp, USE_LINKCHG_REG)) {
  7637. u32 mac_stat;
  7638. int phy_event;
  7639. mac_stat = tr32(MAC_STATUS);
  7640. phy_event = 0;
  7641. if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
  7642. if (mac_stat & MAC_STATUS_MI_INTERRUPT)
  7643. phy_event = 1;
  7644. } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
  7645. phy_event = 1;
  7646. if (phy_event)
  7647. tg3_setup_phy(tp, 0);
  7648. } else if (tg3_flag(tp, POLL_SERDES)) {
  7649. u32 mac_stat = tr32(MAC_STATUS);
  7650. int need_setup = 0;
  7651. if (netif_carrier_ok(tp->dev) &&
  7652. (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
  7653. need_setup = 1;
  7654. }
  7655. if (!netif_carrier_ok(tp->dev) &&
  7656. (mac_stat & (MAC_STATUS_PCS_SYNCED |
  7657. MAC_STATUS_SIGNAL_DET))) {
  7658. need_setup = 1;
  7659. }
  7660. if (need_setup) {
  7661. if (!tp->serdes_counter) {
  7662. tw32_f(MAC_MODE,
  7663. (tp->mac_mode &
  7664. ~MAC_MODE_PORT_MODE_MASK));
  7665. udelay(40);
  7666. tw32_f(MAC_MODE, tp->mac_mode);
  7667. udelay(40);
  7668. }
  7669. tg3_setup_phy(tp, 0);
  7670. }
  7671. } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  7672. tg3_flag(tp, 5780_CLASS)) {
  7673. tg3_serdes_parallel_detect(tp);
  7674. }
  7675. tp->timer_counter = tp->timer_multiplier;
  7676. }
  7677. /* Heartbeat is only sent once every 2 seconds.
  7678. *
  7679. * The heartbeat is to tell the ASF firmware that the host
  7680. * driver is still alive. In the event that the OS crashes,
  7681. * ASF needs to reset the hardware to free up the FIFO space
  7682. * that may be filled with rx packets destined for the host.
  7683. * If the FIFO is full, ASF will no longer function properly.
  7684. *
  7685. * Unintended resets have been reported on real time kernels
  7686. * where the timer doesn't run on time. Netpoll will also have
  7687. * same problem.
  7688. *
  7689. * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
  7690. * to check the ring condition when the heartbeat is expiring
  7691. * before doing the reset. This will prevent most unintended
  7692. * resets.
  7693. */
  7694. if (!--tp->asf_counter) {
  7695. if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
  7696. tg3_wait_for_event_ack(tp);
  7697. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
  7698. FWCMD_NICDRV_ALIVE3);
  7699. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
  7700. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
  7701. TG3_FW_UPDATE_TIMEOUT_SEC);
  7702. tg3_generate_fw_event(tp);
  7703. }
  7704. tp->asf_counter = tp->asf_multiplier;
  7705. }
  7706. spin_unlock(&tp->lock);
  7707. restart_timer:
  7708. tp->timer.expires = jiffies + tp->timer_offset;
  7709. add_timer(&tp->timer);
  7710. }
  7711. static int tg3_request_irq(struct tg3 *tp, int irq_num)
  7712. {
  7713. irq_handler_t fn;
  7714. unsigned long flags;
  7715. char *name;
  7716. struct tg3_napi *tnapi = &tp->napi[irq_num];
  7717. if (tp->irq_cnt == 1)
  7718. name = tp->dev->name;
  7719. else {
  7720. name = &tnapi->irq_lbl[0];
  7721. snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
  7722. name[IFNAMSIZ-1] = 0;
  7723. }
  7724. if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
  7725. fn = tg3_msi;
  7726. if (tg3_flag(tp, 1SHOT_MSI))
  7727. fn = tg3_msi_1shot;
  7728. flags = 0;
  7729. } else {
  7730. fn = tg3_interrupt;
  7731. if (tg3_flag(tp, TAGGED_STATUS))
  7732. fn = tg3_interrupt_tagged;
  7733. flags = IRQF_SHARED;
  7734. }
  7735. return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
  7736. }
  7737. static int tg3_test_interrupt(struct tg3 *tp)
  7738. {
  7739. struct tg3_napi *tnapi = &tp->napi[0];
  7740. struct net_device *dev = tp->dev;
  7741. int err, i, intr_ok = 0;
  7742. u32 val;
  7743. if (!netif_running(dev))
  7744. return -ENODEV;
  7745. tg3_disable_ints(tp);
  7746. free_irq(tnapi->irq_vec, tnapi);
  7747. /*
  7748. * Turn off MSI one shot mode. Otherwise this test has no
  7749. * observable way to know whether the interrupt was delivered.
  7750. */
  7751. if (tg3_flag(tp, 57765_PLUS)) {
  7752. val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
  7753. tw32(MSGINT_MODE, val);
  7754. }
  7755. err = request_irq(tnapi->irq_vec, tg3_test_isr,
  7756. IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
  7757. if (err)
  7758. return err;
  7759. tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
  7760. tg3_enable_ints(tp);
  7761. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  7762. tnapi->coal_now);
  7763. for (i = 0; i < 5; i++) {
  7764. u32 int_mbox, misc_host_ctrl;
  7765. int_mbox = tr32_mailbox(tnapi->int_mbox);
  7766. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  7767. if ((int_mbox != 0) ||
  7768. (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
  7769. intr_ok = 1;
  7770. break;
  7771. }
  7772. if (tg3_flag(tp, 57765_PLUS) &&
  7773. tnapi->hw_status->status_tag != tnapi->last_tag)
  7774. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  7775. msleep(10);
  7776. }
  7777. tg3_disable_ints(tp);
  7778. free_irq(tnapi->irq_vec, tnapi);
  7779. err = tg3_request_irq(tp, 0);
  7780. if (err)
  7781. return err;
  7782. if (intr_ok) {
  7783. /* Reenable MSI one shot mode. */
  7784. if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
  7785. val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
  7786. tw32(MSGINT_MODE, val);
  7787. }
  7788. return 0;
  7789. }
  7790. return -EIO;
  7791. }
  7792. /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
  7793. * successfully restored
  7794. */
  7795. static int tg3_test_msi(struct tg3 *tp)
  7796. {
  7797. int err;
  7798. u16 pci_cmd;
  7799. if (!tg3_flag(tp, USING_MSI))
  7800. return 0;
  7801. /* Turn off SERR reporting in case MSI terminates with Master
  7802. * Abort.
  7803. */
  7804. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  7805. pci_write_config_word(tp->pdev, PCI_COMMAND,
  7806. pci_cmd & ~PCI_COMMAND_SERR);
  7807. err = tg3_test_interrupt(tp);
  7808. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  7809. if (!err)
  7810. return 0;
  7811. /* other failures */
  7812. if (err != -EIO)
  7813. return err;
  7814. /* MSI test failed, go back to INTx mode */
  7815. netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
  7816. "to INTx mode. Please report this failure to the PCI "
  7817. "maintainer and include system chipset information\n");
  7818. free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
  7819. pci_disable_msi(tp->pdev);
  7820. tg3_flag_clear(tp, USING_MSI);
  7821. tp->napi[0].irq_vec = tp->pdev->irq;
  7822. err = tg3_request_irq(tp, 0);
  7823. if (err)
  7824. return err;
  7825. /* Need to reset the chip because the MSI cycle may have terminated
  7826. * with Master Abort.
  7827. */
  7828. tg3_full_lock(tp, 1);
  7829. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7830. err = tg3_init_hw(tp, 1);
  7831. tg3_full_unlock(tp);
  7832. if (err)
  7833. free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
  7834. return err;
  7835. }
  7836. static int tg3_request_firmware(struct tg3 *tp)
  7837. {
  7838. const __be32 *fw_data;
  7839. if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
  7840. netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
  7841. tp->fw_needed);
  7842. return -ENOENT;
  7843. }
  7844. fw_data = (void *)tp->fw->data;
  7845. /* Firmware blob starts with version numbers, followed by
  7846. * start address and _full_ length including BSS sections
  7847. * (which must be longer than the actual data, of course
  7848. */
  7849. tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
  7850. if (tp->fw_len < (tp->fw->size - 12)) {
  7851. netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
  7852. tp->fw_len, tp->fw_needed);
  7853. release_firmware(tp->fw);
  7854. tp->fw = NULL;
  7855. return -EINVAL;
  7856. }
  7857. /* We no longer need firmware; we have it. */
  7858. tp->fw_needed = NULL;
  7859. return 0;
  7860. }
  7861. static bool tg3_enable_msix(struct tg3 *tp)
  7862. {
  7863. int i, rc, cpus = num_online_cpus();
  7864. struct msix_entry msix_ent[tp->irq_max];
  7865. if (cpus == 1)
  7866. /* Just fallback to the simpler MSI mode. */
  7867. return false;
  7868. /*
  7869. * We want as many rx rings enabled as there are cpus.
  7870. * The first MSIX vector only deals with link interrupts, etc,
  7871. * so we add one to the number of vectors we are requesting.
  7872. */
  7873. tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
  7874. for (i = 0; i < tp->irq_max; i++) {
  7875. msix_ent[i].entry = i;
  7876. msix_ent[i].vector = 0;
  7877. }
  7878. rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
  7879. if (rc < 0) {
  7880. return false;
  7881. } else if (rc != 0) {
  7882. if (pci_enable_msix(tp->pdev, msix_ent, rc))
  7883. return false;
  7884. netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
  7885. tp->irq_cnt, rc);
  7886. tp->irq_cnt = rc;
  7887. }
  7888. for (i = 0; i < tp->irq_max; i++)
  7889. tp->napi[i].irq_vec = msix_ent[i].vector;
  7890. netif_set_real_num_tx_queues(tp->dev, 1);
  7891. rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
  7892. if (netif_set_real_num_rx_queues(tp->dev, rc)) {
  7893. pci_disable_msix(tp->pdev);
  7894. return false;
  7895. }
  7896. if (tp->irq_cnt > 1) {
  7897. tg3_flag_set(tp, ENABLE_RSS);
  7898. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  7899. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
  7900. tg3_flag_set(tp, ENABLE_TSS);
  7901. netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
  7902. }
  7903. }
  7904. return true;
  7905. }
  7906. static void tg3_ints_init(struct tg3 *tp)
  7907. {
  7908. if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
  7909. !tg3_flag(tp, TAGGED_STATUS)) {
  7910. /* All MSI supporting chips should support tagged
  7911. * status. Assert that this is the case.
  7912. */
  7913. netdev_warn(tp->dev,
  7914. "MSI without TAGGED_STATUS? Not using MSI\n");
  7915. goto defcfg;
  7916. }
  7917. if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
  7918. tg3_flag_set(tp, USING_MSIX);
  7919. else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
  7920. tg3_flag_set(tp, USING_MSI);
  7921. if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
  7922. u32 msi_mode = tr32(MSGINT_MODE);
  7923. if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
  7924. msi_mode |= MSGINT_MODE_MULTIVEC_EN;
  7925. if (!tg3_flag(tp, 1SHOT_MSI))
  7926. msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
  7927. tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
  7928. }
  7929. defcfg:
  7930. if (!tg3_flag(tp, USING_MSIX)) {
  7931. tp->irq_cnt = 1;
  7932. tp->napi[0].irq_vec = tp->pdev->irq;
  7933. netif_set_real_num_tx_queues(tp->dev, 1);
  7934. netif_set_real_num_rx_queues(tp->dev, 1);
  7935. }
  7936. }
  7937. static void tg3_ints_fini(struct tg3 *tp)
  7938. {
  7939. if (tg3_flag(tp, USING_MSIX))
  7940. pci_disable_msix(tp->pdev);
  7941. else if (tg3_flag(tp, USING_MSI))
  7942. pci_disable_msi(tp->pdev);
  7943. tg3_flag_clear(tp, USING_MSI);
  7944. tg3_flag_clear(tp, USING_MSIX);
  7945. tg3_flag_clear(tp, ENABLE_RSS);
  7946. tg3_flag_clear(tp, ENABLE_TSS);
  7947. }
  7948. static int tg3_open(struct net_device *dev)
  7949. {
  7950. struct tg3 *tp = netdev_priv(dev);
  7951. int i, err;
  7952. if (tp->fw_needed) {
  7953. err = tg3_request_firmware(tp);
  7954. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
  7955. if (err)
  7956. return err;
  7957. } else if (err) {
  7958. netdev_warn(tp->dev, "TSO capability disabled\n");
  7959. tg3_flag_clear(tp, TSO_CAPABLE);
  7960. } else if (!tg3_flag(tp, TSO_CAPABLE)) {
  7961. netdev_notice(tp->dev, "TSO capability restored\n");
  7962. tg3_flag_set(tp, TSO_CAPABLE);
  7963. }
  7964. }
  7965. netif_carrier_off(tp->dev);
  7966. err = tg3_power_up(tp);
  7967. if (err)
  7968. return err;
  7969. tg3_full_lock(tp, 0);
  7970. tg3_disable_ints(tp);
  7971. tg3_flag_clear(tp, INIT_COMPLETE);
  7972. tg3_full_unlock(tp);
  7973. /*
  7974. * Setup interrupts first so we know how
  7975. * many NAPI resources to allocate
  7976. */
  7977. tg3_ints_init(tp);
  7978. /* The placement of this call is tied
  7979. * to the setup and use of Host TX descriptors.
  7980. */
  7981. err = tg3_alloc_consistent(tp);
  7982. if (err)
  7983. goto err_out1;
  7984. tg3_napi_init(tp);
  7985. tg3_napi_enable(tp);
  7986. for (i = 0; i < tp->irq_cnt; i++) {
  7987. struct tg3_napi *tnapi = &tp->napi[i];
  7988. err = tg3_request_irq(tp, i);
  7989. if (err) {
  7990. for (i--; i >= 0; i--) {
  7991. tnapi = &tp->napi[i];
  7992. free_irq(tnapi->irq_vec, tnapi);
  7993. }
  7994. goto err_out2;
  7995. }
  7996. }
  7997. tg3_full_lock(tp, 0);
  7998. err = tg3_init_hw(tp, 1);
  7999. if (err) {
  8000. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8001. tg3_free_rings(tp);
  8002. } else {
  8003. if (tg3_flag(tp, TAGGED_STATUS) &&
  8004. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
  8005. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765)
  8006. tp->timer_offset = HZ;
  8007. else
  8008. tp->timer_offset = HZ / 10;
  8009. BUG_ON(tp->timer_offset > HZ);
  8010. tp->timer_counter = tp->timer_multiplier =
  8011. (HZ / tp->timer_offset);
  8012. tp->asf_counter = tp->asf_multiplier =
  8013. ((HZ / tp->timer_offset) * 2);
  8014. init_timer(&tp->timer);
  8015. tp->timer.expires = jiffies + tp->timer_offset;
  8016. tp->timer.data = (unsigned long) tp;
  8017. tp->timer.function = tg3_timer;
  8018. }
  8019. tg3_full_unlock(tp);
  8020. if (err)
  8021. goto err_out3;
  8022. if (tg3_flag(tp, USING_MSI)) {
  8023. err = tg3_test_msi(tp);
  8024. if (err) {
  8025. tg3_full_lock(tp, 0);
  8026. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8027. tg3_free_rings(tp);
  8028. tg3_full_unlock(tp);
  8029. goto err_out2;
  8030. }
  8031. if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
  8032. u32 val = tr32(PCIE_TRANSACTION_CFG);
  8033. tw32(PCIE_TRANSACTION_CFG,
  8034. val | PCIE_TRANS_CFG_1SHOT_MSI);
  8035. }
  8036. }
  8037. tg3_phy_start(tp);
  8038. tg3_full_lock(tp, 0);
  8039. add_timer(&tp->timer);
  8040. tg3_flag_set(tp, INIT_COMPLETE);
  8041. tg3_enable_ints(tp);
  8042. tg3_full_unlock(tp);
  8043. netif_tx_start_all_queues(dev);
  8044. /*
  8045. * Reset loopback feature if it was turned on while the device was down
  8046. * make sure that it's installed properly now.
  8047. */
  8048. if (dev->features & NETIF_F_LOOPBACK)
  8049. tg3_set_loopback(dev, dev->features);
  8050. return 0;
  8051. err_out3:
  8052. for (i = tp->irq_cnt - 1; i >= 0; i--) {
  8053. struct tg3_napi *tnapi = &tp->napi[i];
  8054. free_irq(tnapi->irq_vec, tnapi);
  8055. }
  8056. err_out2:
  8057. tg3_napi_disable(tp);
  8058. tg3_napi_fini(tp);
  8059. tg3_free_consistent(tp);
  8060. err_out1:
  8061. tg3_ints_fini(tp);
  8062. tg3_frob_aux_power(tp, false);
  8063. pci_set_power_state(tp->pdev, PCI_D3hot);
  8064. return err;
  8065. }
  8066. static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
  8067. struct rtnl_link_stats64 *);
  8068. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
  8069. static int tg3_close(struct net_device *dev)
  8070. {
  8071. int i;
  8072. struct tg3 *tp = netdev_priv(dev);
  8073. tg3_napi_disable(tp);
  8074. tg3_reset_task_cancel(tp);
  8075. netif_tx_stop_all_queues(dev);
  8076. del_timer_sync(&tp->timer);
  8077. tg3_phy_stop(tp);
  8078. tg3_full_lock(tp, 1);
  8079. tg3_disable_ints(tp);
  8080. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8081. tg3_free_rings(tp);
  8082. tg3_flag_clear(tp, INIT_COMPLETE);
  8083. tg3_full_unlock(tp);
  8084. for (i = tp->irq_cnt - 1; i >= 0; i--) {
  8085. struct tg3_napi *tnapi = &tp->napi[i];
  8086. free_irq(tnapi->irq_vec, tnapi);
  8087. }
  8088. tg3_ints_fini(tp);
  8089. tg3_get_stats64(tp->dev, &tp->net_stats_prev);
  8090. memcpy(&tp->estats_prev, tg3_get_estats(tp),
  8091. sizeof(tp->estats_prev));
  8092. tg3_napi_fini(tp);
  8093. tg3_free_consistent(tp);
  8094. tg3_power_down(tp);
  8095. netif_carrier_off(tp->dev);
  8096. return 0;
  8097. }
  8098. static inline u64 get_stat64(tg3_stat64_t *val)
  8099. {
  8100. return ((u64)val->high << 32) | ((u64)val->low);
  8101. }
  8102. static u64 calc_crc_errors(struct tg3 *tp)
  8103. {
  8104. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  8105. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  8106. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  8107. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  8108. u32 val;
  8109. spin_lock_bh(&tp->lock);
  8110. if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
  8111. tg3_writephy(tp, MII_TG3_TEST1,
  8112. val | MII_TG3_TEST1_CRC_EN);
  8113. tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
  8114. } else
  8115. val = 0;
  8116. spin_unlock_bh(&tp->lock);
  8117. tp->phy_crc_errors += val;
  8118. return tp->phy_crc_errors;
  8119. }
  8120. return get_stat64(&hw_stats->rx_fcs_errors);
  8121. }
  8122. #define ESTAT_ADD(member) \
  8123. estats->member = old_estats->member + \
  8124. get_stat64(&hw_stats->member)
  8125. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
  8126. {
  8127. struct tg3_ethtool_stats *estats = &tp->estats;
  8128. struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
  8129. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  8130. if (!hw_stats)
  8131. return old_estats;
  8132. ESTAT_ADD(rx_octets);
  8133. ESTAT_ADD(rx_fragments);
  8134. ESTAT_ADD(rx_ucast_packets);
  8135. ESTAT_ADD(rx_mcast_packets);
  8136. ESTAT_ADD(rx_bcast_packets);
  8137. ESTAT_ADD(rx_fcs_errors);
  8138. ESTAT_ADD(rx_align_errors);
  8139. ESTAT_ADD(rx_xon_pause_rcvd);
  8140. ESTAT_ADD(rx_xoff_pause_rcvd);
  8141. ESTAT_ADD(rx_mac_ctrl_rcvd);
  8142. ESTAT_ADD(rx_xoff_entered);
  8143. ESTAT_ADD(rx_frame_too_long_errors);
  8144. ESTAT_ADD(rx_jabbers);
  8145. ESTAT_ADD(rx_undersize_packets);
  8146. ESTAT_ADD(rx_in_length_errors);
  8147. ESTAT_ADD(rx_out_length_errors);
  8148. ESTAT_ADD(rx_64_or_less_octet_packets);
  8149. ESTAT_ADD(rx_65_to_127_octet_packets);
  8150. ESTAT_ADD(rx_128_to_255_octet_packets);
  8151. ESTAT_ADD(rx_256_to_511_octet_packets);
  8152. ESTAT_ADD(rx_512_to_1023_octet_packets);
  8153. ESTAT_ADD(rx_1024_to_1522_octet_packets);
  8154. ESTAT_ADD(rx_1523_to_2047_octet_packets);
  8155. ESTAT_ADD(rx_2048_to_4095_octet_packets);
  8156. ESTAT_ADD(rx_4096_to_8191_octet_packets);
  8157. ESTAT_ADD(rx_8192_to_9022_octet_packets);
  8158. ESTAT_ADD(tx_octets);
  8159. ESTAT_ADD(tx_collisions);
  8160. ESTAT_ADD(tx_xon_sent);
  8161. ESTAT_ADD(tx_xoff_sent);
  8162. ESTAT_ADD(tx_flow_control);
  8163. ESTAT_ADD(tx_mac_errors);
  8164. ESTAT_ADD(tx_single_collisions);
  8165. ESTAT_ADD(tx_mult_collisions);
  8166. ESTAT_ADD(tx_deferred);
  8167. ESTAT_ADD(tx_excessive_collisions);
  8168. ESTAT_ADD(tx_late_collisions);
  8169. ESTAT_ADD(tx_collide_2times);
  8170. ESTAT_ADD(tx_collide_3times);
  8171. ESTAT_ADD(tx_collide_4times);
  8172. ESTAT_ADD(tx_collide_5times);
  8173. ESTAT_ADD(tx_collide_6times);
  8174. ESTAT_ADD(tx_collide_7times);
  8175. ESTAT_ADD(tx_collide_8times);
  8176. ESTAT_ADD(tx_collide_9times);
  8177. ESTAT_ADD(tx_collide_10times);
  8178. ESTAT_ADD(tx_collide_11times);
  8179. ESTAT_ADD(tx_collide_12times);
  8180. ESTAT_ADD(tx_collide_13times);
  8181. ESTAT_ADD(tx_collide_14times);
  8182. ESTAT_ADD(tx_collide_15times);
  8183. ESTAT_ADD(tx_ucast_packets);
  8184. ESTAT_ADD(tx_mcast_packets);
  8185. ESTAT_ADD(tx_bcast_packets);
  8186. ESTAT_ADD(tx_carrier_sense_errors);
  8187. ESTAT_ADD(tx_discards);
  8188. ESTAT_ADD(tx_errors);
  8189. ESTAT_ADD(dma_writeq_full);
  8190. ESTAT_ADD(dma_write_prioq_full);
  8191. ESTAT_ADD(rxbds_empty);
  8192. ESTAT_ADD(rx_discards);
  8193. ESTAT_ADD(rx_errors);
  8194. ESTAT_ADD(rx_threshold_hit);
  8195. ESTAT_ADD(dma_readq_full);
  8196. ESTAT_ADD(dma_read_prioq_full);
  8197. ESTAT_ADD(tx_comp_queue_full);
  8198. ESTAT_ADD(ring_set_send_prod_index);
  8199. ESTAT_ADD(ring_status_update);
  8200. ESTAT_ADD(nic_irqs);
  8201. ESTAT_ADD(nic_avoided_irqs);
  8202. ESTAT_ADD(nic_tx_threshold_hit);
  8203. ESTAT_ADD(mbuf_lwm_thresh_hit);
  8204. return estats;
  8205. }
  8206. static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
  8207. struct rtnl_link_stats64 *stats)
  8208. {
  8209. struct tg3 *tp = netdev_priv(dev);
  8210. struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
  8211. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  8212. if (!hw_stats)
  8213. return old_stats;
  8214. stats->rx_packets = old_stats->rx_packets +
  8215. get_stat64(&hw_stats->rx_ucast_packets) +
  8216. get_stat64(&hw_stats->rx_mcast_packets) +
  8217. get_stat64(&hw_stats->rx_bcast_packets);
  8218. stats->tx_packets = old_stats->tx_packets +
  8219. get_stat64(&hw_stats->tx_ucast_packets) +
  8220. get_stat64(&hw_stats->tx_mcast_packets) +
  8221. get_stat64(&hw_stats->tx_bcast_packets);
  8222. stats->rx_bytes = old_stats->rx_bytes +
  8223. get_stat64(&hw_stats->rx_octets);
  8224. stats->tx_bytes = old_stats->tx_bytes +
  8225. get_stat64(&hw_stats->tx_octets);
  8226. stats->rx_errors = old_stats->rx_errors +
  8227. get_stat64(&hw_stats->rx_errors);
  8228. stats->tx_errors = old_stats->tx_errors +
  8229. get_stat64(&hw_stats->tx_errors) +
  8230. get_stat64(&hw_stats->tx_mac_errors) +
  8231. get_stat64(&hw_stats->tx_carrier_sense_errors) +
  8232. get_stat64(&hw_stats->tx_discards);
  8233. stats->multicast = old_stats->multicast +
  8234. get_stat64(&hw_stats->rx_mcast_packets);
  8235. stats->collisions = old_stats->collisions +
  8236. get_stat64(&hw_stats->tx_collisions);
  8237. stats->rx_length_errors = old_stats->rx_length_errors +
  8238. get_stat64(&hw_stats->rx_frame_too_long_errors) +
  8239. get_stat64(&hw_stats->rx_undersize_packets);
  8240. stats->rx_over_errors = old_stats->rx_over_errors +
  8241. get_stat64(&hw_stats->rxbds_empty);
  8242. stats->rx_frame_errors = old_stats->rx_frame_errors +
  8243. get_stat64(&hw_stats->rx_align_errors);
  8244. stats->tx_aborted_errors = old_stats->tx_aborted_errors +
  8245. get_stat64(&hw_stats->tx_discards);
  8246. stats->tx_carrier_errors = old_stats->tx_carrier_errors +
  8247. get_stat64(&hw_stats->tx_carrier_sense_errors);
  8248. stats->rx_crc_errors = old_stats->rx_crc_errors +
  8249. calc_crc_errors(tp);
  8250. stats->rx_missed_errors = old_stats->rx_missed_errors +
  8251. get_stat64(&hw_stats->rx_discards);
  8252. stats->rx_dropped = tp->rx_dropped;
  8253. stats->tx_dropped = tp->tx_dropped;
  8254. return stats;
  8255. }
  8256. static inline u32 calc_crc(unsigned char *buf, int len)
  8257. {
  8258. u32 reg;
  8259. u32 tmp;
  8260. int j, k;
  8261. reg = 0xffffffff;
  8262. for (j = 0; j < len; j++) {
  8263. reg ^= buf[j];
  8264. for (k = 0; k < 8; k++) {
  8265. tmp = reg & 0x01;
  8266. reg >>= 1;
  8267. if (tmp)
  8268. reg ^= 0xedb88320;
  8269. }
  8270. }
  8271. return ~reg;
  8272. }
  8273. static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
  8274. {
  8275. /* accept or reject all multicast frames */
  8276. tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
  8277. tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
  8278. tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
  8279. tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
  8280. }
  8281. static void __tg3_set_rx_mode(struct net_device *dev)
  8282. {
  8283. struct tg3 *tp = netdev_priv(dev);
  8284. u32 rx_mode;
  8285. rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
  8286. RX_MODE_KEEP_VLAN_TAG);
  8287. #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
  8288. /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
  8289. * flag clear.
  8290. */
  8291. if (!tg3_flag(tp, ENABLE_ASF))
  8292. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  8293. #endif
  8294. if (dev->flags & IFF_PROMISC) {
  8295. /* Promiscuous mode. */
  8296. rx_mode |= RX_MODE_PROMISC;
  8297. } else if (dev->flags & IFF_ALLMULTI) {
  8298. /* Accept all multicast. */
  8299. tg3_set_multi(tp, 1);
  8300. } else if (netdev_mc_empty(dev)) {
  8301. /* Reject all multicast. */
  8302. tg3_set_multi(tp, 0);
  8303. } else {
  8304. /* Accept one or more multicast(s). */
  8305. struct netdev_hw_addr *ha;
  8306. u32 mc_filter[4] = { 0, };
  8307. u32 regidx;
  8308. u32 bit;
  8309. u32 crc;
  8310. netdev_for_each_mc_addr(ha, dev) {
  8311. crc = calc_crc(ha->addr, ETH_ALEN);
  8312. bit = ~crc & 0x7f;
  8313. regidx = (bit & 0x60) >> 5;
  8314. bit &= 0x1f;
  8315. mc_filter[regidx] |= (1 << bit);
  8316. }
  8317. tw32(MAC_HASH_REG_0, mc_filter[0]);
  8318. tw32(MAC_HASH_REG_1, mc_filter[1]);
  8319. tw32(MAC_HASH_REG_2, mc_filter[2]);
  8320. tw32(MAC_HASH_REG_3, mc_filter[3]);
  8321. }
  8322. if (rx_mode != tp->rx_mode) {
  8323. tp->rx_mode = rx_mode;
  8324. tw32_f(MAC_RX_MODE, rx_mode);
  8325. udelay(10);
  8326. }
  8327. }
  8328. static void tg3_set_rx_mode(struct net_device *dev)
  8329. {
  8330. struct tg3 *tp = netdev_priv(dev);
  8331. if (!netif_running(dev))
  8332. return;
  8333. tg3_full_lock(tp, 0);
  8334. __tg3_set_rx_mode(dev);
  8335. tg3_full_unlock(tp);
  8336. }
  8337. static int tg3_get_regs_len(struct net_device *dev)
  8338. {
  8339. return TG3_REG_BLK_SIZE;
  8340. }
  8341. static void tg3_get_regs(struct net_device *dev,
  8342. struct ethtool_regs *regs, void *_p)
  8343. {
  8344. struct tg3 *tp = netdev_priv(dev);
  8345. regs->version = 0;
  8346. memset(_p, 0, TG3_REG_BLK_SIZE);
  8347. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  8348. return;
  8349. tg3_full_lock(tp, 0);
  8350. tg3_dump_legacy_regs(tp, (u32 *)_p);
  8351. tg3_full_unlock(tp);
  8352. }
  8353. static int tg3_get_eeprom_len(struct net_device *dev)
  8354. {
  8355. struct tg3 *tp = netdev_priv(dev);
  8356. return tp->nvram_size;
  8357. }
  8358. static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  8359. {
  8360. struct tg3 *tp = netdev_priv(dev);
  8361. int ret;
  8362. u8 *pd;
  8363. u32 i, offset, len, b_offset, b_count;
  8364. __be32 val;
  8365. if (tg3_flag(tp, NO_NVRAM))
  8366. return -EINVAL;
  8367. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  8368. return -EAGAIN;
  8369. offset = eeprom->offset;
  8370. len = eeprom->len;
  8371. eeprom->len = 0;
  8372. eeprom->magic = TG3_EEPROM_MAGIC;
  8373. if (offset & 3) {
  8374. /* adjustments to start on required 4 byte boundary */
  8375. b_offset = offset & 3;
  8376. b_count = 4 - b_offset;
  8377. if (b_count > len) {
  8378. /* i.e. offset=1 len=2 */
  8379. b_count = len;
  8380. }
  8381. ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
  8382. if (ret)
  8383. return ret;
  8384. memcpy(data, ((char *)&val) + b_offset, b_count);
  8385. len -= b_count;
  8386. offset += b_count;
  8387. eeprom->len += b_count;
  8388. }
  8389. /* read bytes up to the last 4 byte boundary */
  8390. pd = &data[eeprom->len];
  8391. for (i = 0; i < (len - (len & 3)); i += 4) {
  8392. ret = tg3_nvram_read_be32(tp, offset + i, &val);
  8393. if (ret) {
  8394. eeprom->len += i;
  8395. return ret;
  8396. }
  8397. memcpy(pd + i, &val, 4);
  8398. }
  8399. eeprom->len += i;
  8400. if (len & 3) {
  8401. /* read last bytes not ending on 4 byte boundary */
  8402. pd = &data[eeprom->len];
  8403. b_count = len & 3;
  8404. b_offset = offset + len - b_count;
  8405. ret = tg3_nvram_read_be32(tp, b_offset, &val);
  8406. if (ret)
  8407. return ret;
  8408. memcpy(pd, &val, b_count);
  8409. eeprom->len += b_count;
  8410. }
  8411. return 0;
  8412. }
  8413. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
  8414. static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  8415. {
  8416. struct tg3 *tp = netdev_priv(dev);
  8417. int ret;
  8418. u32 offset, len, b_offset, odd_len;
  8419. u8 *buf;
  8420. __be32 start, end;
  8421. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  8422. return -EAGAIN;
  8423. if (tg3_flag(tp, NO_NVRAM) ||
  8424. eeprom->magic != TG3_EEPROM_MAGIC)
  8425. return -EINVAL;
  8426. offset = eeprom->offset;
  8427. len = eeprom->len;
  8428. if ((b_offset = (offset & 3))) {
  8429. /* adjustments to start on required 4 byte boundary */
  8430. ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
  8431. if (ret)
  8432. return ret;
  8433. len += b_offset;
  8434. offset &= ~3;
  8435. if (len < 4)
  8436. len = 4;
  8437. }
  8438. odd_len = 0;
  8439. if (len & 3) {
  8440. /* adjustments to end on required 4 byte boundary */
  8441. odd_len = 1;
  8442. len = (len + 3) & ~3;
  8443. ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
  8444. if (ret)
  8445. return ret;
  8446. }
  8447. buf = data;
  8448. if (b_offset || odd_len) {
  8449. buf = kmalloc(len, GFP_KERNEL);
  8450. if (!buf)
  8451. return -ENOMEM;
  8452. if (b_offset)
  8453. memcpy(buf, &start, 4);
  8454. if (odd_len)
  8455. memcpy(buf+len-4, &end, 4);
  8456. memcpy(buf + b_offset, data, eeprom->len);
  8457. }
  8458. ret = tg3_nvram_write_block(tp, offset, len, buf);
  8459. if (buf != data)
  8460. kfree(buf);
  8461. return ret;
  8462. }
  8463. static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  8464. {
  8465. struct tg3 *tp = netdev_priv(dev);
  8466. if (tg3_flag(tp, USE_PHYLIB)) {
  8467. struct phy_device *phydev;
  8468. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  8469. return -EAGAIN;
  8470. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  8471. return phy_ethtool_gset(phydev, cmd);
  8472. }
  8473. cmd->supported = (SUPPORTED_Autoneg);
  8474. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  8475. cmd->supported |= (SUPPORTED_1000baseT_Half |
  8476. SUPPORTED_1000baseT_Full);
  8477. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  8478. cmd->supported |= (SUPPORTED_100baseT_Half |
  8479. SUPPORTED_100baseT_Full |
  8480. SUPPORTED_10baseT_Half |
  8481. SUPPORTED_10baseT_Full |
  8482. SUPPORTED_TP);
  8483. cmd->port = PORT_TP;
  8484. } else {
  8485. cmd->supported |= SUPPORTED_FIBRE;
  8486. cmd->port = PORT_FIBRE;
  8487. }
  8488. cmd->advertising = tp->link_config.advertising;
  8489. if (tg3_flag(tp, PAUSE_AUTONEG)) {
  8490. if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
  8491. if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
  8492. cmd->advertising |= ADVERTISED_Pause;
  8493. } else {
  8494. cmd->advertising |= ADVERTISED_Pause |
  8495. ADVERTISED_Asym_Pause;
  8496. }
  8497. } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
  8498. cmd->advertising |= ADVERTISED_Asym_Pause;
  8499. }
  8500. }
  8501. if (netif_running(dev)) {
  8502. ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
  8503. cmd->duplex = tp->link_config.active_duplex;
  8504. } else {
  8505. ethtool_cmd_speed_set(cmd, SPEED_INVALID);
  8506. cmd->duplex = DUPLEX_INVALID;
  8507. }
  8508. cmd->phy_address = tp->phy_addr;
  8509. cmd->transceiver = XCVR_INTERNAL;
  8510. cmd->autoneg = tp->link_config.autoneg;
  8511. cmd->maxtxpkt = 0;
  8512. cmd->maxrxpkt = 0;
  8513. return 0;
  8514. }
  8515. static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  8516. {
  8517. struct tg3 *tp = netdev_priv(dev);
  8518. u32 speed = ethtool_cmd_speed(cmd);
  8519. if (tg3_flag(tp, USE_PHYLIB)) {
  8520. struct phy_device *phydev;
  8521. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  8522. return -EAGAIN;
  8523. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  8524. return phy_ethtool_sset(phydev, cmd);
  8525. }
  8526. if (cmd->autoneg != AUTONEG_ENABLE &&
  8527. cmd->autoneg != AUTONEG_DISABLE)
  8528. return -EINVAL;
  8529. if (cmd->autoneg == AUTONEG_DISABLE &&
  8530. cmd->duplex != DUPLEX_FULL &&
  8531. cmd->duplex != DUPLEX_HALF)
  8532. return -EINVAL;
  8533. if (cmd->autoneg == AUTONEG_ENABLE) {
  8534. u32 mask = ADVERTISED_Autoneg |
  8535. ADVERTISED_Pause |
  8536. ADVERTISED_Asym_Pause;
  8537. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  8538. mask |= ADVERTISED_1000baseT_Half |
  8539. ADVERTISED_1000baseT_Full;
  8540. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  8541. mask |= ADVERTISED_100baseT_Half |
  8542. ADVERTISED_100baseT_Full |
  8543. ADVERTISED_10baseT_Half |
  8544. ADVERTISED_10baseT_Full |
  8545. ADVERTISED_TP;
  8546. else
  8547. mask |= ADVERTISED_FIBRE;
  8548. if (cmd->advertising & ~mask)
  8549. return -EINVAL;
  8550. mask &= (ADVERTISED_1000baseT_Half |
  8551. ADVERTISED_1000baseT_Full |
  8552. ADVERTISED_100baseT_Half |
  8553. ADVERTISED_100baseT_Full |
  8554. ADVERTISED_10baseT_Half |
  8555. ADVERTISED_10baseT_Full);
  8556. cmd->advertising &= mask;
  8557. } else {
  8558. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
  8559. if (speed != SPEED_1000)
  8560. return -EINVAL;
  8561. if (cmd->duplex != DUPLEX_FULL)
  8562. return -EINVAL;
  8563. } else {
  8564. if (speed != SPEED_100 &&
  8565. speed != SPEED_10)
  8566. return -EINVAL;
  8567. }
  8568. }
  8569. tg3_full_lock(tp, 0);
  8570. tp->link_config.autoneg = cmd->autoneg;
  8571. if (cmd->autoneg == AUTONEG_ENABLE) {
  8572. tp->link_config.advertising = (cmd->advertising |
  8573. ADVERTISED_Autoneg);
  8574. tp->link_config.speed = SPEED_INVALID;
  8575. tp->link_config.duplex = DUPLEX_INVALID;
  8576. } else {
  8577. tp->link_config.advertising = 0;
  8578. tp->link_config.speed = speed;
  8579. tp->link_config.duplex = cmd->duplex;
  8580. }
  8581. tp->link_config.orig_speed = tp->link_config.speed;
  8582. tp->link_config.orig_duplex = tp->link_config.duplex;
  8583. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  8584. if (netif_running(dev))
  8585. tg3_setup_phy(tp, 1);
  8586. tg3_full_unlock(tp);
  8587. return 0;
  8588. }
  8589. static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  8590. {
  8591. struct tg3 *tp = netdev_priv(dev);
  8592. strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
  8593. strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
  8594. strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
  8595. strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
  8596. }
  8597. static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  8598. {
  8599. struct tg3 *tp = netdev_priv(dev);
  8600. if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
  8601. wol->supported = WAKE_MAGIC;
  8602. else
  8603. wol->supported = 0;
  8604. wol->wolopts = 0;
  8605. if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
  8606. wol->wolopts = WAKE_MAGIC;
  8607. memset(&wol->sopass, 0, sizeof(wol->sopass));
  8608. }
  8609. static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  8610. {
  8611. struct tg3 *tp = netdev_priv(dev);
  8612. struct device *dp = &tp->pdev->dev;
  8613. if (wol->wolopts & ~WAKE_MAGIC)
  8614. return -EINVAL;
  8615. if ((wol->wolopts & WAKE_MAGIC) &&
  8616. !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
  8617. return -EINVAL;
  8618. device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
  8619. spin_lock_bh(&tp->lock);
  8620. if (device_may_wakeup(dp))
  8621. tg3_flag_set(tp, WOL_ENABLE);
  8622. else
  8623. tg3_flag_clear(tp, WOL_ENABLE);
  8624. spin_unlock_bh(&tp->lock);
  8625. return 0;
  8626. }
  8627. static u32 tg3_get_msglevel(struct net_device *dev)
  8628. {
  8629. struct tg3 *tp = netdev_priv(dev);
  8630. return tp->msg_enable;
  8631. }
  8632. static void tg3_set_msglevel(struct net_device *dev, u32 value)
  8633. {
  8634. struct tg3 *tp = netdev_priv(dev);
  8635. tp->msg_enable = value;
  8636. }
  8637. static int tg3_nway_reset(struct net_device *dev)
  8638. {
  8639. struct tg3 *tp = netdev_priv(dev);
  8640. int r;
  8641. if (!netif_running(dev))
  8642. return -EAGAIN;
  8643. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  8644. return -EINVAL;
  8645. if (tg3_flag(tp, USE_PHYLIB)) {
  8646. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  8647. return -EAGAIN;
  8648. r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  8649. } else {
  8650. u32 bmcr;
  8651. spin_lock_bh(&tp->lock);
  8652. r = -EINVAL;
  8653. tg3_readphy(tp, MII_BMCR, &bmcr);
  8654. if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
  8655. ((bmcr & BMCR_ANENABLE) ||
  8656. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
  8657. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
  8658. BMCR_ANENABLE);
  8659. r = 0;
  8660. }
  8661. spin_unlock_bh(&tp->lock);
  8662. }
  8663. return r;
  8664. }
  8665. static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  8666. {
  8667. struct tg3 *tp = netdev_priv(dev);
  8668. ering->rx_max_pending = tp->rx_std_ring_mask;
  8669. if (tg3_flag(tp, JUMBO_RING_ENABLE))
  8670. ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
  8671. else
  8672. ering->rx_jumbo_max_pending = 0;
  8673. ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
  8674. ering->rx_pending = tp->rx_pending;
  8675. if (tg3_flag(tp, JUMBO_RING_ENABLE))
  8676. ering->rx_jumbo_pending = tp->rx_jumbo_pending;
  8677. else
  8678. ering->rx_jumbo_pending = 0;
  8679. ering->tx_pending = tp->napi[0].tx_pending;
  8680. }
  8681. static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  8682. {
  8683. struct tg3 *tp = netdev_priv(dev);
  8684. int i, irq_sync = 0, err = 0;
  8685. if ((ering->rx_pending > tp->rx_std_ring_mask) ||
  8686. (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
  8687. (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
  8688. (ering->tx_pending <= MAX_SKB_FRAGS) ||
  8689. (tg3_flag(tp, TSO_BUG) &&
  8690. (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
  8691. return -EINVAL;
  8692. if (netif_running(dev)) {
  8693. tg3_phy_stop(tp);
  8694. tg3_netif_stop(tp);
  8695. irq_sync = 1;
  8696. }
  8697. tg3_full_lock(tp, irq_sync);
  8698. tp->rx_pending = ering->rx_pending;
  8699. if (tg3_flag(tp, MAX_RXPEND_64) &&
  8700. tp->rx_pending > 63)
  8701. tp->rx_pending = 63;
  8702. tp->rx_jumbo_pending = ering->rx_jumbo_pending;
  8703. for (i = 0; i < tp->irq_max; i++)
  8704. tp->napi[i].tx_pending = ering->tx_pending;
  8705. if (netif_running(dev)) {
  8706. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8707. err = tg3_restart_hw(tp, 1);
  8708. if (!err)
  8709. tg3_netif_start(tp);
  8710. }
  8711. tg3_full_unlock(tp);
  8712. if (irq_sync && !err)
  8713. tg3_phy_start(tp);
  8714. return err;
  8715. }
  8716. static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  8717. {
  8718. struct tg3 *tp = netdev_priv(dev);
  8719. epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
  8720. if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
  8721. epause->rx_pause = 1;
  8722. else
  8723. epause->rx_pause = 0;
  8724. if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
  8725. epause->tx_pause = 1;
  8726. else
  8727. epause->tx_pause = 0;
  8728. }
  8729. static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  8730. {
  8731. struct tg3 *tp = netdev_priv(dev);
  8732. int err = 0;
  8733. if (tg3_flag(tp, USE_PHYLIB)) {
  8734. u32 newadv;
  8735. struct phy_device *phydev;
  8736. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  8737. if (!(phydev->supported & SUPPORTED_Pause) ||
  8738. (!(phydev->supported & SUPPORTED_Asym_Pause) &&
  8739. (epause->rx_pause != epause->tx_pause)))
  8740. return -EINVAL;
  8741. tp->link_config.flowctrl = 0;
  8742. if (epause->rx_pause) {
  8743. tp->link_config.flowctrl |= FLOW_CTRL_RX;
  8744. if (epause->tx_pause) {
  8745. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  8746. newadv = ADVERTISED_Pause;
  8747. } else
  8748. newadv = ADVERTISED_Pause |
  8749. ADVERTISED_Asym_Pause;
  8750. } else if (epause->tx_pause) {
  8751. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  8752. newadv = ADVERTISED_Asym_Pause;
  8753. } else
  8754. newadv = 0;
  8755. if (epause->autoneg)
  8756. tg3_flag_set(tp, PAUSE_AUTONEG);
  8757. else
  8758. tg3_flag_clear(tp, PAUSE_AUTONEG);
  8759. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  8760. u32 oldadv = phydev->advertising &
  8761. (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
  8762. if (oldadv != newadv) {
  8763. phydev->advertising &=
  8764. ~(ADVERTISED_Pause |
  8765. ADVERTISED_Asym_Pause);
  8766. phydev->advertising |= newadv;
  8767. if (phydev->autoneg) {
  8768. /*
  8769. * Always renegotiate the link to
  8770. * inform our link partner of our
  8771. * flow control settings, even if the
  8772. * flow control is forced. Let
  8773. * tg3_adjust_link() do the final
  8774. * flow control setup.
  8775. */
  8776. return phy_start_aneg(phydev);
  8777. }
  8778. }
  8779. if (!epause->autoneg)
  8780. tg3_setup_flow_control(tp, 0, 0);
  8781. } else {
  8782. tp->link_config.orig_advertising &=
  8783. ~(ADVERTISED_Pause |
  8784. ADVERTISED_Asym_Pause);
  8785. tp->link_config.orig_advertising |= newadv;
  8786. }
  8787. } else {
  8788. int irq_sync = 0;
  8789. if (netif_running(dev)) {
  8790. tg3_netif_stop(tp);
  8791. irq_sync = 1;
  8792. }
  8793. tg3_full_lock(tp, irq_sync);
  8794. if (epause->autoneg)
  8795. tg3_flag_set(tp, PAUSE_AUTONEG);
  8796. else
  8797. tg3_flag_clear(tp, PAUSE_AUTONEG);
  8798. if (epause->rx_pause)
  8799. tp->link_config.flowctrl |= FLOW_CTRL_RX;
  8800. else
  8801. tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
  8802. if (epause->tx_pause)
  8803. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  8804. else
  8805. tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
  8806. if (netif_running(dev)) {
  8807. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8808. err = tg3_restart_hw(tp, 1);
  8809. if (!err)
  8810. tg3_netif_start(tp);
  8811. }
  8812. tg3_full_unlock(tp);
  8813. }
  8814. return err;
  8815. }
  8816. static int tg3_get_sset_count(struct net_device *dev, int sset)
  8817. {
  8818. switch (sset) {
  8819. case ETH_SS_TEST:
  8820. return TG3_NUM_TEST;
  8821. case ETH_SS_STATS:
  8822. return TG3_NUM_STATS;
  8823. default:
  8824. return -EOPNOTSUPP;
  8825. }
  8826. }
  8827. static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
  8828. {
  8829. switch (stringset) {
  8830. case ETH_SS_STATS:
  8831. memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
  8832. break;
  8833. case ETH_SS_TEST:
  8834. memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
  8835. break;
  8836. default:
  8837. WARN_ON(1); /* we need a WARN() */
  8838. break;
  8839. }
  8840. }
  8841. static int tg3_set_phys_id(struct net_device *dev,
  8842. enum ethtool_phys_id_state state)
  8843. {
  8844. struct tg3 *tp = netdev_priv(dev);
  8845. if (!netif_running(tp->dev))
  8846. return -EAGAIN;
  8847. switch (state) {
  8848. case ETHTOOL_ID_ACTIVE:
  8849. return 1; /* cycle on/off once per second */
  8850. case ETHTOOL_ID_ON:
  8851. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  8852. LED_CTRL_1000MBPS_ON |
  8853. LED_CTRL_100MBPS_ON |
  8854. LED_CTRL_10MBPS_ON |
  8855. LED_CTRL_TRAFFIC_OVERRIDE |
  8856. LED_CTRL_TRAFFIC_BLINK |
  8857. LED_CTRL_TRAFFIC_LED);
  8858. break;
  8859. case ETHTOOL_ID_OFF:
  8860. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  8861. LED_CTRL_TRAFFIC_OVERRIDE);
  8862. break;
  8863. case ETHTOOL_ID_INACTIVE:
  8864. tw32(MAC_LED_CTRL, tp->led_ctrl);
  8865. break;
  8866. }
  8867. return 0;
  8868. }
  8869. static void tg3_get_ethtool_stats(struct net_device *dev,
  8870. struct ethtool_stats *estats, u64 *tmp_stats)
  8871. {
  8872. struct tg3 *tp = netdev_priv(dev);
  8873. memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
  8874. }
  8875. static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
  8876. {
  8877. int i;
  8878. __be32 *buf;
  8879. u32 offset = 0, len = 0;
  8880. u32 magic, val;
  8881. if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
  8882. return NULL;
  8883. if (magic == TG3_EEPROM_MAGIC) {
  8884. for (offset = TG3_NVM_DIR_START;
  8885. offset < TG3_NVM_DIR_END;
  8886. offset += TG3_NVM_DIRENT_SIZE) {
  8887. if (tg3_nvram_read(tp, offset, &val))
  8888. return NULL;
  8889. if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
  8890. TG3_NVM_DIRTYPE_EXTVPD)
  8891. break;
  8892. }
  8893. if (offset != TG3_NVM_DIR_END) {
  8894. len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
  8895. if (tg3_nvram_read(tp, offset + 4, &offset))
  8896. return NULL;
  8897. offset = tg3_nvram_logical_addr(tp, offset);
  8898. }
  8899. }
  8900. if (!offset || !len) {
  8901. offset = TG3_NVM_VPD_OFF;
  8902. len = TG3_NVM_VPD_LEN;
  8903. }
  8904. buf = kmalloc(len, GFP_KERNEL);
  8905. if (buf == NULL)
  8906. return NULL;
  8907. if (magic == TG3_EEPROM_MAGIC) {
  8908. for (i = 0; i < len; i += 4) {
  8909. /* The data is in little-endian format in NVRAM.
  8910. * Use the big-endian read routines to preserve
  8911. * the byte order as it exists in NVRAM.
  8912. */
  8913. if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
  8914. goto error;
  8915. }
  8916. } else {
  8917. u8 *ptr;
  8918. ssize_t cnt;
  8919. unsigned int pos = 0;
  8920. ptr = (u8 *)&buf[0];
  8921. for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
  8922. cnt = pci_read_vpd(tp->pdev, pos,
  8923. len - pos, ptr);
  8924. if (cnt == -ETIMEDOUT || cnt == -EINTR)
  8925. cnt = 0;
  8926. else if (cnt < 0)
  8927. goto error;
  8928. }
  8929. if (pos != len)
  8930. goto error;
  8931. }
  8932. *vpdlen = len;
  8933. return buf;
  8934. error:
  8935. kfree(buf);
  8936. return NULL;
  8937. }
  8938. #define NVRAM_TEST_SIZE 0x100
  8939. #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
  8940. #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
  8941. #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
  8942. #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
  8943. #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
  8944. #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
  8945. #define NVRAM_SELFBOOT_HW_SIZE 0x20
  8946. #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
  8947. static int tg3_test_nvram(struct tg3 *tp)
  8948. {
  8949. u32 csum, magic, len;
  8950. __be32 *buf;
  8951. int i, j, k, err = 0, size;
  8952. if (tg3_flag(tp, NO_NVRAM))
  8953. return 0;
  8954. if (tg3_nvram_read(tp, 0, &magic) != 0)
  8955. return -EIO;
  8956. if (magic == TG3_EEPROM_MAGIC)
  8957. size = NVRAM_TEST_SIZE;
  8958. else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
  8959. if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
  8960. TG3_EEPROM_SB_FORMAT_1) {
  8961. switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
  8962. case TG3_EEPROM_SB_REVISION_0:
  8963. size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
  8964. break;
  8965. case TG3_EEPROM_SB_REVISION_2:
  8966. size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
  8967. break;
  8968. case TG3_EEPROM_SB_REVISION_3:
  8969. size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
  8970. break;
  8971. case TG3_EEPROM_SB_REVISION_4:
  8972. size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
  8973. break;
  8974. case TG3_EEPROM_SB_REVISION_5:
  8975. size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
  8976. break;
  8977. case TG3_EEPROM_SB_REVISION_6:
  8978. size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
  8979. break;
  8980. default:
  8981. return -EIO;
  8982. }
  8983. } else
  8984. return 0;
  8985. } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  8986. size = NVRAM_SELFBOOT_HW_SIZE;
  8987. else
  8988. return -EIO;
  8989. buf = kmalloc(size, GFP_KERNEL);
  8990. if (buf == NULL)
  8991. return -ENOMEM;
  8992. err = -EIO;
  8993. for (i = 0, j = 0; i < size; i += 4, j++) {
  8994. err = tg3_nvram_read_be32(tp, i, &buf[j]);
  8995. if (err)
  8996. break;
  8997. }
  8998. if (i < size)
  8999. goto out;
  9000. /* Selfboot format */
  9001. magic = be32_to_cpu(buf[0]);
  9002. if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
  9003. TG3_EEPROM_MAGIC_FW) {
  9004. u8 *buf8 = (u8 *) buf, csum8 = 0;
  9005. if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
  9006. TG3_EEPROM_SB_REVISION_2) {
  9007. /* For rev 2, the csum doesn't include the MBA. */
  9008. for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
  9009. csum8 += buf8[i];
  9010. for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
  9011. csum8 += buf8[i];
  9012. } else {
  9013. for (i = 0; i < size; i++)
  9014. csum8 += buf8[i];
  9015. }
  9016. if (csum8 == 0) {
  9017. err = 0;
  9018. goto out;
  9019. }
  9020. err = -EIO;
  9021. goto out;
  9022. }
  9023. if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
  9024. TG3_EEPROM_MAGIC_HW) {
  9025. u8 data[NVRAM_SELFBOOT_DATA_SIZE];
  9026. u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
  9027. u8 *buf8 = (u8 *) buf;
  9028. /* Separate the parity bits and the data bytes. */
  9029. for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
  9030. if ((i == 0) || (i == 8)) {
  9031. int l;
  9032. u8 msk;
  9033. for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
  9034. parity[k++] = buf8[i] & msk;
  9035. i++;
  9036. } else if (i == 16) {
  9037. int l;
  9038. u8 msk;
  9039. for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
  9040. parity[k++] = buf8[i] & msk;
  9041. i++;
  9042. for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
  9043. parity[k++] = buf8[i] & msk;
  9044. i++;
  9045. }
  9046. data[j++] = buf8[i];
  9047. }
  9048. err = -EIO;
  9049. for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
  9050. u8 hw8 = hweight8(data[i]);
  9051. if ((hw8 & 0x1) && parity[i])
  9052. goto out;
  9053. else if (!(hw8 & 0x1) && !parity[i])
  9054. goto out;
  9055. }
  9056. err = 0;
  9057. goto out;
  9058. }
  9059. err = -EIO;
  9060. /* Bootstrap checksum at offset 0x10 */
  9061. csum = calc_crc((unsigned char *) buf, 0x10);
  9062. if (csum != le32_to_cpu(buf[0x10/4]))
  9063. goto out;
  9064. /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
  9065. csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
  9066. if (csum != le32_to_cpu(buf[0xfc/4]))
  9067. goto out;
  9068. kfree(buf);
  9069. buf = tg3_vpd_readblock(tp, &len);
  9070. if (!buf)
  9071. return -ENOMEM;
  9072. i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
  9073. if (i > 0) {
  9074. j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
  9075. if (j < 0)
  9076. goto out;
  9077. if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
  9078. goto out;
  9079. i += PCI_VPD_LRDT_TAG_SIZE;
  9080. j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
  9081. PCI_VPD_RO_KEYWORD_CHKSUM);
  9082. if (j > 0) {
  9083. u8 csum8 = 0;
  9084. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  9085. for (i = 0; i <= j; i++)
  9086. csum8 += ((u8 *)buf)[i];
  9087. if (csum8)
  9088. goto out;
  9089. }
  9090. }
  9091. err = 0;
  9092. out:
  9093. kfree(buf);
  9094. return err;
  9095. }
  9096. #define TG3_SERDES_TIMEOUT_SEC 2
  9097. #define TG3_COPPER_TIMEOUT_SEC 6
  9098. static int tg3_test_link(struct tg3 *tp)
  9099. {
  9100. int i, max;
  9101. if (!netif_running(tp->dev))
  9102. return -ENODEV;
  9103. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  9104. max = TG3_SERDES_TIMEOUT_SEC;
  9105. else
  9106. max = TG3_COPPER_TIMEOUT_SEC;
  9107. for (i = 0; i < max; i++) {
  9108. if (netif_carrier_ok(tp->dev))
  9109. return 0;
  9110. if (msleep_interruptible(1000))
  9111. break;
  9112. }
  9113. return -EIO;
  9114. }
  9115. /* Only test the commonly used registers */
  9116. static int tg3_test_registers(struct tg3 *tp)
  9117. {
  9118. int i, is_5705, is_5750;
  9119. u32 offset, read_mask, write_mask, val, save_val, read_val;
  9120. static struct {
  9121. u16 offset;
  9122. u16 flags;
  9123. #define TG3_FL_5705 0x1
  9124. #define TG3_FL_NOT_5705 0x2
  9125. #define TG3_FL_NOT_5788 0x4
  9126. #define TG3_FL_NOT_5750 0x8
  9127. u32 read_mask;
  9128. u32 write_mask;
  9129. } reg_tbl[] = {
  9130. /* MAC Control Registers */
  9131. { MAC_MODE, TG3_FL_NOT_5705,
  9132. 0x00000000, 0x00ef6f8c },
  9133. { MAC_MODE, TG3_FL_5705,
  9134. 0x00000000, 0x01ef6b8c },
  9135. { MAC_STATUS, TG3_FL_NOT_5705,
  9136. 0x03800107, 0x00000000 },
  9137. { MAC_STATUS, TG3_FL_5705,
  9138. 0x03800100, 0x00000000 },
  9139. { MAC_ADDR_0_HIGH, 0x0000,
  9140. 0x00000000, 0x0000ffff },
  9141. { MAC_ADDR_0_LOW, 0x0000,
  9142. 0x00000000, 0xffffffff },
  9143. { MAC_RX_MTU_SIZE, 0x0000,
  9144. 0x00000000, 0x0000ffff },
  9145. { MAC_TX_MODE, 0x0000,
  9146. 0x00000000, 0x00000070 },
  9147. { MAC_TX_LENGTHS, 0x0000,
  9148. 0x00000000, 0x00003fff },
  9149. { MAC_RX_MODE, TG3_FL_NOT_5705,
  9150. 0x00000000, 0x000007fc },
  9151. { MAC_RX_MODE, TG3_FL_5705,
  9152. 0x00000000, 0x000007dc },
  9153. { MAC_HASH_REG_0, 0x0000,
  9154. 0x00000000, 0xffffffff },
  9155. { MAC_HASH_REG_1, 0x0000,
  9156. 0x00000000, 0xffffffff },
  9157. { MAC_HASH_REG_2, 0x0000,
  9158. 0x00000000, 0xffffffff },
  9159. { MAC_HASH_REG_3, 0x0000,
  9160. 0x00000000, 0xffffffff },
  9161. /* Receive Data and Receive BD Initiator Control Registers. */
  9162. { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
  9163. 0x00000000, 0xffffffff },
  9164. { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
  9165. 0x00000000, 0xffffffff },
  9166. { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
  9167. 0x00000000, 0x00000003 },
  9168. { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
  9169. 0x00000000, 0xffffffff },
  9170. { RCVDBDI_STD_BD+0, 0x0000,
  9171. 0x00000000, 0xffffffff },
  9172. { RCVDBDI_STD_BD+4, 0x0000,
  9173. 0x00000000, 0xffffffff },
  9174. { RCVDBDI_STD_BD+8, 0x0000,
  9175. 0x00000000, 0xffff0002 },
  9176. { RCVDBDI_STD_BD+0xc, 0x0000,
  9177. 0x00000000, 0xffffffff },
  9178. /* Receive BD Initiator Control Registers. */
  9179. { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
  9180. 0x00000000, 0xffffffff },
  9181. { RCVBDI_STD_THRESH, TG3_FL_5705,
  9182. 0x00000000, 0x000003ff },
  9183. { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
  9184. 0x00000000, 0xffffffff },
  9185. /* Host Coalescing Control Registers. */
  9186. { HOSTCC_MODE, TG3_FL_NOT_5705,
  9187. 0x00000000, 0x00000004 },
  9188. { HOSTCC_MODE, TG3_FL_5705,
  9189. 0x00000000, 0x000000f6 },
  9190. { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
  9191. 0x00000000, 0xffffffff },
  9192. { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
  9193. 0x00000000, 0x000003ff },
  9194. { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
  9195. 0x00000000, 0xffffffff },
  9196. { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
  9197. 0x00000000, 0x000003ff },
  9198. { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
  9199. 0x00000000, 0xffffffff },
  9200. { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  9201. 0x00000000, 0x000000ff },
  9202. { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
  9203. 0x00000000, 0xffffffff },
  9204. { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  9205. 0x00000000, 0x000000ff },
  9206. { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
  9207. 0x00000000, 0xffffffff },
  9208. { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
  9209. 0x00000000, 0xffffffff },
  9210. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  9211. 0x00000000, 0xffffffff },
  9212. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  9213. 0x00000000, 0x000000ff },
  9214. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  9215. 0x00000000, 0xffffffff },
  9216. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  9217. 0x00000000, 0x000000ff },
  9218. { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
  9219. 0x00000000, 0xffffffff },
  9220. { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
  9221. 0x00000000, 0xffffffff },
  9222. { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
  9223. 0x00000000, 0xffffffff },
  9224. { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
  9225. 0x00000000, 0xffffffff },
  9226. { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
  9227. 0x00000000, 0xffffffff },
  9228. { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
  9229. 0xffffffff, 0x00000000 },
  9230. { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
  9231. 0xffffffff, 0x00000000 },
  9232. /* Buffer Manager Control Registers. */
  9233. { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
  9234. 0x00000000, 0x007fff80 },
  9235. { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
  9236. 0x00000000, 0x007fffff },
  9237. { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
  9238. 0x00000000, 0x0000003f },
  9239. { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
  9240. 0x00000000, 0x000001ff },
  9241. { BUFMGR_MB_HIGH_WATER, 0x0000,
  9242. 0x00000000, 0x000001ff },
  9243. { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
  9244. 0xffffffff, 0x00000000 },
  9245. { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
  9246. 0xffffffff, 0x00000000 },
  9247. /* Mailbox Registers */
  9248. { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
  9249. 0x00000000, 0x000001ff },
  9250. { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
  9251. 0x00000000, 0x000001ff },
  9252. { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
  9253. 0x00000000, 0x000007ff },
  9254. { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
  9255. 0x00000000, 0x000001ff },
  9256. { 0xffff, 0x0000, 0x00000000, 0x00000000 },
  9257. };
  9258. is_5705 = is_5750 = 0;
  9259. if (tg3_flag(tp, 5705_PLUS)) {
  9260. is_5705 = 1;
  9261. if (tg3_flag(tp, 5750_PLUS))
  9262. is_5750 = 1;
  9263. }
  9264. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  9265. if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
  9266. continue;
  9267. if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
  9268. continue;
  9269. if (tg3_flag(tp, IS_5788) &&
  9270. (reg_tbl[i].flags & TG3_FL_NOT_5788))
  9271. continue;
  9272. if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
  9273. continue;
  9274. offset = (u32) reg_tbl[i].offset;
  9275. read_mask = reg_tbl[i].read_mask;
  9276. write_mask = reg_tbl[i].write_mask;
  9277. /* Save the original register content */
  9278. save_val = tr32(offset);
  9279. /* Determine the read-only value. */
  9280. read_val = save_val & read_mask;
  9281. /* Write zero to the register, then make sure the read-only bits
  9282. * are not changed and the read/write bits are all zeros.
  9283. */
  9284. tw32(offset, 0);
  9285. val = tr32(offset);
  9286. /* Test the read-only and read/write bits. */
  9287. if (((val & read_mask) != read_val) || (val & write_mask))
  9288. goto out;
  9289. /* Write ones to all the bits defined by RdMask and WrMask, then
  9290. * make sure the read-only bits are not changed and the
  9291. * read/write bits are all ones.
  9292. */
  9293. tw32(offset, read_mask | write_mask);
  9294. val = tr32(offset);
  9295. /* Test the read-only bits. */
  9296. if ((val & read_mask) != read_val)
  9297. goto out;
  9298. /* Test the read/write bits. */
  9299. if ((val & write_mask) != write_mask)
  9300. goto out;
  9301. tw32(offset, save_val);
  9302. }
  9303. return 0;
  9304. out:
  9305. if (netif_msg_hw(tp))
  9306. netdev_err(tp->dev,
  9307. "Register test failed at offset %x\n", offset);
  9308. tw32(offset, save_val);
  9309. return -EIO;
  9310. }
  9311. static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
  9312. {
  9313. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
  9314. int i;
  9315. u32 j;
  9316. for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
  9317. for (j = 0; j < len; j += 4) {
  9318. u32 val;
  9319. tg3_write_mem(tp, offset + j, test_pattern[i]);
  9320. tg3_read_mem(tp, offset + j, &val);
  9321. if (val != test_pattern[i])
  9322. return -EIO;
  9323. }
  9324. }
  9325. return 0;
  9326. }
  9327. static int tg3_test_memory(struct tg3 *tp)
  9328. {
  9329. static struct mem_entry {
  9330. u32 offset;
  9331. u32 len;
  9332. } mem_tbl_570x[] = {
  9333. { 0x00000000, 0x00b50},
  9334. { 0x00002000, 0x1c000},
  9335. { 0xffffffff, 0x00000}
  9336. }, mem_tbl_5705[] = {
  9337. { 0x00000100, 0x0000c},
  9338. { 0x00000200, 0x00008},
  9339. { 0x00004000, 0x00800},
  9340. { 0x00006000, 0x01000},
  9341. { 0x00008000, 0x02000},
  9342. { 0x00010000, 0x0e000},
  9343. { 0xffffffff, 0x00000}
  9344. }, mem_tbl_5755[] = {
  9345. { 0x00000200, 0x00008},
  9346. { 0x00004000, 0x00800},
  9347. { 0x00006000, 0x00800},
  9348. { 0x00008000, 0x02000},
  9349. { 0x00010000, 0x0c000},
  9350. { 0xffffffff, 0x00000}
  9351. }, mem_tbl_5906[] = {
  9352. { 0x00000200, 0x00008},
  9353. { 0x00004000, 0x00400},
  9354. { 0x00006000, 0x00400},
  9355. { 0x00008000, 0x01000},
  9356. { 0x00010000, 0x01000},
  9357. { 0xffffffff, 0x00000}
  9358. }, mem_tbl_5717[] = {
  9359. { 0x00000200, 0x00008},
  9360. { 0x00010000, 0x0a000},
  9361. { 0x00020000, 0x13c00},
  9362. { 0xffffffff, 0x00000}
  9363. }, mem_tbl_57765[] = {
  9364. { 0x00000200, 0x00008},
  9365. { 0x00004000, 0x00800},
  9366. { 0x00006000, 0x09800},
  9367. { 0x00010000, 0x0a000},
  9368. { 0xffffffff, 0x00000}
  9369. };
  9370. struct mem_entry *mem_tbl;
  9371. int err = 0;
  9372. int i;
  9373. if (tg3_flag(tp, 5717_PLUS))
  9374. mem_tbl = mem_tbl_5717;
  9375. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  9376. mem_tbl = mem_tbl_57765;
  9377. else if (tg3_flag(tp, 5755_PLUS))
  9378. mem_tbl = mem_tbl_5755;
  9379. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9380. mem_tbl = mem_tbl_5906;
  9381. else if (tg3_flag(tp, 5705_PLUS))
  9382. mem_tbl = mem_tbl_5705;
  9383. else
  9384. mem_tbl = mem_tbl_570x;
  9385. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  9386. err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
  9387. if (err)
  9388. break;
  9389. }
  9390. return err;
  9391. }
  9392. #define TG3_TSO_MSS 500
  9393. #define TG3_TSO_IP_HDR_LEN 20
  9394. #define TG3_TSO_TCP_HDR_LEN 20
  9395. #define TG3_TSO_TCP_OPT_LEN 12
  9396. static const u8 tg3_tso_header[] = {
  9397. 0x08, 0x00,
  9398. 0x45, 0x00, 0x00, 0x00,
  9399. 0x00, 0x00, 0x40, 0x00,
  9400. 0x40, 0x06, 0x00, 0x00,
  9401. 0x0a, 0x00, 0x00, 0x01,
  9402. 0x0a, 0x00, 0x00, 0x02,
  9403. 0x0d, 0x00, 0xe0, 0x00,
  9404. 0x00, 0x00, 0x01, 0x00,
  9405. 0x00, 0x00, 0x02, 0x00,
  9406. 0x80, 0x10, 0x10, 0x00,
  9407. 0x14, 0x09, 0x00, 0x00,
  9408. 0x01, 0x01, 0x08, 0x0a,
  9409. 0x11, 0x11, 0x11, 0x11,
  9410. 0x11, 0x11, 0x11, 0x11,
  9411. };
  9412. static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
  9413. {
  9414. u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
  9415. u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
  9416. u32 budget;
  9417. struct sk_buff *skb;
  9418. u8 *tx_data, *rx_data;
  9419. dma_addr_t map;
  9420. int num_pkts, tx_len, rx_len, i, err;
  9421. struct tg3_rx_buffer_desc *desc;
  9422. struct tg3_napi *tnapi, *rnapi;
  9423. struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
  9424. tnapi = &tp->napi[0];
  9425. rnapi = &tp->napi[0];
  9426. if (tp->irq_cnt > 1) {
  9427. if (tg3_flag(tp, ENABLE_RSS))
  9428. rnapi = &tp->napi[1];
  9429. if (tg3_flag(tp, ENABLE_TSS))
  9430. tnapi = &tp->napi[1];
  9431. }
  9432. coal_now = tnapi->coal_now | rnapi->coal_now;
  9433. err = -EIO;
  9434. tx_len = pktsz;
  9435. skb = netdev_alloc_skb(tp->dev, tx_len);
  9436. if (!skb)
  9437. return -ENOMEM;
  9438. tx_data = skb_put(skb, tx_len);
  9439. memcpy(tx_data, tp->dev->dev_addr, 6);
  9440. memset(tx_data + 6, 0x0, 8);
  9441. tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
  9442. if (tso_loopback) {
  9443. struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
  9444. u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
  9445. TG3_TSO_TCP_OPT_LEN;
  9446. memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
  9447. sizeof(tg3_tso_header));
  9448. mss = TG3_TSO_MSS;
  9449. val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
  9450. num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
  9451. /* Set the total length field in the IP header */
  9452. iph->tot_len = htons((u16)(mss + hdr_len));
  9453. base_flags = (TXD_FLAG_CPU_PRE_DMA |
  9454. TXD_FLAG_CPU_POST_DMA);
  9455. if (tg3_flag(tp, HW_TSO_1) ||
  9456. tg3_flag(tp, HW_TSO_2) ||
  9457. tg3_flag(tp, HW_TSO_3)) {
  9458. struct tcphdr *th;
  9459. val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
  9460. th = (struct tcphdr *)&tx_data[val];
  9461. th->check = 0;
  9462. } else
  9463. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  9464. if (tg3_flag(tp, HW_TSO_3)) {
  9465. mss |= (hdr_len & 0xc) << 12;
  9466. if (hdr_len & 0x10)
  9467. base_flags |= 0x00000010;
  9468. base_flags |= (hdr_len & 0x3e0) << 5;
  9469. } else if (tg3_flag(tp, HW_TSO_2))
  9470. mss |= hdr_len << 9;
  9471. else if (tg3_flag(tp, HW_TSO_1) ||
  9472. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  9473. mss |= (TG3_TSO_TCP_OPT_LEN << 9);
  9474. } else {
  9475. base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
  9476. }
  9477. data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
  9478. } else {
  9479. num_pkts = 1;
  9480. data_off = ETH_HLEN;
  9481. }
  9482. for (i = data_off; i < tx_len; i++)
  9483. tx_data[i] = (u8) (i & 0xff);
  9484. map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
  9485. if (pci_dma_mapping_error(tp->pdev, map)) {
  9486. dev_kfree_skb(skb);
  9487. return -EIO;
  9488. }
  9489. val = tnapi->tx_prod;
  9490. tnapi->tx_buffers[val].skb = skb;
  9491. dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
  9492. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  9493. rnapi->coal_now);
  9494. udelay(10);
  9495. rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
  9496. budget = tg3_tx_avail(tnapi);
  9497. if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
  9498. base_flags | TXD_FLAG_END, mss, 0)) {
  9499. tnapi->tx_buffers[val].skb = NULL;
  9500. dev_kfree_skb(skb);
  9501. return -EIO;
  9502. }
  9503. tnapi->tx_prod++;
  9504. tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
  9505. tr32_mailbox(tnapi->prodmbox);
  9506. udelay(10);
  9507. /* 350 usec to allow enough time on some 10/100 Mbps devices. */
  9508. for (i = 0; i < 35; i++) {
  9509. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  9510. coal_now);
  9511. udelay(10);
  9512. tx_idx = tnapi->hw_status->idx[0].tx_consumer;
  9513. rx_idx = rnapi->hw_status->idx[0].rx_producer;
  9514. if ((tx_idx == tnapi->tx_prod) &&
  9515. (rx_idx == (rx_start_idx + num_pkts)))
  9516. break;
  9517. }
  9518. tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
  9519. dev_kfree_skb(skb);
  9520. if (tx_idx != tnapi->tx_prod)
  9521. goto out;
  9522. if (rx_idx != rx_start_idx + num_pkts)
  9523. goto out;
  9524. val = data_off;
  9525. while (rx_idx != rx_start_idx) {
  9526. desc = &rnapi->rx_rcb[rx_start_idx++];
  9527. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  9528. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  9529. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  9530. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
  9531. goto out;
  9532. rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
  9533. - ETH_FCS_LEN;
  9534. if (!tso_loopback) {
  9535. if (rx_len != tx_len)
  9536. goto out;
  9537. if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
  9538. if (opaque_key != RXD_OPAQUE_RING_STD)
  9539. goto out;
  9540. } else {
  9541. if (opaque_key != RXD_OPAQUE_RING_JUMBO)
  9542. goto out;
  9543. }
  9544. } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  9545. (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  9546. >> RXD_TCPCSUM_SHIFT != 0xffff) {
  9547. goto out;
  9548. }
  9549. if (opaque_key == RXD_OPAQUE_RING_STD) {
  9550. rx_data = tpr->rx_std_buffers[desc_idx].data;
  9551. map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
  9552. mapping);
  9553. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  9554. rx_data = tpr->rx_jmb_buffers[desc_idx].data;
  9555. map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
  9556. mapping);
  9557. } else
  9558. goto out;
  9559. pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
  9560. PCI_DMA_FROMDEVICE);
  9561. rx_data += TG3_RX_OFFSET(tp);
  9562. for (i = data_off; i < rx_len; i++, val++) {
  9563. if (*(rx_data + i) != (u8) (val & 0xff))
  9564. goto out;
  9565. }
  9566. }
  9567. err = 0;
  9568. /* tg3_free_rings will unmap and free the rx_data */
  9569. out:
  9570. return err;
  9571. }
  9572. #define TG3_STD_LOOPBACK_FAILED 1
  9573. #define TG3_JMB_LOOPBACK_FAILED 2
  9574. #define TG3_TSO_LOOPBACK_FAILED 4
  9575. #define TG3_LOOPBACK_FAILED \
  9576. (TG3_STD_LOOPBACK_FAILED | \
  9577. TG3_JMB_LOOPBACK_FAILED | \
  9578. TG3_TSO_LOOPBACK_FAILED)
  9579. static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
  9580. {
  9581. int err = -EIO;
  9582. u32 eee_cap;
  9583. eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
  9584. tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
  9585. if (!netif_running(tp->dev)) {
  9586. data[0] = TG3_LOOPBACK_FAILED;
  9587. data[1] = TG3_LOOPBACK_FAILED;
  9588. if (do_extlpbk)
  9589. data[2] = TG3_LOOPBACK_FAILED;
  9590. goto done;
  9591. }
  9592. err = tg3_reset_hw(tp, 1);
  9593. if (err) {
  9594. data[0] = TG3_LOOPBACK_FAILED;
  9595. data[1] = TG3_LOOPBACK_FAILED;
  9596. if (do_extlpbk)
  9597. data[2] = TG3_LOOPBACK_FAILED;
  9598. goto done;
  9599. }
  9600. if (tg3_flag(tp, ENABLE_RSS)) {
  9601. int i;
  9602. /* Reroute all rx packets to the 1st queue */
  9603. for (i = MAC_RSS_INDIR_TBL_0;
  9604. i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
  9605. tw32(i, 0x0);
  9606. }
  9607. /* HW errata - mac loopback fails in some cases on 5780.
  9608. * Normal traffic and PHY loopback are not affected by
  9609. * errata. Also, the MAC loopback test is deprecated for
  9610. * all newer ASIC revisions.
  9611. */
  9612. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
  9613. !tg3_flag(tp, CPMU_PRESENT)) {
  9614. tg3_mac_loopback(tp, true);
  9615. if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
  9616. data[0] |= TG3_STD_LOOPBACK_FAILED;
  9617. if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
  9618. tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
  9619. data[0] |= TG3_JMB_LOOPBACK_FAILED;
  9620. tg3_mac_loopback(tp, false);
  9621. }
  9622. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  9623. !tg3_flag(tp, USE_PHYLIB)) {
  9624. int i;
  9625. tg3_phy_lpbk_set(tp, 0, false);
  9626. /* Wait for link */
  9627. for (i = 0; i < 100; i++) {
  9628. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  9629. break;
  9630. mdelay(1);
  9631. }
  9632. if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
  9633. data[1] |= TG3_STD_LOOPBACK_FAILED;
  9634. if (tg3_flag(tp, TSO_CAPABLE) &&
  9635. tg3_run_loopback(tp, ETH_FRAME_LEN, true))
  9636. data[1] |= TG3_TSO_LOOPBACK_FAILED;
  9637. if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
  9638. tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
  9639. data[1] |= TG3_JMB_LOOPBACK_FAILED;
  9640. if (do_extlpbk) {
  9641. tg3_phy_lpbk_set(tp, 0, true);
  9642. /* All link indications report up, but the hardware
  9643. * isn't really ready for about 20 msec. Double it
  9644. * to be sure.
  9645. */
  9646. mdelay(40);
  9647. if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
  9648. data[2] |= TG3_STD_LOOPBACK_FAILED;
  9649. if (tg3_flag(tp, TSO_CAPABLE) &&
  9650. tg3_run_loopback(tp, ETH_FRAME_LEN, true))
  9651. data[2] |= TG3_TSO_LOOPBACK_FAILED;
  9652. if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
  9653. tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
  9654. data[2] |= TG3_JMB_LOOPBACK_FAILED;
  9655. }
  9656. /* Re-enable gphy autopowerdown. */
  9657. if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
  9658. tg3_phy_toggle_apd(tp, true);
  9659. }
  9660. err = (data[0] | data[1] | data[2]) ? -EIO : 0;
  9661. done:
  9662. tp->phy_flags |= eee_cap;
  9663. return err;
  9664. }
  9665. static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
  9666. u64 *data)
  9667. {
  9668. struct tg3 *tp = netdev_priv(dev);
  9669. bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
  9670. if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
  9671. tg3_power_up(tp)) {
  9672. etest->flags |= ETH_TEST_FL_FAILED;
  9673. memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
  9674. return;
  9675. }
  9676. memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
  9677. if (tg3_test_nvram(tp) != 0) {
  9678. etest->flags |= ETH_TEST_FL_FAILED;
  9679. data[0] = 1;
  9680. }
  9681. if (!doextlpbk && tg3_test_link(tp)) {
  9682. etest->flags |= ETH_TEST_FL_FAILED;
  9683. data[1] = 1;
  9684. }
  9685. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  9686. int err, err2 = 0, irq_sync = 0;
  9687. if (netif_running(dev)) {
  9688. tg3_phy_stop(tp);
  9689. tg3_netif_stop(tp);
  9690. irq_sync = 1;
  9691. }
  9692. tg3_full_lock(tp, irq_sync);
  9693. tg3_halt(tp, RESET_KIND_SUSPEND, 1);
  9694. err = tg3_nvram_lock(tp);
  9695. tg3_halt_cpu(tp, RX_CPU_BASE);
  9696. if (!tg3_flag(tp, 5705_PLUS))
  9697. tg3_halt_cpu(tp, TX_CPU_BASE);
  9698. if (!err)
  9699. tg3_nvram_unlock(tp);
  9700. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  9701. tg3_phy_reset(tp);
  9702. if (tg3_test_registers(tp) != 0) {
  9703. etest->flags |= ETH_TEST_FL_FAILED;
  9704. data[2] = 1;
  9705. }
  9706. if (tg3_test_memory(tp) != 0) {
  9707. etest->flags |= ETH_TEST_FL_FAILED;
  9708. data[3] = 1;
  9709. }
  9710. if (doextlpbk)
  9711. etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
  9712. if (tg3_test_loopback(tp, &data[4], doextlpbk))
  9713. etest->flags |= ETH_TEST_FL_FAILED;
  9714. tg3_full_unlock(tp);
  9715. if (tg3_test_interrupt(tp) != 0) {
  9716. etest->flags |= ETH_TEST_FL_FAILED;
  9717. data[7] = 1;
  9718. }
  9719. tg3_full_lock(tp, 0);
  9720. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9721. if (netif_running(dev)) {
  9722. tg3_flag_set(tp, INIT_COMPLETE);
  9723. err2 = tg3_restart_hw(tp, 1);
  9724. if (!err2)
  9725. tg3_netif_start(tp);
  9726. }
  9727. tg3_full_unlock(tp);
  9728. if (irq_sync && !err2)
  9729. tg3_phy_start(tp);
  9730. }
  9731. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  9732. tg3_power_down(tp);
  9733. }
  9734. static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  9735. {
  9736. struct mii_ioctl_data *data = if_mii(ifr);
  9737. struct tg3 *tp = netdev_priv(dev);
  9738. int err;
  9739. if (tg3_flag(tp, USE_PHYLIB)) {
  9740. struct phy_device *phydev;
  9741. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  9742. return -EAGAIN;
  9743. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  9744. return phy_mii_ioctl(phydev, ifr, cmd);
  9745. }
  9746. switch (cmd) {
  9747. case SIOCGMIIPHY:
  9748. data->phy_id = tp->phy_addr;
  9749. /* fallthru */
  9750. case SIOCGMIIREG: {
  9751. u32 mii_regval;
  9752. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  9753. break; /* We have no PHY */
  9754. if (!netif_running(dev))
  9755. return -EAGAIN;
  9756. spin_lock_bh(&tp->lock);
  9757. err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
  9758. spin_unlock_bh(&tp->lock);
  9759. data->val_out = mii_regval;
  9760. return err;
  9761. }
  9762. case SIOCSMIIREG:
  9763. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  9764. break; /* We have no PHY */
  9765. if (!netif_running(dev))
  9766. return -EAGAIN;
  9767. spin_lock_bh(&tp->lock);
  9768. err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
  9769. spin_unlock_bh(&tp->lock);
  9770. return err;
  9771. default:
  9772. /* do nothing */
  9773. break;
  9774. }
  9775. return -EOPNOTSUPP;
  9776. }
  9777. static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  9778. {
  9779. struct tg3 *tp = netdev_priv(dev);
  9780. memcpy(ec, &tp->coal, sizeof(*ec));
  9781. return 0;
  9782. }
  9783. static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  9784. {
  9785. struct tg3 *tp = netdev_priv(dev);
  9786. u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
  9787. u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
  9788. if (!tg3_flag(tp, 5705_PLUS)) {
  9789. max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
  9790. max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
  9791. max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
  9792. min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
  9793. }
  9794. if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
  9795. (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
  9796. (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
  9797. (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
  9798. (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
  9799. (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
  9800. (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
  9801. (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
  9802. (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
  9803. (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
  9804. return -EINVAL;
  9805. /* No rx interrupts will be generated if both are zero */
  9806. if ((ec->rx_coalesce_usecs == 0) &&
  9807. (ec->rx_max_coalesced_frames == 0))
  9808. return -EINVAL;
  9809. /* No tx interrupts will be generated if both are zero */
  9810. if ((ec->tx_coalesce_usecs == 0) &&
  9811. (ec->tx_max_coalesced_frames == 0))
  9812. return -EINVAL;
  9813. /* Only copy relevant parameters, ignore all others. */
  9814. tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
  9815. tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
  9816. tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
  9817. tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
  9818. tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
  9819. tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
  9820. tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
  9821. tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
  9822. tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
  9823. if (netif_running(dev)) {
  9824. tg3_full_lock(tp, 0);
  9825. __tg3_set_coalesce(tp, &tp->coal);
  9826. tg3_full_unlock(tp);
  9827. }
  9828. return 0;
  9829. }
  9830. static const struct ethtool_ops tg3_ethtool_ops = {
  9831. .get_settings = tg3_get_settings,
  9832. .set_settings = tg3_set_settings,
  9833. .get_drvinfo = tg3_get_drvinfo,
  9834. .get_regs_len = tg3_get_regs_len,
  9835. .get_regs = tg3_get_regs,
  9836. .get_wol = tg3_get_wol,
  9837. .set_wol = tg3_set_wol,
  9838. .get_msglevel = tg3_get_msglevel,
  9839. .set_msglevel = tg3_set_msglevel,
  9840. .nway_reset = tg3_nway_reset,
  9841. .get_link = ethtool_op_get_link,
  9842. .get_eeprom_len = tg3_get_eeprom_len,
  9843. .get_eeprom = tg3_get_eeprom,
  9844. .set_eeprom = tg3_set_eeprom,
  9845. .get_ringparam = tg3_get_ringparam,
  9846. .set_ringparam = tg3_set_ringparam,
  9847. .get_pauseparam = tg3_get_pauseparam,
  9848. .set_pauseparam = tg3_set_pauseparam,
  9849. .self_test = tg3_self_test,
  9850. .get_strings = tg3_get_strings,
  9851. .set_phys_id = tg3_set_phys_id,
  9852. .get_ethtool_stats = tg3_get_ethtool_stats,
  9853. .get_coalesce = tg3_get_coalesce,
  9854. .set_coalesce = tg3_set_coalesce,
  9855. .get_sset_count = tg3_get_sset_count,
  9856. };
  9857. static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
  9858. {
  9859. u32 cursize, val, magic;
  9860. tp->nvram_size = EEPROM_CHIP_SIZE;
  9861. if (tg3_nvram_read(tp, 0, &magic) != 0)
  9862. return;
  9863. if ((magic != TG3_EEPROM_MAGIC) &&
  9864. ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
  9865. ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
  9866. return;
  9867. /*
  9868. * Size the chip by reading offsets at increasing powers of two.
  9869. * When we encounter our validation signature, we know the addressing
  9870. * has wrapped around, and thus have our chip size.
  9871. */
  9872. cursize = 0x10;
  9873. while (cursize < tp->nvram_size) {
  9874. if (tg3_nvram_read(tp, cursize, &val) != 0)
  9875. return;
  9876. if (val == magic)
  9877. break;
  9878. cursize <<= 1;
  9879. }
  9880. tp->nvram_size = cursize;
  9881. }
  9882. static void __devinit tg3_get_nvram_size(struct tg3 *tp)
  9883. {
  9884. u32 val;
  9885. if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
  9886. return;
  9887. /* Selfboot format */
  9888. if (val != TG3_EEPROM_MAGIC) {
  9889. tg3_get_eeprom_size(tp);
  9890. return;
  9891. }
  9892. if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
  9893. if (val != 0) {
  9894. /* This is confusing. We want to operate on the
  9895. * 16-bit value at offset 0xf2. The tg3_nvram_read()
  9896. * call will read from NVRAM and byteswap the data
  9897. * according to the byteswapping settings for all
  9898. * other register accesses. This ensures the data we
  9899. * want will always reside in the lower 16-bits.
  9900. * However, the data in NVRAM is in LE format, which
  9901. * means the data from the NVRAM read will always be
  9902. * opposite the endianness of the CPU. The 16-bit
  9903. * byteswap then brings the data to CPU endianness.
  9904. */
  9905. tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
  9906. return;
  9907. }
  9908. }
  9909. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  9910. }
  9911. static void __devinit tg3_get_nvram_info(struct tg3 *tp)
  9912. {
  9913. u32 nvcfg1;
  9914. nvcfg1 = tr32(NVRAM_CFG1);
  9915. if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
  9916. tg3_flag_set(tp, FLASH);
  9917. } else {
  9918. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  9919. tw32(NVRAM_CFG1, nvcfg1);
  9920. }
  9921. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  9922. tg3_flag(tp, 5780_CLASS)) {
  9923. switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
  9924. case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
  9925. tp->nvram_jedecnum = JEDEC_ATMEL;
  9926. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  9927. tg3_flag_set(tp, NVRAM_BUFFERED);
  9928. break;
  9929. case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
  9930. tp->nvram_jedecnum = JEDEC_ATMEL;
  9931. tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
  9932. break;
  9933. case FLASH_VENDOR_ATMEL_EEPROM:
  9934. tp->nvram_jedecnum = JEDEC_ATMEL;
  9935. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9936. tg3_flag_set(tp, NVRAM_BUFFERED);
  9937. break;
  9938. case FLASH_VENDOR_ST:
  9939. tp->nvram_jedecnum = JEDEC_ST;
  9940. tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
  9941. tg3_flag_set(tp, NVRAM_BUFFERED);
  9942. break;
  9943. case FLASH_VENDOR_SAIFUN:
  9944. tp->nvram_jedecnum = JEDEC_SAIFUN;
  9945. tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
  9946. break;
  9947. case FLASH_VENDOR_SST_SMALL:
  9948. case FLASH_VENDOR_SST_LARGE:
  9949. tp->nvram_jedecnum = JEDEC_SST;
  9950. tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
  9951. break;
  9952. }
  9953. } else {
  9954. tp->nvram_jedecnum = JEDEC_ATMEL;
  9955. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  9956. tg3_flag_set(tp, NVRAM_BUFFERED);
  9957. }
  9958. }
  9959. static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
  9960. {
  9961. switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
  9962. case FLASH_5752PAGE_SIZE_256:
  9963. tp->nvram_pagesize = 256;
  9964. break;
  9965. case FLASH_5752PAGE_SIZE_512:
  9966. tp->nvram_pagesize = 512;
  9967. break;
  9968. case FLASH_5752PAGE_SIZE_1K:
  9969. tp->nvram_pagesize = 1024;
  9970. break;
  9971. case FLASH_5752PAGE_SIZE_2K:
  9972. tp->nvram_pagesize = 2048;
  9973. break;
  9974. case FLASH_5752PAGE_SIZE_4K:
  9975. tp->nvram_pagesize = 4096;
  9976. break;
  9977. case FLASH_5752PAGE_SIZE_264:
  9978. tp->nvram_pagesize = 264;
  9979. break;
  9980. case FLASH_5752PAGE_SIZE_528:
  9981. tp->nvram_pagesize = 528;
  9982. break;
  9983. }
  9984. }
  9985. static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
  9986. {
  9987. u32 nvcfg1;
  9988. nvcfg1 = tr32(NVRAM_CFG1);
  9989. /* NVRAM protection for TPM */
  9990. if (nvcfg1 & (1 << 27))
  9991. tg3_flag_set(tp, PROTECTED_NVRAM);
  9992. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9993. case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
  9994. case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
  9995. tp->nvram_jedecnum = JEDEC_ATMEL;
  9996. tg3_flag_set(tp, NVRAM_BUFFERED);
  9997. break;
  9998. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  9999. tp->nvram_jedecnum = JEDEC_ATMEL;
  10000. tg3_flag_set(tp, NVRAM_BUFFERED);
  10001. tg3_flag_set(tp, FLASH);
  10002. break;
  10003. case FLASH_5752VENDOR_ST_M45PE10:
  10004. case FLASH_5752VENDOR_ST_M45PE20:
  10005. case FLASH_5752VENDOR_ST_M45PE40:
  10006. tp->nvram_jedecnum = JEDEC_ST;
  10007. tg3_flag_set(tp, NVRAM_BUFFERED);
  10008. tg3_flag_set(tp, FLASH);
  10009. break;
  10010. }
  10011. if (tg3_flag(tp, FLASH)) {
  10012. tg3_nvram_get_pagesize(tp, nvcfg1);
  10013. } else {
  10014. /* For eeprom, set pagesize to maximum eeprom size */
  10015. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  10016. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  10017. tw32(NVRAM_CFG1, nvcfg1);
  10018. }
  10019. }
  10020. static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
  10021. {
  10022. u32 nvcfg1, protect = 0;
  10023. nvcfg1 = tr32(NVRAM_CFG1);
  10024. /* NVRAM protection for TPM */
  10025. if (nvcfg1 & (1 << 27)) {
  10026. tg3_flag_set(tp, PROTECTED_NVRAM);
  10027. protect = 1;
  10028. }
  10029. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  10030. switch (nvcfg1) {
  10031. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  10032. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  10033. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  10034. case FLASH_5755VENDOR_ATMEL_FLASH_5:
  10035. tp->nvram_jedecnum = JEDEC_ATMEL;
  10036. tg3_flag_set(tp, NVRAM_BUFFERED);
  10037. tg3_flag_set(tp, FLASH);
  10038. tp->nvram_pagesize = 264;
  10039. if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
  10040. nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
  10041. tp->nvram_size = (protect ? 0x3e200 :
  10042. TG3_NVRAM_SIZE_512KB);
  10043. else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
  10044. tp->nvram_size = (protect ? 0x1f200 :
  10045. TG3_NVRAM_SIZE_256KB);
  10046. else
  10047. tp->nvram_size = (protect ? 0x1f200 :
  10048. TG3_NVRAM_SIZE_128KB);
  10049. break;
  10050. case FLASH_5752VENDOR_ST_M45PE10:
  10051. case FLASH_5752VENDOR_ST_M45PE20:
  10052. case FLASH_5752VENDOR_ST_M45PE40:
  10053. tp->nvram_jedecnum = JEDEC_ST;
  10054. tg3_flag_set(tp, NVRAM_BUFFERED);
  10055. tg3_flag_set(tp, FLASH);
  10056. tp->nvram_pagesize = 256;
  10057. if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
  10058. tp->nvram_size = (protect ?
  10059. TG3_NVRAM_SIZE_64KB :
  10060. TG3_NVRAM_SIZE_128KB);
  10061. else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
  10062. tp->nvram_size = (protect ?
  10063. TG3_NVRAM_SIZE_64KB :
  10064. TG3_NVRAM_SIZE_256KB);
  10065. else
  10066. tp->nvram_size = (protect ?
  10067. TG3_NVRAM_SIZE_128KB :
  10068. TG3_NVRAM_SIZE_512KB);
  10069. break;
  10070. }
  10071. }
  10072. static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
  10073. {
  10074. u32 nvcfg1;
  10075. nvcfg1 = tr32(NVRAM_CFG1);
  10076. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  10077. case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
  10078. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  10079. case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
  10080. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  10081. tp->nvram_jedecnum = JEDEC_ATMEL;
  10082. tg3_flag_set(tp, NVRAM_BUFFERED);
  10083. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  10084. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  10085. tw32(NVRAM_CFG1, nvcfg1);
  10086. break;
  10087. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  10088. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  10089. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  10090. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  10091. tp->nvram_jedecnum = JEDEC_ATMEL;
  10092. tg3_flag_set(tp, NVRAM_BUFFERED);
  10093. tg3_flag_set(tp, FLASH);
  10094. tp->nvram_pagesize = 264;
  10095. break;
  10096. case FLASH_5752VENDOR_ST_M45PE10:
  10097. case FLASH_5752VENDOR_ST_M45PE20:
  10098. case FLASH_5752VENDOR_ST_M45PE40:
  10099. tp->nvram_jedecnum = JEDEC_ST;
  10100. tg3_flag_set(tp, NVRAM_BUFFERED);
  10101. tg3_flag_set(tp, FLASH);
  10102. tp->nvram_pagesize = 256;
  10103. break;
  10104. }
  10105. }
  10106. static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
  10107. {
  10108. u32 nvcfg1, protect = 0;
  10109. nvcfg1 = tr32(NVRAM_CFG1);
  10110. /* NVRAM protection for TPM */
  10111. if (nvcfg1 & (1 << 27)) {
  10112. tg3_flag_set(tp, PROTECTED_NVRAM);
  10113. protect = 1;
  10114. }
  10115. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  10116. switch (nvcfg1) {
  10117. case FLASH_5761VENDOR_ATMEL_ADB021D:
  10118. case FLASH_5761VENDOR_ATMEL_ADB041D:
  10119. case FLASH_5761VENDOR_ATMEL_ADB081D:
  10120. case FLASH_5761VENDOR_ATMEL_ADB161D:
  10121. case FLASH_5761VENDOR_ATMEL_MDB021D:
  10122. case FLASH_5761VENDOR_ATMEL_MDB041D:
  10123. case FLASH_5761VENDOR_ATMEL_MDB081D:
  10124. case FLASH_5761VENDOR_ATMEL_MDB161D:
  10125. tp->nvram_jedecnum = JEDEC_ATMEL;
  10126. tg3_flag_set(tp, NVRAM_BUFFERED);
  10127. tg3_flag_set(tp, FLASH);
  10128. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  10129. tp->nvram_pagesize = 256;
  10130. break;
  10131. case FLASH_5761VENDOR_ST_A_M45PE20:
  10132. case FLASH_5761VENDOR_ST_A_M45PE40:
  10133. case FLASH_5761VENDOR_ST_A_M45PE80:
  10134. case FLASH_5761VENDOR_ST_A_M45PE16:
  10135. case FLASH_5761VENDOR_ST_M_M45PE20:
  10136. case FLASH_5761VENDOR_ST_M_M45PE40:
  10137. case FLASH_5761VENDOR_ST_M_M45PE80:
  10138. case FLASH_5761VENDOR_ST_M_M45PE16:
  10139. tp->nvram_jedecnum = JEDEC_ST;
  10140. tg3_flag_set(tp, NVRAM_BUFFERED);
  10141. tg3_flag_set(tp, FLASH);
  10142. tp->nvram_pagesize = 256;
  10143. break;
  10144. }
  10145. if (protect) {
  10146. tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
  10147. } else {
  10148. switch (nvcfg1) {
  10149. case FLASH_5761VENDOR_ATMEL_ADB161D:
  10150. case FLASH_5761VENDOR_ATMEL_MDB161D:
  10151. case FLASH_5761VENDOR_ST_A_M45PE16:
  10152. case FLASH_5761VENDOR_ST_M_M45PE16:
  10153. tp->nvram_size = TG3_NVRAM_SIZE_2MB;
  10154. break;
  10155. case FLASH_5761VENDOR_ATMEL_ADB081D:
  10156. case FLASH_5761VENDOR_ATMEL_MDB081D:
  10157. case FLASH_5761VENDOR_ST_A_M45PE80:
  10158. case FLASH_5761VENDOR_ST_M_M45PE80:
  10159. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  10160. break;
  10161. case FLASH_5761VENDOR_ATMEL_ADB041D:
  10162. case FLASH_5761VENDOR_ATMEL_MDB041D:
  10163. case FLASH_5761VENDOR_ST_A_M45PE40:
  10164. case FLASH_5761VENDOR_ST_M_M45PE40:
  10165. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  10166. break;
  10167. case FLASH_5761VENDOR_ATMEL_ADB021D:
  10168. case FLASH_5761VENDOR_ATMEL_MDB021D:
  10169. case FLASH_5761VENDOR_ST_A_M45PE20:
  10170. case FLASH_5761VENDOR_ST_M_M45PE20:
  10171. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  10172. break;
  10173. }
  10174. }
  10175. }
  10176. static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
  10177. {
  10178. tp->nvram_jedecnum = JEDEC_ATMEL;
  10179. tg3_flag_set(tp, NVRAM_BUFFERED);
  10180. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  10181. }
  10182. static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
  10183. {
  10184. u32 nvcfg1;
  10185. nvcfg1 = tr32(NVRAM_CFG1);
  10186. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  10187. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  10188. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  10189. tp->nvram_jedecnum = JEDEC_ATMEL;
  10190. tg3_flag_set(tp, NVRAM_BUFFERED);
  10191. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  10192. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  10193. tw32(NVRAM_CFG1, nvcfg1);
  10194. return;
  10195. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  10196. case FLASH_57780VENDOR_ATMEL_AT45DB011D:
  10197. case FLASH_57780VENDOR_ATMEL_AT45DB011B:
  10198. case FLASH_57780VENDOR_ATMEL_AT45DB021D:
  10199. case FLASH_57780VENDOR_ATMEL_AT45DB021B:
  10200. case FLASH_57780VENDOR_ATMEL_AT45DB041D:
  10201. case FLASH_57780VENDOR_ATMEL_AT45DB041B:
  10202. tp->nvram_jedecnum = JEDEC_ATMEL;
  10203. tg3_flag_set(tp, NVRAM_BUFFERED);
  10204. tg3_flag_set(tp, FLASH);
  10205. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  10206. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  10207. case FLASH_57780VENDOR_ATMEL_AT45DB011D:
  10208. case FLASH_57780VENDOR_ATMEL_AT45DB011B:
  10209. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  10210. break;
  10211. case FLASH_57780VENDOR_ATMEL_AT45DB021D:
  10212. case FLASH_57780VENDOR_ATMEL_AT45DB021B:
  10213. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  10214. break;
  10215. case FLASH_57780VENDOR_ATMEL_AT45DB041D:
  10216. case FLASH_57780VENDOR_ATMEL_AT45DB041B:
  10217. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  10218. break;
  10219. }
  10220. break;
  10221. case FLASH_5752VENDOR_ST_M45PE10:
  10222. case FLASH_5752VENDOR_ST_M45PE20:
  10223. case FLASH_5752VENDOR_ST_M45PE40:
  10224. tp->nvram_jedecnum = JEDEC_ST;
  10225. tg3_flag_set(tp, NVRAM_BUFFERED);
  10226. tg3_flag_set(tp, FLASH);
  10227. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  10228. case FLASH_5752VENDOR_ST_M45PE10:
  10229. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  10230. break;
  10231. case FLASH_5752VENDOR_ST_M45PE20:
  10232. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  10233. break;
  10234. case FLASH_5752VENDOR_ST_M45PE40:
  10235. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  10236. break;
  10237. }
  10238. break;
  10239. default:
  10240. tg3_flag_set(tp, NO_NVRAM);
  10241. return;
  10242. }
  10243. tg3_nvram_get_pagesize(tp, nvcfg1);
  10244. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  10245. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  10246. }
  10247. static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
  10248. {
  10249. u32 nvcfg1;
  10250. nvcfg1 = tr32(NVRAM_CFG1);
  10251. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  10252. case FLASH_5717VENDOR_ATMEL_EEPROM:
  10253. case FLASH_5717VENDOR_MICRO_EEPROM:
  10254. tp->nvram_jedecnum = JEDEC_ATMEL;
  10255. tg3_flag_set(tp, NVRAM_BUFFERED);
  10256. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  10257. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  10258. tw32(NVRAM_CFG1, nvcfg1);
  10259. return;
  10260. case FLASH_5717VENDOR_ATMEL_MDB011D:
  10261. case FLASH_5717VENDOR_ATMEL_ADB011B:
  10262. case FLASH_5717VENDOR_ATMEL_ADB011D:
  10263. case FLASH_5717VENDOR_ATMEL_MDB021D:
  10264. case FLASH_5717VENDOR_ATMEL_ADB021B:
  10265. case FLASH_5717VENDOR_ATMEL_ADB021D:
  10266. case FLASH_5717VENDOR_ATMEL_45USPT:
  10267. tp->nvram_jedecnum = JEDEC_ATMEL;
  10268. tg3_flag_set(tp, NVRAM_BUFFERED);
  10269. tg3_flag_set(tp, FLASH);
  10270. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  10271. case FLASH_5717VENDOR_ATMEL_MDB021D:
  10272. /* Detect size with tg3_nvram_get_size() */
  10273. break;
  10274. case FLASH_5717VENDOR_ATMEL_ADB021B:
  10275. case FLASH_5717VENDOR_ATMEL_ADB021D:
  10276. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  10277. break;
  10278. default:
  10279. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  10280. break;
  10281. }
  10282. break;
  10283. case FLASH_5717VENDOR_ST_M_M25PE10:
  10284. case FLASH_5717VENDOR_ST_A_M25PE10:
  10285. case FLASH_5717VENDOR_ST_M_M45PE10:
  10286. case FLASH_5717VENDOR_ST_A_M45PE10:
  10287. case FLASH_5717VENDOR_ST_M_M25PE20:
  10288. case FLASH_5717VENDOR_ST_A_M25PE20:
  10289. case FLASH_5717VENDOR_ST_M_M45PE20:
  10290. case FLASH_5717VENDOR_ST_A_M45PE20:
  10291. case FLASH_5717VENDOR_ST_25USPT:
  10292. case FLASH_5717VENDOR_ST_45USPT:
  10293. tp->nvram_jedecnum = JEDEC_ST;
  10294. tg3_flag_set(tp, NVRAM_BUFFERED);
  10295. tg3_flag_set(tp, FLASH);
  10296. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  10297. case FLASH_5717VENDOR_ST_M_M25PE20:
  10298. case FLASH_5717VENDOR_ST_M_M45PE20:
  10299. /* Detect size with tg3_nvram_get_size() */
  10300. break;
  10301. case FLASH_5717VENDOR_ST_A_M25PE20:
  10302. case FLASH_5717VENDOR_ST_A_M45PE20:
  10303. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  10304. break;
  10305. default:
  10306. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  10307. break;
  10308. }
  10309. break;
  10310. default:
  10311. tg3_flag_set(tp, NO_NVRAM);
  10312. return;
  10313. }
  10314. tg3_nvram_get_pagesize(tp, nvcfg1);
  10315. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  10316. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  10317. }
  10318. static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
  10319. {
  10320. u32 nvcfg1, nvmpinstrp;
  10321. nvcfg1 = tr32(NVRAM_CFG1);
  10322. nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
  10323. switch (nvmpinstrp) {
  10324. case FLASH_5720_EEPROM_HD:
  10325. case FLASH_5720_EEPROM_LD:
  10326. tp->nvram_jedecnum = JEDEC_ATMEL;
  10327. tg3_flag_set(tp, NVRAM_BUFFERED);
  10328. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  10329. tw32(NVRAM_CFG1, nvcfg1);
  10330. if (nvmpinstrp == FLASH_5720_EEPROM_HD)
  10331. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  10332. else
  10333. tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
  10334. return;
  10335. case FLASH_5720VENDOR_M_ATMEL_DB011D:
  10336. case FLASH_5720VENDOR_A_ATMEL_DB011B:
  10337. case FLASH_5720VENDOR_A_ATMEL_DB011D:
  10338. case FLASH_5720VENDOR_M_ATMEL_DB021D:
  10339. case FLASH_5720VENDOR_A_ATMEL_DB021B:
  10340. case FLASH_5720VENDOR_A_ATMEL_DB021D:
  10341. case FLASH_5720VENDOR_M_ATMEL_DB041D:
  10342. case FLASH_5720VENDOR_A_ATMEL_DB041B:
  10343. case FLASH_5720VENDOR_A_ATMEL_DB041D:
  10344. case FLASH_5720VENDOR_M_ATMEL_DB081D:
  10345. case FLASH_5720VENDOR_A_ATMEL_DB081D:
  10346. case FLASH_5720VENDOR_ATMEL_45USPT:
  10347. tp->nvram_jedecnum = JEDEC_ATMEL;
  10348. tg3_flag_set(tp, NVRAM_BUFFERED);
  10349. tg3_flag_set(tp, FLASH);
  10350. switch (nvmpinstrp) {
  10351. case FLASH_5720VENDOR_M_ATMEL_DB021D:
  10352. case FLASH_5720VENDOR_A_ATMEL_DB021B:
  10353. case FLASH_5720VENDOR_A_ATMEL_DB021D:
  10354. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  10355. break;
  10356. case FLASH_5720VENDOR_M_ATMEL_DB041D:
  10357. case FLASH_5720VENDOR_A_ATMEL_DB041B:
  10358. case FLASH_5720VENDOR_A_ATMEL_DB041D:
  10359. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  10360. break;
  10361. case FLASH_5720VENDOR_M_ATMEL_DB081D:
  10362. case FLASH_5720VENDOR_A_ATMEL_DB081D:
  10363. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  10364. break;
  10365. default:
  10366. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  10367. break;
  10368. }
  10369. break;
  10370. case FLASH_5720VENDOR_M_ST_M25PE10:
  10371. case FLASH_5720VENDOR_M_ST_M45PE10:
  10372. case FLASH_5720VENDOR_A_ST_M25PE10:
  10373. case FLASH_5720VENDOR_A_ST_M45PE10:
  10374. case FLASH_5720VENDOR_M_ST_M25PE20:
  10375. case FLASH_5720VENDOR_M_ST_M45PE20:
  10376. case FLASH_5720VENDOR_A_ST_M25PE20:
  10377. case FLASH_5720VENDOR_A_ST_M45PE20:
  10378. case FLASH_5720VENDOR_M_ST_M25PE40:
  10379. case FLASH_5720VENDOR_M_ST_M45PE40:
  10380. case FLASH_5720VENDOR_A_ST_M25PE40:
  10381. case FLASH_5720VENDOR_A_ST_M45PE40:
  10382. case FLASH_5720VENDOR_M_ST_M25PE80:
  10383. case FLASH_5720VENDOR_M_ST_M45PE80:
  10384. case FLASH_5720VENDOR_A_ST_M25PE80:
  10385. case FLASH_5720VENDOR_A_ST_M45PE80:
  10386. case FLASH_5720VENDOR_ST_25USPT:
  10387. case FLASH_5720VENDOR_ST_45USPT:
  10388. tp->nvram_jedecnum = JEDEC_ST;
  10389. tg3_flag_set(tp, NVRAM_BUFFERED);
  10390. tg3_flag_set(tp, FLASH);
  10391. switch (nvmpinstrp) {
  10392. case FLASH_5720VENDOR_M_ST_M25PE20:
  10393. case FLASH_5720VENDOR_M_ST_M45PE20:
  10394. case FLASH_5720VENDOR_A_ST_M25PE20:
  10395. case FLASH_5720VENDOR_A_ST_M45PE20:
  10396. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  10397. break;
  10398. case FLASH_5720VENDOR_M_ST_M25PE40:
  10399. case FLASH_5720VENDOR_M_ST_M45PE40:
  10400. case FLASH_5720VENDOR_A_ST_M25PE40:
  10401. case FLASH_5720VENDOR_A_ST_M45PE40:
  10402. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  10403. break;
  10404. case FLASH_5720VENDOR_M_ST_M25PE80:
  10405. case FLASH_5720VENDOR_M_ST_M45PE80:
  10406. case FLASH_5720VENDOR_A_ST_M25PE80:
  10407. case FLASH_5720VENDOR_A_ST_M45PE80:
  10408. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  10409. break;
  10410. default:
  10411. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  10412. break;
  10413. }
  10414. break;
  10415. default:
  10416. tg3_flag_set(tp, NO_NVRAM);
  10417. return;
  10418. }
  10419. tg3_nvram_get_pagesize(tp, nvcfg1);
  10420. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  10421. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  10422. }
  10423. /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  10424. static void __devinit tg3_nvram_init(struct tg3 *tp)
  10425. {
  10426. tw32_f(GRC_EEPROM_ADDR,
  10427. (EEPROM_ADDR_FSM_RESET |
  10428. (EEPROM_DEFAULT_CLOCK_PERIOD <<
  10429. EEPROM_ADDR_CLKPERD_SHIFT)));
  10430. msleep(1);
  10431. /* Enable seeprom accesses. */
  10432. tw32_f(GRC_LOCAL_CTRL,
  10433. tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
  10434. udelay(100);
  10435. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  10436. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  10437. tg3_flag_set(tp, NVRAM);
  10438. if (tg3_nvram_lock(tp)) {
  10439. netdev_warn(tp->dev,
  10440. "Cannot get nvram lock, %s failed\n",
  10441. __func__);
  10442. return;
  10443. }
  10444. tg3_enable_nvram_access(tp);
  10445. tp->nvram_size = 0;
  10446. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  10447. tg3_get_5752_nvram_info(tp);
  10448. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  10449. tg3_get_5755_nvram_info(tp);
  10450. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  10451. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  10452. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  10453. tg3_get_5787_nvram_info(tp);
  10454. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  10455. tg3_get_5761_nvram_info(tp);
  10456. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10457. tg3_get_5906_nvram_info(tp);
  10458. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  10459. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  10460. tg3_get_57780_nvram_info(tp);
  10461. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  10462. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
  10463. tg3_get_5717_nvram_info(tp);
  10464. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
  10465. tg3_get_5720_nvram_info(tp);
  10466. else
  10467. tg3_get_nvram_info(tp);
  10468. if (tp->nvram_size == 0)
  10469. tg3_get_nvram_size(tp);
  10470. tg3_disable_nvram_access(tp);
  10471. tg3_nvram_unlock(tp);
  10472. } else {
  10473. tg3_flag_clear(tp, NVRAM);
  10474. tg3_flag_clear(tp, NVRAM_BUFFERED);
  10475. tg3_get_eeprom_size(tp);
  10476. }
  10477. }
  10478. static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
  10479. u32 offset, u32 len, u8 *buf)
  10480. {
  10481. int i, j, rc = 0;
  10482. u32 val;
  10483. for (i = 0; i < len; i += 4) {
  10484. u32 addr;
  10485. __be32 data;
  10486. addr = offset + i;
  10487. memcpy(&data, buf + i, 4);
  10488. /*
  10489. * The SEEPROM interface expects the data to always be opposite
  10490. * the native endian format. We accomplish this by reversing
  10491. * all the operations that would have been performed on the
  10492. * data from a call to tg3_nvram_read_be32().
  10493. */
  10494. tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
  10495. val = tr32(GRC_EEPROM_ADDR);
  10496. tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
  10497. val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
  10498. EEPROM_ADDR_READ);
  10499. tw32(GRC_EEPROM_ADDR, val |
  10500. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  10501. (addr & EEPROM_ADDR_ADDR_MASK) |
  10502. EEPROM_ADDR_START |
  10503. EEPROM_ADDR_WRITE);
  10504. for (j = 0; j < 1000; j++) {
  10505. val = tr32(GRC_EEPROM_ADDR);
  10506. if (val & EEPROM_ADDR_COMPLETE)
  10507. break;
  10508. msleep(1);
  10509. }
  10510. if (!(val & EEPROM_ADDR_COMPLETE)) {
  10511. rc = -EBUSY;
  10512. break;
  10513. }
  10514. }
  10515. return rc;
  10516. }
  10517. /* offset and length are dword aligned */
  10518. static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
  10519. u8 *buf)
  10520. {
  10521. int ret = 0;
  10522. u32 pagesize = tp->nvram_pagesize;
  10523. u32 pagemask = pagesize - 1;
  10524. u32 nvram_cmd;
  10525. u8 *tmp;
  10526. tmp = kmalloc(pagesize, GFP_KERNEL);
  10527. if (tmp == NULL)
  10528. return -ENOMEM;
  10529. while (len) {
  10530. int j;
  10531. u32 phy_addr, page_off, size;
  10532. phy_addr = offset & ~pagemask;
  10533. for (j = 0; j < pagesize; j += 4) {
  10534. ret = tg3_nvram_read_be32(tp, phy_addr + j,
  10535. (__be32 *) (tmp + j));
  10536. if (ret)
  10537. break;
  10538. }
  10539. if (ret)
  10540. break;
  10541. page_off = offset & pagemask;
  10542. size = pagesize;
  10543. if (len < size)
  10544. size = len;
  10545. len -= size;
  10546. memcpy(tmp + page_off, buf, size);
  10547. offset = offset + (pagesize - page_off);
  10548. tg3_enable_nvram_access(tp);
  10549. /*
  10550. * Before we can erase the flash page, we need
  10551. * to issue a special "write enable" command.
  10552. */
  10553. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  10554. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  10555. break;
  10556. /* Erase the target page */
  10557. tw32(NVRAM_ADDR, phy_addr);
  10558. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
  10559. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
  10560. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  10561. break;
  10562. /* Issue another write enable to start the write. */
  10563. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  10564. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  10565. break;
  10566. for (j = 0; j < pagesize; j += 4) {
  10567. __be32 data;
  10568. data = *((__be32 *) (tmp + j));
  10569. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  10570. tw32(NVRAM_ADDR, phy_addr + j);
  10571. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
  10572. NVRAM_CMD_WR;
  10573. if (j == 0)
  10574. nvram_cmd |= NVRAM_CMD_FIRST;
  10575. else if (j == (pagesize - 4))
  10576. nvram_cmd |= NVRAM_CMD_LAST;
  10577. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  10578. break;
  10579. }
  10580. if (ret)
  10581. break;
  10582. }
  10583. nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  10584. tg3_nvram_exec_cmd(tp, nvram_cmd);
  10585. kfree(tmp);
  10586. return ret;
  10587. }
  10588. /* offset and length are dword aligned */
  10589. static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
  10590. u8 *buf)
  10591. {
  10592. int i, ret = 0;
  10593. for (i = 0; i < len; i += 4, offset += 4) {
  10594. u32 page_off, phy_addr, nvram_cmd;
  10595. __be32 data;
  10596. memcpy(&data, buf + i, 4);
  10597. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  10598. page_off = offset % tp->nvram_pagesize;
  10599. phy_addr = tg3_nvram_phys_addr(tp, offset);
  10600. tw32(NVRAM_ADDR, phy_addr);
  10601. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
  10602. if (page_off == 0 || i == 0)
  10603. nvram_cmd |= NVRAM_CMD_FIRST;
  10604. if (page_off == (tp->nvram_pagesize - 4))
  10605. nvram_cmd |= NVRAM_CMD_LAST;
  10606. if (i == (len - 4))
  10607. nvram_cmd |= NVRAM_CMD_LAST;
  10608. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
  10609. !tg3_flag(tp, 5755_PLUS) &&
  10610. (tp->nvram_jedecnum == JEDEC_ST) &&
  10611. (nvram_cmd & NVRAM_CMD_FIRST)) {
  10612. if ((ret = tg3_nvram_exec_cmd(tp,
  10613. NVRAM_CMD_WREN | NVRAM_CMD_GO |
  10614. NVRAM_CMD_DONE)))
  10615. break;
  10616. }
  10617. if (!tg3_flag(tp, FLASH)) {
  10618. /* We always do complete word writes to eeprom. */
  10619. nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
  10620. }
  10621. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  10622. break;
  10623. }
  10624. return ret;
  10625. }
  10626. /* offset and length are dword aligned */
  10627. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
  10628. {
  10629. int ret;
  10630. if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
  10631. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  10632. ~GRC_LCLCTRL_GPIO_OUTPUT1);
  10633. udelay(40);
  10634. }
  10635. if (!tg3_flag(tp, NVRAM)) {
  10636. ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
  10637. } else {
  10638. u32 grc_mode;
  10639. ret = tg3_nvram_lock(tp);
  10640. if (ret)
  10641. return ret;
  10642. tg3_enable_nvram_access(tp);
  10643. if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
  10644. tw32(NVRAM_WRITE1, 0x406);
  10645. grc_mode = tr32(GRC_MODE);
  10646. tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
  10647. if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
  10648. ret = tg3_nvram_write_block_buffered(tp, offset, len,
  10649. buf);
  10650. } else {
  10651. ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
  10652. buf);
  10653. }
  10654. grc_mode = tr32(GRC_MODE);
  10655. tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
  10656. tg3_disable_nvram_access(tp);
  10657. tg3_nvram_unlock(tp);
  10658. }
  10659. if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
  10660. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  10661. udelay(40);
  10662. }
  10663. return ret;
  10664. }
  10665. struct subsys_tbl_ent {
  10666. u16 subsys_vendor, subsys_devid;
  10667. u32 phy_id;
  10668. };
  10669. static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
  10670. /* Broadcom boards. */
  10671. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  10672. TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
  10673. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  10674. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
  10675. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  10676. TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
  10677. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  10678. TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
  10679. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  10680. TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
  10681. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  10682. TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
  10683. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  10684. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
  10685. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  10686. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
  10687. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  10688. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
  10689. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  10690. TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
  10691. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  10692. TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
  10693. /* 3com boards. */
  10694. { TG3PCI_SUBVENDOR_ID_3COM,
  10695. TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
  10696. { TG3PCI_SUBVENDOR_ID_3COM,
  10697. TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
  10698. { TG3PCI_SUBVENDOR_ID_3COM,
  10699. TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
  10700. { TG3PCI_SUBVENDOR_ID_3COM,
  10701. TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
  10702. { TG3PCI_SUBVENDOR_ID_3COM,
  10703. TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
  10704. /* DELL boards. */
  10705. { TG3PCI_SUBVENDOR_ID_DELL,
  10706. TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
  10707. { TG3PCI_SUBVENDOR_ID_DELL,
  10708. TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
  10709. { TG3PCI_SUBVENDOR_ID_DELL,
  10710. TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
  10711. { TG3PCI_SUBVENDOR_ID_DELL,
  10712. TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
  10713. /* Compaq boards. */
  10714. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  10715. TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
  10716. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  10717. TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
  10718. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  10719. TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
  10720. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  10721. TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
  10722. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  10723. TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
  10724. /* IBM boards. */
  10725. { TG3PCI_SUBVENDOR_ID_IBM,
  10726. TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
  10727. };
  10728. static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
  10729. {
  10730. int i;
  10731. for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
  10732. if ((subsys_id_to_phy_id[i].subsys_vendor ==
  10733. tp->pdev->subsystem_vendor) &&
  10734. (subsys_id_to_phy_id[i].subsys_devid ==
  10735. tp->pdev->subsystem_device))
  10736. return &subsys_id_to_phy_id[i];
  10737. }
  10738. return NULL;
  10739. }
  10740. static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
  10741. {
  10742. u32 val;
  10743. tp->phy_id = TG3_PHY_ID_INVALID;
  10744. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  10745. /* Assume an onboard device and WOL capable by default. */
  10746. tg3_flag_set(tp, EEPROM_WRITE_PROT);
  10747. tg3_flag_set(tp, WOL_CAP);
  10748. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  10749. if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
  10750. tg3_flag_clear(tp, EEPROM_WRITE_PROT);
  10751. tg3_flag_set(tp, IS_NIC);
  10752. }
  10753. val = tr32(VCPU_CFGSHDW);
  10754. if (val & VCPU_CFGSHDW_ASPM_DBNC)
  10755. tg3_flag_set(tp, ASPM_WORKAROUND);
  10756. if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
  10757. (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
  10758. tg3_flag_set(tp, WOL_ENABLE);
  10759. device_set_wakeup_enable(&tp->pdev->dev, true);
  10760. }
  10761. goto done;
  10762. }
  10763. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  10764. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  10765. u32 nic_cfg, led_cfg;
  10766. u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
  10767. int eeprom_phy_serdes = 0;
  10768. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  10769. tp->nic_sram_data_cfg = nic_cfg;
  10770. tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
  10771. ver >>= NIC_SRAM_DATA_VER_SHIFT;
  10772. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  10773. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  10774. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
  10775. (ver > 0) && (ver < 0x100))
  10776. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
  10777. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  10778. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
  10779. if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
  10780. NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
  10781. eeprom_phy_serdes = 1;
  10782. tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
  10783. if (nic_phy_id != 0) {
  10784. u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
  10785. u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
  10786. eeprom_phy_id = (id1 >> 16) << 10;
  10787. eeprom_phy_id |= (id2 & 0xfc00) << 16;
  10788. eeprom_phy_id |= (id2 & 0x03ff) << 0;
  10789. } else
  10790. eeprom_phy_id = 0;
  10791. tp->phy_id = eeprom_phy_id;
  10792. if (eeprom_phy_serdes) {
  10793. if (!tg3_flag(tp, 5705_PLUS))
  10794. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  10795. else
  10796. tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
  10797. }
  10798. if (tg3_flag(tp, 5750_PLUS))
  10799. led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
  10800. SHASTA_EXT_LED_MODE_MASK);
  10801. else
  10802. led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
  10803. switch (led_cfg) {
  10804. default:
  10805. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
  10806. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  10807. break;
  10808. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
  10809. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  10810. break;
  10811. case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
  10812. tp->led_ctrl = LED_CTRL_MODE_MAC;
  10813. /* Default to PHY_1_MODE if 0 (MAC_MODE) is
  10814. * read on some older 5700/5701 bootcode.
  10815. */
  10816. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  10817. ASIC_REV_5700 ||
  10818. GET_ASIC_REV(tp->pci_chip_rev_id) ==
  10819. ASIC_REV_5701)
  10820. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  10821. break;
  10822. case SHASTA_EXT_LED_SHARED:
  10823. tp->led_ctrl = LED_CTRL_MODE_SHARED;
  10824. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
  10825. tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
  10826. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  10827. LED_CTRL_MODE_PHY_2);
  10828. break;
  10829. case SHASTA_EXT_LED_MAC:
  10830. tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
  10831. break;
  10832. case SHASTA_EXT_LED_COMBO:
  10833. tp->led_ctrl = LED_CTRL_MODE_COMBO;
  10834. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
  10835. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  10836. LED_CTRL_MODE_PHY_2);
  10837. break;
  10838. }
  10839. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  10840. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
  10841. tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
  10842. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  10843. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
  10844. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  10845. if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
  10846. tg3_flag_set(tp, EEPROM_WRITE_PROT);
  10847. if ((tp->pdev->subsystem_vendor ==
  10848. PCI_VENDOR_ID_ARIMA) &&
  10849. (tp->pdev->subsystem_device == 0x205a ||
  10850. tp->pdev->subsystem_device == 0x2063))
  10851. tg3_flag_clear(tp, EEPROM_WRITE_PROT);
  10852. } else {
  10853. tg3_flag_clear(tp, EEPROM_WRITE_PROT);
  10854. tg3_flag_set(tp, IS_NIC);
  10855. }
  10856. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  10857. tg3_flag_set(tp, ENABLE_ASF);
  10858. if (tg3_flag(tp, 5750_PLUS))
  10859. tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
  10860. }
  10861. if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
  10862. tg3_flag(tp, 5750_PLUS))
  10863. tg3_flag_set(tp, ENABLE_APE);
  10864. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
  10865. !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
  10866. tg3_flag_clear(tp, WOL_CAP);
  10867. if (tg3_flag(tp, WOL_CAP) &&
  10868. (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
  10869. tg3_flag_set(tp, WOL_ENABLE);
  10870. device_set_wakeup_enable(&tp->pdev->dev, true);
  10871. }
  10872. if (cfg2 & (1 << 17))
  10873. tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
  10874. /* serdes signal pre-emphasis in register 0x590 set by */
  10875. /* bootcode if bit 18 is set */
  10876. if (cfg2 & (1 << 18))
  10877. tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
  10878. if ((tg3_flag(tp, 57765_PLUS) ||
  10879. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  10880. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
  10881. (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
  10882. tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
  10883. if (tg3_flag(tp, PCI_EXPRESS) &&
  10884. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
  10885. !tg3_flag(tp, 57765_PLUS)) {
  10886. u32 cfg3;
  10887. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
  10888. if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
  10889. tg3_flag_set(tp, ASPM_WORKAROUND);
  10890. }
  10891. if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
  10892. tg3_flag_set(tp, RGMII_INBAND_DISABLE);
  10893. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
  10894. tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
  10895. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
  10896. tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
  10897. }
  10898. done:
  10899. if (tg3_flag(tp, WOL_CAP))
  10900. device_set_wakeup_enable(&tp->pdev->dev,
  10901. tg3_flag(tp, WOL_ENABLE));
  10902. else
  10903. device_set_wakeup_capable(&tp->pdev->dev, false);
  10904. }
  10905. static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
  10906. {
  10907. int i;
  10908. u32 val;
  10909. tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
  10910. tw32(OTP_CTRL, cmd);
  10911. /* Wait for up to 1 ms for command to execute. */
  10912. for (i = 0; i < 100; i++) {
  10913. val = tr32(OTP_STATUS);
  10914. if (val & OTP_STATUS_CMD_DONE)
  10915. break;
  10916. udelay(10);
  10917. }
  10918. return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
  10919. }
  10920. /* Read the gphy configuration from the OTP region of the chip. The gphy
  10921. * configuration is a 32-bit value that straddles the alignment boundary.
  10922. * We do two 32-bit reads and then shift and merge the results.
  10923. */
  10924. static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
  10925. {
  10926. u32 bhalf_otp, thalf_otp;
  10927. tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
  10928. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
  10929. return 0;
  10930. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
  10931. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  10932. return 0;
  10933. thalf_otp = tr32(OTP_READ_DATA);
  10934. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
  10935. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  10936. return 0;
  10937. bhalf_otp = tr32(OTP_READ_DATA);
  10938. return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
  10939. }
  10940. static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
  10941. {
  10942. u32 adv = ADVERTISED_Autoneg;
  10943. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  10944. adv |= ADVERTISED_1000baseT_Half |
  10945. ADVERTISED_1000baseT_Full;
  10946. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  10947. adv |= ADVERTISED_100baseT_Half |
  10948. ADVERTISED_100baseT_Full |
  10949. ADVERTISED_10baseT_Half |
  10950. ADVERTISED_10baseT_Full |
  10951. ADVERTISED_TP;
  10952. else
  10953. adv |= ADVERTISED_FIBRE;
  10954. tp->link_config.advertising = adv;
  10955. tp->link_config.speed = SPEED_INVALID;
  10956. tp->link_config.duplex = DUPLEX_INVALID;
  10957. tp->link_config.autoneg = AUTONEG_ENABLE;
  10958. tp->link_config.active_speed = SPEED_INVALID;
  10959. tp->link_config.active_duplex = DUPLEX_INVALID;
  10960. tp->link_config.orig_speed = SPEED_INVALID;
  10961. tp->link_config.orig_duplex = DUPLEX_INVALID;
  10962. tp->link_config.orig_autoneg = AUTONEG_INVALID;
  10963. }
  10964. static int __devinit tg3_phy_probe(struct tg3 *tp)
  10965. {
  10966. u32 hw_phy_id_1, hw_phy_id_2;
  10967. u32 hw_phy_id, hw_phy_id_masked;
  10968. int err;
  10969. /* flow control autonegotiation is default behavior */
  10970. tg3_flag_set(tp, PAUSE_AUTONEG);
  10971. tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  10972. if (tg3_flag(tp, USE_PHYLIB))
  10973. return tg3_phy_init(tp);
  10974. /* Reading the PHY ID register can conflict with ASF
  10975. * firmware access to the PHY hardware.
  10976. */
  10977. err = 0;
  10978. if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
  10979. hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
  10980. } else {
  10981. /* Now read the physical PHY_ID from the chip and verify
  10982. * that it is sane. If it doesn't look good, we fall back
  10983. * to either the hard-coded table based PHY_ID and failing
  10984. * that the value found in the eeprom area.
  10985. */
  10986. err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
  10987. err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
  10988. hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
  10989. hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
  10990. hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
  10991. hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
  10992. }
  10993. if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
  10994. tp->phy_id = hw_phy_id;
  10995. if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
  10996. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  10997. else
  10998. tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
  10999. } else {
  11000. if (tp->phy_id != TG3_PHY_ID_INVALID) {
  11001. /* Do nothing, phy ID already set up in
  11002. * tg3_get_eeprom_hw_cfg().
  11003. */
  11004. } else {
  11005. struct subsys_tbl_ent *p;
  11006. /* No eeprom signature? Try the hardcoded
  11007. * subsys device table.
  11008. */
  11009. p = tg3_lookup_by_subsys(tp);
  11010. if (!p)
  11011. return -ENODEV;
  11012. tp->phy_id = p->phy_id;
  11013. if (!tp->phy_id ||
  11014. tp->phy_id == TG3_PHY_ID_BCM8002)
  11015. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  11016. }
  11017. }
  11018. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
  11019. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  11020. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
  11021. (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
  11022. tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
  11023. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
  11024. tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
  11025. tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
  11026. tg3_phy_init_link_config(tp);
  11027. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
  11028. !tg3_flag(tp, ENABLE_APE) &&
  11029. !tg3_flag(tp, ENABLE_ASF)) {
  11030. u32 bmsr, mask;
  11031. tg3_readphy(tp, MII_BMSR, &bmsr);
  11032. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  11033. (bmsr & BMSR_LSTATUS))
  11034. goto skip_phy_reset;
  11035. err = tg3_phy_reset(tp);
  11036. if (err)
  11037. return err;
  11038. tg3_phy_set_wirespeed(tp);
  11039. mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  11040. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  11041. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
  11042. if (!tg3_copper_is_advertising_all(tp, mask)) {
  11043. tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
  11044. tp->link_config.flowctrl);
  11045. tg3_writephy(tp, MII_BMCR,
  11046. BMCR_ANENABLE | BMCR_ANRESTART);
  11047. }
  11048. }
  11049. skip_phy_reset:
  11050. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  11051. err = tg3_init_5401phy_dsp(tp);
  11052. if (err)
  11053. return err;
  11054. err = tg3_init_5401phy_dsp(tp);
  11055. }
  11056. return err;
  11057. }
  11058. static void __devinit tg3_read_vpd(struct tg3 *tp)
  11059. {
  11060. u8 *vpd_data;
  11061. unsigned int block_end, rosize, len;
  11062. u32 vpdlen;
  11063. int j, i = 0;
  11064. vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
  11065. if (!vpd_data)
  11066. goto out_no_vpd;
  11067. i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
  11068. if (i < 0)
  11069. goto out_not_found;
  11070. rosize = pci_vpd_lrdt_size(&vpd_data[i]);
  11071. block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
  11072. i += PCI_VPD_LRDT_TAG_SIZE;
  11073. if (block_end > vpdlen)
  11074. goto out_not_found;
  11075. j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  11076. PCI_VPD_RO_KEYWORD_MFR_ID);
  11077. if (j > 0) {
  11078. len = pci_vpd_info_field_size(&vpd_data[j]);
  11079. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  11080. if (j + len > block_end || len != 4 ||
  11081. memcmp(&vpd_data[j], "1028", 4))
  11082. goto partno;
  11083. j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  11084. PCI_VPD_RO_KEYWORD_VENDOR0);
  11085. if (j < 0)
  11086. goto partno;
  11087. len = pci_vpd_info_field_size(&vpd_data[j]);
  11088. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  11089. if (j + len > block_end)
  11090. goto partno;
  11091. memcpy(tp->fw_ver, &vpd_data[j], len);
  11092. strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
  11093. }
  11094. partno:
  11095. i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  11096. PCI_VPD_RO_KEYWORD_PARTNO);
  11097. if (i < 0)
  11098. goto out_not_found;
  11099. len = pci_vpd_info_field_size(&vpd_data[i]);
  11100. i += PCI_VPD_INFO_FLD_HDR_SIZE;
  11101. if (len > TG3_BPN_SIZE ||
  11102. (len + i) > vpdlen)
  11103. goto out_not_found;
  11104. memcpy(tp->board_part_number, &vpd_data[i], len);
  11105. out_not_found:
  11106. kfree(vpd_data);
  11107. if (tp->board_part_number[0])
  11108. return;
  11109. out_no_vpd:
  11110. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
  11111. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
  11112. strcpy(tp->board_part_number, "BCM5717");
  11113. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
  11114. strcpy(tp->board_part_number, "BCM5718");
  11115. else
  11116. goto nomatch;
  11117. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
  11118. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
  11119. strcpy(tp->board_part_number, "BCM57780");
  11120. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
  11121. strcpy(tp->board_part_number, "BCM57760");
  11122. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
  11123. strcpy(tp->board_part_number, "BCM57790");
  11124. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
  11125. strcpy(tp->board_part_number, "BCM57788");
  11126. else
  11127. goto nomatch;
  11128. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
  11129. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
  11130. strcpy(tp->board_part_number, "BCM57761");
  11131. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
  11132. strcpy(tp->board_part_number, "BCM57765");
  11133. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
  11134. strcpy(tp->board_part_number, "BCM57781");
  11135. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
  11136. strcpy(tp->board_part_number, "BCM57785");
  11137. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
  11138. strcpy(tp->board_part_number, "BCM57791");
  11139. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
  11140. strcpy(tp->board_part_number, "BCM57795");
  11141. else
  11142. goto nomatch;
  11143. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  11144. strcpy(tp->board_part_number, "BCM95906");
  11145. } else {
  11146. nomatch:
  11147. strcpy(tp->board_part_number, "none");
  11148. }
  11149. }
  11150. static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
  11151. {
  11152. u32 val;
  11153. if (tg3_nvram_read(tp, offset, &val) ||
  11154. (val & 0xfc000000) != 0x0c000000 ||
  11155. tg3_nvram_read(tp, offset + 4, &val) ||
  11156. val != 0)
  11157. return 0;
  11158. return 1;
  11159. }
  11160. static void __devinit tg3_read_bc_ver(struct tg3 *tp)
  11161. {
  11162. u32 val, offset, start, ver_offset;
  11163. int i, dst_off;
  11164. bool newver = false;
  11165. if (tg3_nvram_read(tp, 0xc, &offset) ||
  11166. tg3_nvram_read(tp, 0x4, &start))
  11167. return;
  11168. offset = tg3_nvram_logical_addr(tp, offset);
  11169. if (tg3_nvram_read(tp, offset, &val))
  11170. return;
  11171. if ((val & 0xfc000000) == 0x0c000000) {
  11172. if (tg3_nvram_read(tp, offset + 4, &val))
  11173. return;
  11174. if (val == 0)
  11175. newver = true;
  11176. }
  11177. dst_off = strlen(tp->fw_ver);
  11178. if (newver) {
  11179. if (TG3_VER_SIZE - dst_off < 16 ||
  11180. tg3_nvram_read(tp, offset + 8, &ver_offset))
  11181. return;
  11182. offset = offset + ver_offset - start;
  11183. for (i = 0; i < 16; i += 4) {
  11184. __be32 v;
  11185. if (tg3_nvram_read_be32(tp, offset + i, &v))
  11186. return;
  11187. memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
  11188. }
  11189. } else {
  11190. u32 major, minor;
  11191. if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
  11192. return;
  11193. major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
  11194. TG3_NVM_BCVER_MAJSFT;
  11195. minor = ver_offset & TG3_NVM_BCVER_MINMSK;
  11196. snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
  11197. "v%d.%02d", major, minor);
  11198. }
  11199. }
  11200. static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
  11201. {
  11202. u32 val, major, minor;
  11203. /* Use native endian representation */
  11204. if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
  11205. return;
  11206. major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
  11207. TG3_NVM_HWSB_CFG1_MAJSFT;
  11208. minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
  11209. TG3_NVM_HWSB_CFG1_MINSFT;
  11210. snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
  11211. }
  11212. static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
  11213. {
  11214. u32 offset, major, minor, build;
  11215. strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
  11216. if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
  11217. return;
  11218. switch (val & TG3_EEPROM_SB_REVISION_MASK) {
  11219. case TG3_EEPROM_SB_REVISION_0:
  11220. offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
  11221. break;
  11222. case TG3_EEPROM_SB_REVISION_2:
  11223. offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
  11224. break;
  11225. case TG3_EEPROM_SB_REVISION_3:
  11226. offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
  11227. break;
  11228. case TG3_EEPROM_SB_REVISION_4:
  11229. offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
  11230. break;
  11231. case TG3_EEPROM_SB_REVISION_5:
  11232. offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
  11233. break;
  11234. case TG3_EEPROM_SB_REVISION_6:
  11235. offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
  11236. break;
  11237. default:
  11238. return;
  11239. }
  11240. if (tg3_nvram_read(tp, offset, &val))
  11241. return;
  11242. build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
  11243. TG3_EEPROM_SB_EDH_BLD_SHFT;
  11244. major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
  11245. TG3_EEPROM_SB_EDH_MAJ_SHFT;
  11246. minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
  11247. if (minor > 99 || build > 26)
  11248. return;
  11249. offset = strlen(tp->fw_ver);
  11250. snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
  11251. " v%d.%02d", major, minor);
  11252. if (build > 0) {
  11253. offset = strlen(tp->fw_ver);
  11254. if (offset < TG3_VER_SIZE - 1)
  11255. tp->fw_ver[offset] = 'a' + build - 1;
  11256. }
  11257. }
  11258. static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
  11259. {
  11260. u32 val, offset, start;
  11261. int i, vlen;
  11262. for (offset = TG3_NVM_DIR_START;
  11263. offset < TG3_NVM_DIR_END;
  11264. offset += TG3_NVM_DIRENT_SIZE) {
  11265. if (tg3_nvram_read(tp, offset, &val))
  11266. return;
  11267. if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
  11268. break;
  11269. }
  11270. if (offset == TG3_NVM_DIR_END)
  11271. return;
  11272. if (!tg3_flag(tp, 5705_PLUS))
  11273. start = 0x08000000;
  11274. else if (tg3_nvram_read(tp, offset - 4, &start))
  11275. return;
  11276. if (tg3_nvram_read(tp, offset + 4, &offset) ||
  11277. !tg3_fw_img_is_valid(tp, offset) ||
  11278. tg3_nvram_read(tp, offset + 8, &val))
  11279. return;
  11280. offset += val - start;
  11281. vlen = strlen(tp->fw_ver);
  11282. tp->fw_ver[vlen++] = ',';
  11283. tp->fw_ver[vlen++] = ' ';
  11284. for (i = 0; i < 4; i++) {
  11285. __be32 v;
  11286. if (tg3_nvram_read_be32(tp, offset, &v))
  11287. return;
  11288. offset += sizeof(v);
  11289. if (vlen > TG3_VER_SIZE - sizeof(v)) {
  11290. memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
  11291. break;
  11292. }
  11293. memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
  11294. vlen += sizeof(v);
  11295. }
  11296. }
  11297. static void __devinit tg3_read_dash_ver(struct tg3 *tp)
  11298. {
  11299. int vlen;
  11300. u32 apedata;
  11301. char *fwtype;
  11302. if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
  11303. return;
  11304. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  11305. if (apedata != APE_SEG_SIG_MAGIC)
  11306. return;
  11307. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  11308. if (!(apedata & APE_FW_STATUS_READY))
  11309. return;
  11310. apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
  11311. if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
  11312. tg3_flag_set(tp, APE_HAS_NCSI);
  11313. fwtype = "NCSI";
  11314. } else {
  11315. fwtype = "DASH";
  11316. }
  11317. vlen = strlen(tp->fw_ver);
  11318. snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
  11319. fwtype,
  11320. (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
  11321. (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
  11322. (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
  11323. (apedata & APE_FW_VERSION_BLDMSK));
  11324. }
  11325. static void __devinit tg3_read_fw_ver(struct tg3 *tp)
  11326. {
  11327. u32 val;
  11328. bool vpd_vers = false;
  11329. if (tp->fw_ver[0] != 0)
  11330. vpd_vers = true;
  11331. if (tg3_flag(tp, NO_NVRAM)) {
  11332. strcat(tp->fw_ver, "sb");
  11333. return;
  11334. }
  11335. if (tg3_nvram_read(tp, 0, &val))
  11336. return;
  11337. if (val == TG3_EEPROM_MAGIC)
  11338. tg3_read_bc_ver(tp);
  11339. else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
  11340. tg3_read_sb_ver(tp, val);
  11341. else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  11342. tg3_read_hwsb_ver(tp);
  11343. else
  11344. return;
  11345. if (vpd_vers)
  11346. goto done;
  11347. if (tg3_flag(tp, ENABLE_APE)) {
  11348. if (tg3_flag(tp, ENABLE_ASF))
  11349. tg3_read_dash_ver(tp);
  11350. } else if (tg3_flag(tp, ENABLE_ASF)) {
  11351. tg3_read_mgmtfw_ver(tp);
  11352. }
  11353. done:
  11354. tp->fw_ver[TG3_VER_SIZE - 1] = 0;
  11355. }
  11356. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
  11357. static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
  11358. {
  11359. if (tg3_flag(tp, LRG_PROD_RING_CAP))
  11360. return TG3_RX_RET_MAX_SIZE_5717;
  11361. else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
  11362. return TG3_RX_RET_MAX_SIZE_5700;
  11363. else
  11364. return TG3_RX_RET_MAX_SIZE_5705;
  11365. }
  11366. static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
  11367. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
  11368. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
  11369. { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
  11370. { },
  11371. };
  11372. static int __devinit tg3_get_invariants(struct tg3 *tp)
  11373. {
  11374. u32 misc_ctrl_reg;
  11375. u32 pci_state_reg, grc_misc_cfg;
  11376. u32 val;
  11377. u16 pci_cmd;
  11378. int err;
  11379. /* Force memory write invalidate off. If we leave it on,
  11380. * then on 5700_BX chips we have to enable a workaround.
  11381. * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
  11382. * to match the cacheline size. The Broadcom driver have this
  11383. * workaround but turns MWI off all the times so never uses
  11384. * it. This seems to suggest that the workaround is insufficient.
  11385. */
  11386. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  11387. pci_cmd &= ~PCI_COMMAND_INVALIDATE;
  11388. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  11389. /* Important! -- Make sure register accesses are byteswapped
  11390. * correctly. Also, for those chips that require it, make
  11391. * sure that indirect register accesses are enabled before
  11392. * the first operation.
  11393. */
  11394. pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  11395. &misc_ctrl_reg);
  11396. tp->misc_host_ctrl |= (misc_ctrl_reg &
  11397. MISC_HOST_CTRL_CHIPREV);
  11398. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  11399. tp->misc_host_ctrl);
  11400. tp->pci_chip_rev_id = (misc_ctrl_reg >>
  11401. MISC_HOST_CTRL_CHIPREV_SHIFT);
  11402. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
  11403. u32 prod_id_asic_rev;
  11404. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  11405. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
  11406. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
  11407. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
  11408. pci_read_config_dword(tp->pdev,
  11409. TG3PCI_GEN2_PRODID_ASICREV,
  11410. &prod_id_asic_rev);
  11411. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
  11412. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
  11413. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
  11414. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
  11415. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
  11416. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
  11417. pci_read_config_dword(tp->pdev,
  11418. TG3PCI_GEN15_PRODID_ASICREV,
  11419. &prod_id_asic_rev);
  11420. else
  11421. pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
  11422. &prod_id_asic_rev);
  11423. tp->pci_chip_rev_id = prod_id_asic_rev;
  11424. }
  11425. /* Wrong chip ID in 5752 A0. This code can be removed later
  11426. * as A0 is not in production.
  11427. */
  11428. if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
  11429. tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
  11430. /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
  11431. * we need to disable memory and use config. cycles
  11432. * only to access all registers. The 5702/03 chips
  11433. * can mistakenly decode the special cycles from the
  11434. * ICH chipsets as memory write cycles, causing corruption
  11435. * of register and memory space. Only certain ICH bridges
  11436. * will drive special cycles with non-zero data during the
  11437. * address phase which can fall within the 5703's address
  11438. * range. This is not an ICH bug as the PCI spec allows
  11439. * non-zero address during special cycles. However, only
  11440. * these ICH bridges are known to drive non-zero addresses
  11441. * during special cycles.
  11442. *
  11443. * Since special cycles do not cross PCI bridges, we only
  11444. * enable this workaround if the 5703 is on the secondary
  11445. * bus of these ICH bridges.
  11446. */
  11447. if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
  11448. (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
  11449. static struct tg3_dev_id {
  11450. u32 vendor;
  11451. u32 device;
  11452. u32 rev;
  11453. } ich_chipsets[] = {
  11454. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
  11455. PCI_ANY_ID },
  11456. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
  11457. PCI_ANY_ID },
  11458. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
  11459. 0xa },
  11460. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
  11461. PCI_ANY_ID },
  11462. { },
  11463. };
  11464. struct tg3_dev_id *pci_id = &ich_chipsets[0];
  11465. struct pci_dev *bridge = NULL;
  11466. while (pci_id->vendor != 0) {
  11467. bridge = pci_get_device(pci_id->vendor, pci_id->device,
  11468. bridge);
  11469. if (!bridge) {
  11470. pci_id++;
  11471. continue;
  11472. }
  11473. if (pci_id->rev != PCI_ANY_ID) {
  11474. if (bridge->revision > pci_id->rev)
  11475. continue;
  11476. }
  11477. if (bridge->subordinate &&
  11478. (bridge->subordinate->number ==
  11479. tp->pdev->bus->number)) {
  11480. tg3_flag_set(tp, ICH_WORKAROUND);
  11481. pci_dev_put(bridge);
  11482. break;
  11483. }
  11484. }
  11485. }
  11486. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  11487. static struct tg3_dev_id {
  11488. u32 vendor;
  11489. u32 device;
  11490. } bridge_chipsets[] = {
  11491. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
  11492. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
  11493. { },
  11494. };
  11495. struct tg3_dev_id *pci_id = &bridge_chipsets[0];
  11496. struct pci_dev *bridge = NULL;
  11497. while (pci_id->vendor != 0) {
  11498. bridge = pci_get_device(pci_id->vendor,
  11499. pci_id->device,
  11500. bridge);
  11501. if (!bridge) {
  11502. pci_id++;
  11503. continue;
  11504. }
  11505. if (bridge->subordinate &&
  11506. (bridge->subordinate->number <=
  11507. tp->pdev->bus->number) &&
  11508. (bridge->subordinate->subordinate >=
  11509. tp->pdev->bus->number)) {
  11510. tg3_flag_set(tp, 5701_DMA_BUG);
  11511. pci_dev_put(bridge);
  11512. break;
  11513. }
  11514. }
  11515. }
  11516. /* The EPB bridge inside 5714, 5715, and 5780 cannot support
  11517. * DMA addresses > 40-bit. This bridge may have other additional
  11518. * 57xx devices behind it in some 4-port NIC designs for example.
  11519. * Any tg3 device found behind the bridge will also need the 40-bit
  11520. * DMA workaround.
  11521. */
  11522. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
  11523. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  11524. tg3_flag_set(tp, 5780_CLASS);
  11525. tg3_flag_set(tp, 40BIT_DMA_BUG);
  11526. tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
  11527. } else {
  11528. struct pci_dev *bridge = NULL;
  11529. do {
  11530. bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  11531. PCI_DEVICE_ID_SERVERWORKS_EPB,
  11532. bridge);
  11533. if (bridge && bridge->subordinate &&
  11534. (bridge->subordinate->number <=
  11535. tp->pdev->bus->number) &&
  11536. (bridge->subordinate->subordinate >=
  11537. tp->pdev->bus->number)) {
  11538. tg3_flag_set(tp, 40BIT_DMA_BUG);
  11539. pci_dev_put(bridge);
  11540. break;
  11541. }
  11542. } while (bridge);
  11543. }
  11544. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  11545. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
  11546. tp->pdev_peer = tg3_find_peer(tp);
  11547. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  11548. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  11549. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
  11550. tg3_flag_set(tp, 5717_PLUS);
  11551. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
  11552. tg3_flag(tp, 5717_PLUS))
  11553. tg3_flag_set(tp, 57765_PLUS);
  11554. /* Intentionally exclude ASIC_REV_5906 */
  11555. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  11556. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  11557. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  11558. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  11559. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  11560. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  11561. tg3_flag(tp, 57765_PLUS))
  11562. tg3_flag_set(tp, 5755_PLUS);
  11563. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  11564. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  11565. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  11566. tg3_flag(tp, 5755_PLUS) ||
  11567. tg3_flag(tp, 5780_CLASS))
  11568. tg3_flag_set(tp, 5750_PLUS);
  11569. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
  11570. tg3_flag(tp, 5750_PLUS))
  11571. tg3_flag_set(tp, 5705_PLUS);
  11572. /* Determine TSO capabilities */
  11573. if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
  11574. ; /* Do nothing. HW bug. */
  11575. else if (tg3_flag(tp, 57765_PLUS))
  11576. tg3_flag_set(tp, HW_TSO_3);
  11577. else if (tg3_flag(tp, 5755_PLUS) ||
  11578. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  11579. tg3_flag_set(tp, HW_TSO_2);
  11580. else if (tg3_flag(tp, 5750_PLUS)) {
  11581. tg3_flag_set(tp, HW_TSO_1);
  11582. tg3_flag_set(tp, TSO_BUG);
  11583. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
  11584. tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
  11585. tg3_flag_clear(tp, TSO_BUG);
  11586. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  11587. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  11588. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
  11589. tg3_flag_set(tp, TSO_BUG);
  11590. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
  11591. tp->fw_needed = FIRMWARE_TG3TSO5;
  11592. else
  11593. tp->fw_needed = FIRMWARE_TG3TSO;
  11594. }
  11595. /* Selectively allow TSO based on operating conditions */
  11596. if (tg3_flag(tp, HW_TSO_1) ||
  11597. tg3_flag(tp, HW_TSO_2) ||
  11598. tg3_flag(tp, HW_TSO_3) ||
  11599. (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF)))
  11600. tg3_flag_set(tp, TSO_CAPABLE);
  11601. else {
  11602. tg3_flag_clear(tp, TSO_CAPABLE);
  11603. tg3_flag_clear(tp, TSO_BUG);
  11604. tp->fw_needed = NULL;
  11605. }
  11606. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
  11607. tp->fw_needed = FIRMWARE_TG3;
  11608. tp->irq_max = 1;
  11609. if (tg3_flag(tp, 5750_PLUS)) {
  11610. tg3_flag_set(tp, SUPPORT_MSI);
  11611. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
  11612. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
  11613. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
  11614. tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
  11615. tp->pdev_peer == tp->pdev))
  11616. tg3_flag_clear(tp, SUPPORT_MSI);
  11617. if (tg3_flag(tp, 5755_PLUS) ||
  11618. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  11619. tg3_flag_set(tp, 1SHOT_MSI);
  11620. }
  11621. if (tg3_flag(tp, 57765_PLUS)) {
  11622. tg3_flag_set(tp, SUPPORT_MSIX);
  11623. tp->irq_max = TG3_IRQ_MAX_VECS;
  11624. }
  11625. }
  11626. if (tg3_flag(tp, 5755_PLUS))
  11627. tg3_flag_set(tp, SHORT_DMA_BUG);
  11628. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
  11629. tg3_flag_set(tp, 4K_FIFO_LIMIT);
  11630. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  11631. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  11632. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
  11633. tg3_flag_set(tp, LRG_PROD_RING_CAP);
  11634. if (tg3_flag(tp, 57765_PLUS) &&
  11635. tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
  11636. tg3_flag_set(tp, USE_JUMBO_BDFLAG);
  11637. if (!tg3_flag(tp, 5705_PLUS) ||
  11638. tg3_flag(tp, 5780_CLASS) ||
  11639. tg3_flag(tp, USE_JUMBO_BDFLAG))
  11640. tg3_flag_set(tp, JUMBO_CAPABLE);
  11641. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  11642. &pci_state_reg);
  11643. if (pci_is_pcie(tp->pdev)) {
  11644. u16 lnkctl;
  11645. tg3_flag_set(tp, PCI_EXPRESS);
  11646. tp->pcie_readrq = 4096;
  11647. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  11648. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
  11649. tp->pcie_readrq = 2048;
  11650. pcie_set_readrq(tp->pdev, tp->pcie_readrq);
  11651. pci_read_config_word(tp->pdev,
  11652. pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
  11653. &lnkctl);
  11654. if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
  11655. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  11656. ASIC_REV_5906) {
  11657. tg3_flag_clear(tp, HW_TSO_2);
  11658. tg3_flag_clear(tp, TSO_CAPABLE);
  11659. }
  11660. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  11661. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  11662. tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
  11663. tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
  11664. tg3_flag_set(tp, CLKREQ_BUG);
  11665. } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
  11666. tg3_flag_set(tp, L1PLLPD_EN);
  11667. }
  11668. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
  11669. /* BCM5785 devices are effectively PCIe devices, and should
  11670. * follow PCIe codepaths, but do not have a PCIe capabilities
  11671. * section.
  11672. */
  11673. tg3_flag_set(tp, PCI_EXPRESS);
  11674. } else if (!tg3_flag(tp, 5705_PLUS) ||
  11675. tg3_flag(tp, 5780_CLASS)) {
  11676. tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
  11677. if (!tp->pcix_cap) {
  11678. dev_err(&tp->pdev->dev,
  11679. "Cannot find PCI-X capability, aborting\n");
  11680. return -EIO;
  11681. }
  11682. if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
  11683. tg3_flag_set(tp, PCIX_MODE);
  11684. }
  11685. /* If we have an AMD 762 or VIA K8T800 chipset, write
  11686. * reordering to the mailbox registers done by the host
  11687. * controller can cause major troubles. We read back from
  11688. * every mailbox register write to force the writes to be
  11689. * posted to the chip in order.
  11690. */
  11691. if (pci_dev_present(tg3_write_reorder_chipsets) &&
  11692. !tg3_flag(tp, PCI_EXPRESS))
  11693. tg3_flag_set(tp, MBOX_WRITE_REORDER);
  11694. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  11695. &tp->pci_cacheline_sz);
  11696. pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  11697. &tp->pci_lat_timer);
  11698. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  11699. tp->pci_lat_timer < 64) {
  11700. tp->pci_lat_timer = 64;
  11701. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  11702. tp->pci_lat_timer);
  11703. }
  11704. /* Important! -- It is critical that the PCI-X hw workaround
  11705. * situation is decided before the first MMIO register access.
  11706. */
  11707. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
  11708. /* 5700 BX chips need to have their TX producer index
  11709. * mailboxes written twice to workaround a bug.
  11710. */
  11711. tg3_flag_set(tp, TXD_MBOX_HWBUG);
  11712. /* If we are in PCI-X mode, enable register write workaround.
  11713. *
  11714. * The workaround is to use indirect register accesses
  11715. * for all chip writes not to mailbox registers.
  11716. */
  11717. if (tg3_flag(tp, PCIX_MODE)) {
  11718. u32 pm_reg;
  11719. tg3_flag_set(tp, PCIX_TARGET_HWBUG);
  11720. /* The chip can have it's power management PCI config
  11721. * space registers clobbered due to this bug.
  11722. * So explicitly force the chip into D0 here.
  11723. */
  11724. pci_read_config_dword(tp->pdev,
  11725. tp->pm_cap + PCI_PM_CTRL,
  11726. &pm_reg);
  11727. pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
  11728. pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
  11729. pci_write_config_dword(tp->pdev,
  11730. tp->pm_cap + PCI_PM_CTRL,
  11731. pm_reg);
  11732. /* Also, force SERR#/PERR# in PCI command. */
  11733. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  11734. pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  11735. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  11736. }
  11737. }
  11738. if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
  11739. tg3_flag_set(tp, PCI_HIGH_SPEED);
  11740. if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
  11741. tg3_flag_set(tp, PCI_32BIT);
  11742. /* Chip-specific fixup from Broadcom driver */
  11743. if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
  11744. (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
  11745. pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
  11746. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  11747. }
  11748. /* Default fast path register access methods */
  11749. tp->read32 = tg3_read32;
  11750. tp->write32 = tg3_write32;
  11751. tp->read32_mbox = tg3_read32;
  11752. tp->write32_mbox = tg3_write32;
  11753. tp->write32_tx_mbox = tg3_write32;
  11754. tp->write32_rx_mbox = tg3_write32;
  11755. /* Various workaround register access methods */
  11756. if (tg3_flag(tp, PCIX_TARGET_HWBUG))
  11757. tp->write32 = tg3_write_indirect_reg32;
  11758. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  11759. (tg3_flag(tp, PCI_EXPRESS) &&
  11760. tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
  11761. /*
  11762. * Back to back register writes can cause problems on these
  11763. * chips, the workaround is to read back all reg writes
  11764. * except those to mailbox regs.
  11765. *
  11766. * See tg3_write_indirect_reg32().
  11767. */
  11768. tp->write32 = tg3_write_flush_reg32;
  11769. }
  11770. if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
  11771. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  11772. if (tg3_flag(tp, MBOX_WRITE_REORDER))
  11773. tp->write32_rx_mbox = tg3_write_flush_reg32;
  11774. }
  11775. if (tg3_flag(tp, ICH_WORKAROUND)) {
  11776. tp->read32 = tg3_read_indirect_reg32;
  11777. tp->write32 = tg3_write_indirect_reg32;
  11778. tp->read32_mbox = tg3_read_indirect_mbox;
  11779. tp->write32_mbox = tg3_write_indirect_mbox;
  11780. tp->write32_tx_mbox = tg3_write_indirect_mbox;
  11781. tp->write32_rx_mbox = tg3_write_indirect_mbox;
  11782. iounmap(tp->regs);
  11783. tp->regs = NULL;
  11784. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  11785. pci_cmd &= ~PCI_COMMAND_MEMORY;
  11786. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  11787. }
  11788. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  11789. tp->read32_mbox = tg3_read32_mbox_5906;
  11790. tp->write32_mbox = tg3_write32_mbox_5906;
  11791. tp->write32_tx_mbox = tg3_write32_mbox_5906;
  11792. tp->write32_rx_mbox = tg3_write32_mbox_5906;
  11793. }
  11794. if (tp->write32 == tg3_write_indirect_reg32 ||
  11795. (tg3_flag(tp, PCIX_MODE) &&
  11796. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  11797. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
  11798. tg3_flag_set(tp, SRAM_USE_CONFIG);
  11799. /* The memory arbiter has to be enabled in order for SRAM accesses
  11800. * to succeed. Normally on powerup the tg3 chip firmware will make
  11801. * sure it is enabled, but other entities such as system netboot
  11802. * code might disable it.
  11803. */
  11804. val = tr32(MEMARB_MODE);
  11805. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  11806. tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
  11807. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  11808. tg3_flag(tp, 5780_CLASS)) {
  11809. if (tg3_flag(tp, PCIX_MODE)) {
  11810. pci_read_config_dword(tp->pdev,
  11811. tp->pcix_cap + PCI_X_STATUS,
  11812. &val);
  11813. tp->pci_fn = val & 0x7;
  11814. }
  11815. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
  11816. tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
  11817. if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
  11818. NIC_SRAM_CPMUSTAT_SIG) {
  11819. tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
  11820. tp->pci_fn = tp->pci_fn ? 1 : 0;
  11821. }
  11822. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
  11823. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
  11824. tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
  11825. if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
  11826. NIC_SRAM_CPMUSTAT_SIG) {
  11827. tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
  11828. TG3_CPMU_STATUS_FSHFT_5719;
  11829. }
  11830. }
  11831. /* Get eeprom hw config before calling tg3_set_power_state().
  11832. * In particular, the TG3_FLAG_IS_NIC flag must be
  11833. * determined before calling tg3_set_power_state() so that
  11834. * we know whether or not to switch out of Vaux power.
  11835. * When the flag is set, it means that GPIO1 is used for eeprom
  11836. * write protect and also implies that it is a LOM where GPIOs
  11837. * are not used to switch power.
  11838. */
  11839. tg3_get_eeprom_hw_cfg(tp);
  11840. if (tg3_flag(tp, ENABLE_APE)) {
  11841. /* Allow reads and writes to the
  11842. * APE register and memory space.
  11843. */
  11844. pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  11845. PCISTATE_ALLOW_APE_SHMEM_WR |
  11846. PCISTATE_ALLOW_APE_PSPACE_WR;
  11847. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
  11848. pci_state_reg);
  11849. tg3_ape_lock_init(tp);
  11850. }
  11851. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  11852. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  11853. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  11854. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  11855. tg3_flag(tp, 57765_PLUS))
  11856. tg3_flag_set(tp, CPMU_PRESENT);
  11857. /* Set up tp->grc_local_ctrl before calling
  11858. * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
  11859. * will bring 5700's external PHY out of reset.
  11860. * It is also used as eeprom write protect on LOMs.
  11861. */
  11862. tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
  11863. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  11864. tg3_flag(tp, EEPROM_WRITE_PROT))
  11865. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  11866. GRC_LCLCTRL_GPIO_OUTPUT1);
  11867. /* Unused GPIO3 must be driven as output on 5752 because there
  11868. * are no pull-up resistors on unused GPIO pins.
  11869. */
  11870. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  11871. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  11872. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  11873. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  11874. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  11875. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  11876. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  11877. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
  11878. /* Turn off the debug UART. */
  11879. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  11880. if (tg3_flag(tp, IS_NIC))
  11881. /* Keep VMain power. */
  11882. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  11883. GRC_LCLCTRL_GPIO_OUTPUT0;
  11884. }
  11885. /* Switch out of Vaux if it is a NIC */
  11886. tg3_pwrsrc_switch_to_vmain(tp);
  11887. /* Derive initial jumbo mode from MTU assigned in
  11888. * ether_setup() via the alloc_etherdev() call
  11889. */
  11890. if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
  11891. tg3_flag_set(tp, JUMBO_RING_ENABLE);
  11892. /* Determine WakeOnLan speed to use. */
  11893. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  11894. tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  11895. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
  11896. tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
  11897. tg3_flag_clear(tp, WOL_SPEED_100MB);
  11898. } else {
  11899. tg3_flag_set(tp, WOL_SPEED_100MB);
  11900. }
  11901. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  11902. tp->phy_flags |= TG3_PHYFLG_IS_FET;
  11903. /* A few boards don't want Ethernet@WireSpeed phy feature */
  11904. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  11905. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  11906. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
  11907. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
  11908. (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
  11909. (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  11910. tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
  11911. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
  11912. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
  11913. tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
  11914. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
  11915. tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
  11916. if (tg3_flag(tp, 5705_PLUS) &&
  11917. !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  11918. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
  11919. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
  11920. !tg3_flag(tp, 57765_PLUS)) {
  11921. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  11922. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  11923. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  11924. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
  11925. if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
  11926. tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
  11927. tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
  11928. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
  11929. tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
  11930. } else
  11931. tp->phy_flags |= TG3_PHYFLG_BER_BUG;
  11932. }
  11933. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  11934. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
  11935. tp->phy_otp = tg3_read_otp_phycfg(tp);
  11936. if (tp->phy_otp == 0)
  11937. tp->phy_otp = TG3_OTP_DEFAULT;
  11938. }
  11939. if (tg3_flag(tp, CPMU_PRESENT))
  11940. tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
  11941. else
  11942. tp->mi_mode = MAC_MI_MODE_BASE;
  11943. tp->coalesce_mode = 0;
  11944. if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
  11945. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
  11946. tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
  11947. /* Set these bits to enable statistics workaround. */
  11948. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  11949. tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
  11950. tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
  11951. tp->coalesce_mode |= HOSTCC_MODE_ATTN;
  11952. tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
  11953. }
  11954. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  11955. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  11956. tg3_flag_set(tp, USE_PHYLIB);
  11957. err = tg3_mdio_init(tp);
  11958. if (err)
  11959. return err;
  11960. /* Initialize data/descriptor byte/word swapping. */
  11961. val = tr32(GRC_MODE);
  11962. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
  11963. val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
  11964. GRC_MODE_WORD_SWAP_B2HRX_DATA |
  11965. GRC_MODE_B2HRX_ENABLE |
  11966. GRC_MODE_HTX2B_ENABLE |
  11967. GRC_MODE_HOST_STACKUP);
  11968. else
  11969. val &= GRC_MODE_HOST_STACKUP;
  11970. tw32(GRC_MODE, val | tp->grc_mode);
  11971. tg3_switch_clocks(tp);
  11972. /* Clear this out for sanity. */
  11973. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  11974. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  11975. &pci_state_reg);
  11976. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
  11977. !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
  11978. u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
  11979. if (chiprevid == CHIPREV_ID_5701_A0 ||
  11980. chiprevid == CHIPREV_ID_5701_B0 ||
  11981. chiprevid == CHIPREV_ID_5701_B2 ||
  11982. chiprevid == CHIPREV_ID_5701_B5) {
  11983. void __iomem *sram_base;
  11984. /* Write some dummy words into the SRAM status block
  11985. * area, see if it reads back correctly. If the return
  11986. * value is bad, force enable the PCIX workaround.
  11987. */
  11988. sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
  11989. writel(0x00000000, sram_base);
  11990. writel(0x00000000, sram_base + 4);
  11991. writel(0xffffffff, sram_base + 4);
  11992. if (readl(sram_base) != 0x00000000)
  11993. tg3_flag_set(tp, PCIX_TARGET_HWBUG);
  11994. }
  11995. }
  11996. udelay(50);
  11997. tg3_nvram_init(tp);
  11998. grc_misc_cfg = tr32(GRC_MISC_CFG);
  11999. grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
  12000. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  12001. (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
  12002. grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
  12003. tg3_flag_set(tp, IS_5788);
  12004. if (!tg3_flag(tp, IS_5788) &&
  12005. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
  12006. tg3_flag_set(tp, TAGGED_STATUS);
  12007. if (tg3_flag(tp, TAGGED_STATUS)) {
  12008. tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
  12009. HOSTCC_MODE_CLRTICK_TXBD);
  12010. tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
  12011. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  12012. tp->misc_host_ctrl);
  12013. }
  12014. /* Preserve the APE MAC_MODE bits */
  12015. if (tg3_flag(tp, ENABLE_APE))
  12016. tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  12017. else
  12018. tp->mac_mode = 0;
  12019. /* these are limited to 10/100 only */
  12020. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  12021. (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
  12022. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  12023. tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  12024. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
  12025. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
  12026. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
  12027. (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  12028. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
  12029. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
  12030. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
  12031. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
  12032. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
  12033. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
  12034. (tp->phy_flags & TG3_PHYFLG_IS_FET))
  12035. tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
  12036. err = tg3_phy_probe(tp);
  12037. if (err) {
  12038. dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
  12039. /* ... but do not return immediately ... */
  12040. tg3_mdio_fini(tp);
  12041. }
  12042. tg3_read_vpd(tp);
  12043. tg3_read_fw_ver(tp);
  12044. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  12045. tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
  12046. } else {
  12047. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  12048. tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
  12049. else
  12050. tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
  12051. }
  12052. /* 5700 {AX,BX} chips have a broken status block link
  12053. * change bit implementation, so we must use the
  12054. * status register in those cases.
  12055. */
  12056. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  12057. tg3_flag_set(tp, USE_LINKCHG_REG);
  12058. else
  12059. tg3_flag_clear(tp, USE_LINKCHG_REG);
  12060. /* The led_ctrl is set during tg3_phy_probe, here we might
  12061. * have to force the link status polling mechanism based
  12062. * upon subsystem IDs.
  12063. */
  12064. if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  12065. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  12066. !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  12067. tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
  12068. tg3_flag_set(tp, USE_LINKCHG_REG);
  12069. }
  12070. /* For all SERDES we poll the MAC status register. */
  12071. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  12072. tg3_flag_set(tp, POLL_SERDES);
  12073. else
  12074. tg3_flag_clear(tp, POLL_SERDES);
  12075. tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
  12076. tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
  12077. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  12078. tg3_flag(tp, PCIX_MODE)) {
  12079. tp->rx_offset = NET_SKB_PAD;
  12080. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  12081. tp->rx_copy_thresh = ~(u16)0;
  12082. #endif
  12083. }
  12084. tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
  12085. tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
  12086. tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
  12087. tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
  12088. /* Increment the rx prod index on the rx std ring by at most
  12089. * 8 for these chips to workaround hw errata.
  12090. */
  12091. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  12092. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  12093. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  12094. tp->rx_std_max_post = 8;
  12095. if (tg3_flag(tp, ASPM_WORKAROUND))
  12096. tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
  12097. PCIE_PWR_MGMT_L1_THRESH_MSK;
  12098. return err;
  12099. }
  12100. #ifdef CONFIG_SPARC
  12101. static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
  12102. {
  12103. struct net_device *dev = tp->dev;
  12104. struct pci_dev *pdev = tp->pdev;
  12105. struct device_node *dp = pci_device_to_OF_node(pdev);
  12106. const unsigned char *addr;
  12107. int len;
  12108. addr = of_get_property(dp, "local-mac-address", &len);
  12109. if (addr && len == 6) {
  12110. memcpy(dev->dev_addr, addr, 6);
  12111. memcpy(dev->perm_addr, dev->dev_addr, 6);
  12112. return 0;
  12113. }
  12114. return -ENODEV;
  12115. }
  12116. static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
  12117. {
  12118. struct net_device *dev = tp->dev;
  12119. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  12120. memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
  12121. return 0;
  12122. }
  12123. #endif
  12124. static int __devinit tg3_get_device_address(struct tg3 *tp)
  12125. {
  12126. struct net_device *dev = tp->dev;
  12127. u32 hi, lo, mac_offset;
  12128. int addr_ok = 0;
  12129. #ifdef CONFIG_SPARC
  12130. if (!tg3_get_macaddr_sparc(tp))
  12131. return 0;
  12132. #endif
  12133. mac_offset = 0x7c;
  12134. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  12135. tg3_flag(tp, 5780_CLASS)) {
  12136. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  12137. mac_offset = 0xcc;
  12138. if (tg3_nvram_lock(tp))
  12139. tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
  12140. else
  12141. tg3_nvram_unlock(tp);
  12142. } else if (tg3_flag(tp, 5717_PLUS)) {
  12143. if (tp->pci_fn & 1)
  12144. mac_offset = 0xcc;
  12145. if (tp->pci_fn > 1)
  12146. mac_offset += 0x18c;
  12147. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  12148. mac_offset = 0x10;
  12149. /* First try to get it from MAC address mailbox. */
  12150. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
  12151. if ((hi >> 16) == 0x484b) {
  12152. dev->dev_addr[0] = (hi >> 8) & 0xff;
  12153. dev->dev_addr[1] = (hi >> 0) & 0xff;
  12154. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
  12155. dev->dev_addr[2] = (lo >> 24) & 0xff;
  12156. dev->dev_addr[3] = (lo >> 16) & 0xff;
  12157. dev->dev_addr[4] = (lo >> 8) & 0xff;
  12158. dev->dev_addr[5] = (lo >> 0) & 0xff;
  12159. /* Some old bootcode may report a 0 MAC address in SRAM */
  12160. addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
  12161. }
  12162. if (!addr_ok) {
  12163. /* Next, try NVRAM. */
  12164. if (!tg3_flag(tp, NO_NVRAM) &&
  12165. !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
  12166. !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
  12167. memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
  12168. memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
  12169. }
  12170. /* Finally just fetch it out of the MAC control regs. */
  12171. else {
  12172. hi = tr32(MAC_ADDR_0_HIGH);
  12173. lo = tr32(MAC_ADDR_0_LOW);
  12174. dev->dev_addr[5] = lo & 0xff;
  12175. dev->dev_addr[4] = (lo >> 8) & 0xff;
  12176. dev->dev_addr[3] = (lo >> 16) & 0xff;
  12177. dev->dev_addr[2] = (lo >> 24) & 0xff;
  12178. dev->dev_addr[1] = hi & 0xff;
  12179. dev->dev_addr[0] = (hi >> 8) & 0xff;
  12180. }
  12181. }
  12182. if (!is_valid_ether_addr(&dev->dev_addr[0])) {
  12183. #ifdef CONFIG_SPARC
  12184. if (!tg3_get_default_macaddr_sparc(tp))
  12185. return 0;
  12186. #endif
  12187. return -EINVAL;
  12188. }
  12189. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  12190. return 0;
  12191. }
  12192. #define BOUNDARY_SINGLE_CACHELINE 1
  12193. #define BOUNDARY_MULTI_CACHELINE 2
  12194. static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
  12195. {
  12196. int cacheline_size;
  12197. u8 byte;
  12198. int goal;
  12199. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
  12200. if (byte == 0)
  12201. cacheline_size = 1024;
  12202. else
  12203. cacheline_size = (int) byte * 4;
  12204. /* On 5703 and later chips, the boundary bits have no
  12205. * effect.
  12206. */
  12207. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  12208. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  12209. !tg3_flag(tp, PCI_EXPRESS))
  12210. goto out;
  12211. #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
  12212. goal = BOUNDARY_MULTI_CACHELINE;
  12213. #else
  12214. #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
  12215. goal = BOUNDARY_SINGLE_CACHELINE;
  12216. #else
  12217. goal = 0;
  12218. #endif
  12219. #endif
  12220. if (tg3_flag(tp, 57765_PLUS)) {
  12221. val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
  12222. goto out;
  12223. }
  12224. if (!goal)
  12225. goto out;
  12226. /* PCI controllers on most RISC systems tend to disconnect
  12227. * when a device tries to burst across a cache-line boundary.
  12228. * Therefore, letting tg3 do so just wastes PCI bandwidth.
  12229. *
  12230. * Unfortunately, for PCI-E there are only limited
  12231. * write-side controls for this, and thus for reads
  12232. * we will still get the disconnects. We'll also waste
  12233. * these PCI cycles for both read and write for chips
  12234. * other than 5700 and 5701 which do not implement the
  12235. * boundary bits.
  12236. */
  12237. if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
  12238. switch (cacheline_size) {
  12239. case 16:
  12240. case 32:
  12241. case 64:
  12242. case 128:
  12243. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  12244. val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
  12245. DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
  12246. } else {
  12247. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  12248. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  12249. }
  12250. break;
  12251. case 256:
  12252. val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
  12253. DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
  12254. break;
  12255. default:
  12256. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  12257. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  12258. break;
  12259. }
  12260. } else if (tg3_flag(tp, PCI_EXPRESS)) {
  12261. switch (cacheline_size) {
  12262. case 16:
  12263. case 32:
  12264. case 64:
  12265. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  12266. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  12267. val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
  12268. break;
  12269. }
  12270. /* fallthrough */
  12271. case 128:
  12272. default:
  12273. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  12274. val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
  12275. break;
  12276. }
  12277. } else {
  12278. switch (cacheline_size) {
  12279. case 16:
  12280. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  12281. val |= (DMA_RWCTRL_READ_BNDRY_16 |
  12282. DMA_RWCTRL_WRITE_BNDRY_16);
  12283. break;
  12284. }
  12285. /* fallthrough */
  12286. case 32:
  12287. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  12288. val |= (DMA_RWCTRL_READ_BNDRY_32 |
  12289. DMA_RWCTRL_WRITE_BNDRY_32);
  12290. break;
  12291. }
  12292. /* fallthrough */
  12293. case 64:
  12294. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  12295. val |= (DMA_RWCTRL_READ_BNDRY_64 |
  12296. DMA_RWCTRL_WRITE_BNDRY_64);
  12297. break;
  12298. }
  12299. /* fallthrough */
  12300. case 128:
  12301. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  12302. val |= (DMA_RWCTRL_READ_BNDRY_128 |
  12303. DMA_RWCTRL_WRITE_BNDRY_128);
  12304. break;
  12305. }
  12306. /* fallthrough */
  12307. case 256:
  12308. val |= (DMA_RWCTRL_READ_BNDRY_256 |
  12309. DMA_RWCTRL_WRITE_BNDRY_256);
  12310. break;
  12311. case 512:
  12312. val |= (DMA_RWCTRL_READ_BNDRY_512 |
  12313. DMA_RWCTRL_WRITE_BNDRY_512);
  12314. break;
  12315. case 1024:
  12316. default:
  12317. val |= (DMA_RWCTRL_READ_BNDRY_1024 |
  12318. DMA_RWCTRL_WRITE_BNDRY_1024);
  12319. break;
  12320. }
  12321. }
  12322. out:
  12323. return val;
  12324. }
  12325. static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
  12326. {
  12327. struct tg3_internal_buffer_desc test_desc;
  12328. u32 sram_dma_descs;
  12329. int i, ret;
  12330. sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
  12331. tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
  12332. tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
  12333. tw32(RDMAC_STATUS, 0);
  12334. tw32(WDMAC_STATUS, 0);
  12335. tw32(BUFMGR_MODE, 0);
  12336. tw32(FTQ_RESET, 0);
  12337. test_desc.addr_hi = ((u64) buf_dma) >> 32;
  12338. test_desc.addr_lo = buf_dma & 0xffffffff;
  12339. test_desc.nic_mbuf = 0x00002100;
  12340. test_desc.len = size;
  12341. /*
  12342. * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
  12343. * the *second* time the tg3 driver was getting loaded after an
  12344. * initial scan.
  12345. *
  12346. * Broadcom tells me:
  12347. * ...the DMA engine is connected to the GRC block and a DMA
  12348. * reset may affect the GRC block in some unpredictable way...
  12349. * The behavior of resets to individual blocks has not been tested.
  12350. *
  12351. * Broadcom noted the GRC reset will also reset all sub-components.
  12352. */
  12353. if (to_device) {
  12354. test_desc.cqid_sqid = (13 << 8) | 2;
  12355. tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
  12356. udelay(40);
  12357. } else {
  12358. test_desc.cqid_sqid = (16 << 8) | 7;
  12359. tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
  12360. udelay(40);
  12361. }
  12362. test_desc.flags = 0x00000005;
  12363. for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
  12364. u32 val;
  12365. val = *(((u32 *)&test_desc) + i);
  12366. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
  12367. sram_dma_descs + (i * sizeof(u32)));
  12368. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  12369. }
  12370. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  12371. if (to_device)
  12372. tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
  12373. else
  12374. tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
  12375. ret = -ENODEV;
  12376. for (i = 0; i < 40; i++) {
  12377. u32 val;
  12378. if (to_device)
  12379. val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
  12380. else
  12381. val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
  12382. if ((val & 0xffff) == sram_dma_descs) {
  12383. ret = 0;
  12384. break;
  12385. }
  12386. udelay(100);
  12387. }
  12388. return ret;
  12389. }
  12390. #define TEST_BUFFER_SIZE 0x2000
  12391. static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
  12392. { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
  12393. { },
  12394. };
  12395. static int __devinit tg3_test_dma(struct tg3 *tp)
  12396. {
  12397. dma_addr_t buf_dma;
  12398. u32 *buf, saved_dma_rwctrl;
  12399. int ret = 0;
  12400. buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
  12401. &buf_dma, GFP_KERNEL);
  12402. if (!buf) {
  12403. ret = -ENOMEM;
  12404. goto out_nofree;
  12405. }
  12406. tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  12407. (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
  12408. tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
  12409. if (tg3_flag(tp, 57765_PLUS))
  12410. goto out;
  12411. if (tg3_flag(tp, PCI_EXPRESS)) {
  12412. /* DMA read watermark not used on PCIE */
  12413. tp->dma_rwctrl |= 0x00180000;
  12414. } else if (!tg3_flag(tp, PCIX_MODE)) {
  12415. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
  12416. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
  12417. tp->dma_rwctrl |= 0x003f0000;
  12418. else
  12419. tp->dma_rwctrl |= 0x003f000f;
  12420. } else {
  12421. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  12422. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  12423. u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
  12424. u32 read_water = 0x7;
  12425. /* If the 5704 is behind the EPB bridge, we can
  12426. * do the less restrictive ONE_DMA workaround for
  12427. * better performance.
  12428. */
  12429. if (tg3_flag(tp, 40BIT_DMA_BUG) &&
  12430. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  12431. tp->dma_rwctrl |= 0x8000;
  12432. else if (ccval == 0x6 || ccval == 0x7)
  12433. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  12434. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
  12435. read_water = 4;
  12436. /* Set bit 23 to enable PCIX hw bug fix */
  12437. tp->dma_rwctrl |=
  12438. (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
  12439. (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  12440. (1 << 23);
  12441. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
  12442. /* 5780 always in PCIX mode */
  12443. tp->dma_rwctrl |= 0x00144000;
  12444. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  12445. /* 5714 always in PCIX mode */
  12446. tp->dma_rwctrl |= 0x00148000;
  12447. } else {
  12448. tp->dma_rwctrl |= 0x001b000f;
  12449. }
  12450. }
  12451. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  12452. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  12453. tp->dma_rwctrl &= 0xfffffff0;
  12454. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  12455. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  12456. /* Remove this if it causes problems for some boards. */
  12457. tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  12458. /* On 5700/5701 chips, we need to set this bit.
  12459. * Otherwise the chip will issue cacheline transactions
  12460. * to streamable DMA memory with not all the byte
  12461. * enables turned on. This is an error on several
  12462. * RISC PCI controllers, in particular sparc64.
  12463. *
  12464. * On 5703/5704 chips, this bit has been reassigned
  12465. * a different meaning. In particular, it is used
  12466. * on those chips to enable a PCI-X workaround.
  12467. */
  12468. tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  12469. }
  12470. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  12471. #if 0
  12472. /* Unneeded, already done by tg3_get_invariants. */
  12473. tg3_switch_clocks(tp);
  12474. #endif
  12475. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  12476. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  12477. goto out;
  12478. /* It is best to perform DMA test with maximum write burst size
  12479. * to expose the 5700/5701 write DMA bug.
  12480. */
  12481. saved_dma_rwctrl = tp->dma_rwctrl;
  12482. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  12483. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  12484. while (1) {
  12485. u32 *p = buf, i;
  12486. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  12487. p[i] = i;
  12488. /* Send the buffer to the chip. */
  12489. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
  12490. if (ret) {
  12491. dev_err(&tp->pdev->dev,
  12492. "%s: Buffer write failed. err = %d\n",
  12493. __func__, ret);
  12494. break;
  12495. }
  12496. #if 0
  12497. /* validate data reached card RAM correctly. */
  12498. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  12499. u32 val;
  12500. tg3_read_mem(tp, 0x2100 + (i*4), &val);
  12501. if (le32_to_cpu(val) != p[i]) {
  12502. dev_err(&tp->pdev->dev,
  12503. "%s: Buffer corrupted on device! "
  12504. "(%d != %d)\n", __func__, val, i);
  12505. /* ret = -ENODEV here? */
  12506. }
  12507. p[i] = 0;
  12508. }
  12509. #endif
  12510. /* Now read it back. */
  12511. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
  12512. if (ret) {
  12513. dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
  12514. "err = %d\n", __func__, ret);
  12515. break;
  12516. }
  12517. /* Verify it. */
  12518. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  12519. if (p[i] == i)
  12520. continue;
  12521. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  12522. DMA_RWCTRL_WRITE_BNDRY_16) {
  12523. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  12524. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  12525. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  12526. break;
  12527. } else {
  12528. dev_err(&tp->pdev->dev,
  12529. "%s: Buffer corrupted on read back! "
  12530. "(%d != %d)\n", __func__, p[i], i);
  12531. ret = -ENODEV;
  12532. goto out;
  12533. }
  12534. }
  12535. if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
  12536. /* Success. */
  12537. ret = 0;
  12538. break;
  12539. }
  12540. }
  12541. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  12542. DMA_RWCTRL_WRITE_BNDRY_16) {
  12543. /* DMA test passed without adjusting DMA boundary,
  12544. * now look for chipsets that are known to expose the
  12545. * DMA bug without failing the test.
  12546. */
  12547. if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
  12548. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  12549. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  12550. } else {
  12551. /* Safe to use the calculated DMA boundary. */
  12552. tp->dma_rwctrl = saved_dma_rwctrl;
  12553. }
  12554. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  12555. }
  12556. out:
  12557. dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
  12558. out_nofree:
  12559. return ret;
  12560. }
  12561. static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
  12562. {
  12563. if (tg3_flag(tp, 57765_PLUS)) {
  12564. tp->bufmgr_config.mbuf_read_dma_low_water =
  12565. DEFAULT_MB_RDMA_LOW_WATER_5705;
  12566. tp->bufmgr_config.mbuf_mac_rx_low_water =
  12567. DEFAULT_MB_MACRX_LOW_WATER_57765;
  12568. tp->bufmgr_config.mbuf_high_water =
  12569. DEFAULT_MB_HIGH_WATER_57765;
  12570. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  12571. DEFAULT_MB_RDMA_LOW_WATER_5705;
  12572. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  12573. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
  12574. tp->bufmgr_config.mbuf_high_water_jumbo =
  12575. DEFAULT_MB_HIGH_WATER_JUMBO_57765;
  12576. } else if (tg3_flag(tp, 5705_PLUS)) {
  12577. tp->bufmgr_config.mbuf_read_dma_low_water =
  12578. DEFAULT_MB_RDMA_LOW_WATER_5705;
  12579. tp->bufmgr_config.mbuf_mac_rx_low_water =
  12580. DEFAULT_MB_MACRX_LOW_WATER_5705;
  12581. tp->bufmgr_config.mbuf_high_water =
  12582. DEFAULT_MB_HIGH_WATER_5705;
  12583. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  12584. tp->bufmgr_config.mbuf_mac_rx_low_water =
  12585. DEFAULT_MB_MACRX_LOW_WATER_5906;
  12586. tp->bufmgr_config.mbuf_high_water =
  12587. DEFAULT_MB_HIGH_WATER_5906;
  12588. }
  12589. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  12590. DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
  12591. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  12592. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
  12593. tp->bufmgr_config.mbuf_high_water_jumbo =
  12594. DEFAULT_MB_HIGH_WATER_JUMBO_5780;
  12595. } else {
  12596. tp->bufmgr_config.mbuf_read_dma_low_water =
  12597. DEFAULT_MB_RDMA_LOW_WATER;
  12598. tp->bufmgr_config.mbuf_mac_rx_low_water =
  12599. DEFAULT_MB_MACRX_LOW_WATER;
  12600. tp->bufmgr_config.mbuf_high_water =
  12601. DEFAULT_MB_HIGH_WATER;
  12602. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  12603. DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
  12604. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  12605. DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
  12606. tp->bufmgr_config.mbuf_high_water_jumbo =
  12607. DEFAULT_MB_HIGH_WATER_JUMBO;
  12608. }
  12609. tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
  12610. tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
  12611. }
  12612. static char * __devinit tg3_phy_string(struct tg3 *tp)
  12613. {
  12614. switch (tp->phy_id & TG3_PHY_ID_MASK) {
  12615. case TG3_PHY_ID_BCM5400: return "5400";
  12616. case TG3_PHY_ID_BCM5401: return "5401";
  12617. case TG3_PHY_ID_BCM5411: return "5411";
  12618. case TG3_PHY_ID_BCM5701: return "5701";
  12619. case TG3_PHY_ID_BCM5703: return "5703";
  12620. case TG3_PHY_ID_BCM5704: return "5704";
  12621. case TG3_PHY_ID_BCM5705: return "5705";
  12622. case TG3_PHY_ID_BCM5750: return "5750";
  12623. case TG3_PHY_ID_BCM5752: return "5752";
  12624. case TG3_PHY_ID_BCM5714: return "5714";
  12625. case TG3_PHY_ID_BCM5780: return "5780";
  12626. case TG3_PHY_ID_BCM5755: return "5755";
  12627. case TG3_PHY_ID_BCM5787: return "5787";
  12628. case TG3_PHY_ID_BCM5784: return "5784";
  12629. case TG3_PHY_ID_BCM5756: return "5722/5756";
  12630. case TG3_PHY_ID_BCM5906: return "5906";
  12631. case TG3_PHY_ID_BCM5761: return "5761";
  12632. case TG3_PHY_ID_BCM5718C: return "5718C";
  12633. case TG3_PHY_ID_BCM5718S: return "5718S";
  12634. case TG3_PHY_ID_BCM57765: return "57765";
  12635. case TG3_PHY_ID_BCM5719C: return "5719C";
  12636. case TG3_PHY_ID_BCM5720C: return "5720C";
  12637. case TG3_PHY_ID_BCM8002: return "8002/serdes";
  12638. case 0: return "serdes";
  12639. default: return "unknown";
  12640. }
  12641. }
  12642. static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
  12643. {
  12644. if (tg3_flag(tp, PCI_EXPRESS)) {
  12645. strcpy(str, "PCI Express");
  12646. return str;
  12647. } else if (tg3_flag(tp, PCIX_MODE)) {
  12648. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
  12649. strcpy(str, "PCIX:");
  12650. if ((clock_ctrl == 7) ||
  12651. ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
  12652. GRC_MISC_CFG_BOARD_ID_5704CIOBE))
  12653. strcat(str, "133MHz");
  12654. else if (clock_ctrl == 0)
  12655. strcat(str, "33MHz");
  12656. else if (clock_ctrl == 2)
  12657. strcat(str, "50MHz");
  12658. else if (clock_ctrl == 4)
  12659. strcat(str, "66MHz");
  12660. else if (clock_ctrl == 6)
  12661. strcat(str, "100MHz");
  12662. } else {
  12663. strcpy(str, "PCI:");
  12664. if (tg3_flag(tp, PCI_HIGH_SPEED))
  12665. strcat(str, "66MHz");
  12666. else
  12667. strcat(str, "33MHz");
  12668. }
  12669. if (tg3_flag(tp, PCI_32BIT))
  12670. strcat(str, ":32-bit");
  12671. else
  12672. strcat(str, ":64-bit");
  12673. return str;
  12674. }
  12675. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
  12676. {
  12677. struct pci_dev *peer;
  12678. unsigned int func, devnr = tp->pdev->devfn & ~7;
  12679. for (func = 0; func < 8; func++) {
  12680. peer = pci_get_slot(tp->pdev->bus, devnr | func);
  12681. if (peer && peer != tp->pdev)
  12682. break;
  12683. pci_dev_put(peer);
  12684. }
  12685. /* 5704 can be configured in single-port mode, set peer to
  12686. * tp->pdev in that case.
  12687. */
  12688. if (!peer) {
  12689. peer = tp->pdev;
  12690. return peer;
  12691. }
  12692. /*
  12693. * We don't need to keep the refcount elevated; there's no way
  12694. * to remove one half of this device without removing the other
  12695. */
  12696. pci_dev_put(peer);
  12697. return peer;
  12698. }
  12699. static void __devinit tg3_init_coal(struct tg3 *tp)
  12700. {
  12701. struct ethtool_coalesce *ec = &tp->coal;
  12702. memset(ec, 0, sizeof(*ec));
  12703. ec->cmd = ETHTOOL_GCOALESCE;
  12704. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
  12705. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
  12706. ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
  12707. ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
  12708. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
  12709. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
  12710. ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
  12711. ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
  12712. ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
  12713. if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
  12714. HOSTCC_MODE_CLRTICK_TXBD)) {
  12715. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
  12716. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
  12717. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
  12718. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
  12719. }
  12720. if (tg3_flag(tp, 5705_PLUS)) {
  12721. ec->rx_coalesce_usecs_irq = 0;
  12722. ec->tx_coalesce_usecs_irq = 0;
  12723. ec->stats_block_coalesce_usecs = 0;
  12724. }
  12725. }
  12726. static const struct net_device_ops tg3_netdev_ops = {
  12727. .ndo_open = tg3_open,
  12728. .ndo_stop = tg3_close,
  12729. .ndo_start_xmit = tg3_start_xmit,
  12730. .ndo_get_stats64 = tg3_get_stats64,
  12731. .ndo_validate_addr = eth_validate_addr,
  12732. .ndo_set_rx_mode = tg3_set_rx_mode,
  12733. .ndo_set_mac_address = tg3_set_mac_addr,
  12734. .ndo_do_ioctl = tg3_ioctl,
  12735. .ndo_tx_timeout = tg3_tx_timeout,
  12736. .ndo_change_mtu = tg3_change_mtu,
  12737. .ndo_fix_features = tg3_fix_features,
  12738. .ndo_set_features = tg3_set_features,
  12739. #ifdef CONFIG_NET_POLL_CONTROLLER
  12740. .ndo_poll_controller = tg3_poll_controller,
  12741. #endif
  12742. };
  12743. static int __devinit tg3_init_one(struct pci_dev *pdev,
  12744. const struct pci_device_id *ent)
  12745. {
  12746. struct net_device *dev;
  12747. struct tg3 *tp;
  12748. int i, err, pm_cap;
  12749. u32 sndmbx, rcvmbx, intmbx;
  12750. char str[40];
  12751. u64 dma_mask, persist_dma_mask;
  12752. netdev_features_t features = 0;
  12753. printk_once(KERN_INFO "%s\n", version);
  12754. err = pci_enable_device(pdev);
  12755. if (err) {
  12756. dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
  12757. return err;
  12758. }
  12759. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  12760. if (err) {
  12761. dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
  12762. goto err_out_disable_pdev;
  12763. }
  12764. pci_set_master(pdev);
  12765. /* Find power-management capability. */
  12766. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  12767. if (pm_cap == 0) {
  12768. dev_err(&pdev->dev,
  12769. "Cannot find Power Management capability, aborting\n");
  12770. err = -EIO;
  12771. goto err_out_free_res;
  12772. }
  12773. err = pci_set_power_state(pdev, PCI_D0);
  12774. if (err) {
  12775. dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
  12776. goto err_out_free_res;
  12777. }
  12778. dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
  12779. if (!dev) {
  12780. dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
  12781. err = -ENOMEM;
  12782. goto err_out_power_down;
  12783. }
  12784. SET_NETDEV_DEV(dev, &pdev->dev);
  12785. tp = netdev_priv(dev);
  12786. tp->pdev = pdev;
  12787. tp->dev = dev;
  12788. tp->pm_cap = pm_cap;
  12789. tp->rx_mode = TG3_DEF_RX_MODE;
  12790. tp->tx_mode = TG3_DEF_TX_MODE;
  12791. if (tg3_debug > 0)
  12792. tp->msg_enable = tg3_debug;
  12793. else
  12794. tp->msg_enable = TG3_DEF_MSG_ENABLE;
  12795. /* The word/byte swap controls here control register access byte
  12796. * swapping. DMA data byte swapping is controlled in the GRC_MODE
  12797. * setting below.
  12798. */
  12799. tp->misc_host_ctrl =
  12800. MISC_HOST_CTRL_MASK_PCI_INT |
  12801. MISC_HOST_CTRL_WORD_SWAP |
  12802. MISC_HOST_CTRL_INDIR_ACCESS |
  12803. MISC_HOST_CTRL_PCISTATE_RW;
  12804. /* The NONFRM (non-frame) byte/word swap controls take effect
  12805. * on descriptor entries, anything which isn't packet data.
  12806. *
  12807. * The StrongARM chips on the board (one for tx, one for rx)
  12808. * are running in big-endian mode.
  12809. */
  12810. tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
  12811. GRC_MODE_WSWAP_NONFRM_DATA);
  12812. #ifdef __BIG_ENDIAN
  12813. tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
  12814. #endif
  12815. spin_lock_init(&tp->lock);
  12816. spin_lock_init(&tp->indirect_lock);
  12817. INIT_WORK(&tp->reset_task, tg3_reset_task);
  12818. tp->regs = pci_ioremap_bar(pdev, BAR_0);
  12819. if (!tp->regs) {
  12820. dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
  12821. err = -ENOMEM;
  12822. goto err_out_free_dev;
  12823. }
  12824. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  12825. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
  12826. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
  12827. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
  12828. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  12829. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
  12830. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
  12831. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
  12832. tg3_flag_set(tp, ENABLE_APE);
  12833. tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
  12834. if (!tp->aperegs) {
  12835. dev_err(&pdev->dev,
  12836. "Cannot map APE registers, aborting\n");
  12837. err = -ENOMEM;
  12838. goto err_out_iounmap;
  12839. }
  12840. }
  12841. tp->rx_pending = TG3_DEF_RX_RING_PENDING;
  12842. tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
  12843. dev->ethtool_ops = &tg3_ethtool_ops;
  12844. dev->watchdog_timeo = TG3_TX_TIMEOUT;
  12845. dev->netdev_ops = &tg3_netdev_ops;
  12846. dev->irq = pdev->irq;
  12847. err = tg3_get_invariants(tp);
  12848. if (err) {
  12849. dev_err(&pdev->dev,
  12850. "Problem fetching invariants of chip, aborting\n");
  12851. goto err_out_apeunmap;
  12852. }
  12853. /* The EPB bridge inside 5714, 5715, and 5780 and any
  12854. * device behind the EPB cannot support DMA addresses > 40-bit.
  12855. * On 64-bit systems with IOMMU, use 40-bit dma_mask.
  12856. * On 64-bit systems without IOMMU, use 64-bit dma_mask and
  12857. * do DMA address check in tg3_start_xmit().
  12858. */
  12859. if (tg3_flag(tp, IS_5788))
  12860. persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
  12861. else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
  12862. persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
  12863. #ifdef CONFIG_HIGHMEM
  12864. dma_mask = DMA_BIT_MASK(64);
  12865. #endif
  12866. } else
  12867. persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
  12868. /* Configure DMA attributes. */
  12869. if (dma_mask > DMA_BIT_MASK(32)) {
  12870. err = pci_set_dma_mask(pdev, dma_mask);
  12871. if (!err) {
  12872. features |= NETIF_F_HIGHDMA;
  12873. err = pci_set_consistent_dma_mask(pdev,
  12874. persist_dma_mask);
  12875. if (err < 0) {
  12876. dev_err(&pdev->dev, "Unable to obtain 64 bit "
  12877. "DMA for consistent allocations\n");
  12878. goto err_out_apeunmap;
  12879. }
  12880. }
  12881. }
  12882. if (err || dma_mask == DMA_BIT_MASK(32)) {
  12883. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  12884. if (err) {
  12885. dev_err(&pdev->dev,
  12886. "No usable DMA configuration, aborting\n");
  12887. goto err_out_apeunmap;
  12888. }
  12889. }
  12890. tg3_init_bufmgr_config(tp);
  12891. features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  12892. /* 5700 B0 chips do not support checksumming correctly due
  12893. * to hardware bugs.
  12894. */
  12895. if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
  12896. features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
  12897. if (tg3_flag(tp, 5755_PLUS))
  12898. features |= NETIF_F_IPV6_CSUM;
  12899. }
  12900. /* TSO is on by default on chips that support hardware TSO.
  12901. * Firmware TSO on older chips gives lower performance, so it
  12902. * is off by default, but can be enabled using ethtool.
  12903. */
  12904. if ((tg3_flag(tp, HW_TSO_1) ||
  12905. tg3_flag(tp, HW_TSO_2) ||
  12906. tg3_flag(tp, HW_TSO_3)) &&
  12907. (features & NETIF_F_IP_CSUM))
  12908. features |= NETIF_F_TSO;
  12909. if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
  12910. if (features & NETIF_F_IPV6_CSUM)
  12911. features |= NETIF_F_TSO6;
  12912. if (tg3_flag(tp, HW_TSO_3) ||
  12913. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  12914. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  12915. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
  12916. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  12917. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  12918. features |= NETIF_F_TSO_ECN;
  12919. }
  12920. dev->features |= features;
  12921. dev->vlan_features |= features;
  12922. /*
  12923. * Add loopback capability only for a subset of devices that support
  12924. * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
  12925. * loopback for the remaining devices.
  12926. */
  12927. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
  12928. !tg3_flag(tp, CPMU_PRESENT))
  12929. /* Add the loopback capability */
  12930. features |= NETIF_F_LOOPBACK;
  12931. dev->hw_features |= features;
  12932. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
  12933. !tg3_flag(tp, TSO_CAPABLE) &&
  12934. !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
  12935. tg3_flag_set(tp, MAX_RXPEND_64);
  12936. tp->rx_pending = 63;
  12937. }
  12938. err = tg3_get_device_address(tp);
  12939. if (err) {
  12940. dev_err(&pdev->dev,
  12941. "Could not obtain valid ethernet address, aborting\n");
  12942. goto err_out_apeunmap;
  12943. }
  12944. /*
  12945. * Reset chip in case UNDI or EFI driver did not shutdown
  12946. * DMA self test will enable WDMAC and we'll see (spurious)
  12947. * pending DMA on the PCI bus at that point.
  12948. */
  12949. if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
  12950. (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  12951. tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  12952. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  12953. }
  12954. err = tg3_test_dma(tp);
  12955. if (err) {
  12956. dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
  12957. goto err_out_apeunmap;
  12958. }
  12959. intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
  12960. rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
  12961. sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
  12962. for (i = 0; i < tp->irq_max; i++) {
  12963. struct tg3_napi *tnapi = &tp->napi[i];
  12964. tnapi->tp = tp;
  12965. tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
  12966. tnapi->int_mbox = intmbx;
  12967. if (i <= 4)
  12968. intmbx += 0x8;
  12969. else
  12970. intmbx += 0x4;
  12971. tnapi->consmbox = rcvmbx;
  12972. tnapi->prodmbox = sndmbx;
  12973. if (i)
  12974. tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
  12975. else
  12976. tnapi->coal_now = HOSTCC_MODE_NOW;
  12977. if (!tg3_flag(tp, SUPPORT_MSIX))
  12978. break;
  12979. /*
  12980. * If we support MSIX, we'll be using RSS. If we're using
  12981. * RSS, the first vector only handles link interrupts and the
  12982. * remaining vectors handle rx and tx interrupts. Reuse the
  12983. * mailbox values for the next iteration. The values we setup
  12984. * above are still useful for the single vectored mode.
  12985. */
  12986. if (!i)
  12987. continue;
  12988. rcvmbx += 0x8;
  12989. if (sndmbx & 0x4)
  12990. sndmbx -= 0x4;
  12991. else
  12992. sndmbx += 0xc;
  12993. }
  12994. tg3_init_coal(tp);
  12995. pci_set_drvdata(pdev, dev);
  12996. if (tg3_flag(tp, 5717_PLUS)) {
  12997. /* Resume a low-power mode */
  12998. tg3_frob_aux_power(tp, false);
  12999. }
  13000. err = register_netdev(dev);
  13001. if (err) {
  13002. dev_err(&pdev->dev, "Cannot register net device, aborting\n");
  13003. goto err_out_apeunmap;
  13004. }
  13005. netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
  13006. tp->board_part_number,
  13007. tp->pci_chip_rev_id,
  13008. tg3_bus_string(tp, str),
  13009. dev->dev_addr);
  13010. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  13011. struct phy_device *phydev;
  13012. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  13013. netdev_info(dev,
  13014. "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
  13015. phydev->drv->name, dev_name(&phydev->dev));
  13016. } else {
  13017. char *ethtype;
  13018. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  13019. ethtype = "10/100Base-TX";
  13020. else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  13021. ethtype = "1000Base-SX";
  13022. else
  13023. ethtype = "10/100/1000Base-T";
  13024. netdev_info(dev, "attached PHY is %s (%s Ethernet) "
  13025. "(WireSpeed[%d], EEE[%d])\n",
  13026. tg3_phy_string(tp), ethtype,
  13027. (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
  13028. (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
  13029. }
  13030. netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
  13031. (dev->features & NETIF_F_RXCSUM) != 0,
  13032. tg3_flag(tp, USE_LINKCHG_REG) != 0,
  13033. (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
  13034. tg3_flag(tp, ENABLE_ASF) != 0,
  13035. tg3_flag(tp, TSO_CAPABLE) != 0);
  13036. netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
  13037. tp->dma_rwctrl,
  13038. pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
  13039. ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
  13040. pci_save_state(pdev);
  13041. return 0;
  13042. err_out_apeunmap:
  13043. if (tp->aperegs) {
  13044. iounmap(tp->aperegs);
  13045. tp->aperegs = NULL;
  13046. }
  13047. err_out_iounmap:
  13048. if (tp->regs) {
  13049. iounmap(tp->regs);
  13050. tp->regs = NULL;
  13051. }
  13052. err_out_free_dev:
  13053. free_netdev(dev);
  13054. err_out_power_down:
  13055. pci_set_power_state(pdev, PCI_D3hot);
  13056. err_out_free_res:
  13057. pci_release_regions(pdev);
  13058. err_out_disable_pdev:
  13059. pci_disable_device(pdev);
  13060. pci_set_drvdata(pdev, NULL);
  13061. return err;
  13062. }
  13063. static void __devexit tg3_remove_one(struct pci_dev *pdev)
  13064. {
  13065. struct net_device *dev = pci_get_drvdata(pdev);
  13066. if (dev) {
  13067. struct tg3 *tp = netdev_priv(dev);
  13068. if (tp->fw)
  13069. release_firmware(tp->fw);
  13070. tg3_reset_task_cancel(tp);
  13071. if (tg3_flag(tp, USE_PHYLIB)) {
  13072. tg3_phy_fini(tp);
  13073. tg3_mdio_fini(tp);
  13074. }
  13075. unregister_netdev(dev);
  13076. if (tp->aperegs) {
  13077. iounmap(tp->aperegs);
  13078. tp->aperegs = NULL;
  13079. }
  13080. if (tp->regs) {
  13081. iounmap(tp->regs);
  13082. tp->regs = NULL;
  13083. }
  13084. free_netdev(dev);
  13085. pci_release_regions(pdev);
  13086. pci_disable_device(pdev);
  13087. pci_set_drvdata(pdev, NULL);
  13088. }
  13089. }
  13090. #ifdef CONFIG_PM_SLEEP
  13091. static int tg3_suspend(struct device *device)
  13092. {
  13093. struct pci_dev *pdev = to_pci_dev(device);
  13094. struct net_device *dev = pci_get_drvdata(pdev);
  13095. struct tg3 *tp = netdev_priv(dev);
  13096. int err;
  13097. if (!netif_running(dev))
  13098. return 0;
  13099. tg3_reset_task_cancel(tp);
  13100. tg3_phy_stop(tp);
  13101. tg3_netif_stop(tp);
  13102. del_timer_sync(&tp->timer);
  13103. tg3_full_lock(tp, 1);
  13104. tg3_disable_ints(tp);
  13105. tg3_full_unlock(tp);
  13106. netif_device_detach(dev);
  13107. tg3_full_lock(tp, 0);
  13108. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  13109. tg3_flag_clear(tp, INIT_COMPLETE);
  13110. tg3_full_unlock(tp);
  13111. err = tg3_power_down_prepare(tp);
  13112. if (err) {
  13113. int err2;
  13114. tg3_full_lock(tp, 0);
  13115. tg3_flag_set(tp, INIT_COMPLETE);
  13116. err2 = tg3_restart_hw(tp, 1);
  13117. if (err2)
  13118. goto out;
  13119. tp->timer.expires = jiffies + tp->timer_offset;
  13120. add_timer(&tp->timer);
  13121. netif_device_attach(dev);
  13122. tg3_netif_start(tp);
  13123. out:
  13124. tg3_full_unlock(tp);
  13125. if (!err2)
  13126. tg3_phy_start(tp);
  13127. }
  13128. return err;
  13129. }
  13130. static int tg3_resume(struct device *device)
  13131. {
  13132. struct pci_dev *pdev = to_pci_dev(device);
  13133. struct net_device *dev = pci_get_drvdata(pdev);
  13134. struct tg3 *tp = netdev_priv(dev);
  13135. int err;
  13136. if (!netif_running(dev))
  13137. return 0;
  13138. netif_device_attach(dev);
  13139. tg3_full_lock(tp, 0);
  13140. tg3_flag_set(tp, INIT_COMPLETE);
  13141. err = tg3_restart_hw(tp, 1);
  13142. if (err)
  13143. goto out;
  13144. tp->timer.expires = jiffies + tp->timer_offset;
  13145. add_timer(&tp->timer);
  13146. tg3_netif_start(tp);
  13147. out:
  13148. tg3_full_unlock(tp);
  13149. if (!err)
  13150. tg3_phy_start(tp);
  13151. return err;
  13152. }
  13153. static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
  13154. #define TG3_PM_OPS (&tg3_pm_ops)
  13155. #else
  13156. #define TG3_PM_OPS NULL
  13157. #endif /* CONFIG_PM_SLEEP */
  13158. /**
  13159. * tg3_io_error_detected - called when PCI error is detected
  13160. * @pdev: Pointer to PCI device
  13161. * @state: The current pci connection state
  13162. *
  13163. * This function is called after a PCI bus error affecting
  13164. * this device has been detected.
  13165. */
  13166. static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
  13167. pci_channel_state_t state)
  13168. {
  13169. struct net_device *netdev = pci_get_drvdata(pdev);
  13170. struct tg3 *tp = netdev_priv(netdev);
  13171. pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
  13172. netdev_info(netdev, "PCI I/O error detected\n");
  13173. rtnl_lock();
  13174. if (!netif_running(netdev))
  13175. goto done;
  13176. tg3_phy_stop(tp);
  13177. tg3_netif_stop(tp);
  13178. del_timer_sync(&tp->timer);
  13179. /* Want to make sure that the reset task doesn't run */
  13180. tg3_reset_task_cancel(tp);
  13181. tg3_flag_clear(tp, TX_RECOVERY_PENDING);
  13182. netif_device_detach(netdev);
  13183. /* Clean up software state, even if MMIO is blocked */
  13184. tg3_full_lock(tp, 0);
  13185. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  13186. tg3_full_unlock(tp);
  13187. done:
  13188. if (state == pci_channel_io_perm_failure)
  13189. err = PCI_ERS_RESULT_DISCONNECT;
  13190. else
  13191. pci_disable_device(pdev);
  13192. rtnl_unlock();
  13193. return err;
  13194. }
  13195. /**
  13196. * tg3_io_slot_reset - called after the pci bus has been reset.
  13197. * @pdev: Pointer to PCI device
  13198. *
  13199. * Restart the card from scratch, as if from a cold-boot.
  13200. * At this point, the card has exprienced a hard reset,
  13201. * followed by fixups by BIOS, and has its config space
  13202. * set up identically to what it was at cold boot.
  13203. */
  13204. static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
  13205. {
  13206. struct net_device *netdev = pci_get_drvdata(pdev);
  13207. struct tg3 *tp = netdev_priv(netdev);
  13208. pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
  13209. int err;
  13210. rtnl_lock();
  13211. if (pci_enable_device(pdev)) {
  13212. netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
  13213. goto done;
  13214. }
  13215. pci_set_master(pdev);
  13216. pci_restore_state(pdev);
  13217. pci_save_state(pdev);
  13218. if (!netif_running(netdev)) {
  13219. rc = PCI_ERS_RESULT_RECOVERED;
  13220. goto done;
  13221. }
  13222. err = tg3_power_up(tp);
  13223. if (err)
  13224. goto done;
  13225. rc = PCI_ERS_RESULT_RECOVERED;
  13226. done:
  13227. rtnl_unlock();
  13228. return rc;
  13229. }
  13230. /**
  13231. * tg3_io_resume - called when traffic can start flowing again.
  13232. * @pdev: Pointer to PCI device
  13233. *
  13234. * This callback is called when the error recovery driver tells
  13235. * us that its OK to resume normal operation.
  13236. */
  13237. static void tg3_io_resume(struct pci_dev *pdev)
  13238. {
  13239. struct net_device *netdev = pci_get_drvdata(pdev);
  13240. struct tg3 *tp = netdev_priv(netdev);
  13241. int err;
  13242. rtnl_lock();
  13243. if (!netif_running(netdev))
  13244. goto done;
  13245. tg3_full_lock(tp, 0);
  13246. tg3_flag_set(tp, INIT_COMPLETE);
  13247. err = tg3_restart_hw(tp, 1);
  13248. tg3_full_unlock(tp);
  13249. if (err) {
  13250. netdev_err(netdev, "Cannot restart hardware after reset.\n");
  13251. goto done;
  13252. }
  13253. netif_device_attach(netdev);
  13254. tp->timer.expires = jiffies + tp->timer_offset;
  13255. add_timer(&tp->timer);
  13256. tg3_netif_start(tp);
  13257. tg3_phy_start(tp);
  13258. done:
  13259. rtnl_unlock();
  13260. }
  13261. static struct pci_error_handlers tg3_err_handler = {
  13262. .error_detected = tg3_io_error_detected,
  13263. .slot_reset = tg3_io_slot_reset,
  13264. .resume = tg3_io_resume
  13265. };
  13266. static struct pci_driver tg3_driver = {
  13267. .name = DRV_MODULE_NAME,
  13268. .id_table = tg3_pci_tbl,
  13269. .probe = tg3_init_one,
  13270. .remove = __devexit_p(tg3_remove_one),
  13271. .err_handler = &tg3_err_handler,
  13272. .driver.pm = TG3_PM_OPS,
  13273. };
  13274. static int __init tg3_init(void)
  13275. {
  13276. return pci_register_driver(&tg3_driver);
  13277. }
  13278. static void __exit tg3_cleanup(void)
  13279. {
  13280. pci_unregister_driver(&tg3_driver);
  13281. }
  13282. module_init(tg3_init);
  13283. module_exit(tg3_cleanup);