intel_display.c 197 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/module.h>
  28. #include <linux/input.h>
  29. #include <linux/i2c.h>
  30. #include <linux/kernel.h>
  31. #include <linux/slab.h>
  32. #include <linux/vgaarb.h>
  33. #include <drm/drm_edid.h>
  34. #include "drmP.h"
  35. #include "intel_drv.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #include "i915_trace.h"
  39. #include "drm_dp_helper.h"
  40. #include "drm_crtc_helper.h"
  41. #include <linux/dma_remapping.h>
  42. #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43. bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  44. static void intel_increase_pllclock(struct drm_crtc *crtc);
  45. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46. typedef struct {
  47. /* given values */
  48. int n;
  49. int m1, m2;
  50. int p1, p2;
  51. /* derived values */
  52. int dot;
  53. int vco;
  54. int m;
  55. int p;
  56. } intel_clock_t;
  57. typedef struct {
  58. int min, max;
  59. } intel_range_t;
  60. typedef struct {
  61. int dot_limit;
  62. int p2_slow, p2_fast;
  63. } intel_p2_t;
  64. #define INTEL_P2_NUM 2
  65. typedef struct intel_limit intel_limit_t;
  66. struct intel_limit {
  67. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  68. intel_p2_t p2;
  69. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  70. int, int, intel_clock_t *, intel_clock_t *);
  71. };
  72. /* FDI */
  73. #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
  74. static bool
  75. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  76. int target, int refclk, intel_clock_t *match_clock,
  77. intel_clock_t *best_clock);
  78. static bool
  79. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  80. int target, int refclk, intel_clock_t *match_clock,
  81. intel_clock_t *best_clock);
  82. static bool
  83. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  84. int target, int refclk, intel_clock_t *match_clock,
  85. intel_clock_t *best_clock);
  86. static bool
  87. intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  88. int target, int refclk, intel_clock_t *match_clock,
  89. intel_clock_t *best_clock);
  90. static bool
  91. intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
  92. int target, int refclk, intel_clock_t *match_clock,
  93. intel_clock_t *best_clock);
  94. static inline u32 /* units of 100MHz */
  95. intel_fdi_link_freq(struct drm_device *dev)
  96. {
  97. if (IS_GEN5(dev)) {
  98. struct drm_i915_private *dev_priv = dev->dev_private;
  99. return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  100. } else
  101. return 27;
  102. }
  103. static const intel_limit_t intel_limits_i8xx_dvo = {
  104. .dot = { .min = 25000, .max = 350000 },
  105. .vco = { .min = 930000, .max = 1400000 },
  106. .n = { .min = 3, .max = 16 },
  107. .m = { .min = 96, .max = 140 },
  108. .m1 = { .min = 18, .max = 26 },
  109. .m2 = { .min = 6, .max = 16 },
  110. .p = { .min = 4, .max = 128 },
  111. .p1 = { .min = 2, .max = 33 },
  112. .p2 = { .dot_limit = 165000,
  113. .p2_slow = 4, .p2_fast = 2 },
  114. .find_pll = intel_find_best_PLL,
  115. };
  116. static const intel_limit_t intel_limits_i8xx_lvds = {
  117. .dot = { .min = 25000, .max = 350000 },
  118. .vco = { .min = 930000, .max = 1400000 },
  119. .n = { .min = 3, .max = 16 },
  120. .m = { .min = 96, .max = 140 },
  121. .m1 = { .min = 18, .max = 26 },
  122. .m2 = { .min = 6, .max = 16 },
  123. .p = { .min = 4, .max = 128 },
  124. .p1 = { .min = 1, .max = 6 },
  125. .p2 = { .dot_limit = 165000,
  126. .p2_slow = 14, .p2_fast = 7 },
  127. .find_pll = intel_find_best_PLL,
  128. };
  129. static const intel_limit_t intel_limits_i9xx_sdvo = {
  130. .dot = { .min = 20000, .max = 400000 },
  131. .vco = { .min = 1400000, .max = 2800000 },
  132. .n = { .min = 1, .max = 6 },
  133. .m = { .min = 70, .max = 120 },
  134. .m1 = { .min = 10, .max = 22 },
  135. .m2 = { .min = 5, .max = 9 },
  136. .p = { .min = 5, .max = 80 },
  137. .p1 = { .min = 1, .max = 8 },
  138. .p2 = { .dot_limit = 200000,
  139. .p2_slow = 10, .p2_fast = 5 },
  140. .find_pll = intel_find_best_PLL,
  141. };
  142. static const intel_limit_t intel_limits_i9xx_lvds = {
  143. .dot = { .min = 20000, .max = 400000 },
  144. .vco = { .min = 1400000, .max = 2800000 },
  145. .n = { .min = 1, .max = 6 },
  146. .m = { .min = 70, .max = 120 },
  147. .m1 = { .min = 10, .max = 22 },
  148. .m2 = { .min = 5, .max = 9 },
  149. .p = { .min = 7, .max = 98 },
  150. .p1 = { .min = 1, .max = 8 },
  151. .p2 = { .dot_limit = 112000,
  152. .p2_slow = 14, .p2_fast = 7 },
  153. .find_pll = intel_find_best_PLL,
  154. };
  155. static const intel_limit_t intel_limits_g4x_sdvo = {
  156. .dot = { .min = 25000, .max = 270000 },
  157. .vco = { .min = 1750000, .max = 3500000},
  158. .n = { .min = 1, .max = 4 },
  159. .m = { .min = 104, .max = 138 },
  160. .m1 = { .min = 17, .max = 23 },
  161. .m2 = { .min = 5, .max = 11 },
  162. .p = { .min = 10, .max = 30 },
  163. .p1 = { .min = 1, .max = 3},
  164. .p2 = { .dot_limit = 270000,
  165. .p2_slow = 10,
  166. .p2_fast = 10
  167. },
  168. .find_pll = intel_g4x_find_best_PLL,
  169. };
  170. static const intel_limit_t intel_limits_g4x_hdmi = {
  171. .dot = { .min = 22000, .max = 400000 },
  172. .vco = { .min = 1750000, .max = 3500000},
  173. .n = { .min = 1, .max = 4 },
  174. .m = { .min = 104, .max = 138 },
  175. .m1 = { .min = 16, .max = 23 },
  176. .m2 = { .min = 5, .max = 11 },
  177. .p = { .min = 5, .max = 80 },
  178. .p1 = { .min = 1, .max = 8},
  179. .p2 = { .dot_limit = 165000,
  180. .p2_slow = 10, .p2_fast = 5 },
  181. .find_pll = intel_g4x_find_best_PLL,
  182. };
  183. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  184. .dot = { .min = 20000, .max = 115000 },
  185. .vco = { .min = 1750000, .max = 3500000 },
  186. .n = { .min = 1, .max = 3 },
  187. .m = { .min = 104, .max = 138 },
  188. .m1 = { .min = 17, .max = 23 },
  189. .m2 = { .min = 5, .max = 11 },
  190. .p = { .min = 28, .max = 112 },
  191. .p1 = { .min = 2, .max = 8 },
  192. .p2 = { .dot_limit = 0,
  193. .p2_slow = 14, .p2_fast = 14
  194. },
  195. .find_pll = intel_g4x_find_best_PLL,
  196. };
  197. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  198. .dot = { .min = 80000, .max = 224000 },
  199. .vco = { .min = 1750000, .max = 3500000 },
  200. .n = { .min = 1, .max = 3 },
  201. .m = { .min = 104, .max = 138 },
  202. .m1 = { .min = 17, .max = 23 },
  203. .m2 = { .min = 5, .max = 11 },
  204. .p = { .min = 14, .max = 42 },
  205. .p1 = { .min = 2, .max = 6 },
  206. .p2 = { .dot_limit = 0,
  207. .p2_slow = 7, .p2_fast = 7
  208. },
  209. .find_pll = intel_g4x_find_best_PLL,
  210. };
  211. static const intel_limit_t intel_limits_g4x_display_port = {
  212. .dot = { .min = 161670, .max = 227000 },
  213. .vco = { .min = 1750000, .max = 3500000},
  214. .n = { .min = 1, .max = 2 },
  215. .m = { .min = 97, .max = 108 },
  216. .m1 = { .min = 0x10, .max = 0x12 },
  217. .m2 = { .min = 0x05, .max = 0x06 },
  218. .p = { .min = 10, .max = 20 },
  219. .p1 = { .min = 1, .max = 2},
  220. .p2 = { .dot_limit = 0,
  221. .p2_slow = 10, .p2_fast = 10 },
  222. .find_pll = intel_find_pll_g4x_dp,
  223. };
  224. static const intel_limit_t intel_limits_pineview_sdvo = {
  225. .dot = { .min = 20000, .max = 400000},
  226. .vco = { .min = 1700000, .max = 3500000 },
  227. /* Pineview's Ncounter is a ring counter */
  228. .n = { .min = 3, .max = 6 },
  229. .m = { .min = 2, .max = 256 },
  230. /* Pineview only has one combined m divider, which we treat as m2. */
  231. .m1 = { .min = 0, .max = 0 },
  232. .m2 = { .min = 0, .max = 254 },
  233. .p = { .min = 5, .max = 80 },
  234. .p1 = { .min = 1, .max = 8 },
  235. .p2 = { .dot_limit = 200000,
  236. .p2_slow = 10, .p2_fast = 5 },
  237. .find_pll = intel_find_best_PLL,
  238. };
  239. static const intel_limit_t intel_limits_pineview_lvds = {
  240. .dot = { .min = 20000, .max = 400000 },
  241. .vco = { .min = 1700000, .max = 3500000 },
  242. .n = { .min = 3, .max = 6 },
  243. .m = { .min = 2, .max = 256 },
  244. .m1 = { .min = 0, .max = 0 },
  245. .m2 = { .min = 0, .max = 254 },
  246. .p = { .min = 7, .max = 112 },
  247. .p1 = { .min = 1, .max = 8 },
  248. .p2 = { .dot_limit = 112000,
  249. .p2_slow = 14, .p2_fast = 14 },
  250. .find_pll = intel_find_best_PLL,
  251. };
  252. /* Ironlake / Sandybridge
  253. *
  254. * We calculate clock using (register_value + 2) for N/M1/M2, so here
  255. * the range value for them is (actual_value - 2).
  256. */
  257. static const intel_limit_t intel_limits_ironlake_dac = {
  258. .dot = { .min = 25000, .max = 350000 },
  259. .vco = { .min = 1760000, .max = 3510000 },
  260. .n = { .min = 1, .max = 5 },
  261. .m = { .min = 79, .max = 127 },
  262. .m1 = { .min = 12, .max = 22 },
  263. .m2 = { .min = 5, .max = 9 },
  264. .p = { .min = 5, .max = 80 },
  265. .p1 = { .min = 1, .max = 8 },
  266. .p2 = { .dot_limit = 225000,
  267. .p2_slow = 10, .p2_fast = 5 },
  268. .find_pll = intel_g4x_find_best_PLL,
  269. };
  270. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  271. .dot = { .min = 25000, .max = 350000 },
  272. .vco = { .min = 1760000, .max = 3510000 },
  273. .n = { .min = 1, .max = 3 },
  274. .m = { .min = 79, .max = 118 },
  275. .m1 = { .min = 12, .max = 22 },
  276. .m2 = { .min = 5, .max = 9 },
  277. .p = { .min = 28, .max = 112 },
  278. .p1 = { .min = 2, .max = 8 },
  279. .p2 = { .dot_limit = 225000,
  280. .p2_slow = 14, .p2_fast = 14 },
  281. .find_pll = intel_g4x_find_best_PLL,
  282. };
  283. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  284. .dot = { .min = 25000, .max = 350000 },
  285. .vco = { .min = 1760000, .max = 3510000 },
  286. .n = { .min = 1, .max = 3 },
  287. .m = { .min = 79, .max = 127 },
  288. .m1 = { .min = 12, .max = 22 },
  289. .m2 = { .min = 5, .max = 9 },
  290. .p = { .min = 14, .max = 56 },
  291. .p1 = { .min = 2, .max = 8 },
  292. .p2 = { .dot_limit = 225000,
  293. .p2_slow = 7, .p2_fast = 7 },
  294. .find_pll = intel_g4x_find_best_PLL,
  295. };
  296. /* LVDS 100mhz refclk limits. */
  297. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  298. .dot = { .min = 25000, .max = 350000 },
  299. .vco = { .min = 1760000, .max = 3510000 },
  300. .n = { .min = 1, .max = 2 },
  301. .m = { .min = 79, .max = 126 },
  302. .m1 = { .min = 12, .max = 22 },
  303. .m2 = { .min = 5, .max = 9 },
  304. .p = { .min = 28, .max = 112 },
  305. .p1 = { .min = 2, .max = 8 },
  306. .p2 = { .dot_limit = 225000,
  307. .p2_slow = 14, .p2_fast = 14 },
  308. .find_pll = intel_g4x_find_best_PLL,
  309. };
  310. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  311. .dot = { .min = 25000, .max = 350000 },
  312. .vco = { .min = 1760000, .max = 3510000 },
  313. .n = { .min = 1, .max = 3 },
  314. .m = { .min = 79, .max = 126 },
  315. .m1 = { .min = 12, .max = 22 },
  316. .m2 = { .min = 5, .max = 9 },
  317. .p = { .min = 14, .max = 42 },
  318. .p1 = { .min = 2, .max = 6 },
  319. .p2 = { .dot_limit = 225000,
  320. .p2_slow = 7, .p2_fast = 7 },
  321. .find_pll = intel_g4x_find_best_PLL,
  322. };
  323. static const intel_limit_t intel_limits_ironlake_display_port = {
  324. .dot = { .min = 25000, .max = 350000 },
  325. .vco = { .min = 1760000, .max = 3510000},
  326. .n = { .min = 1, .max = 2 },
  327. .m = { .min = 81, .max = 90 },
  328. .m1 = { .min = 12, .max = 22 },
  329. .m2 = { .min = 5, .max = 9 },
  330. .p = { .min = 10, .max = 20 },
  331. .p1 = { .min = 1, .max = 2},
  332. .p2 = { .dot_limit = 0,
  333. .p2_slow = 10, .p2_fast = 10 },
  334. .find_pll = intel_find_pll_ironlake_dp,
  335. };
  336. static const intel_limit_t intel_limits_vlv_dac = {
  337. .dot = { .min = 25000, .max = 270000 },
  338. .vco = { .min = 4000000, .max = 6000000 },
  339. .n = { .min = 1, .max = 7 },
  340. .m = { .min = 22, .max = 450 }, /* guess */
  341. .m1 = { .min = 2, .max = 3 },
  342. .m2 = { .min = 11, .max = 156 },
  343. .p = { .min = 10, .max = 30 },
  344. .p1 = { .min = 2, .max = 3 },
  345. .p2 = { .dot_limit = 270000,
  346. .p2_slow = 2, .p2_fast = 20 },
  347. .find_pll = intel_vlv_find_best_pll,
  348. };
  349. static const intel_limit_t intel_limits_vlv_hdmi = {
  350. .dot = { .min = 20000, .max = 165000 },
  351. .vco = { .min = 5994000, .max = 4000000 },
  352. .n = { .min = 1, .max = 7 },
  353. .m = { .min = 60, .max = 300 }, /* guess */
  354. .m1 = { .min = 2, .max = 3 },
  355. .m2 = { .min = 11, .max = 156 },
  356. .p = { .min = 10, .max = 30 },
  357. .p1 = { .min = 2, .max = 3 },
  358. .p2 = { .dot_limit = 270000,
  359. .p2_slow = 2, .p2_fast = 20 },
  360. .find_pll = intel_vlv_find_best_pll,
  361. };
  362. static const intel_limit_t intel_limits_vlv_dp = {
  363. .dot = { .min = 162000, .max = 270000 },
  364. .vco = { .min = 5994000, .max = 4000000 },
  365. .n = { .min = 1, .max = 7 },
  366. .m = { .min = 60, .max = 300 }, /* guess */
  367. .m1 = { .min = 2, .max = 3 },
  368. .m2 = { .min = 11, .max = 156 },
  369. .p = { .min = 10, .max = 30 },
  370. .p1 = { .min = 2, .max = 3 },
  371. .p2 = { .dot_limit = 270000,
  372. .p2_slow = 2, .p2_fast = 20 },
  373. .find_pll = intel_vlv_find_best_pll,
  374. };
  375. u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
  376. {
  377. unsigned long flags;
  378. u32 val = 0;
  379. spin_lock_irqsave(&dev_priv->dpio_lock, flags);
  380. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
  381. DRM_ERROR("DPIO idle wait timed out\n");
  382. goto out_unlock;
  383. }
  384. I915_WRITE(DPIO_REG, reg);
  385. I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
  386. DPIO_BYTE);
  387. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
  388. DRM_ERROR("DPIO read wait timed out\n");
  389. goto out_unlock;
  390. }
  391. val = I915_READ(DPIO_DATA);
  392. out_unlock:
  393. spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
  394. return val;
  395. }
  396. static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
  397. u32 val)
  398. {
  399. unsigned long flags;
  400. spin_lock_irqsave(&dev_priv->dpio_lock, flags);
  401. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
  402. DRM_ERROR("DPIO idle wait timed out\n");
  403. goto out_unlock;
  404. }
  405. I915_WRITE(DPIO_DATA, val);
  406. I915_WRITE(DPIO_REG, reg);
  407. I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
  408. DPIO_BYTE);
  409. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
  410. DRM_ERROR("DPIO write wait timed out\n");
  411. out_unlock:
  412. spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
  413. }
  414. static void vlv_init_dpio(struct drm_device *dev)
  415. {
  416. struct drm_i915_private *dev_priv = dev->dev_private;
  417. /* Reset the DPIO config */
  418. I915_WRITE(DPIO_CTL, 0);
  419. POSTING_READ(DPIO_CTL);
  420. I915_WRITE(DPIO_CTL, 1);
  421. POSTING_READ(DPIO_CTL);
  422. }
  423. static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
  424. {
  425. DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
  426. return 1;
  427. }
  428. static const struct dmi_system_id intel_dual_link_lvds[] = {
  429. {
  430. .callback = intel_dual_link_lvds_callback,
  431. .ident = "Apple MacBook Pro (Core i5/i7 Series)",
  432. .matches = {
  433. DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
  434. DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
  435. },
  436. },
  437. { } /* terminating entry */
  438. };
  439. static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
  440. unsigned int reg)
  441. {
  442. unsigned int val;
  443. /* use the module option value if specified */
  444. if (i915_lvds_channel_mode > 0)
  445. return i915_lvds_channel_mode == 2;
  446. if (dmi_check_system(intel_dual_link_lvds))
  447. return true;
  448. if (dev_priv->lvds_val)
  449. val = dev_priv->lvds_val;
  450. else {
  451. /* BIOS should set the proper LVDS register value at boot, but
  452. * in reality, it doesn't set the value when the lid is closed;
  453. * we need to check "the value to be set" in VBT when LVDS
  454. * register is uninitialized.
  455. */
  456. val = I915_READ(reg);
  457. if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
  458. val = dev_priv->bios_lvds_val;
  459. dev_priv->lvds_val = val;
  460. }
  461. return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
  462. }
  463. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  464. int refclk)
  465. {
  466. struct drm_device *dev = crtc->dev;
  467. struct drm_i915_private *dev_priv = dev->dev_private;
  468. const intel_limit_t *limit;
  469. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  470. if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
  471. /* LVDS dual channel */
  472. if (refclk == 100000)
  473. limit = &intel_limits_ironlake_dual_lvds_100m;
  474. else
  475. limit = &intel_limits_ironlake_dual_lvds;
  476. } else {
  477. if (refclk == 100000)
  478. limit = &intel_limits_ironlake_single_lvds_100m;
  479. else
  480. limit = &intel_limits_ironlake_single_lvds;
  481. }
  482. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  483. HAS_eDP)
  484. limit = &intel_limits_ironlake_display_port;
  485. else
  486. limit = &intel_limits_ironlake_dac;
  487. return limit;
  488. }
  489. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  490. {
  491. struct drm_device *dev = crtc->dev;
  492. struct drm_i915_private *dev_priv = dev->dev_private;
  493. const intel_limit_t *limit;
  494. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  495. if (is_dual_link_lvds(dev_priv, LVDS))
  496. /* LVDS with dual channel */
  497. limit = &intel_limits_g4x_dual_channel_lvds;
  498. else
  499. /* LVDS with dual channel */
  500. limit = &intel_limits_g4x_single_channel_lvds;
  501. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  502. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  503. limit = &intel_limits_g4x_hdmi;
  504. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  505. limit = &intel_limits_g4x_sdvo;
  506. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  507. limit = &intel_limits_g4x_display_port;
  508. } else /* The option is for other outputs */
  509. limit = &intel_limits_i9xx_sdvo;
  510. return limit;
  511. }
  512. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  513. {
  514. struct drm_device *dev = crtc->dev;
  515. const intel_limit_t *limit;
  516. if (HAS_PCH_SPLIT(dev))
  517. limit = intel_ironlake_limit(crtc, refclk);
  518. else if (IS_G4X(dev)) {
  519. limit = intel_g4x_limit(crtc);
  520. } else if (IS_PINEVIEW(dev)) {
  521. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  522. limit = &intel_limits_pineview_lvds;
  523. else
  524. limit = &intel_limits_pineview_sdvo;
  525. } else if (IS_VALLEYVIEW(dev)) {
  526. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
  527. limit = &intel_limits_vlv_dac;
  528. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
  529. limit = &intel_limits_vlv_hdmi;
  530. else
  531. limit = &intel_limits_vlv_dp;
  532. } else if (!IS_GEN2(dev)) {
  533. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  534. limit = &intel_limits_i9xx_lvds;
  535. else
  536. limit = &intel_limits_i9xx_sdvo;
  537. } else {
  538. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  539. limit = &intel_limits_i8xx_lvds;
  540. else
  541. limit = &intel_limits_i8xx_dvo;
  542. }
  543. return limit;
  544. }
  545. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  546. static void pineview_clock(int refclk, intel_clock_t *clock)
  547. {
  548. clock->m = clock->m2 + 2;
  549. clock->p = clock->p1 * clock->p2;
  550. clock->vco = refclk * clock->m / clock->n;
  551. clock->dot = clock->vco / clock->p;
  552. }
  553. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  554. {
  555. if (IS_PINEVIEW(dev)) {
  556. pineview_clock(refclk, clock);
  557. return;
  558. }
  559. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  560. clock->p = clock->p1 * clock->p2;
  561. clock->vco = refclk * clock->m / (clock->n + 2);
  562. clock->dot = clock->vco / clock->p;
  563. }
  564. /**
  565. * Returns whether any output on the specified pipe is of the specified type
  566. */
  567. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  568. {
  569. struct drm_device *dev = crtc->dev;
  570. struct intel_encoder *encoder;
  571. for_each_encoder_on_crtc(dev, crtc, encoder)
  572. if (encoder->type == type)
  573. return true;
  574. return false;
  575. }
  576. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  577. /**
  578. * Returns whether the given set of divisors are valid for a given refclk with
  579. * the given connectors.
  580. */
  581. static bool intel_PLL_is_valid(struct drm_device *dev,
  582. const intel_limit_t *limit,
  583. const intel_clock_t *clock)
  584. {
  585. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  586. INTELPllInvalid("p1 out of range\n");
  587. if (clock->p < limit->p.min || limit->p.max < clock->p)
  588. INTELPllInvalid("p out of range\n");
  589. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  590. INTELPllInvalid("m2 out of range\n");
  591. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  592. INTELPllInvalid("m1 out of range\n");
  593. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  594. INTELPllInvalid("m1 <= m2\n");
  595. if (clock->m < limit->m.min || limit->m.max < clock->m)
  596. INTELPllInvalid("m out of range\n");
  597. if (clock->n < limit->n.min || limit->n.max < clock->n)
  598. INTELPllInvalid("n out of range\n");
  599. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  600. INTELPllInvalid("vco out of range\n");
  601. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  602. * connector, etc., rather than just a single range.
  603. */
  604. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  605. INTELPllInvalid("dot out of range\n");
  606. return true;
  607. }
  608. static bool
  609. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  610. int target, int refclk, intel_clock_t *match_clock,
  611. intel_clock_t *best_clock)
  612. {
  613. struct drm_device *dev = crtc->dev;
  614. struct drm_i915_private *dev_priv = dev->dev_private;
  615. intel_clock_t clock;
  616. int err = target;
  617. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  618. (I915_READ(LVDS)) != 0) {
  619. /*
  620. * For LVDS, if the panel is on, just rely on its current
  621. * settings for dual-channel. We haven't figured out how to
  622. * reliably set up different single/dual channel state, if we
  623. * even can.
  624. */
  625. if (is_dual_link_lvds(dev_priv, LVDS))
  626. clock.p2 = limit->p2.p2_fast;
  627. else
  628. clock.p2 = limit->p2.p2_slow;
  629. } else {
  630. if (target < limit->p2.dot_limit)
  631. clock.p2 = limit->p2.p2_slow;
  632. else
  633. clock.p2 = limit->p2.p2_fast;
  634. }
  635. memset(best_clock, 0, sizeof(*best_clock));
  636. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  637. clock.m1++) {
  638. for (clock.m2 = limit->m2.min;
  639. clock.m2 <= limit->m2.max; clock.m2++) {
  640. /* m1 is always 0 in Pineview */
  641. if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
  642. break;
  643. for (clock.n = limit->n.min;
  644. clock.n <= limit->n.max; clock.n++) {
  645. for (clock.p1 = limit->p1.min;
  646. clock.p1 <= limit->p1.max; clock.p1++) {
  647. int this_err;
  648. intel_clock(dev, refclk, &clock);
  649. if (!intel_PLL_is_valid(dev, limit,
  650. &clock))
  651. continue;
  652. if (match_clock &&
  653. clock.p != match_clock->p)
  654. continue;
  655. this_err = abs(clock.dot - target);
  656. if (this_err < err) {
  657. *best_clock = clock;
  658. err = this_err;
  659. }
  660. }
  661. }
  662. }
  663. }
  664. return (err != target);
  665. }
  666. static bool
  667. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  668. int target, int refclk, intel_clock_t *match_clock,
  669. intel_clock_t *best_clock)
  670. {
  671. struct drm_device *dev = crtc->dev;
  672. struct drm_i915_private *dev_priv = dev->dev_private;
  673. intel_clock_t clock;
  674. int max_n;
  675. bool found;
  676. /* approximately equals target * 0.00585 */
  677. int err_most = (target >> 8) + (target >> 9);
  678. found = false;
  679. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  680. int lvds_reg;
  681. if (HAS_PCH_SPLIT(dev))
  682. lvds_reg = PCH_LVDS;
  683. else
  684. lvds_reg = LVDS;
  685. if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
  686. LVDS_CLKB_POWER_UP)
  687. clock.p2 = limit->p2.p2_fast;
  688. else
  689. clock.p2 = limit->p2.p2_slow;
  690. } else {
  691. if (target < limit->p2.dot_limit)
  692. clock.p2 = limit->p2.p2_slow;
  693. else
  694. clock.p2 = limit->p2.p2_fast;
  695. }
  696. memset(best_clock, 0, sizeof(*best_clock));
  697. max_n = limit->n.max;
  698. /* based on hardware requirement, prefer smaller n to precision */
  699. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  700. /* based on hardware requirement, prefere larger m1,m2 */
  701. for (clock.m1 = limit->m1.max;
  702. clock.m1 >= limit->m1.min; clock.m1--) {
  703. for (clock.m2 = limit->m2.max;
  704. clock.m2 >= limit->m2.min; clock.m2--) {
  705. for (clock.p1 = limit->p1.max;
  706. clock.p1 >= limit->p1.min; clock.p1--) {
  707. int this_err;
  708. intel_clock(dev, refclk, &clock);
  709. if (!intel_PLL_is_valid(dev, limit,
  710. &clock))
  711. continue;
  712. if (match_clock &&
  713. clock.p != match_clock->p)
  714. continue;
  715. this_err = abs(clock.dot - target);
  716. if (this_err < err_most) {
  717. *best_clock = clock;
  718. err_most = this_err;
  719. max_n = clock.n;
  720. found = true;
  721. }
  722. }
  723. }
  724. }
  725. }
  726. return found;
  727. }
  728. static bool
  729. intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  730. int target, int refclk, intel_clock_t *match_clock,
  731. intel_clock_t *best_clock)
  732. {
  733. struct drm_device *dev = crtc->dev;
  734. intel_clock_t clock;
  735. if (target < 200000) {
  736. clock.n = 1;
  737. clock.p1 = 2;
  738. clock.p2 = 10;
  739. clock.m1 = 12;
  740. clock.m2 = 9;
  741. } else {
  742. clock.n = 2;
  743. clock.p1 = 1;
  744. clock.p2 = 10;
  745. clock.m1 = 14;
  746. clock.m2 = 8;
  747. }
  748. intel_clock(dev, refclk, &clock);
  749. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  750. return true;
  751. }
  752. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  753. static bool
  754. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  755. int target, int refclk, intel_clock_t *match_clock,
  756. intel_clock_t *best_clock)
  757. {
  758. intel_clock_t clock;
  759. if (target < 200000) {
  760. clock.p1 = 2;
  761. clock.p2 = 10;
  762. clock.n = 2;
  763. clock.m1 = 23;
  764. clock.m2 = 8;
  765. } else {
  766. clock.p1 = 1;
  767. clock.p2 = 10;
  768. clock.n = 1;
  769. clock.m1 = 14;
  770. clock.m2 = 2;
  771. }
  772. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  773. clock.p = (clock.p1 * clock.p2);
  774. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  775. clock.vco = 0;
  776. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  777. return true;
  778. }
  779. static bool
  780. intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
  781. int target, int refclk, intel_clock_t *match_clock,
  782. intel_clock_t *best_clock)
  783. {
  784. u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
  785. u32 m, n, fastclk;
  786. u32 updrate, minupdate, fracbits, p;
  787. unsigned long bestppm, ppm, absppm;
  788. int dotclk, flag;
  789. flag = 0;
  790. dotclk = target * 1000;
  791. bestppm = 1000000;
  792. ppm = absppm = 0;
  793. fastclk = dotclk / (2*100);
  794. updrate = 0;
  795. minupdate = 19200;
  796. fracbits = 1;
  797. n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
  798. bestm1 = bestm2 = bestp1 = bestp2 = 0;
  799. /* based on hardware requirement, prefer smaller n to precision */
  800. for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
  801. updrate = refclk / n;
  802. for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
  803. for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
  804. if (p2 > 10)
  805. p2 = p2 - 1;
  806. p = p1 * p2;
  807. /* based on hardware requirement, prefer bigger m1,m2 values */
  808. for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
  809. m2 = (((2*(fastclk * p * n / m1 )) +
  810. refclk) / (2*refclk));
  811. m = m1 * m2;
  812. vco = updrate * m;
  813. if (vco >= limit->vco.min && vco < limit->vco.max) {
  814. ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
  815. absppm = (ppm > 0) ? ppm : (-ppm);
  816. if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
  817. bestppm = 0;
  818. flag = 1;
  819. }
  820. if (absppm < bestppm - 10) {
  821. bestppm = absppm;
  822. flag = 1;
  823. }
  824. if (flag) {
  825. bestn = n;
  826. bestm1 = m1;
  827. bestm2 = m2;
  828. bestp1 = p1;
  829. bestp2 = p2;
  830. flag = 0;
  831. }
  832. }
  833. }
  834. }
  835. }
  836. }
  837. best_clock->n = bestn;
  838. best_clock->m1 = bestm1;
  839. best_clock->m2 = bestm2;
  840. best_clock->p1 = bestp1;
  841. best_clock->p2 = bestp2;
  842. return true;
  843. }
  844. static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
  845. {
  846. struct drm_i915_private *dev_priv = dev->dev_private;
  847. u32 frame, frame_reg = PIPEFRAME(pipe);
  848. frame = I915_READ(frame_reg);
  849. if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
  850. DRM_DEBUG_KMS("vblank wait timed out\n");
  851. }
  852. /**
  853. * intel_wait_for_vblank - wait for vblank on a given pipe
  854. * @dev: drm device
  855. * @pipe: pipe to wait for
  856. *
  857. * Wait for vblank to occur on a given pipe. Needed for various bits of
  858. * mode setting code.
  859. */
  860. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  861. {
  862. struct drm_i915_private *dev_priv = dev->dev_private;
  863. int pipestat_reg = PIPESTAT(pipe);
  864. if (INTEL_INFO(dev)->gen >= 5) {
  865. ironlake_wait_for_vblank(dev, pipe);
  866. return;
  867. }
  868. /* Clear existing vblank status. Note this will clear any other
  869. * sticky status fields as well.
  870. *
  871. * This races with i915_driver_irq_handler() with the result
  872. * that either function could miss a vblank event. Here it is not
  873. * fatal, as we will either wait upon the next vblank interrupt or
  874. * timeout. Generally speaking intel_wait_for_vblank() is only
  875. * called during modeset at which time the GPU should be idle and
  876. * should *not* be performing page flips and thus not waiting on
  877. * vblanks...
  878. * Currently, the result of us stealing a vblank from the irq
  879. * handler is that a single frame will be skipped during swapbuffers.
  880. */
  881. I915_WRITE(pipestat_reg,
  882. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  883. /* Wait for vblank interrupt bit to set */
  884. if (wait_for(I915_READ(pipestat_reg) &
  885. PIPE_VBLANK_INTERRUPT_STATUS,
  886. 50))
  887. DRM_DEBUG_KMS("vblank wait timed out\n");
  888. }
  889. /*
  890. * intel_wait_for_pipe_off - wait for pipe to turn off
  891. * @dev: drm device
  892. * @pipe: pipe to wait for
  893. *
  894. * After disabling a pipe, we can't wait for vblank in the usual way,
  895. * spinning on the vblank interrupt status bit, since we won't actually
  896. * see an interrupt when the pipe is disabled.
  897. *
  898. * On Gen4 and above:
  899. * wait for the pipe register state bit to turn off
  900. *
  901. * Otherwise:
  902. * wait for the display line value to settle (it usually
  903. * ends up stopping at the start of the next frame).
  904. *
  905. */
  906. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  907. {
  908. struct drm_i915_private *dev_priv = dev->dev_private;
  909. if (INTEL_INFO(dev)->gen >= 4) {
  910. int reg = PIPECONF(pipe);
  911. /* Wait for the Pipe State to go off */
  912. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  913. 100))
  914. DRM_DEBUG_KMS("pipe_off wait timed out\n");
  915. } else {
  916. u32 last_line, line_mask;
  917. int reg = PIPEDSL(pipe);
  918. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  919. if (IS_GEN2(dev))
  920. line_mask = DSL_LINEMASK_GEN2;
  921. else
  922. line_mask = DSL_LINEMASK_GEN3;
  923. /* Wait for the display line to settle */
  924. do {
  925. last_line = I915_READ(reg) & line_mask;
  926. mdelay(5);
  927. } while (((I915_READ(reg) & line_mask) != last_line) &&
  928. time_after(timeout, jiffies));
  929. if (time_after(jiffies, timeout))
  930. DRM_DEBUG_KMS("pipe_off wait timed out\n");
  931. }
  932. }
  933. static const char *state_string(bool enabled)
  934. {
  935. return enabled ? "on" : "off";
  936. }
  937. /* Only for pre-ILK configs */
  938. static void assert_pll(struct drm_i915_private *dev_priv,
  939. enum pipe pipe, bool state)
  940. {
  941. int reg;
  942. u32 val;
  943. bool cur_state;
  944. reg = DPLL(pipe);
  945. val = I915_READ(reg);
  946. cur_state = !!(val & DPLL_VCO_ENABLE);
  947. WARN(cur_state != state,
  948. "PLL state assertion failure (expected %s, current %s)\n",
  949. state_string(state), state_string(cur_state));
  950. }
  951. #define assert_pll_enabled(d, p) assert_pll(d, p, true)
  952. #define assert_pll_disabled(d, p) assert_pll(d, p, false)
  953. /* For ILK+ */
  954. static void assert_pch_pll(struct drm_i915_private *dev_priv,
  955. struct intel_pch_pll *pll,
  956. struct intel_crtc *crtc,
  957. bool state)
  958. {
  959. u32 val;
  960. bool cur_state;
  961. if (HAS_PCH_LPT(dev_priv->dev)) {
  962. DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
  963. return;
  964. }
  965. if (WARN (!pll,
  966. "asserting PCH PLL %s with no PLL\n", state_string(state)))
  967. return;
  968. val = I915_READ(pll->pll_reg);
  969. cur_state = !!(val & DPLL_VCO_ENABLE);
  970. WARN(cur_state != state,
  971. "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
  972. pll->pll_reg, state_string(state), state_string(cur_state), val);
  973. /* Make sure the selected PLL is correctly attached to the transcoder */
  974. if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
  975. u32 pch_dpll;
  976. pch_dpll = I915_READ(PCH_DPLL_SEL);
  977. cur_state = pll->pll_reg == _PCH_DPLL_B;
  978. if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
  979. "PLL[%d] not attached to this transcoder %d: %08x\n",
  980. cur_state, crtc->pipe, pch_dpll)) {
  981. cur_state = !!(val >> (4*crtc->pipe + 3));
  982. WARN(cur_state != state,
  983. "PLL[%d] not %s on this transcoder %d: %08x\n",
  984. pll->pll_reg == _PCH_DPLL_B,
  985. state_string(state),
  986. crtc->pipe,
  987. val);
  988. }
  989. }
  990. }
  991. #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
  992. #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
  993. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  994. enum pipe pipe, bool state)
  995. {
  996. int reg;
  997. u32 val;
  998. bool cur_state;
  999. if (IS_HASWELL(dev_priv->dev)) {
  1000. /* On Haswell, DDI is used instead of FDI_TX_CTL */
  1001. reg = DDI_FUNC_CTL(pipe);
  1002. val = I915_READ(reg);
  1003. cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
  1004. } else {
  1005. reg = FDI_TX_CTL(pipe);
  1006. val = I915_READ(reg);
  1007. cur_state = !!(val & FDI_TX_ENABLE);
  1008. }
  1009. WARN(cur_state != state,
  1010. "FDI TX state assertion failure (expected %s, current %s)\n",
  1011. state_string(state), state_string(cur_state));
  1012. }
  1013. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  1014. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  1015. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  1016. enum pipe pipe, bool state)
  1017. {
  1018. int reg;
  1019. u32 val;
  1020. bool cur_state;
  1021. if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
  1022. DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
  1023. return;
  1024. } else {
  1025. reg = FDI_RX_CTL(pipe);
  1026. val = I915_READ(reg);
  1027. cur_state = !!(val & FDI_RX_ENABLE);
  1028. }
  1029. WARN(cur_state != state,
  1030. "FDI RX state assertion failure (expected %s, current %s)\n",
  1031. state_string(state), state_string(cur_state));
  1032. }
  1033. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  1034. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  1035. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  1036. enum pipe pipe)
  1037. {
  1038. int reg;
  1039. u32 val;
  1040. /* ILK FDI PLL is always enabled */
  1041. if (dev_priv->info->gen == 5)
  1042. return;
  1043. /* On Haswell, DDI ports are responsible for the FDI PLL setup */
  1044. if (IS_HASWELL(dev_priv->dev))
  1045. return;
  1046. reg = FDI_TX_CTL(pipe);
  1047. val = I915_READ(reg);
  1048. WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  1049. }
  1050. static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
  1051. enum pipe pipe)
  1052. {
  1053. int reg;
  1054. u32 val;
  1055. if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
  1056. DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
  1057. return;
  1058. }
  1059. reg = FDI_RX_CTL(pipe);
  1060. val = I915_READ(reg);
  1061. WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
  1062. }
  1063. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  1064. enum pipe pipe)
  1065. {
  1066. int pp_reg, lvds_reg;
  1067. u32 val;
  1068. enum pipe panel_pipe = PIPE_A;
  1069. bool locked = true;
  1070. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  1071. pp_reg = PCH_PP_CONTROL;
  1072. lvds_reg = PCH_LVDS;
  1073. } else {
  1074. pp_reg = PP_CONTROL;
  1075. lvds_reg = LVDS;
  1076. }
  1077. val = I915_READ(pp_reg);
  1078. if (!(val & PANEL_POWER_ON) ||
  1079. ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  1080. locked = false;
  1081. if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  1082. panel_pipe = PIPE_B;
  1083. WARN(panel_pipe == pipe && locked,
  1084. "panel assertion failure, pipe %c regs locked\n",
  1085. pipe_name(pipe));
  1086. }
  1087. void assert_pipe(struct drm_i915_private *dev_priv,
  1088. enum pipe pipe, bool state)
  1089. {
  1090. int reg;
  1091. u32 val;
  1092. bool cur_state;
  1093. /* if we need the pipe A quirk it must be always on */
  1094. if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  1095. state = true;
  1096. reg = PIPECONF(pipe);
  1097. val = I915_READ(reg);
  1098. cur_state = !!(val & PIPECONF_ENABLE);
  1099. WARN(cur_state != state,
  1100. "pipe %c assertion failure (expected %s, current %s)\n",
  1101. pipe_name(pipe), state_string(state), state_string(cur_state));
  1102. }
  1103. static void assert_plane(struct drm_i915_private *dev_priv,
  1104. enum plane plane, bool state)
  1105. {
  1106. int reg;
  1107. u32 val;
  1108. bool cur_state;
  1109. reg = DSPCNTR(plane);
  1110. val = I915_READ(reg);
  1111. cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  1112. WARN(cur_state != state,
  1113. "plane %c assertion failure (expected %s, current %s)\n",
  1114. plane_name(plane), state_string(state), state_string(cur_state));
  1115. }
  1116. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  1117. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  1118. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  1119. enum pipe pipe)
  1120. {
  1121. int reg, i;
  1122. u32 val;
  1123. int cur_pipe;
  1124. /* Planes are fixed to pipes on ILK+ */
  1125. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  1126. reg = DSPCNTR(pipe);
  1127. val = I915_READ(reg);
  1128. WARN((val & DISPLAY_PLANE_ENABLE),
  1129. "plane %c assertion failure, should be disabled but not\n",
  1130. plane_name(pipe));
  1131. return;
  1132. }
  1133. /* Need to check both planes against the pipe */
  1134. for (i = 0; i < 2; i++) {
  1135. reg = DSPCNTR(i);
  1136. val = I915_READ(reg);
  1137. cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  1138. DISPPLANE_SEL_PIPE_SHIFT;
  1139. WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  1140. "plane %c assertion failure, should be off on pipe %c but is still active\n",
  1141. plane_name(i), pipe_name(pipe));
  1142. }
  1143. }
  1144. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  1145. {
  1146. u32 val;
  1147. bool enabled;
  1148. if (HAS_PCH_LPT(dev_priv->dev)) {
  1149. DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
  1150. return;
  1151. }
  1152. val = I915_READ(PCH_DREF_CONTROL);
  1153. enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  1154. DREF_SUPERSPREAD_SOURCE_MASK));
  1155. WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  1156. }
  1157. static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
  1158. enum pipe pipe)
  1159. {
  1160. int reg;
  1161. u32 val;
  1162. bool enabled;
  1163. reg = TRANSCONF(pipe);
  1164. val = I915_READ(reg);
  1165. enabled = !!(val & TRANS_ENABLE);
  1166. WARN(enabled,
  1167. "transcoder assertion failed, should be off on pipe %c but is still active\n",
  1168. pipe_name(pipe));
  1169. }
  1170. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  1171. enum pipe pipe, u32 port_sel, u32 val)
  1172. {
  1173. if ((val & DP_PORT_EN) == 0)
  1174. return false;
  1175. if (HAS_PCH_CPT(dev_priv->dev)) {
  1176. u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  1177. u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  1178. if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  1179. return false;
  1180. } else {
  1181. if ((val & DP_PIPE_MASK) != (pipe << 30))
  1182. return false;
  1183. }
  1184. return true;
  1185. }
  1186. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  1187. enum pipe pipe, u32 val)
  1188. {
  1189. if ((val & PORT_ENABLE) == 0)
  1190. return false;
  1191. if (HAS_PCH_CPT(dev_priv->dev)) {
  1192. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1193. return false;
  1194. } else {
  1195. if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
  1196. return false;
  1197. }
  1198. return true;
  1199. }
  1200. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  1201. enum pipe pipe, u32 val)
  1202. {
  1203. if ((val & LVDS_PORT_EN) == 0)
  1204. return false;
  1205. if (HAS_PCH_CPT(dev_priv->dev)) {
  1206. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1207. return false;
  1208. } else {
  1209. if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  1210. return false;
  1211. }
  1212. return true;
  1213. }
  1214. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  1215. enum pipe pipe, u32 val)
  1216. {
  1217. if ((val & ADPA_DAC_ENABLE) == 0)
  1218. return false;
  1219. if (HAS_PCH_CPT(dev_priv->dev)) {
  1220. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1221. return false;
  1222. } else {
  1223. if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  1224. return false;
  1225. }
  1226. return true;
  1227. }
  1228. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  1229. enum pipe pipe, int reg, u32 port_sel)
  1230. {
  1231. u32 val = I915_READ(reg);
  1232. WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  1233. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  1234. reg, pipe_name(pipe));
  1235. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
  1236. "IBX PCH dp port still using transcoder B\n");
  1237. }
  1238. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  1239. enum pipe pipe, int reg)
  1240. {
  1241. u32 val = I915_READ(reg);
  1242. WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
  1243. "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  1244. reg, pipe_name(pipe));
  1245. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
  1246. "IBX PCH hdmi port still using transcoder B\n");
  1247. }
  1248. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  1249. enum pipe pipe)
  1250. {
  1251. int reg;
  1252. u32 val;
  1253. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1254. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1255. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1256. reg = PCH_ADPA;
  1257. val = I915_READ(reg);
  1258. WARN(adpa_pipe_enabled(dev_priv, pipe, val),
  1259. "PCH VGA enabled on transcoder %c, should be disabled\n",
  1260. pipe_name(pipe));
  1261. reg = PCH_LVDS;
  1262. val = I915_READ(reg);
  1263. WARN(lvds_pipe_enabled(dev_priv, pipe, val),
  1264. "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1265. pipe_name(pipe));
  1266. assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
  1267. assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
  1268. assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
  1269. }
  1270. /**
  1271. * intel_enable_pll - enable a PLL
  1272. * @dev_priv: i915 private structure
  1273. * @pipe: pipe PLL to enable
  1274. *
  1275. * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
  1276. * make sure the PLL reg is writable first though, since the panel write
  1277. * protect mechanism may be enabled.
  1278. *
  1279. * Note! This is for pre-ILK only.
  1280. *
  1281. * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
  1282. */
  1283. static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1284. {
  1285. int reg;
  1286. u32 val;
  1287. /* No really, not for ILK+ */
  1288. BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
  1289. /* PLL is protected by panel, make sure we can write it */
  1290. if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  1291. assert_panel_unlocked(dev_priv, pipe);
  1292. reg = DPLL(pipe);
  1293. val = I915_READ(reg);
  1294. val |= DPLL_VCO_ENABLE;
  1295. /* We do this three times for luck */
  1296. I915_WRITE(reg, val);
  1297. POSTING_READ(reg);
  1298. udelay(150); /* wait for warmup */
  1299. I915_WRITE(reg, val);
  1300. POSTING_READ(reg);
  1301. udelay(150); /* wait for warmup */
  1302. I915_WRITE(reg, val);
  1303. POSTING_READ(reg);
  1304. udelay(150); /* wait for warmup */
  1305. }
  1306. /**
  1307. * intel_disable_pll - disable a PLL
  1308. * @dev_priv: i915 private structure
  1309. * @pipe: pipe PLL to disable
  1310. *
  1311. * Disable the PLL for @pipe, making sure the pipe is off first.
  1312. *
  1313. * Note! This is for pre-ILK only.
  1314. */
  1315. static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1316. {
  1317. int reg;
  1318. u32 val;
  1319. /* Don't disable pipe A or pipe A PLLs if needed */
  1320. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1321. return;
  1322. /* Make sure the pipe isn't still relying on us */
  1323. assert_pipe_disabled(dev_priv, pipe);
  1324. reg = DPLL(pipe);
  1325. val = I915_READ(reg);
  1326. val &= ~DPLL_VCO_ENABLE;
  1327. I915_WRITE(reg, val);
  1328. POSTING_READ(reg);
  1329. }
  1330. /* SBI access */
  1331. static void
  1332. intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
  1333. {
  1334. unsigned long flags;
  1335. spin_lock_irqsave(&dev_priv->dpio_lock, flags);
  1336. if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
  1337. 100)) {
  1338. DRM_ERROR("timeout waiting for SBI to become ready\n");
  1339. goto out_unlock;
  1340. }
  1341. I915_WRITE(SBI_ADDR,
  1342. (reg << 16));
  1343. I915_WRITE(SBI_DATA,
  1344. value);
  1345. I915_WRITE(SBI_CTL_STAT,
  1346. SBI_BUSY |
  1347. SBI_CTL_OP_CRWR);
  1348. if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
  1349. 100)) {
  1350. DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
  1351. goto out_unlock;
  1352. }
  1353. out_unlock:
  1354. spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
  1355. }
  1356. static u32
  1357. intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
  1358. {
  1359. unsigned long flags;
  1360. u32 value = 0;
  1361. spin_lock_irqsave(&dev_priv->dpio_lock, flags);
  1362. if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
  1363. 100)) {
  1364. DRM_ERROR("timeout waiting for SBI to become ready\n");
  1365. goto out_unlock;
  1366. }
  1367. I915_WRITE(SBI_ADDR,
  1368. (reg << 16));
  1369. I915_WRITE(SBI_CTL_STAT,
  1370. SBI_BUSY |
  1371. SBI_CTL_OP_CRRD);
  1372. if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
  1373. 100)) {
  1374. DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
  1375. goto out_unlock;
  1376. }
  1377. value = I915_READ(SBI_DATA);
  1378. out_unlock:
  1379. spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
  1380. return value;
  1381. }
  1382. /**
  1383. * intel_enable_pch_pll - enable PCH PLL
  1384. * @dev_priv: i915 private structure
  1385. * @pipe: pipe PLL to enable
  1386. *
  1387. * The PCH PLL needs to be enabled before the PCH transcoder, since it
  1388. * drives the transcoder clock.
  1389. */
  1390. static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
  1391. {
  1392. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  1393. struct intel_pch_pll *pll;
  1394. int reg;
  1395. u32 val;
  1396. /* PCH PLLs only available on ILK, SNB and IVB */
  1397. BUG_ON(dev_priv->info->gen < 5);
  1398. pll = intel_crtc->pch_pll;
  1399. if (pll == NULL)
  1400. return;
  1401. if (WARN_ON(pll->refcount == 0))
  1402. return;
  1403. DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
  1404. pll->pll_reg, pll->active, pll->on,
  1405. intel_crtc->base.base.id);
  1406. /* PCH refclock must be enabled first */
  1407. assert_pch_refclk_enabled(dev_priv);
  1408. if (pll->active++ && pll->on) {
  1409. assert_pch_pll_enabled(dev_priv, pll, NULL);
  1410. return;
  1411. }
  1412. DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
  1413. reg = pll->pll_reg;
  1414. val = I915_READ(reg);
  1415. val |= DPLL_VCO_ENABLE;
  1416. I915_WRITE(reg, val);
  1417. POSTING_READ(reg);
  1418. udelay(200);
  1419. pll->on = true;
  1420. }
  1421. static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
  1422. {
  1423. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  1424. struct intel_pch_pll *pll = intel_crtc->pch_pll;
  1425. int reg;
  1426. u32 val;
  1427. /* PCH only available on ILK+ */
  1428. BUG_ON(dev_priv->info->gen < 5);
  1429. if (pll == NULL)
  1430. return;
  1431. if (WARN_ON(pll->refcount == 0))
  1432. return;
  1433. DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
  1434. pll->pll_reg, pll->active, pll->on,
  1435. intel_crtc->base.base.id);
  1436. if (WARN_ON(pll->active == 0)) {
  1437. assert_pch_pll_disabled(dev_priv, pll, NULL);
  1438. return;
  1439. }
  1440. if (--pll->active) {
  1441. assert_pch_pll_enabled(dev_priv, pll, NULL);
  1442. return;
  1443. }
  1444. DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
  1445. /* Make sure transcoder isn't still depending on us */
  1446. assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
  1447. reg = pll->pll_reg;
  1448. val = I915_READ(reg);
  1449. val &= ~DPLL_VCO_ENABLE;
  1450. I915_WRITE(reg, val);
  1451. POSTING_READ(reg);
  1452. udelay(200);
  1453. pll->on = false;
  1454. }
  1455. static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
  1456. enum pipe pipe)
  1457. {
  1458. int reg;
  1459. u32 val, pipeconf_val;
  1460. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1461. /* PCH only available on ILK+ */
  1462. BUG_ON(dev_priv->info->gen < 5);
  1463. /* Make sure PCH DPLL is enabled */
  1464. assert_pch_pll_enabled(dev_priv,
  1465. to_intel_crtc(crtc)->pch_pll,
  1466. to_intel_crtc(crtc));
  1467. /* FDI must be feeding us bits for PCH ports */
  1468. assert_fdi_tx_enabled(dev_priv, pipe);
  1469. assert_fdi_rx_enabled(dev_priv, pipe);
  1470. if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
  1471. DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
  1472. return;
  1473. }
  1474. reg = TRANSCONF(pipe);
  1475. val = I915_READ(reg);
  1476. pipeconf_val = I915_READ(PIPECONF(pipe));
  1477. if (HAS_PCH_IBX(dev_priv->dev)) {
  1478. /*
  1479. * make the BPC in transcoder be consistent with
  1480. * that in pipeconf reg.
  1481. */
  1482. val &= ~PIPE_BPC_MASK;
  1483. val |= pipeconf_val & PIPE_BPC_MASK;
  1484. }
  1485. val &= ~TRANS_INTERLACE_MASK;
  1486. if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  1487. if (HAS_PCH_IBX(dev_priv->dev) &&
  1488. intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
  1489. val |= TRANS_LEGACY_INTERLACED_ILK;
  1490. else
  1491. val |= TRANS_INTERLACED;
  1492. else
  1493. val |= TRANS_PROGRESSIVE;
  1494. I915_WRITE(reg, val | TRANS_ENABLE);
  1495. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1496. DRM_ERROR("failed to enable transcoder %d\n", pipe);
  1497. }
  1498. static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
  1499. enum pipe pipe)
  1500. {
  1501. int reg;
  1502. u32 val;
  1503. /* FDI relies on the transcoder */
  1504. assert_fdi_tx_disabled(dev_priv, pipe);
  1505. assert_fdi_rx_disabled(dev_priv, pipe);
  1506. /* Ports must be off as well */
  1507. assert_pch_ports_disabled(dev_priv, pipe);
  1508. reg = TRANSCONF(pipe);
  1509. val = I915_READ(reg);
  1510. val &= ~TRANS_ENABLE;
  1511. I915_WRITE(reg, val);
  1512. /* wait for PCH transcoder off, transcoder state */
  1513. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1514. DRM_ERROR("failed to disable transcoder %d\n", pipe);
  1515. }
  1516. /**
  1517. * intel_enable_pipe - enable a pipe, asserting requirements
  1518. * @dev_priv: i915 private structure
  1519. * @pipe: pipe to enable
  1520. * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1521. *
  1522. * Enable @pipe, making sure that various hardware specific requirements
  1523. * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1524. *
  1525. * @pipe should be %PIPE_A or %PIPE_B.
  1526. *
  1527. * Will wait until the pipe is actually running (i.e. first vblank) before
  1528. * returning.
  1529. */
  1530. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1531. bool pch_port)
  1532. {
  1533. int reg;
  1534. u32 val;
  1535. /*
  1536. * A pipe without a PLL won't actually be able to drive bits from
  1537. * a plane. On ILK+ the pipe PLLs are integrated, so we don't
  1538. * need the check.
  1539. */
  1540. if (!HAS_PCH_SPLIT(dev_priv->dev))
  1541. assert_pll_enabled(dev_priv, pipe);
  1542. else {
  1543. if (pch_port) {
  1544. /* if driving the PCH, we need FDI enabled */
  1545. assert_fdi_rx_pll_enabled(dev_priv, pipe);
  1546. assert_fdi_tx_pll_enabled(dev_priv, pipe);
  1547. }
  1548. /* FIXME: assert CPU port conditions for SNB+ */
  1549. }
  1550. reg = PIPECONF(pipe);
  1551. val = I915_READ(reg);
  1552. if (val & PIPECONF_ENABLE)
  1553. return;
  1554. I915_WRITE(reg, val | PIPECONF_ENABLE);
  1555. intel_wait_for_vblank(dev_priv->dev, pipe);
  1556. }
  1557. /**
  1558. * intel_disable_pipe - disable a pipe, asserting requirements
  1559. * @dev_priv: i915 private structure
  1560. * @pipe: pipe to disable
  1561. *
  1562. * Disable @pipe, making sure that various hardware specific requirements
  1563. * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1564. *
  1565. * @pipe should be %PIPE_A or %PIPE_B.
  1566. *
  1567. * Will wait until the pipe has shut down before returning.
  1568. */
  1569. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1570. enum pipe pipe)
  1571. {
  1572. int reg;
  1573. u32 val;
  1574. /*
  1575. * Make sure planes won't keep trying to pump pixels to us,
  1576. * or we might hang the display.
  1577. */
  1578. assert_planes_disabled(dev_priv, pipe);
  1579. /* Don't disable pipe A or pipe A PLLs if needed */
  1580. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1581. return;
  1582. reg = PIPECONF(pipe);
  1583. val = I915_READ(reg);
  1584. if ((val & PIPECONF_ENABLE) == 0)
  1585. return;
  1586. I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1587. intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1588. }
  1589. /*
  1590. * Plane regs are double buffered, going from enabled->disabled needs a
  1591. * trigger in order to latch. The display address reg provides this.
  1592. */
  1593. void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  1594. enum plane plane)
  1595. {
  1596. I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
  1597. I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
  1598. }
  1599. /**
  1600. * intel_enable_plane - enable a display plane on a given pipe
  1601. * @dev_priv: i915 private structure
  1602. * @plane: plane to enable
  1603. * @pipe: pipe being fed
  1604. *
  1605. * Enable @plane on @pipe, making sure that @pipe is running first.
  1606. */
  1607. static void intel_enable_plane(struct drm_i915_private *dev_priv,
  1608. enum plane plane, enum pipe pipe)
  1609. {
  1610. int reg;
  1611. u32 val;
  1612. /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1613. assert_pipe_enabled(dev_priv, pipe);
  1614. reg = DSPCNTR(plane);
  1615. val = I915_READ(reg);
  1616. if (val & DISPLAY_PLANE_ENABLE)
  1617. return;
  1618. I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1619. intel_flush_display_plane(dev_priv, plane);
  1620. intel_wait_for_vblank(dev_priv->dev, pipe);
  1621. }
  1622. /**
  1623. * intel_disable_plane - disable a display plane
  1624. * @dev_priv: i915 private structure
  1625. * @plane: plane to disable
  1626. * @pipe: pipe consuming the data
  1627. *
  1628. * Disable @plane; should be an independent operation.
  1629. */
  1630. static void intel_disable_plane(struct drm_i915_private *dev_priv,
  1631. enum plane plane, enum pipe pipe)
  1632. {
  1633. int reg;
  1634. u32 val;
  1635. reg = DSPCNTR(plane);
  1636. val = I915_READ(reg);
  1637. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1638. return;
  1639. I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1640. intel_flush_display_plane(dev_priv, plane);
  1641. intel_wait_for_vblank(dev_priv->dev, pipe);
  1642. }
  1643. static void disable_pch_dp(struct drm_i915_private *dev_priv,
  1644. enum pipe pipe, int reg, u32 port_sel)
  1645. {
  1646. u32 val = I915_READ(reg);
  1647. if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
  1648. DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
  1649. I915_WRITE(reg, val & ~DP_PORT_EN);
  1650. }
  1651. }
  1652. static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
  1653. enum pipe pipe, int reg)
  1654. {
  1655. u32 val = I915_READ(reg);
  1656. if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
  1657. DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
  1658. reg, pipe);
  1659. I915_WRITE(reg, val & ~PORT_ENABLE);
  1660. }
  1661. }
  1662. /* Disable any ports connected to this transcoder */
  1663. static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
  1664. enum pipe pipe)
  1665. {
  1666. u32 reg, val;
  1667. val = I915_READ(PCH_PP_CONTROL);
  1668. I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
  1669. disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1670. disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1671. disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1672. reg = PCH_ADPA;
  1673. val = I915_READ(reg);
  1674. if (adpa_pipe_enabled(dev_priv, pipe, val))
  1675. I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
  1676. reg = PCH_LVDS;
  1677. val = I915_READ(reg);
  1678. if (lvds_pipe_enabled(dev_priv, pipe, val)) {
  1679. DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
  1680. I915_WRITE(reg, val & ~LVDS_PORT_EN);
  1681. POSTING_READ(reg);
  1682. udelay(100);
  1683. }
  1684. disable_pch_hdmi(dev_priv, pipe, HDMIB);
  1685. disable_pch_hdmi(dev_priv, pipe, HDMIC);
  1686. disable_pch_hdmi(dev_priv, pipe, HDMID);
  1687. }
  1688. int
  1689. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1690. struct drm_i915_gem_object *obj,
  1691. struct intel_ring_buffer *pipelined)
  1692. {
  1693. struct drm_i915_private *dev_priv = dev->dev_private;
  1694. u32 alignment;
  1695. int ret;
  1696. switch (obj->tiling_mode) {
  1697. case I915_TILING_NONE:
  1698. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1699. alignment = 128 * 1024;
  1700. else if (INTEL_INFO(dev)->gen >= 4)
  1701. alignment = 4 * 1024;
  1702. else
  1703. alignment = 64 * 1024;
  1704. break;
  1705. case I915_TILING_X:
  1706. /* pin() will align the object as required by fence */
  1707. alignment = 0;
  1708. break;
  1709. case I915_TILING_Y:
  1710. /* FIXME: Is this true? */
  1711. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1712. return -EINVAL;
  1713. default:
  1714. BUG();
  1715. }
  1716. dev_priv->mm.interruptible = false;
  1717. ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
  1718. if (ret)
  1719. goto err_interruptible;
  1720. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1721. * fence, whereas 965+ only requires a fence if using
  1722. * framebuffer compression. For simplicity, we always install
  1723. * a fence as the cost is not that onerous.
  1724. */
  1725. ret = i915_gem_object_get_fence(obj);
  1726. if (ret)
  1727. goto err_unpin;
  1728. i915_gem_object_pin_fence(obj);
  1729. dev_priv->mm.interruptible = true;
  1730. return 0;
  1731. err_unpin:
  1732. i915_gem_object_unpin(obj);
  1733. err_interruptible:
  1734. dev_priv->mm.interruptible = true;
  1735. return ret;
  1736. }
  1737. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
  1738. {
  1739. i915_gem_object_unpin_fence(obj);
  1740. i915_gem_object_unpin(obj);
  1741. }
  1742. /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  1743. * is assumed to be a power-of-two. */
  1744. static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
  1745. unsigned int bpp,
  1746. unsigned int pitch)
  1747. {
  1748. int tile_rows, tiles;
  1749. tile_rows = *y / 8;
  1750. *y %= 8;
  1751. tiles = *x / (512/bpp);
  1752. *x %= 512/bpp;
  1753. return tile_rows * pitch * 8 + tiles * 4096;
  1754. }
  1755. static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1756. int x, int y)
  1757. {
  1758. struct drm_device *dev = crtc->dev;
  1759. struct drm_i915_private *dev_priv = dev->dev_private;
  1760. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1761. struct intel_framebuffer *intel_fb;
  1762. struct drm_i915_gem_object *obj;
  1763. int plane = intel_crtc->plane;
  1764. unsigned long linear_offset;
  1765. u32 dspcntr;
  1766. u32 reg;
  1767. switch (plane) {
  1768. case 0:
  1769. case 1:
  1770. break;
  1771. default:
  1772. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1773. return -EINVAL;
  1774. }
  1775. intel_fb = to_intel_framebuffer(fb);
  1776. obj = intel_fb->obj;
  1777. reg = DSPCNTR(plane);
  1778. dspcntr = I915_READ(reg);
  1779. /* Mask out pixel format bits in case we change it */
  1780. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1781. switch (fb->bits_per_pixel) {
  1782. case 8:
  1783. dspcntr |= DISPPLANE_8BPP;
  1784. break;
  1785. case 16:
  1786. if (fb->depth == 15)
  1787. dspcntr |= DISPPLANE_15_16BPP;
  1788. else
  1789. dspcntr |= DISPPLANE_16BPP;
  1790. break;
  1791. case 24:
  1792. case 32:
  1793. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1794. break;
  1795. default:
  1796. DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
  1797. return -EINVAL;
  1798. }
  1799. if (INTEL_INFO(dev)->gen >= 4) {
  1800. if (obj->tiling_mode != I915_TILING_NONE)
  1801. dspcntr |= DISPPLANE_TILED;
  1802. else
  1803. dspcntr &= ~DISPPLANE_TILED;
  1804. }
  1805. I915_WRITE(reg, dspcntr);
  1806. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1807. if (INTEL_INFO(dev)->gen >= 4) {
  1808. intel_crtc->dspaddr_offset =
  1809. gen4_compute_dspaddr_offset_xtiled(&x, &y,
  1810. fb->bits_per_pixel / 8,
  1811. fb->pitches[0]);
  1812. linear_offset -= intel_crtc->dspaddr_offset;
  1813. } else {
  1814. intel_crtc->dspaddr_offset = linear_offset;
  1815. }
  1816. DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
  1817. obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
  1818. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1819. if (INTEL_INFO(dev)->gen >= 4) {
  1820. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1821. obj->gtt_offset + intel_crtc->dspaddr_offset);
  1822. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1823. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1824. } else
  1825. I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
  1826. POSTING_READ(reg);
  1827. return 0;
  1828. }
  1829. static int ironlake_update_plane(struct drm_crtc *crtc,
  1830. struct drm_framebuffer *fb, int x, int y)
  1831. {
  1832. struct drm_device *dev = crtc->dev;
  1833. struct drm_i915_private *dev_priv = dev->dev_private;
  1834. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1835. struct intel_framebuffer *intel_fb;
  1836. struct drm_i915_gem_object *obj;
  1837. int plane = intel_crtc->plane;
  1838. unsigned long linear_offset;
  1839. u32 dspcntr;
  1840. u32 reg;
  1841. switch (plane) {
  1842. case 0:
  1843. case 1:
  1844. case 2:
  1845. break;
  1846. default:
  1847. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1848. return -EINVAL;
  1849. }
  1850. intel_fb = to_intel_framebuffer(fb);
  1851. obj = intel_fb->obj;
  1852. reg = DSPCNTR(plane);
  1853. dspcntr = I915_READ(reg);
  1854. /* Mask out pixel format bits in case we change it */
  1855. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1856. switch (fb->bits_per_pixel) {
  1857. case 8:
  1858. dspcntr |= DISPPLANE_8BPP;
  1859. break;
  1860. case 16:
  1861. if (fb->depth != 16)
  1862. return -EINVAL;
  1863. dspcntr |= DISPPLANE_16BPP;
  1864. break;
  1865. case 24:
  1866. case 32:
  1867. if (fb->depth == 24)
  1868. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1869. else if (fb->depth == 30)
  1870. dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
  1871. else
  1872. return -EINVAL;
  1873. break;
  1874. default:
  1875. DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
  1876. return -EINVAL;
  1877. }
  1878. if (obj->tiling_mode != I915_TILING_NONE)
  1879. dspcntr |= DISPPLANE_TILED;
  1880. else
  1881. dspcntr &= ~DISPPLANE_TILED;
  1882. /* must disable */
  1883. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1884. I915_WRITE(reg, dspcntr);
  1885. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1886. intel_crtc->dspaddr_offset =
  1887. gen4_compute_dspaddr_offset_xtiled(&x, &y,
  1888. fb->bits_per_pixel / 8,
  1889. fb->pitches[0]);
  1890. linear_offset -= intel_crtc->dspaddr_offset;
  1891. DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
  1892. obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
  1893. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1894. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1895. obj->gtt_offset + intel_crtc->dspaddr_offset);
  1896. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1897. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1898. POSTING_READ(reg);
  1899. return 0;
  1900. }
  1901. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1902. static int
  1903. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1904. int x, int y, enum mode_set_atomic state)
  1905. {
  1906. struct drm_device *dev = crtc->dev;
  1907. struct drm_i915_private *dev_priv = dev->dev_private;
  1908. if (dev_priv->display.disable_fbc)
  1909. dev_priv->display.disable_fbc(dev);
  1910. intel_increase_pllclock(crtc);
  1911. return dev_priv->display.update_plane(crtc, fb, x, y);
  1912. }
  1913. static int
  1914. intel_finish_fb(struct drm_framebuffer *old_fb)
  1915. {
  1916. struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  1917. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1918. bool was_interruptible = dev_priv->mm.interruptible;
  1919. int ret;
  1920. wait_event(dev_priv->pending_flip_queue,
  1921. atomic_read(&dev_priv->mm.wedged) ||
  1922. atomic_read(&obj->pending_flip) == 0);
  1923. /* Big Hammer, we also need to ensure that any pending
  1924. * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  1925. * current scanout is retired before unpinning the old
  1926. * framebuffer.
  1927. *
  1928. * This should only fail upon a hung GPU, in which case we
  1929. * can safely continue.
  1930. */
  1931. dev_priv->mm.interruptible = false;
  1932. ret = i915_gem_object_finish_gpu(obj);
  1933. dev_priv->mm.interruptible = was_interruptible;
  1934. return ret;
  1935. }
  1936. static int
  1937. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1938. struct drm_framebuffer *old_fb)
  1939. {
  1940. struct drm_device *dev = crtc->dev;
  1941. struct drm_i915_private *dev_priv = dev->dev_private;
  1942. struct drm_i915_master_private *master_priv;
  1943. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1944. int ret;
  1945. /* no fb bound */
  1946. if (!crtc->fb) {
  1947. DRM_ERROR("No FB bound\n");
  1948. return 0;
  1949. }
  1950. if(intel_crtc->plane > dev_priv->num_pipe) {
  1951. DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
  1952. intel_crtc->plane,
  1953. dev_priv->num_pipe);
  1954. return -EINVAL;
  1955. }
  1956. mutex_lock(&dev->struct_mutex);
  1957. ret = intel_pin_and_fence_fb_obj(dev,
  1958. to_intel_framebuffer(crtc->fb)->obj,
  1959. NULL);
  1960. if (ret != 0) {
  1961. mutex_unlock(&dev->struct_mutex);
  1962. DRM_ERROR("pin & fence failed\n");
  1963. return ret;
  1964. }
  1965. if (old_fb)
  1966. intel_finish_fb(old_fb);
  1967. ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
  1968. if (ret) {
  1969. intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
  1970. mutex_unlock(&dev->struct_mutex);
  1971. DRM_ERROR("failed to update base address\n");
  1972. return ret;
  1973. }
  1974. if (old_fb) {
  1975. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1976. intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
  1977. }
  1978. intel_update_fbc(dev);
  1979. mutex_unlock(&dev->struct_mutex);
  1980. if (!dev->primary->master)
  1981. return 0;
  1982. master_priv = dev->primary->master->driver_priv;
  1983. if (!master_priv->sarea_priv)
  1984. return 0;
  1985. if (intel_crtc->pipe) {
  1986. master_priv->sarea_priv->pipeB_x = x;
  1987. master_priv->sarea_priv->pipeB_y = y;
  1988. } else {
  1989. master_priv->sarea_priv->pipeA_x = x;
  1990. master_priv->sarea_priv->pipeA_y = y;
  1991. }
  1992. return 0;
  1993. }
  1994. static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
  1995. {
  1996. struct drm_device *dev = crtc->dev;
  1997. struct drm_i915_private *dev_priv = dev->dev_private;
  1998. u32 dpa_ctl;
  1999. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  2000. dpa_ctl = I915_READ(DP_A);
  2001. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  2002. if (clock < 200000) {
  2003. u32 temp;
  2004. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  2005. /* workaround for 160Mhz:
  2006. 1) program 0x4600c bits 15:0 = 0x8124
  2007. 2) program 0x46010 bit 0 = 1
  2008. 3) program 0x46034 bit 24 = 1
  2009. 4) program 0x64000 bit 14 = 1
  2010. */
  2011. temp = I915_READ(0x4600c);
  2012. temp &= 0xffff0000;
  2013. I915_WRITE(0x4600c, temp | 0x8124);
  2014. temp = I915_READ(0x46010);
  2015. I915_WRITE(0x46010, temp | 1);
  2016. temp = I915_READ(0x46034);
  2017. I915_WRITE(0x46034, temp | (1 << 24));
  2018. } else {
  2019. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  2020. }
  2021. I915_WRITE(DP_A, dpa_ctl);
  2022. POSTING_READ(DP_A);
  2023. udelay(500);
  2024. }
  2025. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  2026. {
  2027. struct drm_device *dev = crtc->dev;
  2028. struct drm_i915_private *dev_priv = dev->dev_private;
  2029. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2030. int pipe = intel_crtc->pipe;
  2031. u32 reg, temp;
  2032. /* enable normal train */
  2033. reg = FDI_TX_CTL(pipe);
  2034. temp = I915_READ(reg);
  2035. if (IS_IVYBRIDGE(dev)) {
  2036. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2037. temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  2038. } else {
  2039. temp &= ~FDI_LINK_TRAIN_NONE;
  2040. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  2041. }
  2042. I915_WRITE(reg, temp);
  2043. reg = FDI_RX_CTL(pipe);
  2044. temp = I915_READ(reg);
  2045. if (HAS_PCH_CPT(dev)) {
  2046. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2047. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  2048. } else {
  2049. temp &= ~FDI_LINK_TRAIN_NONE;
  2050. temp |= FDI_LINK_TRAIN_NONE;
  2051. }
  2052. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  2053. /* wait one idle pattern time */
  2054. POSTING_READ(reg);
  2055. udelay(1000);
  2056. /* IVB wants error correction enabled */
  2057. if (IS_IVYBRIDGE(dev))
  2058. I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  2059. FDI_FE_ERRC_ENABLE);
  2060. }
  2061. static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
  2062. {
  2063. struct drm_i915_private *dev_priv = dev->dev_private;
  2064. u32 flags = I915_READ(SOUTH_CHICKEN1);
  2065. flags |= FDI_PHASE_SYNC_OVR(pipe);
  2066. I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
  2067. flags |= FDI_PHASE_SYNC_EN(pipe);
  2068. I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
  2069. POSTING_READ(SOUTH_CHICKEN1);
  2070. }
  2071. /* The FDI link training functions for ILK/Ibexpeak. */
  2072. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  2073. {
  2074. struct drm_device *dev = crtc->dev;
  2075. struct drm_i915_private *dev_priv = dev->dev_private;
  2076. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2077. int pipe = intel_crtc->pipe;
  2078. int plane = intel_crtc->plane;
  2079. u32 reg, temp, tries;
  2080. /* FDI needs bits from pipe & plane first */
  2081. assert_pipe_enabled(dev_priv, pipe);
  2082. assert_plane_enabled(dev_priv, plane);
  2083. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2084. for train result */
  2085. reg = FDI_RX_IMR(pipe);
  2086. temp = I915_READ(reg);
  2087. temp &= ~FDI_RX_SYMBOL_LOCK;
  2088. temp &= ~FDI_RX_BIT_LOCK;
  2089. I915_WRITE(reg, temp);
  2090. I915_READ(reg);
  2091. udelay(150);
  2092. /* enable CPU FDI TX and PCH FDI RX */
  2093. reg = FDI_TX_CTL(pipe);
  2094. temp = I915_READ(reg);
  2095. temp &= ~(7 << 19);
  2096. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2097. temp &= ~FDI_LINK_TRAIN_NONE;
  2098. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2099. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2100. reg = FDI_RX_CTL(pipe);
  2101. temp = I915_READ(reg);
  2102. temp &= ~FDI_LINK_TRAIN_NONE;
  2103. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2104. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2105. POSTING_READ(reg);
  2106. udelay(150);
  2107. /* Ironlake workaround, enable clock pointer after FDI enable*/
  2108. if (HAS_PCH_IBX(dev)) {
  2109. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2110. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2111. FDI_RX_PHASE_SYNC_POINTER_EN);
  2112. }
  2113. reg = FDI_RX_IIR(pipe);
  2114. for (tries = 0; tries < 5; tries++) {
  2115. temp = I915_READ(reg);
  2116. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2117. if ((temp & FDI_RX_BIT_LOCK)) {
  2118. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2119. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2120. break;
  2121. }
  2122. }
  2123. if (tries == 5)
  2124. DRM_ERROR("FDI train 1 fail!\n");
  2125. /* Train 2 */
  2126. reg = FDI_TX_CTL(pipe);
  2127. temp = I915_READ(reg);
  2128. temp &= ~FDI_LINK_TRAIN_NONE;
  2129. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2130. I915_WRITE(reg, temp);
  2131. reg = FDI_RX_CTL(pipe);
  2132. temp = I915_READ(reg);
  2133. temp &= ~FDI_LINK_TRAIN_NONE;
  2134. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2135. I915_WRITE(reg, temp);
  2136. POSTING_READ(reg);
  2137. udelay(150);
  2138. reg = FDI_RX_IIR(pipe);
  2139. for (tries = 0; tries < 5; tries++) {
  2140. temp = I915_READ(reg);
  2141. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2142. if (temp & FDI_RX_SYMBOL_LOCK) {
  2143. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2144. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2145. break;
  2146. }
  2147. }
  2148. if (tries == 5)
  2149. DRM_ERROR("FDI train 2 fail!\n");
  2150. DRM_DEBUG_KMS("FDI train done\n");
  2151. }
  2152. static const int snb_b_fdi_train_param[] = {
  2153. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2154. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2155. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2156. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2157. };
  2158. /* The FDI link training functions for SNB/Cougarpoint. */
  2159. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2160. {
  2161. struct drm_device *dev = crtc->dev;
  2162. struct drm_i915_private *dev_priv = dev->dev_private;
  2163. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2164. int pipe = intel_crtc->pipe;
  2165. u32 reg, temp, i, retry;
  2166. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2167. for train result */
  2168. reg = FDI_RX_IMR(pipe);
  2169. temp = I915_READ(reg);
  2170. temp &= ~FDI_RX_SYMBOL_LOCK;
  2171. temp &= ~FDI_RX_BIT_LOCK;
  2172. I915_WRITE(reg, temp);
  2173. POSTING_READ(reg);
  2174. udelay(150);
  2175. /* enable CPU FDI TX and PCH FDI RX */
  2176. reg = FDI_TX_CTL(pipe);
  2177. temp = I915_READ(reg);
  2178. temp &= ~(7 << 19);
  2179. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2180. temp &= ~FDI_LINK_TRAIN_NONE;
  2181. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2182. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2183. /* SNB-B */
  2184. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2185. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2186. reg = FDI_RX_CTL(pipe);
  2187. temp = I915_READ(reg);
  2188. if (HAS_PCH_CPT(dev)) {
  2189. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2190. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2191. } else {
  2192. temp &= ~FDI_LINK_TRAIN_NONE;
  2193. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2194. }
  2195. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2196. POSTING_READ(reg);
  2197. udelay(150);
  2198. if (HAS_PCH_CPT(dev))
  2199. cpt_phase_pointer_enable(dev, pipe);
  2200. for (i = 0; i < 4; i++) {
  2201. reg = FDI_TX_CTL(pipe);
  2202. temp = I915_READ(reg);
  2203. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2204. temp |= snb_b_fdi_train_param[i];
  2205. I915_WRITE(reg, temp);
  2206. POSTING_READ(reg);
  2207. udelay(500);
  2208. for (retry = 0; retry < 5; retry++) {
  2209. reg = FDI_RX_IIR(pipe);
  2210. temp = I915_READ(reg);
  2211. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2212. if (temp & FDI_RX_BIT_LOCK) {
  2213. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2214. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2215. break;
  2216. }
  2217. udelay(50);
  2218. }
  2219. if (retry < 5)
  2220. break;
  2221. }
  2222. if (i == 4)
  2223. DRM_ERROR("FDI train 1 fail!\n");
  2224. /* Train 2 */
  2225. reg = FDI_TX_CTL(pipe);
  2226. temp = I915_READ(reg);
  2227. temp &= ~FDI_LINK_TRAIN_NONE;
  2228. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2229. if (IS_GEN6(dev)) {
  2230. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2231. /* SNB-B */
  2232. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2233. }
  2234. I915_WRITE(reg, temp);
  2235. reg = FDI_RX_CTL(pipe);
  2236. temp = I915_READ(reg);
  2237. if (HAS_PCH_CPT(dev)) {
  2238. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2239. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2240. } else {
  2241. temp &= ~FDI_LINK_TRAIN_NONE;
  2242. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2243. }
  2244. I915_WRITE(reg, temp);
  2245. POSTING_READ(reg);
  2246. udelay(150);
  2247. for (i = 0; i < 4; i++) {
  2248. reg = FDI_TX_CTL(pipe);
  2249. temp = I915_READ(reg);
  2250. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2251. temp |= snb_b_fdi_train_param[i];
  2252. I915_WRITE(reg, temp);
  2253. POSTING_READ(reg);
  2254. udelay(500);
  2255. for (retry = 0; retry < 5; retry++) {
  2256. reg = FDI_RX_IIR(pipe);
  2257. temp = I915_READ(reg);
  2258. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2259. if (temp & FDI_RX_SYMBOL_LOCK) {
  2260. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2261. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2262. break;
  2263. }
  2264. udelay(50);
  2265. }
  2266. if (retry < 5)
  2267. break;
  2268. }
  2269. if (i == 4)
  2270. DRM_ERROR("FDI train 2 fail!\n");
  2271. DRM_DEBUG_KMS("FDI train done.\n");
  2272. }
  2273. /* Manual link training for Ivy Bridge A0 parts */
  2274. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2275. {
  2276. struct drm_device *dev = crtc->dev;
  2277. struct drm_i915_private *dev_priv = dev->dev_private;
  2278. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2279. int pipe = intel_crtc->pipe;
  2280. u32 reg, temp, i;
  2281. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2282. for train result */
  2283. reg = FDI_RX_IMR(pipe);
  2284. temp = I915_READ(reg);
  2285. temp &= ~FDI_RX_SYMBOL_LOCK;
  2286. temp &= ~FDI_RX_BIT_LOCK;
  2287. I915_WRITE(reg, temp);
  2288. POSTING_READ(reg);
  2289. udelay(150);
  2290. /* enable CPU FDI TX and PCH FDI RX */
  2291. reg = FDI_TX_CTL(pipe);
  2292. temp = I915_READ(reg);
  2293. temp &= ~(7 << 19);
  2294. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2295. temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2296. temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  2297. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2298. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2299. temp |= FDI_COMPOSITE_SYNC;
  2300. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2301. reg = FDI_RX_CTL(pipe);
  2302. temp = I915_READ(reg);
  2303. temp &= ~FDI_LINK_TRAIN_AUTO;
  2304. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2305. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2306. temp |= FDI_COMPOSITE_SYNC;
  2307. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2308. POSTING_READ(reg);
  2309. udelay(150);
  2310. if (HAS_PCH_CPT(dev))
  2311. cpt_phase_pointer_enable(dev, pipe);
  2312. for (i = 0; i < 4; i++) {
  2313. reg = FDI_TX_CTL(pipe);
  2314. temp = I915_READ(reg);
  2315. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2316. temp |= snb_b_fdi_train_param[i];
  2317. I915_WRITE(reg, temp);
  2318. POSTING_READ(reg);
  2319. udelay(500);
  2320. reg = FDI_RX_IIR(pipe);
  2321. temp = I915_READ(reg);
  2322. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2323. if (temp & FDI_RX_BIT_LOCK ||
  2324. (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  2325. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2326. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2327. break;
  2328. }
  2329. }
  2330. if (i == 4)
  2331. DRM_ERROR("FDI train 1 fail!\n");
  2332. /* Train 2 */
  2333. reg = FDI_TX_CTL(pipe);
  2334. temp = I915_READ(reg);
  2335. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2336. temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  2337. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2338. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2339. I915_WRITE(reg, temp);
  2340. reg = FDI_RX_CTL(pipe);
  2341. temp = I915_READ(reg);
  2342. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2343. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2344. I915_WRITE(reg, temp);
  2345. POSTING_READ(reg);
  2346. udelay(150);
  2347. for (i = 0; i < 4; i++) {
  2348. reg = FDI_TX_CTL(pipe);
  2349. temp = I915_READ(reg);
  2350. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2351. temp |= snb_b_fdi_train_param[i];
  2352. I915_WRITE(reg, temp);
  2353. POSTING_READ(reg);
  2354. udelay(500);
  2355. reg = FDI_RX_IIR(pipe);
  2356. temp = I915_READ(reg);
  2357. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2358. if (temp & FDI_RX_SYMBOL_LOCK) {
  2359. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2360. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2361. break;
  2362. }
  2363. }
  2364. if (i == 4)
  2365. DRM_ERROR("FDI train 2 fail!\n");
  2366. DRM_DEBUG_KMS("FDI train done.\n");
  2367. }
  2368. static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
  2369. {
  2370. struct drm_device *dev = intel_crtc->base.dev;
  2371. struct drm_i915_private *dev_priv = dev->dev_private;
  2372. int pipe = intel_crtc->pipe;
  2373. u32 reg, temp;
  2374. /* Write the TU size bits so error detection works */
  2375. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  2376. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  2377. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  2378. reg = FDI_RX_CTL(pipe);
  2379. temp = I915_READ(reg);
  2380. temp &= ~((0x7 << 19) | (0x7 << 16));
  2381. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2382. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2383. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  2384. POSTING_READ(reg);
  2385. udelay(200);
  2386. /* Switch from Rawclk to PCDclk */
  2387. temp = I915_READ(reg);
  2388. I915_WRITE(reg, temp | FDI_PCDCLK);
  2389. POSTING_READ(reg);
  2390. udelay(200);
  2391. /* On Haswell, the PLL configuration for ports and pipes is handled
  2392. * separately, as part of DDI setup */
  2393. if (!IS_HASWELL(dev)) {
  2394. /* Enable CPU FDI TX PLL, always on for Ironlake */
  2395. reg = FDI_TX_CTL(pipe);
  2396. temp = I915_READ(reg);
  2397. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  2398. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  2399. POSTING_READ(reg);
  2400. udelay(100);
  2401. }
  2402. }
  2403. }
  2404. static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
  2405. {
  2406. struct drm_device *dev = intel_crtc->base.dev;
  2407. struct drm_i915_private *dev_priv = dev->dev_private;
  2408. int pipe = intel_crtc->pipe;
  2409. u32 reg, temp;
  2410. /* Switch from PCDclk to Rawclk */
  2411. reg = FDI_RX_CTL(pipe);
  2412. temp = I915_READ(reg);
  2413. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  2414. /* Disable CPU FDI TX PLL */
  2415. reg = FDI_TX_CTL(pipe);
  2416. temp = I915_READ(reg);
  2417. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  2418. POSTING_READ(reg);
  2419. udelay(100);
  2420. reg = FDI_RX_CTL(pipe);
  2421. temp = I915_READ(reg);
  2422. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2423. /* Wait for the clocks to turn off. */
  2424. POSTING_READ(reg);
  2425. udelay(100);
  2426. }
  2427. static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
  2428. {
  2429. struct drm_i915_private *dev_priv = dev->dev_private;
  2430. u32 flags = I915_READ(SOUTH_CHICKEN1);
  2431. flags &= ~(FDI_PHASE_SYNC_EN(pipe));
  2432. I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
  2433. flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
  2434. I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
  2435. POSTING_READ(SOUTH_CHICKEN1);
  2436. }
  2437. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  2438. {
  2439. struct drm_device *dev = crtc->dev;
  2440. struct drm_i915_private *dev_priv = dev->dev_private;
  2441. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2442. int pipe = intel_crtc->pipe;
  2443. u32 reg, temp;
  2444. /* disable CPU FDI tx and PCH FDI rx */
  2445. reg = FDI_TX_CTL(pipe);
  2446. temp = I915_READ(reg);
  2447. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  2448. POSTING_READ(reg);
  2449. reg = FDI_RX_CTL(pipe);
  2450. temp = I915_READ(reg);
  2451. temp &= ~(0x7 << 16);
  2452. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2453. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  2454. POSTING_READ(reg);
  2455. udelay(100);
  2456. /* Ironlake workaround, disable clock pointer after downing FDI */
  2457. if (HAS_PCH_IBX(dev)) {
  2458. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2459. I915_WRITE(FDI_RX_CHICKEN(pipe),
  2460. I915_READ(FDI_RX_CHICKEN(pipe) &
  2461. ~FDI_RX_PHASE_SYNC_POINTER_EN));
  2462. } else if (HAS_PCH_CPT(dev)) {
  2463. cpt_phase_pointer_disable(dev, pipe);
  2464. }
  2465. /* still set train pattern 1 */
  2466. reg = FDI_TX_CTL(pipe);
  2467. temp = I915_READ(reg);
  2468. temp &= ~FDI_LINK_TRAIN_NONE;
  2469. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2470. I915_WRITE(reg, temp);
  2471. reg = FDI_RX_CTL(pipe);
  2472. temp = I915_READ(reg);
  2473. if (HAS_PCH_CPT(dev)) {
  2474. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2475. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2476. } else {
  2477. temp &= ~FDI_LINK_TRAIN_NONE;
  2478. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2479. }
  2480. /* BPC in FDI rx is consistent with that in PIPECONF */
  2481. temp &= ~(0x07 << 16);
  2482. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2483. I915_WRITE(reg, temp);
  2484. POSTING_READ(reg);
  2485. udelay(100);
  2486. }
  2487. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  2488. {
  2489. struct drm_device *dev = crtc->dev;
  2490. if (crtc->fb == NULL)
  2491. return;
  2492. mutex_lock(&dev->struct_mutex);
  2493. intel_finish_fb(crtc->fb);
  2494. mutex_unlock(&dev->struct_mutex);
  2495. }
  2496. static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
  2497. {
  2498. struct drm_device *dev = crtc->dev;
  2499. struct intel_encoder *intel_encoder;
  2500. /*
  2501. * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
  2502. * must be driven by its own crtc; no sharing is possible.
  2503. */
  2504. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  2505. /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
  2506. * CPU handles all others */
  2507. if (IS_HASWELL(dev)) {
  2508. /* It is still unclear how this will work on PPT, so throw up a warning */
  2509. WARN_ON(!HAS_PCH_LPT(dev));
  2510. if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
  2511. DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
  2512. return true;
  2513. } else {
  2514. DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
  2515. intel_encoder->type);
  2516. return false;
  2517. }
  2518. }
  2519. switch (intel_encoder->type) {
  2520. case INTEL_OUTPUT_EDP:
  2521. if (!intel_encoder_is_pch_edp(&intel_encoder->base))
  2522. return false;
  2523. continue;
  2524. }
  2525. }
  2526. return true;
  2527. }
  2528. /* Program iCLKIP clock to the desired frequency */
  2529. static void lpt_program_iclkip(struct drm_crtc *crtc)
  2530. {
  2531. struct drm_device *dev = crtc->dev;
  2532. struct drm_i915_private *dev_priv = dev->dev_private;
  2533. u32 divsel, phaseinc, auxdiv, phasedir = 0;
  2534. u32 temp;
  2535. /* It is necessary to ungate the pixclk gate prior to programming
  2536. * the divisors, and gate it back when it is done.
  2537. */
  2538. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
  2539. /* Disable SSCCTL */
  2540. intel_sbi_write(dev_priv, SBI_SSCCTL6,
  2541. intel_sbi_read(dev_priv, SBI_SSCCTL6) |
  2542. SBI_SSCCTL_DISABLE);
  2543. /* 20MHz is a corner case which is out of range for the 7-bit divisor */
  2544. if (crtc->mode.clock == 20000) {
  2545. auxdiv = 1;
  2546. divsel = 0x41;
  2547. phaseinc = 0x20;
  2548. } else {
  2549. /* The iCLK virtual clock root frequency is in MHz,
  2550. * but the crtc->mode.clock in in KHz. To get the divisors,
  2551. * it is necessary to divide one by another, so we
  2552. * convert the virtual clock precision to KHz here for higher
  2553. * precision.
  2554. */
  2555. u32 iclk_virtual_root_freq = 172800 * 1000;
  2556. u32 iclk_pi_range = 64;
  2557. u32 desired_divisor, msb_divisor_value, pi_value;
  2558. desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
  2559. msb_divisor_value = desired_divisor / iclk_pi_range;
  2560. pi_value = desired_divisor % iclk_pi_range;
  2561. auxdiv = 0;
  2562. divsel = msb_divisor_value - 2;
  2563. phaseinc = pi_value;
  2564. }
  2565. /* This should not happen with any sane values */
  2566. WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
  2567. ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
  2568. WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
  2569. ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
  2570. DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
  2571. crtc->mode.clock,
  2572. auxdiv,
  2573. divsel,
  2574. phasedir,
  2575. phaseinc);
  2576. /* Program SSCDIVINTPHASE6 */
  2577. temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
  2578. temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
  2579. temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
  2580. temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
  2581. temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
  2582. temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
  2583. temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
  2584. intel_sbi_write(dev_priv,
  2585. SBI_SSCDIVINTPHASE6,
  2586. temp);
  2587. /* Program SSCAUXDIV */
  2588. temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
  2589. temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
  2590. temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
  2591. intel_sbi_write(dev_priv,
  2592. SBI_SSCAUXDIV6,
  2593. temp);
  2594. /* Enable modulator and associated divider */
  2595. temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
  2596. temp &= ~SBI_SSCCTL_DISABLE;
  2597. intel_sbi_write(dev_priv,
  2598. SBI_SSCCTL6,
  2599. temp);
  2600. /* Wait for initialization time */
  2601. udelay(24);
  2602. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
  2603. }
  2604. /*
  2605. * Enable PCH resources required for PCH ports:
  2606. * - PCH PLLs
  2607. * - FDI training & RX/TX
  2608. * - update transcoder timings
  2609. * - DP transcoding bits
  2610. * - transcoder
  2611. */
  2612. static void ironlake_pch_enable(struct drm_crtc *crtc)
  2613. {
  2614. struct drm_device *dev = crtc->dev;
  2615. struct drm_i915_private *dev_priv = dev->dev_private;
  2616. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2617. int pipe = intel_crtc->pipe;
  2618. u32 reg, temp;
  2619. assert_transcoder_disabled(dev_priv, pipe);
  2620. /* For PCH output, training FDI link */
  2621. dev_priv->display.fdi_link_train(crtc);
  2622. intel_enable_pch_pll(intel_crtc);
  2623. if (HAS_PCH_LPT(dev)) {
  2624. DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
  2625. lpt_program_iclkip(crtc);
  2626. } else if (HAS_PCH_CPT(dev)) {
  2627. u32 sel;
  2628. temp = I915_READ(PCH_DPLL_SEL);
  2629. switch (pipe) {
  2630. default:
  2631. case 0:
  2632. temp |= TRANSA_DPLL_ENABLE;
  2633. sel = TRANSA_DPLLB_SEL;
  2634. break;
  2635. case 1:
  2636. temp |= TRANSB_DPLL_ENABLE;
  2637. sel = TRANSB_DPLLB_SEL;
  2638. break;
  2639. case 2:
  2640. temp |= TRANSC_DPLL_ENABLE;
  2641. sel = TRANSC_DPLLB_SEL;
  2642. break;
  2643. }
  2644. if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
  2645. temp |= sel;
  2646. else
  2647. temp &= ~sel;
  2648. I915_WRITE(PCH_DPLL_SEL, temp);
  2649. }
  2650. /* set transcoder timing, panel must allow it */
  2651. assert_panel_unlocked(dev_priv, pipe);
  2652. I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
  2653. I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
  2654. I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
  2655. I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
  2656. I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
  2657. I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
  2658. I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
  2659. if (!IS_HASWELL(dev))
  2660. intel_fdi_normal_train(crtc);
  2661. /* For PCH DP, enable TRANS_DP_CTL */
  2662. if (HAS_PCH_CPT(dev) &&
  2663. (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  2664. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2665. u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
  2666. reg = TRANS_DP_CTL(pipe);
  2667. temp = I915_READ(reg);
  2668. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  2669. TRANS_DP_SYNC_MASK |
  2670. TRANS_DP_BPC_MASK);
  2671. temp |= (TRANS_DP_OUTPUT_ENABLE |
  2672. TRANS_DP_ENH_FRAMING);
  2673. temp |= bpc << 9; /* same format but at 11:9 */
  2674. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  2675. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  2676. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  2677. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  2678. switch (intel_trans_dp_port_sel(crtc)) {
  2679. case PCH_DP_B:
  2680. temp |= TRANS_DP_PORT_SEL_B;
  2681. break;
  2682. case PCH_DP_C:
  2683. temp |= TRANS_DP_PORT_SEL_C;
  2684. break;
  2685. case PCH_DP_D:
  2686. temp |= TRANS_DP_PORT_SEL_D;
  2687. break;
  2688. default:
  2689. DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
  2690. temp |= TRANS_DP_PORT_SEL_B;
  2691. break;
  2692. }
  2693. I915_WRITE(reg, temp);
  2694. }
  2695. intel_enable_transcoder(dev_priv, pipe);
  2696. }
  2697. static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
  2698. {
  2699. struct intel_pch_pll *pll = intel_crtc->pch_pll;
  2700. if (pll == NULL)
  2701. return;
  2702. if (pll->refcount == 0) {
  2703. WARN(1, "bad PCH PLL refcount\n");
  2704. return;
  2705. }
  2706. --pll->refcount;
  2707. intel_crtc->pch_pll = NULL;
  2708. }
  2709. static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
  2710. {
  2711. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  2712. struct intel_pch_pll *pll;
  2713. int i;
  2714. pll = intel_crtc->pch_pll;
  2715. if (pll) {
  2716. DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
  2717. intel_crtc->base.base.id, pll->pll_reg);
  2718. goto prepare;
  2719. }
  2720. if (HAS_PCH_IBX(dev_priv->dev)) {
  2721. /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
  2722. i = intel_crtc->pipe;
  2723. pll = &dev_priv->pch_plls[i];
  2724. DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
  2725. intel_crtc->base.base.id, pll->pll_reg);
  2726. goto found;
  2727. }
  2728. for (i = 0; i < dev_priv->num_pch_pll; i++) {
  2729. pll = &dev_priv->pch_plls[i];
  2730. /* Only want to check enabled timings first */
  2731. if (pll->refcount == 0)
  2732. continue;
  2733. if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
  2734. fp == I915_READ(pll->fp0_reg)) {
  2735. DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
  2736. intel_crtc->base.base.id,
  2737. pll->pll_reg, pll->refcount, pll->active);
  2738. goto found;
  2739. }
  2740. }
  2741. /* Ok no matching timings, maybe there's a free one? */
  2742. for (i = 0; i < dev_priv->num_pch_pll; i++) {
  2743. pll = &dev_priv->pch_plls[i];
  2744. if (pll->refcount == 0) {
  2745. DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
  2746. intel_crtc->base.base.id, pll->pll_reg);
  2747. goto found;
  2748. }
  2749. }
  2750. return NULL;
  2751. found:
  2752. intel_crtc->pch_pll = pll;
  2753. pll->refcount++;
  2754. DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
  2755. prepare: /* separate function? */
  2756. DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
  2757. /* Wait for the clocks to stabilize before rewriting the regs */
  2758. I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
  2759. POSTING_READ(pll->pll_reg);
  2760. udelay(150);
  2761. I915_WRITE(pll->fp0_reg, fp);
  2762. I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
  2763. pll->on = false;
  2764. return pll;
  2765. }
  2766. void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
  2767. {
  2768. struct drm_i915_private *dev_priv = dev->dev_private;
  2769. int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
  2770. u32 temp;
  2771. temp = I915_READ(dslreg);
  2772. udelay(500);
  2773. if (wait_for(I915_READ(dslreg) != temp, 5)) {
  2774. /* Without this, mode sets may fail silently on FDI */
  2775. I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
  2776. udelay(250);
  2777. I915_WRITE(tc2reg, 0);
  2778. if (wait_for(I915_READ(dslreg) != temp, 5))
  2779. DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
  2780. }
  2781. }
  2782. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  2783. {
  2784. struct drm_device *dev = crtc->dev;
  2785. struct drm_i915_private *dev_priv = dev->dev_private;
  2786. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2787. struct intel_encoder *encoder;
  2788. int pipe = intel_crtc->pipe;
  2789. int plane = intel_crtc->plane;
  2790. u32 temp;
  2791. bool is_pch_port;
  2792. /* XXX: For compatability with the crtc helper code, call the encoder's
  2793. * enable function unconditionally for now. */
  2794. if (intel_crtc->active)
  2795. goto encoders;
  2796. intel_crtc->active = true;
  2797. intel_update_watermarks(dev);
  2798. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  2799. temp = I915_READ(PCH_LVDS);
  2800. if ((temp & LVDS_PORT_EN) == 0)
  2801. I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
  2802. }
  2803. is_pch_port = intel_crtc_driving_pch(crtc);
  2804. if (is_pch_port)
  2805. ironlake_fdi_pll_enable(intel_crtc);
  2806. else
  2807. ironlake_fdi_disable(crtc);
  2808. /* Enable panel fitting for LVDS */
  2809. if (dev_priv->pch_pf_size &&
  2810. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
  2811. /* Force use of hard-coded filter coefficients
  2812. * as some pre-programmed values are broken,
  2813. * e.g. x201.
  2814. */
  2815. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  2816. I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
  2817. I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
  2818. }
  2819. /*
  2820. * On ILK+ LUT must be loaded before the pipe is running but with
  2821. * clocks enabled
  2822. */
  2823. intel_crtc_load_lut(crtc);
  2824. intel_enable_pipe(dev_priv, pipe, is_pch_port);
  2825. intel_enable_plane(dev_priv, plane, pipe);
  2826. if (is_pch_port)
  2827. ironlake_pch_enable(crtc);
  2828. mutex_lock(&dev->struct_mutex);
  2829. intel_update_fbc(dev);
  2830. mutex_unlock(&dev->struct_mutex);
  2831. intel_crtc_update_cursor(crtc, true);
  2832. encoders:
  2833. for_each_encoder_on_crtc(dev, crtc, encoder)
  2834. encoder->enable(encoder);
  2835. }
  2836. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  2837. {
  2838. struct drm_device *dev = crtc->dev;
  2839. struct drm_i915_private *dev_priv = dev->dev_private;
  2840. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2841. struct intel_encoder *encoder;
  2842. int pipe = intel_crtc->pipe;
  2843. int plane = intel_crtc->plane;
  2844. u32 reg, temp;
  2845. /* XXX: For compatability with the crtc helper code, call the encoder's
  2846. * disable function unconditionally for now. */
  2847. for_each_encoder_on_crtc(dev, crtc, encoder)
  2848. encoder->disable(encoder);
  2849. if (!intel_crtc->active)
  2850. return;
  2851. intel_crtc_wait_for_pending_flips(crtc);
  2852. drm_vblank_off(dev, pipe);
  2853. intel_crtc_update_cursor(crtc, false);
  2854. intel_disable_plane(dev_priv, plane, pipe);
  2855. if (dev_priv->cfb_plane == plane)
  2856. intel_disable_fbc(dev);
  2857. intel_disable_pipe(dev_priv, pipe);
  2858. /* Disable PF */
  2859. I915_WRITE(PF_CTL(pipe), 0);
  2860. I915_WRITE(PF_WIN_SZ(pipe), 0);
  2861. ironlake_fdi_disable(crtc);
  2862. /* This is a horrible layering violation; we should be doing this in
  2863. * the connector/encoder ->prepare instead, but we don't always have
  2864. * enough information there about the config to know whether it will
  2865. * actually be necessary or just cause undesired flicker.
  2866. */
  2867. intel_disable_pch_ports(dev_priv, pipe);
  2868. intel_disable_transcoder(dev_priv, pipe);
  2869. if (HAS_PCH_CPT(dev)) {
  2870. /* disable TRANS_DP_CTL */
  2871. reg = TRANS_DP_CTL(pipe);
  2872. temp = I915_READ(reg);
  2873. temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
  2874. temp |= TRANS_DP_PORT_SEL_NONE;
  2875. I915_WRITE(reg, temp);
  2876. /* disable DPLL_SEL */
  2877. temp = I915_READ(PCH_DPLL_SEL);
  2878. switch (pipe) {
  2879. case 0:
  2880. temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
  2881. break;
  2882. case 1:
  2883. temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  2884. break;
  2885. case 2:
  2886. /* C shares PLL A or B */
  2887. temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
  2888. break;
  2889. default:
  2890. BUG(); /* wtf */
  2891. }
  2892. I915_WRITE(PCH_DPLL_SEL, temp);
  2893. }
  2894. /* disable PCH DPLL */
  2895. intel_disable_pch_pll(intel_crtc);
  2896. ironlake_fdi_pll_disable(intel_crtc);
  2897. intel_crtc->active = false;
  2898. intel_update_watermarks(dev);
  2899. mutex_lock(&dev->struct_mutex);
  2900. intel_update_fbc(dev);
  2901. mutex_unlock(&dev->struct_mutex);
  2902. }
  2903. static void ironlake_crtc_off(struct drm_crtc *crtc)
  2904. {
  2905. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2906. intel_put_pch_pll(intel_crtc);
  2907. }
  2908. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  2909. {
  2910. if (!enable && intel_crtc->overlay) {
  2911. struct drm_device *dev = intel_crtc->base.dev;
  2912. struct drm_i915_private *dev_priv = dev->dev_private;
  2913. mutex_lock(&dev->struct_mutex);
  2914. dev_priv->mm.interruptible = false;
  2915. (void) intel_overlay_switch_off(intel_crtc->overlay);
  2916. dev_priv->mm.interruptible = true;
  2917. mutex_unlock(&dev->struct_mutex);
  2918. }
  2919. /* Let userspace switch the overlay on again. In most cases userspace
  2920. * has to recompute where to put it anyway.
  2921. */
  2922. }
  2923. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  2924. {
  2925. struct drm_device *dev = crtc->dev;
  2926. struct drm_i915_private *dev_priv = dev->dev_private;
  2927. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2928. struct intel_encoder *encoder;
  2929. int pipe = intel_crtc->pipe;
  2930. int plane = intel_crtc->plane;
  2931. /* XXX: For compatability with the crtc helper code, call the encoder's
  2932. * enable function unconditionally for now. */
  2933. if (intel_crtc->active)
  2934. goto encoders;
  2935. intel_crtc->active = true;
  2936. intel_update_watermarks(dev);
  2937. intel_enable_pll(dev_priv, pipe);
  2938. intel_enable_pipe(dev_priv, pipe, false);
  2939. intel_enable_plane(dev_priv, plane, pipe);
  2940. intel_crtc_load_lut(crtc);
  2941. intel_update_fbc(dev);
  2942. /* Give the overlay scaler a chance to enable if it's on this pipe */
  2943. intel_crtc_dpms_overlay(intel_crtc, true);
  2944. intel_crtc_update_cursor(crtc, true);
  2945. encoders:
  2946. for_each_encoder_on_crtc(dev, crtc, encoder)
  2947. encoder->enable(encoder);
  2948. }
  2949. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  2950. {
  2951. struct drm_device *dev = crtc->dev;
  2952. struct drm_i915_private *dev_priv = dev->dev_private;
  2953. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2954. struct intel_encoder *encoder;
  2955. int pipe = intel_crtc->pipe;
  2956. int plane = intel_crtc->plane;
  2957. /* XXX: For compatability with the crtc helper code, call the encoder's
  2958. * disable function unconditionally for now. */
  2959. for_each_encoder_on_crtc(dev, crtc, encoder)
  2960. encoder->disable(encoder);
  2961. if (!intel_crtc->active)
  2962. return;
  2963. /* Give the overlay scaler a chance to disable if it's on this pipe */
  2964. intel_crtc_wait_for_pending_flips(crtc);
  2965. drm_vblank_off(dev, pipe);
  2966. intel_crtc_dpms_overlay(intel_crtc, false);
  2967. intel_crtc_update_cursor(crtc, false);
  2968. if (dev_priv->cfb_plane == plane)
  2969. intel_disable_fbc(dev);
  2970. intel_disable_plane(dev_priv, plane, pipe);
  2971. intel_disable_pipe(dev_priv, pipe);
  2972. intel_disable_pll(dev_priv, pipe);
  2973. intel_crtc->active = false;
  2974. intel_update_fbc(dev);
  2975. intel_update_watermarks(dev);
  2976. }
  2977. static void i9xx_crtc_off(struct drm_crtc *crtc)
  2978. {
  2979. }
  2980. /**
  2981. * Sets the power management mode of the pipe and plane.
  2982. */
  2983. void intel_crtc_update_dpms(struct drm_crtc *crtc)
  2984. {
  2985. struct drm_device *dev = crtc->dev;
  2986. struct drm_i915_private *dev_priv = dev->dev_private;
  2987. struct drm_i915_master_private *master_priv;
  2988. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2989. struct intel_encoder *intel_encoder;
  2990. int pipe = intel_crtc->pipe;
  2991. bool enabled, enable = false;
  2992. int mode;
  2993. for_each_encoder_on_crtc(dev, crtc, intel_encoder)
  2994. enable |= intel_encoder->connectors_active;
  2995. mode = enable ? DRM_MODE_DPMS_ON : DRM_MODE_DPMS_OFF;
  2996. if (intel_crtc->dpms_mode == mode)
  2997. return;
  2998. intel_crtc->dpms_mode = mode;
  2999. if (enable)
  3000. dev_priv->display.crtc_enable(crtc);
  3001. else
  3002. dev_priv->display.crtc_disable(crtc);
  3003. if (!dev->primary->master)
  3004. return;
  3005. master_priv = dev->primary->master->driver_priv;
  3006. if (!master_priv->sarea_priv)
  3007. return;
  3008. enabled = crtc->enabled && enable;
  3009. switch (pipe) {
  3010. case 0:
  3011. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  3012. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  3013. break;
  3014. case 1:
  3015. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  3016. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  3017. break;
  3018. default:
  3019. DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
  3020. break;
  3021. }
  3022. }
  3023. static void intel_crtc_disable(struct drm_crtc *crtc)
  3024. {
  3025. struct drm_device *dev = crtc->dev;
  3026. struct drm_i915_private *dev_priv = dev->dev_private;
  3027. /* crtc->disable is only called when we have no encoders, hence this
  3028. * will disable the pipe. */
  3029. intel_crtc_update_dpms(crtc);
  3030. dev_priv->display.off(crtc);
  3031. assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
  3032. assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
  3033. if (crtc->fb) {
  3034. mutex_lock(&dev->struct_mutex);
  3035. intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
  3036. mutex_unlock(&dev->struct_mutex);
  3037. }
  3038. }
  3039. void intel_encoder_prepare(struct drm_encoder *encoder)
  3040. {
  3041. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3042. /* lvds has its own version of prepare see intel_lvds_prepare */
  3043. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  3044. }
  3045. void intel_encoder_commit(struct drm_encoder *encoder)
  3046. {
  3047. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3048. struct drm_device *dev = encoder->dev;
  3049. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  3050. /* lvds has its own version of commit see intel_lvds_commit */
  3051. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  3052. if (HAS_PCH_CPT(dev))
  3053. intel_cpt_verify_modeset(dev, intel_crtc->pipe);
  3054. }
  3055. void intel_encoder_noop(struct drm_encoder *encoder)
  3056. {
  3057. }
  3058. void intel_encoder_disable(struct drm_encoder *encoder)
  3059. {
  3060. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  3061. intel_encoder->disable(intel_encoder);
  3062. }
  3063. void intel_encoder_destroy(struct drm_encoder *encoder)
  3064. {
  3065. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  3066. drm_encoder_cleanup(encoder);
  3067. kfree(intel_encoder);
  3068. }
  3069. /* Simple dpms helper for encodres with just one connector, no cloning and only
  3070. * one kind of off state. It clamps all !ON modes to fully OFF and changes the
  3071. * state of the entire output pipe. */
  3072. void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
  3073. {
  3074. if (mode == DRM_MODE_DPMS_ON) {
  3075. encoder->connectors_active = true;
  3076. intel_crtc_update_dpms(encoder->base.crtc);
  3077. } else {
  3078. encoder->connectors_active = false;
  3079. intel_crtc_update_dpms(encoder->base.crtc);
  3080. }
  3081. }
  3082. /* Even simpler default implementation, if there's really no special case to
  3083. * consider. */
  3084. void intel_connector_dpms(struct drm_connector *connector, int mode)
  3085. {
  3086. struct intel_encoder *encoder = intel_attached_encoder(connector);
  3087. /* All the simple cases only support two dpms states. */
  3088. if (mode != DRM_MODE_DPMS_ON)
  3089. mode = DRM_MODE_DPMS_OFF;
  3090. if (mode == connector->dpms)
  3091. return;
  3092. connector->dpms = mode;
  3093. /* Only need to change hw state when actually enabled */
  3094. if (encoder->base.crtc)
  3095. intel_encoder_dpms(encoder, mode);
  3096. else
  3097. encoder->connectors_active = false;
  3098. }
  3099. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  3100. const struct drm_display_mode *mode,
  3101. struct drm_display_mode *adjusted_mode)
  3102. {
  3103. struct drm_device *dev = crtc->dev;
  3104. if (HAS_PCH_SPLIT(dev)) {
  3105. /* FDI link clock is fixed at 2.7G */
  3106. if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
  3107. return false;
  3108. }
  3109. /* All interlaced capable intel hw wants timings in frames. Note though
  3110. * that intel_lvds_mode_fixup does some funny tricks with the crtc
  3111. * timings, so we need to be careful not to clobber these.*/
  3112. if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
  3113. drm_mode_set_crtcinfo(adjusted_mode, 0);
  3114. return true;
  3115. }
  3116. static int valleyview_get_display_clock_speed(struct drm_device *dev)
  3117. {
  3118. return 400000; /* FIXME */
  3119. }
  3120. static int i945_get_display_clock_speed(struct drm_device *dev)
  3121. {
  3122. return 400000;
  3123. }
  3124. static int i915_get_display_clock_speed(struct drm_device *dev)
  3125. {
  3126. return 333000;
  3127. }
  3128. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  3129. {
  3130. return 200000;
  3131. }
  3132. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  3133. {
  3134. u16 gcfgc = 0;
  3135. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3136. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  3137. return 133000;
  3138. else {
  3139. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  3140. case GC_DISPLAY_CLOCK_333_MHZ:
  3141. return 333000;
  3142. default:
  3143. case GC_DISPLAY_CLOCK_190_200_MHZ:
  3144. return 190000;
  3145. }
  3146. }
  3147. }
  3148. static int i865_get_display_clock_speed(struct drm_device *dev)
  3149. {
  3150. return 266000;
  3151. }
  3152. static int i855_get_display_clock_speed(struct drm_device *dev)
  3153. {
  3154. u16 hpllcc = 0;
  3155. /* Assume that the hardware is in the high speed state. This
  3156. * should be the default.
  3157. */
  3158. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  3159. case GC_CLOCK_133_200:
  3160. case GC_CLOCK_100_200:
  3161. return 200000;
  3162. case GC_CLOCK_166_250:
  3163. return 250000;
  3164. case GC_CLOCK_100_133:
  3165. return 133000;
  3166. }
  3167. /* Shouldn't happen */
  3168. return 0;
  3169. }
  3170. static int i830_get_display_clock_speed(struct drm_device *dev)
  3171. {
  3172. return 133000;
  3173. }
  3174. struct fdi_m_n {
  3175. u32 tu;
  3176. u32 gmch_m;
  3177. u32 gmch_n;
  3178. u32 link_m;
  3179. u32 link_n;
  3180. };
  3181. static void
  3182. fdi_reduce_ratio(u32 *num, u32 *den)
  3183. {
  3184. while (*num > 0xffffff || *den > 0xffffff) {
  3185. *num >>= 1;
  3186. *den >>= 1;
  3187. }
  3188. }
  3189. static void
  3190. ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
  3191. int link_clock, struct fdi_m_n *m_n)
  3192. {
  3193. m_n->tu = 64; /* default size */
  3194. /* BUG_ON(pixel_clock > INT_MAX / 36); */
  3195. m_n->gmch_m = bits_per_pixel * pixel_clock;
  3196. m_n->gmch_n = link_clock * nlanes * 8;
  3197. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  3198. m_n->link_m = pixel_clock;
  3199. m_n->link_n = link_clock;
  3200. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  3201. }
  3202. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  3203. {
  3204. if (i915_panel_use_ssc >= 0)
  3205. return i915_panel_use_ssc != 0;
  3206. return dev_priv->lvds_use_ssc
  3207. && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  3208. }
  3209. /**
  3210. * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
  3211. * @crtc: CRTC structure
  3212. * @mode: requested mode
  3213. *
  3214. * A pipe may be connected to one or more outputs. Based on the depth of the
  3215. * attached framebuffer, choose a good color depth to use on the pipe.
  3216. *
  3217. * If possible, match the pipe depth to the fb depth. In some cases, this
  3218. * isn't ideal, because the connected output supports a lesser or restricted
  3219. * set of depths. Resolve that here:
  3220. * LVDS typically supports only 6bpc, so clamp down in that case
  3221. * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
  3222. * Displays may support a restricted set as well, check EDID and clamp as
  3223. * appropriate.
  3224. * DP may want to dither down to 6bpc to fit larger modes
  3225. *
  3226. * RETURNS:
  3227. * Dithering requirement (i.e. false if display bpc and pipe bpc match,
  3228. * true if they don't match).
  3229. */
  3230. static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
  3231. unsigned int *pipe_bpp,
  3232. struct drm_display_mode *mode)
  3233. {
  3234. struct drm_device *dev = crtc->dev;
  3235. struct drm_i915_private *dev_priv = dev->dev_private;
  3236. struct drm_connector *connector;
  3237. struct intel_encoder *intel_encoder;
  3238. unsigned int display_bpc = UINT_MAX, bpc;
  3239. /* Walk the encoders & connectors on this crtc, get min bpc */
  3240. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  3241. if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
  3242. unsigned int lvds_bpc;
  3243. if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
  3244. LVDS_A3_POWER_UP)
  3245. lvds_bpc = 8;
  3246. else
  3247. lvds_bpc = 6;
  3248. if (lvds_bpc < display_bpc) {
  3249. DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
  3250. display_bpc = lvds_bpc;
  3251. }
  3252. continue;
  3253. }
  3254. /* Not one of the known troublemakers, check the EDID */
  3255. list_for_each_entry(connector, &dev->mode_config.connector_list,
  3256. head) {
  3257. if (connector->encoder != &intel_encoder->base)
  3258. continue;
  3259. /* Don't use an invalid EDID bpc value */
  3260. if (connector->display_info.bpc &&
  3261. connector->display_info.bpc < display_bpc) {
  3262. DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
  3263. display_bpc = connector->display_info.bpc;
  3264. }
  3265. }
  3266. /*
  3267. * HDMI is either 12 or 8, so if the display lets 10bpc sneak
  3268. * through, clamp it down. (Note: >12bpc will be caught below.)
  3269. */
  3270. if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
  3271. if (display_bpc > 8 && display_bpc < 12) {
  3272. DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
  3273. display_bpc = 12;
  3274. } else {
  3275. DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
  3276. display_bpc = 8;
  3277. }
  3278. }
  3279. }
  3280. if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
  3281. DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
  3282. display_bpc = 6;
  3283. }
  3284. /*
  3285. * We could just drive the pipe at the highest bpc all the time and
  3286. * enable dithering as needed, but that costs bandwidth. So choose
  3287. * the minimum value that expresses the full color range of the fb but
  3288. * also stays within the max display bpc discovered above.
  3289. */
  3290. switch (crtc->fb->depth) {
  3291. case 8:
  3292. bpc = 8; /* since we go through a colormap */
  3293. break;
  3294. case 15:
  3295. case 16:
  3296. bpc = 6; /* min is 18bpp */
  3297. break;
  3298. case 24:
  3299. bpc = 8;
  3300. break;
  3301. case 30:
  3302. bpc = 10;
  3303. break;
  3304. case 48:
  3305. bpc = 12;
  3306. break;
  3307. default:
  3308. DRM_DEBUG("unsupported depth, assuming 24 bits\n");
  3309. bpc = min((unsigned int)8, display_bpc);
  3310. break;
  3311. }
  3312. display_bpc = min(display_bpc, bpc);
  3313. DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
  3314. bpc, display_bpc);
  3315. *pipe_bpp = display_bpc * 3;
  3316. return display_bpc != bpc;
  3317. }
  3318. static int vlv_get_refclk(struct drm_crtc *crtc)
  3319. {
  3320. struct drm_device *dev = crtc->dev;
  3321. struct drm_i915_private *dev_priv = dev->dev_private;
  3322. int refclk = 27000; /* for DP & HDMI */
  3323. return 100000; /* only one validated so far */
  3324. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  3325. refclk = 96000;
  3326. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  3327. if (intel_panel_use_ssc(dev_priv))
  3328. refclk = 100000;
  3329. else
  3330. refclk = 96000;
  3331. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
  3332. refclk = 100000;
  3333. }
  3334. return refclk;
  3335. }
  3336. static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
  3337. {
  3338. struct drm_device *dev = crtc->dev;
  3339. struct drm_i915_private *dev_priv = dev->dev_private;
  3340. int refclk;
  3341. if (IS_VALLEYVIEW(dev)) {
  3342. refclk = vlv_get_refclk(crtc);
  3343. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3344. intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  3345. refclk = dev_priv->lvds_ssc_freq * 1000;
  3346. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3347. refclk / 1000);
  3348. } else if (!IS_GEN2(dev)) {
  3349. refclk = 96000;
  3350. } else {
  3351. refclk = 48000;
  3352. }
  3353. return refclk;
  3354. }
  3355. static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
  3356. intel_clock_t *clock)
  3357. {
  3358. /* SDVO TV has fixed PLL values depend on its clock range,
  3359. this mirrors vbios setting. */
  3360. if (adjusted_mode->clock >= 100000
  3361. && adjusted_mode->clock < 140500) {
  3362. clock->p1 = 2;
  3363. clock->p2 = 10;
  3364. clock->n = 3;
  3365. clock->m1 = 16;
  3366. clock->m2 = 8;
  3367. } else if (adjusted_mode->clock >= 140500
  3368. && adjusted_mode->clock <= 200000) {
  3369. clock->p1 = 1;
  3370. clock->p2 = 10;
  3371. clock->n = 6;
  3372. clock->m1 = 12;
  3373. clock->m2 = 8;
  3374. }
  3375. }
  3376. static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
  3377. intel_clock_t *clock,
  3378. intel_clock_t *reduced_clock)
  3379. {
  3380. struct drm_device *dev = crtc->dev;
  3381. struct drm_i915_private *dev_priv = dev->dev_private;
  3382. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3383. int pipe = intel_crtc->pipe;
  3384. u32 fp, fp2 = 0;
  3385. if (IS_PINEVIEW(dev)) {
  3386. fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
  3387. if (reduced_clock)
  3388. fp2 = (1 << reduced_clock->n) << 16 |
  3389. reduced_clock->m1 << 8 | reduced_clock->m2;
  3390. } else {
  3391. fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
  3392. if (reduced_clock)
  3393. fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
  3394. reduced_clock->m2;
  3395. }
  3396. I915_WRITE(FP0(pipe), fp);
  3397. intel_crtc->lowfreq_avail = false;
  3398. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3399. reduced_clock && i915_powersave) {
  3400. I915_WRITE(FP1(pipe), fp2);
  3401. intel_crtc->lowfreq_avail = true;
  3402. } else {
  3403. I915_WRITE(FP1(pipe), fp);
  3404. }
  3405. }
  3406. static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
  3407. struct drm_display_mode *adjusted_mode)
  3408. {
  3409. struct drm_device *dev = crtc->dev;
  3410. struct drm_i915_private *dev_priv = dev->dev_private;
  3411. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3412. int pipe = intel_crtc->pipe;
  3413. u32 temp;
  3414. temp = I915_READ(LVDS);
  3415. temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  3416. if (pipe == 1) {
  3417. temp |= LVDS_PIPEB_SELECT;
  3418. } else {
  3419. temp &= ~LVDS_PIPEB_SELECT;
  3420. }
  3421. /* set the corresponsding LVDS_BORDER bit */
  3422. temp |= dev_priv->lvds_border_bits;
  3423. /* Set the B0-B3 data pairs corresponding to whether we're going to
  3424. * set the DPLLs for dual-channel mode or not.
  3425. */
  3426. if (clock->p2 == 7)
  3427. temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  3428. else
  3429. temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  3430. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  3431. * appropriately here, but we need to look more thoroughly into how
  3432. * panels behave in the two modes.
  3433. */
  3434. /* set the dithering flag on LVDS as needed */
  3435. if (INTEL_INFO(dev)->gen >= 4) {
  3436. if (dev_priv->lvds_dither)
  3437. temp |= LVDS_ENABLE_DITHER;
  3438. else
  3439. temp &= ~LVDS_ENABLE_DITHER;
  3440. }
  3441. temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
  3442. if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  3443. temp |= LVDS_HSYNC_POLARITY;
  3444. if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  3445. temp |= LVDS_VSYNC_POLARITY;
  3446. I915_WRITE(LVDS, temp);
  3447. }
  3448. static void vlv_update_pll(struct drm_crtc *crtc,
  3449. struct drm_display_mode *mode,
  3450. struct drm_display_mode *adjusted_mode,
  3451. intel_clock_t *clock, intel_clock_t *reduced_clock,
  3452. int refclk, int num_connectors)
  3453. {
  3454. struct drm_device *dev = crtc->dev;
  3455. struct drm_i915_private *dev_priv = dev->dev_private;
  3456. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3457. int pipe = intel_crtc->pipe;
  3458. u32 dpll, mdiv, pdiv;
  3459. u32 bestn, bestm1, bestm2, bestp1, bestp2;
  3460. bool is_hdmi;
  3461. is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
  3462. bestn = clock->n;
  3463. bestm1 = clock->m1;
  3464. bestm2 = clock->m2;
  3465. bestp1 = clock->p1;
  3466. bestp2 = clock->p2;
  3467. /* Enable DPIO clock input */
  3468. dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
  3469. DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
  3470. I915_WRITE(DPLL(pipe), dpll);
  3471. POSTING_READ(DPLL(pipe));
  3472. mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
  3473. mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
  3474. mdiv |= ((bestn << DPIO_N_SHIFT));
  3475. mdiv |= (1 << DPIO_POST_DIV_SHIFT);
  3476. mdiv |= (1 << DPIO_K_SHIFT);
  3477. mdiv |= DPIO_ENABLE_CALIBRATION;
  3478. intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
  3479. intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
  3480. pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
  3481. (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
  3482. (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
  3483. intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
  3484. intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
  3485. dpll |= DPLL_VCO_ENABLE;
  3486. I915_WRITE(DPLL(pipe), dpll);
  3487. POSTING_READ(DPLL(pipe));
  3488. if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  3489. DRM_ERROR("DPLL %d failed to lock\n", pipe);
  3490. if (is_hdmi) {
  3491. u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
  3492. if (temp > 1)
  3493. temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3494. else
  3495. temp = 0;
  3496. I915_WRITE(DPLL_MD(pipe), temp);
  3497. POSTING_READ(DPLL_MD(pipe));
  3498. }
  3499. intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
  3500. }
  3501. static void i9xx_update_pll(struct drm_crtc *crtc,
  3502. struct drm_display_mode *mode,
  3503. struct drm_display_mode *adjusted_mode,
  3504. intel_clock_t *clock, intel_clock_t *reduced_clock,
  3505. int num_connectors)
  3506. {
  3507. struct drm_device *dev = crtc->dev;
  3508. struct drm_i915_private *dev_priv = dev->dev_private;
  3509. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3510. int pipe = intel_crtc->pipe;
  3511. u32 dpll;
  3512. bool is_sdvo;
  3513. is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
  3514. intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
  3515. dpll = DPLL_VGA_MODE_DIS;
  3516. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  3517. dpll |= DPLLB_MODE_LVDS;
  3518. else
  3519. dpll |= DPLLB_MODE_DAC_SERIAL;
  3520. if (is_sdvo) {
  3521. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  3522. if (pixel_multiplier > 1) {
  3523. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  3524. dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  3525. }
  3526. dpll |= DPLL_DVO_HIGH_SPEED;
  3527. }
  3528. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
  3529. dpll |= DPLL_DVO_HIGH_SPEED;
  3530. /* compute bitmask from p1 value */
  3531. if (IS_PINEVIEW(dev))
  3532. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3533. else {
  3534. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3535. if (IS_G4X(dev) && reduced_clock)
  3536. dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3537. }
  3538. switch (clock->p2) {
  3539. case 5:
  3540. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3541. break;
  3542. case 7:
  3543. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3544. break;
  3545. case 10:
  3546. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3547. break;
  3548. case 14:
  3549. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3550. break;
  3551. }
  3552. if (INTEL_INFO(dev)->gen >= 4)
  3553. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3554. if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
  3555. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3556. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
  3557. /* XXX: just matching BIOS for now */
  3558. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3559. dpll |= 3;
  3560. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3561. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3562. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3563. else
  3564. dpll |= PLL_REF_INPUT_DREFCLK;
  3565. dpll |= DPLL_VCO_ENABLE;
  3566. I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  3567. POSTING_READ(DPLL(pipe));
  3568. udelay(150);
  3569. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  3570. * This is an exception to the general rule that mode_set doesn't turn
  3571. * things on.
  3572. */
  3573. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  3574. intel_update_lvds(crtc, clock, adjusted_mode);
  3575. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
  3576. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  3577. I915_WRITE(DPLL(pipe), dpll);
  3578. /* Wait for the clocks to stabilize. */
  3579. POSTING_READ(DPLL(pipe));
  3580. udelay(150);
  3581. if (INTEL_INFO(dev)->gen >= 4) {
  3582. u32 temp = 0;
  3583. if (is_sdvo) {
  3584. temp = intel_mode_get_pixel_multiplier(adjusted_mode);
  3585. if (temp > 1)
  3586. temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3587. else
  3588. temp = 0;
  3589. }
  3590. I915_WRITE(DPLL_MD(pipe), temp);
  3591. } else {
  3592. /* The pixel multiplier can only be updated once the
  3593. * DPLL is enabled and the clocks are stable.
  3594. *
  3595. * So write it again.
  3596. */
  3597. I915_WRITE(DPLL(pipe), dpll);
  3598. }
  3599. }
  3600. static void i8xx_update_pll(struct drm_crtc *crtc,
  3601. struct drm_display_mode *adjusted_mode,
  3602. intel_clock_t *clock,
  3603. int num_connectors)
  3604. {
  3605. struct drm_device *dev = crtc->dev;
  3606. struct drm_i915_private *dev_priv = dev->dev_private;
  3607. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3608. int pipe = intel_crtc->pipe;
  3609. u32 dpll;
  3610. dpll = DPLL_VGA_MODE_DIS;
  3611. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  3612. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3613. } else {
  3614. if (clock->p1 == 2)
  3615. dpll |= PLL_P1_DIVIDE_BY_TWO;
  3616. else
  3617. dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3618. if (clock->p2 == 4)
  3619. dpll |= PLL_P2_DIVIDE_BY_4;
  3620. }
  3621. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
  3622. /* XXX: just matching BIOS for now */
  3623. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3624. dpll |= 3;
  3625. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3626. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3627. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3628. else
  3629. dpll |= PLL_REF_INPUT_DREFCLK;
  3630. dpll |= DPLL_VCO_ENABLE;
  3631. I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  3632. POSTING_READ(DPLL(pipe));
  3633. udelay(150);
  3634. I915_WRITE(DPLL(pipe), dpll);
  3635. /* Wait for the clocks to stabilize. */
  3636. POSTING_READ(DPLL(pipe));
  3637. udelay(150);
  3638. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  3639. * This is an exception to the general rule that mode_set doesn't turn
  3640. * things on.
  3641. */
  3642. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  3643. intel_update_lvds(crtc, clock, adjusted_mode);
  3644. /* The pixel multiplier can only be updated once the
  3645. * DPLL is enabled and the clocks are stable.
  3646. *
  3647. * So write it again.
  3648. */
  3649. I915_WRITE(DPLL(pipe), dpll);
  3650. }
  3651. static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  3652. struct drm_display_mode *mode,
  3653. struct drm_display_mode *adjusted_mode,
  3654. int x, int y,
  3655. struct drm_framebuffer *old_fb)
  3656. {
  3657. struct drm_device *dev = crtc->dev;
  3658. struct drm_i915_private *dev_priv = dev->dev_private;
  3659. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3660. int pipe = intel_crtc->pipe;
  3661. int plane = intel_crtc->plane;
  3662. int refclk, num_connectors = 0;
  3663. intel_clock_t clock, reduced_clock;
  3664. u32 dspcntr, pipeconf, vsyncshift;
  3665. bool ok, has_reduced_clock = false, is_sdvo = false;
  3666. bool is_lvds = false, is_tv = false, is_dp = false;
  3667. struct intel_encoder *encoder;
  3668. const intel_limit_t *limit;
  3669. int ret;
  3670. for_each_encoder_on_crtc(dev, crtc, encoder) {
  3671. switch (encoder->type) {
  3672. case INTEL_OUTPUT_LVDS:
  3673. is_lvds = true;
  3674. break;
  3675. case INTEL_OUTPUT_SDVO:
  3676. case INTEL_OUTPUT_HDMI:
  3677. is_sdvo = true;
  3678. if (encoder->needs_tv_clock)
  3679. is_tv = true;
  3680. break;
  3681. case INTEL_OUTPUT_TVOUT:
  3682. is_tv = true;
  3683. break;
  3684. case INTEL_OUTPUT_DISPLAYPORT:
  3685. is_dp = true;
  3686. break;
  3687. }
  3688. num_connectors++;
  3689. }
  3690. refclk = i9xx_get_refclk(crtc, num_connectors);
  3691. /*
  3692. * Returns a set of divisors for the desired target clock with the given
  3693. * refclk, or FALSE. The returned values represent the clock equation:
  3694. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  3695. */
  3696. limit = intel_limit(crtc, refclk);
  3697. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
  3698. &clock);
  3699. if (!ok) {
  3700. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  3701. return -EINVAL;
  3702. }
  3703. /* Ensure that the cursor is valid for the new mode before changing... */
  3704. intel_crtc_update_cursor(crtc, true);
  3705. if (is_lvds && dev_priv->lvds_downclock_avail) {
  3706. /*
  3707. * Ensure we match the reduced clock's P to the target clock.
  3708. * If the clocks don't match, we can't switch the display clock
  3709. * by using the FP0/FP1. In such case we will disable the LVDS
  3710. * downclock feature.
  3711. */
  3712. has_reduced_clock = limit->find_pll(limit, crtc,
  3713. dev_priv->lvds_downclock,
  3714. refclk,
  3715. &clock,
  3716. &reduced_clock);
  3717. }
  3718. if (is_sdvo && is_tv)
  3719. i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
  3720. i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
  3721. &reduced_clock : NULL);
  3722. if (IS_GEN2(dev))
  3723. i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
  3724. else if (IS_VALLEYVIEW(dev))
  3725. vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
  3726. refclk, num_connectors);
  3727. else
  3728. i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
  3729. has_reduced_clock ? &reduced_clock : NULL,
  3730. num_connectors);
  3731. /* setup pipeconf */
  3732. pipeconf = I915_READ(PIPECONF(pipe));
  3733. /* Set up the display plane register */
  3734. dspcntr = DISPPLANE_GAMMA_ENABLE;
  3735. if (pipe == 0)
  3736. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  3737. else
  3738. dspcntr |= DISPPLANE_SEL_PIPE_B;
  3739. if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
  3740. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  3741. * core speed.
  3742. *
  3743. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  3744. * pipe == 0 check?
  3745. */
  3746. if (mode->clock >
  3747. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  3748. pipeconf |= PIPECONF_DOUBLE_WIDE;
  3749. else
  3750. pipeconf &= ~PIPECONF_DOUBLE_WIDE;
  3751. }
  3752. /* default to 8bpc */
  3753. pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
  3754. if (is_dp) {
  3755. if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
  3756. pipeconf |= PIPECONF_BPP_6 |
  3757. PIPECONF_DITHER_EN |
  3758. PIPECONF_DITHER_TYPE_SP;
  3759. }
  3760. }
  3761. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  3762. drm_mode_debug_printmodeline(mode);
  3763. if (HAS_PIPE_CXSR(dev)) {
  3764. if (intel_crtc->lowfreq_avail) {
  3765. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  3766. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  3767. } else {
  3768. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  3769. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  3770. }
  3771. }
  3772. pipeconf &= ~PIPECONF_INTERLACE_MASK;
  3773. if (!IS_GEN2(dev) &&
  3774. adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  3775. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  3776. /* the chip adds 2 halflines automatically */
  3777. adjusted_mode->crtc_vtotal -= 1;
  3778. adjusted_mode->crtc_vblank_end -= 1;
  3779. vsyncshift = adjusted_mode->crtc_hsync_start
  3780. - adjusted_mode->crtc_htotal/2;
  3781. } else {
  3782. pipeconf |= PIPECONF_PROGRESSIVE;
  3783. vsyncshift = 0;
  3784. }
  3785. if (!IS_GEN3(dev))
  3786. I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
  3787. I915_WRITE(HTOTAL(pipe),
  3788. (adjusted_mode->crtc_hdisplay - 1) |
  3789. ((adjusted_mode->crtc_htotal - 1) << 16));
  3790. I915_WRITE(HBLANK(pipe),
  3791. (adjusted_mode->crtc_hblank_start - 1) |
  3792. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  3793. I915_WRITE(HSYNC(pipe),
  3794. (adjusted_mode->crtc_hsync_start - 1) |
  3795. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  3796. I915_WRITE(VTOTAL(pipe),
  3797. (adjusted_mode->crtc_vdisplay - 1) |
  3798. ((adjusted_mode->crtc_vtotal - 1) << 16));
  3799. I915_WRITE(VBLANK(pipe),
  3800. (adjusted_mode->crtc_vblank_start - 1) |
  3801. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  3802. I915_WRITE(VSYNC(pipe),
  3803. (adjusted_mode->crtc_vsync_start - 1) |
  3804. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  3805. /* pipesrc and dspsize control the size that is scaled from,
  3806. * which should always be the user's requested size.
  3807. */
  3808. I915_WRITE(DSPSIZE(plane),
  3809. ((mode->vdisplay - 1) << 16) |
  3810. (mode->hdisplay - 1));
  3811. I915_WRITE(DSPPOS(plane), 0);
  3812. I915_WRITE(PIPESRC(pipe),
  3813. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  3814. I915_WRITE(PIPECONF(pipe), pipeconf);
  3815. POSTING_READ(PIPECONF(pipe));
  3816. intel_enable_pipe(dev_priv, pipe, false);
  3817. intel_wait_for_vblank(dev, pipe);
  3818. I915_WRITE(DSPCNTR(plane), dspcntr);
  3819. POSTING_READ(DSPCNTR(plane));
  3820. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  3821. intel_update_watermarks(dev);
  3822. return ret;
  3823. }
  3824. /*
  3825. * Initialize reference clocks when the driver loads
  3826. */
  3827. void ironlake_init_pch_refclk(struct drm_device *dev)
  3828. {
  3829. struct drm_i915_private *dev_priv = dev->dev_private;
  3830. struct drm_mode_config *mode_config = &dev->mode_config;
  3831. struct intel_encoder *encoder;
  3832. u32 temp;
  3833. bool has_lvds = false;
  3834. bool has_cpu_edp = false;
  3835. bool has_pch_edp = false;
  3836. bool has_panel = false;
  3837. bool has_ck505 = false;
  3838. bool can_ssc = false;
  3839. /* We need to take the global config into account */
  3840. list_for_each_entry(encoder, &mode_config->encoder_list,
  3841. base.head) {
  3842. switch (encoder->type) {
  3843. case INTEL_OUTPUT_LVDS:
  3844. has_panel = true;
  3845. has_lvds = true;
  3846. break;
  3847. case INTEL_OUTPUT_EDP:
  3848. has_panel = true;
  3849. if (intel_encoder_is_pch_edp(&encoder->base))
  3850. has_pch_edp = true;
  3851. else
  3852. has_cpu_edp = true;
  3853. break;
  3854. }
  3855. }
  3856. if (HAS_PCH_IBX(dev)) {
  3857. has_ck505 = dev_priv->display_clock_mode;
  3858. can_ssc = has_ck505;
  3859. } else {
  3860. has_ck505 = false;
  3861. can_ssc = true;
  3862. }
  3863. DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
  3864. has_panel, has_lvds, has_pch_edp, has_cpu_edp,
  3865. has_ck505);
  3866. /* Ironlake: try to setup display ref clock before DPLL
  3867. * enabling. This is only under driver's control after
  3868. * PCH B stepping, previous chipset stepping should be
  3869. * ignoring this setting.
  3870. */
  3871. temp = I915_READ(PCH_DREF_CONTROL);
  3872. /* Always enable nonspread source */
  3873. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  3874. if (has_ck505)
  3875. temp |= DREF_NONSPREAD_CK505_ENABLE;
  3876. else
  3877. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  3878. if (has_panel) {
  3879. temp &= ~DREF_SSC_SOURCE_MASK;
  3880. temp |= DREF_SSC_SOURCE_ENABLE;
  3881. /* SSC must be turned on before enabling the CPU output */
  3882. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  3883. DRM_DEBUG_KMS("Using SSC on panel\n");
  3884. temp |= DREF_SSC1_ENABLE;
  3885. } else
  3886. temp &= ~DREF_SSC1_ENABLE;
  3887. /* Get SSC going before enabling the outputs */
  3888. I915_WRITE(PCH_DREF_CONTROL, temp);
  3889. POSTING_READ(PCH_DREF_CONTROL);
  3890. udelay(200);
  3891. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  3892. /* Enable CPU source on CPU attached eDP */
  3893. if (has_cpu_edp) {
  3894. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  3895. DRM_DEBUG_KMS("Using SSC on eDP\n");
  3896. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  3897. }
  3898. else
  3899. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  3900. } else
  3901. temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  3902. I915_WRITE(PCH_DREF_CONTROL, temp);
  3903. POSTING_READ(PCH_DREF_CONTROL);
  3904. udelay(200);
  3905. } else {
  3906. DRM_DEBUG_KMS("Disabling SSC entirely\n");
  3907. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  3908. /* Turn off CPU output */
  3909. temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  3910. I915_WRITE(PCH_DREF_CONTROL, temp);
  3911. POSTING_READ(PCH_DREF_CONTROL);
  3912. udelay(200);
  3913. /* Turn off the SSC source */
  3914. temp &= ~DREF_SSC_SOURCE_MASK;
  3915. temp |= DREF_SSC_SOURCE_DISABLE;
  3916. /* Turn off SSC1 */
  3917. temp &= ~ DREF_SSC1_ENABLE;
  3918. I915_WRITE(PCH_DREF_CONTROL, temp);
  3919. POSTING_READ(PCH_DREF_CONTROL);
  3920. udelay(200);
  3921. }
  3922. }
  3923. static int ironlake_get_refclk(struct drm_crtc *crtc)
  3924. {
  3925. struct drm_device *dev = crtc->dev;
  3926. struct drm_i915_private *dev_priv = dev->dev_private;
  3927. struct intel_encoder *encoder;
  3928. struct intel_encoder *edp_encoder = NULL;
  3929. int num_connectors = 0;
  3930. bool is_lvds = false;
  3931. for_each_encoder_on_crtc(dev, crtc, encoder) {
  3932. switch (encoder->type) {
  3933. case INTEL_OUTPUT_LVDS:
  3934. is_lvds = true;
  3935. break;
  3936. case INTEL_OUTPUT_EDP:
  3937. edp_encoder = encoder;
  3938. break;
  3939. }
  3940. num_connectors++;
  3941. }
  3942. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  3943. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3944. dev_priv->lvds_ssc_freq);
  3945. return dev_priv->lvds_ssc_freq * 1000;
  3946. }
  3947. return 120000;
  3948. }
  3949. static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  3950. struct drm_display_mode *mode,
  3951. struct drm_display_mode *adjusted_mode,
  3952. int x, int y,
  3953. struct drm_framebuffer *old_fb)
  3954. {
  3955. struct drm_device *dev = crtc->dev;
  3956. struct drm_i915_private *dev_priv = dev->dev_private;
  3957. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3958. int pipe = intel_crtc->pipe;
  3959. int plane = intel_crtc->plane;
  3960. int refclk, num_connectors = 0;
  3961. intel_clock_t clock, reduced_clock;
  3962. u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
  3963. bool ok, has_reduced_clock = false, is_sdvo = false;
  3964. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  3965. struct intel_encoder *encoder, *edp_encoder = NULL;
  3966. const intel_limit_t *limit;
  3967. int ret;
  3968. struct fdi_m_n m_n = {0};
  3969. u32 temp;
  3970. int target_clock, pixel_multiplier, lane, link_bw, factor;
  3971. unsigned int pipe_bpp;
  3972. bool dither;
  3973. bool is_cpu_edp = false, is_pch_edp = false;
  3974. for_each_encoder_on_crtc(dev, crtc, encoder) {
  3975. switch (encoder->type) {
  3976. case INTEL_OUTPUT_LVDS:
  3977. is_lvds = true;
  3978. break;
  3979. case INTEL_OUTPUT_SDVO:
  3980. case INTEL_OUTPUT_HDMI:
  3981. is_sdvo = true;
  3982. if (encoder->needs_tv_clock)
  3983. is_tv = true;
  3984. break;
  3985. case INTEL_OUTPUT_TVOUT:
  3986. is_tv = true;
  3987. break;
  3988. case INTEL_OUTPUT_ANALOG:
  3989. is_crt = true;
  3990. break;
  3991. case INTEL_OUTPUT_DISPLAYPORT:
  3992. is_dp = true;
  3993. break;
  3994. case INTEL_OUTPUT_EDP:
  3995. is_dp = true;
  3996. if (intel_encoder_is_pch_edp(&encoder->base))
  3997. is_pch_edp = true;
  3998. else
  3999. is_cpu_edp = true;
  4000. edp_encoder = encoder;
  4001. break;
  4002. }
  4003. num_connectors++;
  4004. }
  4005. refclk = ironlake_get_refclk(crtc);
  4006. /*
  4007. * Returns a set of divisors for the desired target clock with the given
  4008. * refclk, or FALSE. The returned values represent the clock equation:
  4009. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4010. */
  4011. limit = intel_limit(crtc, refclk);
  4012. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
  4013. &clock);
  4014. if (!ok) {
  4015. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4016. return -EINVAL;
  4017. }
  4018. /* Ensure that the cursor is valid for the new mode before changing... */
  4019. intel_crtc_update_cursor(crtc, true);
  4020. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4021. /*
  4022. * Ensure we match the reduced clock's P to the target clock.
  4023. * If the clocks don't match, we can't switch the display clock
  4024. * by using the FP0/FP1. In such case we will disable the LVDS
  4025. * downclock feature.
  4026. */
  4027. has_reduced_clock = limit->find_pll(limit, crtc,
  4028. dev_priv->lvds_downclock,
  4029. refclk,
  4030. &clock,
  4031. &reduced_clock);
  4032. }
  4033. if (is_sdvo && is_tv)
  4034. i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
  4035. /* FDI link */
  4036. pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4037. lane = 0;
  4038. /* CPU eDP doesn't require FDI link, so just set DP M/N
  4039. according to current link config */
  4040. if (is_cpu_edp) {
  4041. intel_edp_link_config(edp_encoder, &lane, &link_bw);
  4042. } else {
  4043. /* FDI is a binary signal running at ~2.7GHz, encoding
  4044. * each output octet as 10 bits. The actual frequency
  4045. * is stored as a divider into a 100MHz clock, and the
  4046. * mode pixel clock is stored in units of 1KHz.
  4047. * Hence the bw of each lane in terms of the mode signal
  4048. * is:
  4049. */
  4050. link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  4051. }
  4052. /* [e]DP over FDI requires target mode clock instead of link clock. */
  4053. if (edp_encoder)
  4054. target_clock = intel_edp_target_clock(edp_encoder, mode);
  4055. else if (is_dp)
  4056. target_clock = mode->clock;
  4057. else
  4058. target_clock = adjusted_mode->clock;
  4059. /* determine panel color depth */
  4060. temp = I915_READ(PIPECONF(pipe));
  4061. temp &= ~PIPE_BPC_MASK;
  4062. dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
  4063. switch (pipe_bpp) {
  4064. case 18:
  4065. temp |= PIPE_6BPC;
  4066. break;
  4067. case 24:
  4068. temp |= PIPE_8BPC;
  4069. break;
  4070. case 30:
  4071. temp |= PIPE_10BPC;
  4072. break;
  4073. case 36:
  4074. temp |= PIPE_12BPC;
  4075. break;
  4076. default:
  4077. WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
  4078. pipe_bpp);
  4079. temp |= PIPE_8BPC;
  4080. pipe_bpp = 24;
  4081. break;
  4082. }
  4083. intel_crtc->bpp = pipe_bpp;
  4084. I915_WRITE(PIPECONF(pipe), temp);
  4085. if (!lane) {
  4086. /*
  4087. * Account for spread spectrum to avoid
  4088. * oversubscribing the link. Max center spread
  4089. * is 2.5%; use 5% for safety's sake.
  4090. */
  4091. u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
  4092. lane = bps / (link_bw * 8) + 1;
  4093. }
  4094. intel_crtc->fdi_lanes = lane;
  4095. if (pixel_multiplier > 1)
  4096. link_bw *= pixel_multiplier;
  4097. ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
  4098. &m_n);
  4099. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  4100. if (has_reduced_clock)
  4101. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  4102. reduced_clock.m2;
  4103. /* Enable autotuning of the PLL clock (if permissible) */
  4104. factor = 21;
  4105. if (is_lvds) {
  4106. if ((intel_panel_use_ssc(dev_priv) &&
  4107. dev_priv->lvds_ssc_freq == 100) ||
  4108. (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
  4109. factor = 25;
  4110. } else if (is_sdvo && is_tv)
  4111. factor = 20;
  4112. if (clock.m < factor * clock.n)
  4113. fp |= FP_CB_TUNE;
  4114. dpll = 0;
  4115. if (is_lvds)
  4116. dpll |= DPLLB_MODE_LVDS;
  4117. else
  4118. dpll |= DPLLB_MODE_DAC_SERIAL;
  4119. if (is_sdvo) {
  4120. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4121. if (pixel_multiplier > 1) {
  4122. dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  4123. }
  4124. dpll |= DPLL_DVO_HIGH_SPEED;
  4125. }
  4126. if (is_dp && !is_cpu_edp)
  4127. dpll |= DPLL_DVO_HIGH_SPEED;
  4128. /* compute bitmask from p1 value */
  4129. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4130. /* also FPA1 */
  4131. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4132. switch (clock.p2) {
  4133. case 5:
  4134. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4135. break;
  4136. case 7:
  4137. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4138. break;
  4139. case 10:
  4140. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4141. break;
  4142. case 14:
  4143. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4144. break;
  4145. }
  4146. if (is_sdvo && is_tv)
  4147. dpll |= PLL_REF_INPUT_TVCLKINBC;
  4148. else if (is_tv)
  4149. /* XXX: just matching BIOS for now */
  4150. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  4151. dpll |= 3;
  4152. else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4153. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4154. else
  4155. dpll |= PLL_REF_INPUT_DREFCLK;
  4156. /* setup pipeconf */
  4157. pipeconf = I915_READ(PIPECONF(pipe));
  4158. /* Set up the display plane register */
  4159. dspcntr = DISPPLANE_GAMMA_ENABLE;
  4160. DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
  4161. drm_mode_debug_printmodeline(mode);
  4162. /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
  4163. * pre-Haswell/LPT generation */
  4164. if (HAS_PCH_LPT(dev)) {
  4165. DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
  4166. pipe);
  4167. } else if (!is_cpu_edp) {
  4168. struct intel_pch_pll *pll;
  4169. pll = intel_get_pch_pll(intel_crtc, dpll, fp);
  4170. if (pll == NULL) {
  4171. DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
  4172. pipe);
  4173. return -EINVAL;
  4174. }
  4175. } else
  4176. intel_put_pch_pll(intel_crtc);
  4177. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  4178. * This is an exception to the general rule that mode_set doesn't turn
  4179. * things on.
  4180. */
  4181. if (is_lvds) {
  4182. temp = I915_READ(PCH_LVDS);
  4183. temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  4184. if (HAS_PCH_CPT(dev)) {
  4185. temp &= ~PORT_TRANS_SEL_MASK;
  4186. temp |= PORT_TRANS_SEL_CPT(pipe);
  4187. } else {
  4188. if (pipe == 1)
  4189. temp |= LVDS_PIPEB_SELECT;
  4190. else
  4191. temp &= ~LVDS_PIPEB_SELECT;
  4192. }
  4193. /* set the corresponsding LVDS_BORDER bit */
  4194. temp |= dev_priv->lvds_border_bits;
  4195. /* Set the B0-B3 data pairs corresponding to whether we're going to
  4196. * set the DPLLs for dual-channel mode or not.
  4197. */
  4198. if (clock.p2 == 7)
  4199. temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  4200. else
  4201. temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  4202. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  4203. * appropriately here, but we need to look more thoroughly into how
  4204. * panels behave in the two modes.
  4205. */
  4206. temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
  4207. if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  4208. temp |= LVDS_HSYNC_POLARITY;
  4209. if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  4210. temp |= LVDS_VSYNC_POLARITY;
  4211. I915_WRITE(PCH_LVDS, temp);
  4212. }
  4213. pipeconf &= ~PIPECONF_DITHER_EN;
  4214. pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
  4215. if ((is_lvds && dev_priv->lvds_dither) || dither) {
  4216. pipeconf |= PIPECONF_DITHER_EN;
  4217. pipeconf |= PIPECONF_DITHER_TYPE_SP;
  4218. }
  4219. if (is_dp && !is_cpu_edp) {
  4220. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  4221. } else {
  4222. /* For non-DP output, clear any trans DP clock recovery setting.*/
  4223. I915_WRITE(TRANSDATA_M1(pipe), 0);
  4224. I915_WRITE(TRANSDATA_N1(pipe), 0);
  4225. I915_WRITE(TRANSDPLINK_M1(pipe), 0);
  4226. I915_WRITE(TRANSDPLINK_N1(pipe), 0);
  4227. }
  4228. if (intel_crtc->pch_pll) {
  4229. I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
  4230. /* Wait for the clocks to stabilize. */
  4231. POSTING_READ(intel_crtc->pch_pll->pll_reg);
  4232. udelay(150);
  4233. /* The pixel multiplier can only be updated once the
  4234. * DPLL is enabled and the clocks are stable.
  4235. *
  4236. * So write it again.
  4237. */
  4238. I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
  4239. }
  4240. intel_crtc->lowfreq_avail = false;
  4241. if (intel_crtc->pch_pll) {
  4242. if (is_lvds && has_reduced_clock && i915_powersave) {
  4243. I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
  4244. intel_crtc->lowfreq_avail = true;
  4245. } else {
  4246. I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
  4247. }
  4248. }
  4249. pipeconf &= ~PIPECONF_INTERLACE_MASK;
  4250. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  4251. pipeconf |= PIPECONF_INTERLACED_ILK;
  4252. /* the chip adds 2 halflines automatically */
  4253. adjusted_mode->crtc_vtotal -= 1;
  4254. adjusted_mode->crtc_vblank_end -= 1;
  4255. I915_WRITE(VSYNCSHIFT(pipe),
  4256. adjusted_mode->crtc_hsync_start
  4257. - adjusted_mode->crtc_htotal/2);
  4258. } else {
  4259. pipeconf |= PIPECONF_PROGRESSIVE;
  4260. I915_WRITE(VSYNCSHIFT(pipe), 0);
  4261. }
  4262. I915_WRITE(HTOTAL(pipe),
  4263. (adjusted_mode->crtc_hdisplay - 1) |
  4264. ((adjusted_mode->crtc_htotal - 1) << 16));
  4265. I915_WRITE(HBLANK(pipe),
  4266. (adjusted_mode->crtc_hblank_start - 1) |
  4267. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  4268. I915_WRITE(HSYNC(pipe),
  4269. (adjusted_mode->crtc_hsync_start - 1) |
  4270. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  4271. I915_WRITE(VTOTAL(pipe),
  4272. (adjusted_mode->crtc_vdisplay - 1) |
  4273. ((adjusted_mode->crtc_vtotal - 1) << 16));
  4274. I915_WRITE(VBLANK(pipe),
  4275. (adjusted_mode->crtc_vblank_start - 1) |
  4276. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  4277. I915_WRITE(VSYNC(pipe),
  4278. (adjusted_mode->crtc_vsync_start - 1) |
  4279. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  4280. /* pipesrc controls the size that is scaled from, which should
  4281. * always be the user's requested size.
  4282. */
  4283. I915_WRITE(PIPESRC(pipe),
  4284. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  4285. I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
  4286. I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
  4287. I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
  4288. I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
  4289. if (is_cpu_edp)
  4290. ironlake_set_pll_edp(crtc, adjusted_mode->clock);
  4291. I915_WRITE(PIPECONF(pipe), pipeconf);
  4292. POSTING_READ(PIPECONF(pipe));
  4293. intel_wait_for_vblank(dev, pipe);
  4294. I915_WRITE(DSPCNTR(plane), dspcntr);
  4295. POSTING_READ(DSPCNTR(plane));
  4296. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  4297. intel_update_watermarks(dev);
  4298. intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
  4299. return ret;
  4300. }
  4301. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  4302. struct drm_display_mode *mode,
  4303. struct drm_display_mode *adjusted_mode,
  4304. int x, int y,
  4305. struct drm_framebuffer *old_fb)
  4306. {
  4307. struct drm_device *dev = crtc->dev;
  4308. struct drm_i915_private *dev_priv = dev->dev_private;
  4309. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4310. int pipe = intel_crtc->pipe;
  4311. int ret;
  4312. drm_vblank_pre_modeset(dev, pipe);
  4313. ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
  4314. x, y, old_fb);
  4315. drm_vblank_post_modeset(dev, pipe);
  4316. if (ret)
  4317. intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
  4318. else
  4319. intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
  4320. return ret;
  4321. }
  4322. static bool intel_eld_uptodate(struct drm_connector *connector,
  4323. int reg_eldv, uint32_t bits_eldv,
  4324. int reg_elda, uint32_t bits_elda,
  4325. int reg_edid)
  4326. {
  4327. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  4328. uint8_t *eld = connector->eld;
  4329. uint32_t i;
  4330. i = I915_READ(reg_eldv);
  4331. i &= bits_eldv;
  4332. if (!eld[0])
  4333. return !i;
  4334. if (!i)
  4335. return false;
  4336. i = I915_READ(reg_elda);
  4337. i &= ~bits_elda;
  4338. I915_WRITE(reg_elda, i);
  4339. for (i = 0; i < eld[2]; i++)
  4340. if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  4341. return false;
  4342. return true;
  4343. }
  4344. static void g4x_write_eld(struct drm_connector *connector,
  4345. struct drm_crtc *crtc)
  4346. {
  4347. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  4348. uint8_t *eld = connector->eld;
  4349. uint32_t eldv;
  4350. uint32_t len;
  4351. uint32_t i;
  4352. i = I915_READ(G4X_AUD_VID_DID);
  4353. if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
  4354. eldv = G4X_ELDV_DEVCL_DEVBLC;
  4355. else
  4356. eldv = G4X_ELDV_DEVCTG;
  4357. if (intel_eld_uptodate(connector,
  4358. G4X_AUD_CNTL_ST, eldv,
  4359. G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
  4360. G4X_HDMIW_HDMIEDID))
  4361. return;
  4362. i = I915_READ(G4X_AUD_CNTL_ST);
  4363. i &= ~(eldv | G4X_ELD_ADDR);
  4364. len = (i >> 9) & 0x1f; /* ELD buffer size */
  4365. I915_WRITE(G4X_AUD_CNTL_ST, i);
  4366. if (!eld[0])
  4367. return;
  4368. len = min_t(uint8_t, eld[2], len);
  4369. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  4370. for (i = 0; i < len; i++)
  4371. I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
  4372. i = I915_READ(G4X_AUD_CNTL_ST);
  4373. i |= eldv;
  4374. I915_WRITE(G4X_AUD_CNTL_ST, i);
  4375. }
  4376. static void haswell_write_eld(struct drm_connector *connector,
  4377. struct drm_crtc *crtc)
  4378. {
  4379. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  4380. uint8_t *eld = connector->eld;
  4381. struct drm_device *dev = crtc->dev;
  4382. uint32_t eldv;
  4383. uint32_t i;
  4384. int len;
  4385. int pipe = to_intel_crtc(crtc)->pipe;
  4386. int tmp;
  4387. int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
  4388. int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
  4389. int aud_config = HSW_AUD_CFG(pipe);
  4390. int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
  4391. DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
  4392. /* Audio output enable */
  4393. DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
  4394. tmp = I915_READ(aud_cntrl_st2);
  4395. tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
  4396. I915_WRITE(aud_cntrl_st2, tmp);
  4397. /* Wait for 1 vertical blank */
  4398. intel_wait_for_vblank(dev, pipe);
  4399. /* Set ELD valid state */
  4400. tmp = I915_READ(aud_cntrl_st2);
  4401. DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
  4402. tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
  4403. I915_WRITE(aud_cntrl_st2, tmp);
  4404. tmp = I915_READ(aud_cntrl_st2);
  4405. DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
  4406. /* Enable HDMI mode */
  4407. tmp = I915_READ(aud_config);
  4408. DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
  4409. /* clear N_programing_enable and N_value_index */
  4410. tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
  4411. I915_WRITE(aud_config, tmp);
  4412. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  4413. eldv = AUDIO_ELD_VALID_A << (pipe * 4);
  4414. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  4415. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  4416. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  4417. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  4418. } else
  4419. I915_WRITE(aud_config, 0);
  4420. if (intel_eld_uptodate(connector,
  4421. aud_cntrl_st2, eldv,
  4422. aud_cntl_st, IBX_ELD_ADDRESS,
  4423. hdmiw_hdmiedid))
  4424. return;
  4425. i = I915_READ(aud_cntrl_st2);
  4426. i &= ~eldv;
  4427. I915_WRITE(aud_cntrl_st2, i);
  4428. if (!eld[0])
  4429. return;
  4430. i = I915_READ(aud_cntl_st);
  4431. i &= ~IBX_ELD_ADDRESS;
  4432. I915_WRITE(aud_cntl_st, i);
  4433. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  4434. DRM_DEBUG_DRIVER("port num:%d\n", i);
  4435. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  4436. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  4437. for (i = 0; i < len; i++)
  4438. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  4439. i = I915_READ(aud_cntrl_st2);
  4440. i |= eldv;
  4441. I915_WRITE(aud_cntrl_st2, i);
  4442. }
  4443. static void ironlake_write_eld(struct drm_connector *connector,
  4444. struct drm_crtc *crtc)
  4445. {
  4446. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  4447. uint8_t *eld = connector->eld;
  4448. uint32_t eldv;
  4449. uint32_t i;
  4450. int len;
  4451. int hdmiw_hdmiedid;
  4452. int aud_config;
  4453. int aud_cntl_st;
  4454. int aud_cntrl_st2;
  4455. int pipe = to_intel_crtc(crtc)->pipe;
  4456. if (HAS_PCH_IBX(connector->dev)) {
  4457. hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
  4458. aud_config = IBX_AUD_CFG(pipe);
  4459. aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
  4460. aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
  4461. } else {
  4462. hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
  4463. aud_config = CPT_AUD_CFG(pipe);
  4464. aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
  4465. aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
  4466. }
  4467. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  4468. i = I915_READ(aud_cntl_st);
  4469. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  4470. if (!i) {
  4471. DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
  4472. /* operate blindly on all ports */
  4473. eldv = IBX_ELD_VALIDB;
  4474. eldv |= IBX_ELD_VALIDB << 4;
  4475. eldv |= IBX_ELD_VALIDB << 8;
  4476. } else {
  4477. DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
  4478. eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
  4479. }
  4480. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  4481. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  4482. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  4483. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  4484. } else
  4485. I915_WRITE(aud_config, 0);
  4486. if (intel_eld_uptodate(connector,
  4487. aud_cntrl_st2, eldv,
  4488. aud_cntl_st, IBX_ELD_ADDRESS,
  4489. hdmiw_hdmiedid))
  4490. return;
  4491. i = I915_READ(aud_cntrl_st2);
  4492. i &= ~eldv;
  4493. I915_WRITE(aud_cntrl_st2, i);
  4494. if (!eld[0])
  4495. return;
  4496. i = I915_READ(aud_cntl_st);
  4497. i &= ~IBX_ELD_ADDRESS;
  4498. I915_WRITE(aud_cntl_st, i);
  4499. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  4500. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  4501. for (i = 0; i < len; i++)
  4502. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  4503. i = I915_READ(aud_cntrl_st2);
  4504. i |= eldv;
  4505. I915_WRITE(aud_cntrl_st2, i);
  4506. }
  4507. void intel_write_eld(struct drm_encoder *encoder,
  4508. struct drm_display_mode *mode)
  4509. {
  4510. struct drm_crtc *crtc = encoder->crtc;
  4511. struct drm_connector *connector;
  4512. struct drm_device *dev = encoder->dev;
  4513. struct drm_i915_private *dev_priv = dev->dev_private;
  4514. connector = drm_select_eld(encoder, mode);
  4515. if (!connector)
  4516. return;
  4517. DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  4518. connector->base.id,
  4519. drm_get_connector_name(connector),
  4520. connector->encoder->base.id,
  4521. drm_get_encoder_name(connector->encoder));
  4522. connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
  4523. if (dev_priv->display.write_eld)
  4524. dev_priv->display.write_eld(connector, crtc);
  4525. }
  4526. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  4527. void intel_crtc_load_lut(struct drm_crtc *crtc)
  4528. {
  4529. struct drm_device *dev = crtc->dev;
  4530. struct drm_i915_private *dev_priv = dev->dev_private;
  4531. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4532. int palreg = PALETTE(intel_crtc->pipe);
  4533. int i;
  4534. /* The clocks have to be on to load the palette. */
  4535. if (!crtc->enabled || !intel_crtc->active)
  4536. return;
  4537. /* use legacy palette for Ironlake */
  4538. if (HAS_PCH_SPLIT(dev))
  4539. palreg = LGC_PALETTE(intel_crtc->pipe);
  4540. for (i = 0; i < 256; i++) {
  4541. I915_WRITE(palreg + 4 * i,
  4542. (intel_crtc->lut_r[i] << 16) |
  4543. (intel_crtc->lut_g[i] << 8) |
  4544. intel_crtc->lut_b[i]);
  4545. }
  4546. }
  4547. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  4548. {
  4549. struct drm_device *dev = crtc->dev;
  4550. struct drm_i915_private *dev_priv = dev->dev_private;
  4551. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4552. bool visible = base != 0;
  4553. u32 cntl;
  4554. if (intel_crtc->cursor_visible == visible)
  4555. return;
  4556. cntl = I915_READ(_CURACNTR);
  4557. if (visible) {
  4558. /* On these chipsets we can only modify the base whilst
  4559. * the cursor is disabled.
  4560. */
  4561. I915_WRITE(_CURABASE, base);
  4562. cntl &= ~(CURSOR_FORMAT_MASK);
  4563. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  4564. cntl |= CURSOR_ENABLE |
  4565. CURSOR_GAMMA_ENABLE |
  4566. CURSOR_FORMAT_ARGB;
  4567. } else
  4568. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  4569. I915_WRITE(_CURACNTR, cntl);
  4570. intel_crtc->cursor_visible = visible;
  4571. }
  4572. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  4573. {
  4574. struct drm_device *dev = crtc->dev;
  4575. struct drm_i915_private *dev_priv = dev->dev_private;
  4576. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4577. int pipe = intel_crtc->pipe;
  4578. bool visible = base != 0;
  4579. if (intel_crtc->cursor_visible != visible) {
  4580. uint32_t cntl = I915_READ(CURCNTR(pipe));
  4581. if (base) {
  4582. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  4583. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  4584. cntl |= pipe << 28; /* Connect to correct pipe */
  4585. } else {
  4586. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  4587. cntl |= CURSOR_MODE_DISABLE;
  4588. }
  4589. I915_WRITE(CURCNTR(pipe), cntl);
  4590. intel_crtc->cursor_visible = visible;
  4591. }
  4592. /* and commit changes on next vblank */
  4593. I915_WRITE(CURBASE(pipe), base);
  4594. }
  4595. static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
  4596. {
  4597. struct drm_device *dev = crtc->dev;
  4598. struct drm_i915_private *dev_priv = dev->dev_private;
  4599. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4600. int pipe = intel_crtc->pipe;
  4601. bool visible = base != 0;
  4602. if (intel_crtc->cursor_visible != visible) {
  4603. uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
  4604. if (base) {
  4605. cntl &= ~CURSOR_MODE;
  4606. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  4607. } else {
  4608. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  4609. cntl |= CURSOR_MODE_DISABLE;
  4610. }
  4611. I915_WRITE(CURCNTR_IVB(pipe), cntl);
  4612. intel_crtc->cursor_visible = visible;
  4613. }
  4614. /* and commit changes on next vblank */
  4615. I915_WRITE(CURBASE_IVB(pipe), base);
  4616. }
  4617. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  4618. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  4619. bool on)
  4620. {
  4621. struct drm_device *dev = crtc->dev;
  4622. struct drm_i915_private *dev_priv = dev->dev_private;
  4623. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4624. int pipe = intel_crtc->pipe;
  4625. int x = intel_crtc->cursor_x;
  4626. int y = intel_crtc->cursor_y;
  4627. u32 base, pos;
  4628. bool visible;
  4629. pos = 0;
  4630. if (on && crtc->enabled && crtc->fb) {
  4631. base = intel_crtc->cursor_addr;
  4632. if (x > (int) crtc->fb->width)
  4633. base = 0;
  4634. if (y > (int) crtc->fb->height)
  4635. base = 0;
  4636. } else
  4637. base = 0;
  4638. if (x < 0) {
  4639. if (x + intel_crtc->cursor_width < 0)
  4640. base = 0;
  4641. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  4642. x = -x;
  4643. }
  4644. pos |= x << CURSOR_X_SHIFT;
  4645. if (y < 0) {
  4646. if (y + intel_crtc->cursor_height < 0)
  4647. base = 0;
  4648. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  4649. y = -y;
  4650. }
  4651. pos |= y << CURSOR_Y_SHIFT;
  4652. visible = base != 0;
  4653. if (!visible && !intel_crtc->cursor_visible)
  4654. return;
  4655. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  4656. I915_WRITE(CURPOS_IVB(pipe), pos);
  4657. ivb_update_cursor(crtc, base);
  4658. } else {
  4659. I915_WRITE(CURPOS(pipe), pos);
  4660. if (IS_845G(dev) || IS_I865G(dev))
  4661. i845_update_cursor(crtc, base);
  4662. else
  4663. i9xx_update_cursor(crtc, base);
  4664. }
  4665. }
  4666. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  4667. struct drm_file *file,
  4668. uint32_t handle,
  4669. uint32_t width, uint32_t height)
  4670. {
  4671. struct drm_device *dev = crtc->dev;
  4672. struct drm_i915_private *dev_priv = dev->dev_private;
  4673. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4674. struct drm_i915_gem_object *obj;
  4675. uint32_t addr;
  4676. int ret;
  4677. DRM_DEBUG_KMS("\n");
  4678. /* if we want to turn off the cursor ignore width and height */
  4679. if (!handle) {
  4680. DRM_DEBUG_KMS("cursor off\n");
  4681. addr = 0;
  4682. obj = NULL;
  4683. mutex_lock(&dev->struct_mutex);
  4684. goto finish;
  4685. }
  4686. /* Currently we only support 64x64 cursors */
  4687. if (width != 64 || height != 64) {
  4688. DRM_ERROR("we currently only support 64x64 cursors\n");
  4689. return -EINVAL;
  4690. }
  4691. obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  4692. if (&obj->base == NULL)
  4693. return -ENOENT;
  4694. if (obj->base.size < width * height * 4) {
  4695. DRM_ERROR("buffer is to small\n");
  4696. ret = -ENOMEM;
  4697. goto fail;
  4698. }
  4699. /* we only need to pin inside GTT if cursor is non-phy */
  4700. mutex_lock(&dev->struct_mutex);
  4701. if (!dev_priv->info->cursor_needs_physical) {
  4702. if (obj->tiling_mode) {
  4703. DRM_ERROR("cursor cannot be tiled\n");
  4704. ret = -EINVAL;
  4705. goto fail_locked;
  4706. }
  4707. ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
  4708. if (ret) {
  4709. DRM_ERROR("failed to move cursor bo into the GTT\n");
  4710. goto fail_locked;
  4711. }
  4712. ret = i915_gem_object_put_fence(obj);
  4713. if (ret) {
  4714. DRM_ERROR("failed to release fence for cursor");
  4715. goto fail_unpin;
  4716. }
  4717. addr = obj->gtt_offset;
  4718. } else {
  4719. int align = IS_I830(dev) ? 16 * 1024 : 256;
  4720. ret = i915_gem_attach_phys_object(dev, obj,
  4721. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  4722. align);
  4723. if (ret) {
  4724. DRM_ERROR("failed to attach phys object\n");
  4725. goto fail_locked;
  4726. }
  4727. addr = obj->phys_obj->handle->busaddr;
  4728. }
  4729. if (IS_GEN2(dev))
  4730. I915_WRITE(CURSIZE, (height << 12) | width);
  4731. finish:
  4732. if (intel_crtc->cursor_bo) {
  4733. if (dev_priv->info->cursor_needs_physical) {
  4734. if (intel_crtc->cursor_bo != obj)
  4735. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  4736. } else
  4737. i915_gem_object_unpin(intel_crtc->cursor_bo);
  4738. drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
  4739. }
  4740. mutex_unlock(&dev->struct_mutex);
  4741. intel_crtc->cursor_addr = addr;
  4742. intel_crtc->cursor_bo = obj;
  4743. intel_crtc->cursor_width = width;
  4744. intel_crtc->cursor_height = height;
  4745. intel_crtc_update_cursor(crtc, true);
  4746. return 0;
  4747. fail_unpin:
  4748. i915_gem_object_unpin(obj);
  4749. fail_locked:
  4750. mutex_unlock(&dev->struct_mutex);
  4751. fail:
  4752. drm_gem_object_unreference_unlocked(&obj->base);
  4753. return ret;
  4754. }
  4755. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  4756. {
  4757. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4758. intel_crtc->cursor_x = x;
  4759. intel_crtc->cursor_y = y;
  4760. intel_crtc_update_cursor(crtc, true);
  4761. return 0;
  4762. }
  4763. /** Sets the color ramps on behalf of RandR */
  4764. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  4765. u16 blue, int regno)
  4766. {
  4767. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4768. intel_crtc->lut_r[regno] = red >> 8;
  4769. intel_crtc->lut_g[regno] = green >> 8;
  4770. intel_crtc->lut_b[regno] = blue >> 8;
  4771. }
  4772. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  4773. u16 *blue, int regno)
  4774. {
  4775. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4776. *red = intel_crtc->lut_r[regno] << 8;
  4777. *green = intel_crtc->lut_g[regno] << 8;
  4778. *blue = intel_crtc->lut_b[regno] << 8;
  4779. }
  4780. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  4781. u16 *blue, uint32_t start, uint32_t size)
  4782. {
  4783. int end = (start + size > 256) ? 256 : start + size, i;
  4784. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4785. for (i = start; i < end; i++) {
  4786. intel_crtc->lut_r[i] = red[i] >> 8;
  4787. intel_crtc->lut_g[i] = green[i] >> 8;
  4788. intel_crtc->lut_b[i] = blue[i] >> 8;
  4789. }
  4790. intel_crtc_load_lut(crtc);
  4791. }
  4792. /**
  4793. * Get a pipe with a simple mode set on it for doing load-based monitor
  4794. * detection.
  4795. *
  4796. * It will be up to the load-detect code to adjust the pipe as appropriate for
  4797. * its requirements. The pipe will be connected to no other encoders.
  4798. *
  4799. * Currently this code will only succeed if there is a pipe with no encoders
  4800. * configured for it. In the future, it could choose to temporarily disable
  4801. * some outputs to free up a pipe for its use.
  4802. *
  4803. * \return crtc, or NULL if no pipes are available.
  4804. */
  4805. /* VESA 640x480x72Hz mode to set on the pipe */
  4806. static struct drm_display_mode load_detect_mode = {
  4807. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  4808. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  4809. };
  4810. static struct drm_framebuffer *
  4811. intel_framebuffer_create(struct drm_device *dev,
  4812. struct drm_mode_fb_cmd2 *mode_cmd,
  4813. struct drm_i915_gem_object *obj)
  4814. {
  4815. struct intel_framebuffer *intel_fb;
  4816. int ret;
  4817. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  4818. if (!intel_fb) {
  4819. drm_gem_object_unreference_unlocked(&obj->base);
  4820. return ERR_PTR(-ENOMEM);
  4821. }
  4822. ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  4823. if (ret) {
  4824. drm_gem_object_unreference_unlocked(&obj->base);
  4825. kfree(intel_fb);
  4826. return ERR_PTR(ret);
  4827. }
  4828. return &intel_fb->base;
  4829. }
  4830. static u32
  4831. intel_framebuffer_pitch_for_width(int width, int bpp)
  4832. {
  4833. u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  4834. return ALIGN(pitch, 64);
  4835. }
  4836. static u32
  4837. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  4838. {
  4839. u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  4840. return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
  4841. }
  4842. static struct drm_framebuffer *
  4843. intel_framebuffer_create_for_mode(struct drm_device *dev,
  4844. struct drm_display_mode *mode,
  4845. int depth, int bpp)
  4846. {
  4847. struct drm_i915_gem_object *obj;
  4848. struct drm_mode_fb_cmd2 mode_cmd;
  4849. obj = i915_gem_alloc_object(dev,
  4850. intel_framebuffer_size_for_mode(mode, bpp));
  4851. if (obj == NULL)
  4852. return ERR_PTR(-ENOMEM);
  4853. mode_cmd.width = mode->hdisplay;
  4854. mode_cmd.height = mode->vdisplay;
  4855. mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
  4856. bpp);
  4857. mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
  4858. return intel_framebuffer_create(dev, &mode_cmd, obj);
  4859. }
  4860. static struct drm_framebuffer *
  4861. mode_fits_in_fbdev(struct drm_device *dev,
  4862. struct drm_display_mode *mode)
  4863. {
  4864. struct drm_i915_private *dev_priv = dev->dev_private;
  4865. struct drm_i915_gem_object *obj;
  4866. struct drm_framebuffer *fb;
  4867. if (dev_priv->fbdev == NULL)
  4868. return NULL;
  4869. obj = dev_priv->fbdev->ifb.obj;
  4870. if (obj == NULL)
  4871. return NULL;
  4872. fb = &dev_priv->fbdev->ifb.base;
  4873. if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
  4874. fb->bits_per_pixel))
  4875. return NULL;
  4876. if (obj->base.size < mode->vdisplay * fb->pitches[0])
  4877. return NULL;
  4878. return fb;
  4879. }
  4880. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  4881. struct drm_display_mode *mode,
  4882. struct intel_load_detect_pipe *old)
  4883. {
  4884. struct intel_crtc *intel_crtc;
  4885. struct intel_encoder *intel_encoder =
  4886. intel_attached_encoder(connector);
  4887. struct drm_crtc *possible_crtc;
  4888. struct drm_encoder *encoder = &intel_encoder->base;
  4889. struct drm_crtc *crtc = NULL;
  4890. struct drm_device *dev = encoder->dev;
  4891. struct drm_framebuffer *old_fb;
  4892. int i = -1;
  4893. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  4894. connector->base.id, drm_get_connector_name(connector),
  4895. encoder->base.id, drm_get_encoder_name(encoder));
  4896. /*
  4897. * Algorithm gets a little messy:
  4898. *
  4899. * - if the connector already has an assigned crtc, use it (but make
  4900. * sure it's on first)
  4901. *
  4902. * - try to find the first unused crtc that can drive this connector,
  4903. * and use that if we find one
  4904. */
  4905. /* See if we already have a CRTC for this connector */
  4906. if (encoder->crtc) {
  4907. crtc = encoder->crtc;
  4908. old->dpms_mode = connector->dpms;
  4909. old->load_detect_temp = false;
  4910. /* Make sure the crtc and connector are running */
  4911. if (connector->dpms != DRM_MODE_DPMS_ON)
  4912. connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
  4913. return true;
  4914. }
  4915. /* Find an unused one (if possible) */
  4916. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  4917. i++;
  4918. if (!(encoder->possible_crtcs & (1 << i)))
  4919. continue;
  4920. if (!possible_crtc->enabled) {
  4921. crtc = possible_crtc;
  4922. break;
  4923. }
  4924. }
  4925. /*
  4926. * If we didn't find an unused CRTC, don't use any.
  4927. */
  4928. if (!crtc) {
  4929. DRM_DEBUG_KMS("no pipe available for load-detect\n");
  4930. return false;
  4931. }
  4932. encoder->crtc = crtc;
  4933. connector->encoder = encoder;
  4934. intel_crtc = to_intel_crtc(crtc);
  4935. old->dpms_mode = connector->dpms;
  4936. old->load_detect_temp = true;
  4937. old->release_fb = NULL;
  4938. if (!mode)
  4939. mode = &load_detect_mode;
  4940. old_fb = crtc->fb;
  4941. /* We need a framebuffer large enough to accommodate all accesses
  4942. * that the plane may generate whilst we perform load detection.
  4943. * We can not rely on the fbcon either being present (we get called
  4944. * during its initialisation to detect all boot displays, or it may
  4945. * not even exist) or that it is large enough to satisfy the
  4946. * requested mode.
  4947. */
  4948. crtc->fb = mode_fits_in_fbdev(dev, mode);
  4949. if (crtc->fb == NULL) {
  4950. DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  4951. crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  4952. old->release_fb = crtc->fb;
  4953. } else
  4954. DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  4955. if (IS_ERR(crtc->fb)) {
  4956. DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  4957. goto fail;
  4958. }
  4959. if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
  4960. DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  4961. if (old->release_fb)
  4962. old->release_fb->funcs->destroy(old->release_fb);
  4963. goto fail;
  4964. }
  4965. /* let the connector get through one full cycle before testing */
  4966. intel_wait_for_vblank(dev, intel_crtc->pipe);
  4967. return true;
  4968. fail:
  4969. connector->encoder = NULL;
  4970. encoder->crtc = NULL;
  4971. crtc->fb = old_fb;
  4972. return false;
  4973. }
  4974. void intel_release_load_detect_pipe(struct drm_connector *connector,
  4975. struct intel_load_detect_pipe *old)
  4976. {
  4977. struct intel_encoder *intel_encoder =
  4978. intel_attached_encoder(connector);
  4979. struct drm_encoder *encoder = &intel_encoder->base;
  4980. struct drm_device *dev = encoder->dev;
  4981. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  4982. connector->base.id, drm_get_connector_name(connector),
  4983. encoder->base.id, drm_get_encoder_name(encoder));
  4984. if (old->load_detect_temp) {
  4985. connector->encoder = NULL;
  4986. encoder->crtc = NULL;
  4987. drm_helper_disable_unused_functions(dev);
  4988. if (old->release_fb)
  4989. old->release_fb->funcs->destroy(old->release_fb);
  4990. return;
  4991. }
  4992. /* Switch crtc and encoder back off if necessary */
  4993. if (old->dpms_mode != DRM_MODE_DPMS_ON)
  4994. connector->funcs->dpms(connector, old->dpms_mode);
  4995. }
  4996. /* Returns the clock of the currently programmed mode of the given pipe. */
  4997. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  4998. {
  4999. struct drm_i915_private *dev_priv = dev->dev_private;
  5000. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5001. int pipe = intel_crtc->pipe;
  5002. u32 dpll = I915_READ(DPLL(pipe));
  5003. u32 fp;
  5004. intel_clock_t clock;
  5005. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  5006. fp = I915_READ(FP0(pipe));
  5007. else
  5008. fp = I915_READ(FP1(pipe));
  5009. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  5010. if (IS_PINEVIEW(dev)) {
  5011. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  5012. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5013. } else {
  5014. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  5015. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5016. }
  5017. if (!IS_GEN2(dev)) {
  5018. if (IS_PINEVIEW(dev))
  5019. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  5020. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  5021. else
  5022. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  5023. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5024. switch (dpll & DPLL_MODE_MASK) {
  5025. case DPLLB_MODE_DAC_SERIAL:
  5026. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  5027. 5 : 10;
  5028. break;
  5029. case DPLLB_MODE_LVDS:
  5030. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  5031. 7 : 14;
  5032. break;
  5033. default:
  5034. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  5035. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  5036. return 0;
  5037. }
  5038. /* XXX: Handle the 100Mhz refclk */
  5039. intel_clock(dev, 96000, &clock);
  5040. } else {
  5041. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  5042. if (is_lvds) {
  5043. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  5044. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5045. clock.p2 = 14;
  5046. if ((dpll & PLL_REF_INPUT_MASK) ==
  5047. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  5048. /* XXX: might not be 66MHz */
  5049. intel_clock(dev, 66000, &clock);
  5050. } else
  5051. intel_clock(dev, 48000, &clock);
  5052. } else {
  5053. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  5054. clock.p1 = 2;
  5055. else {
  5056. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  5057. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  5058. }
  5059. if (dpll & PLL_P2_DIVIDE_BY_4)
  5060. clock.p2 = 4;
  5061. else
  5062. clock.p2 = 2;
  5063. intel_clock(dev, 48000, &clock);
  5064. }
  5065. }
  5066. /* XXX: It would be nice to validate the clocks, but we can't reuse
  5067. * i830PllIsValid() because it relies on the xf86_config connector
  5068. * configuration being accurate, which it isn't necessarily.
  5069. */
  5070. return clock.dot;
  5071. }
  5072. /** Returns the currently programmed mode of the given pipe. */
  5073. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  5074. struct drm_crtc *crtc)
  5075. {
  5076. struct drm_i915_private *dev_priv = dev->dev_private;
  5077. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5078. int pipe = intel_crtc->pipe;
  5079. struct drm_display_mode *mode;
  5080. int htot = I915_READ(HTOTAL(pipe));
  5081. int hsync = I915_READ(HSYNC(pipe));
  5082. int vtot = I915_READ(VTOTAL(pipe));
  5083. int vsync = I915_READ(VSYNC(pipe));
  5084. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  5085. if (!mode)
  5086. return NULL;
  5087. mode->clock = intel_crtc_clock_get(dev, crtc);
  5088. mode->hdisplay = (htot & 0xffff) + 1;
  5089. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  5090. mode->hsync_start = (hsync & 0xffff) + 1;
  5091. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  5092. mode->vdisplay = (vtot & 0xffff) + 1;
  5093. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  5094. mode->vsync_start = (vsync & 0xffff) + 1;
  5095. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  5096. drm_mode_set_name(mode);
  5097. return mode;
  5098. }
  5099. static void intel_increase_pllclock(struct drm_crtc *crtc)
  5100. {
  5101. struct drm_device *dev = crtc->dev;
  5102. drm_i915_private_t *dev_priv = dev->dev_private;
  5103. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5104. int pipe = intel_crtc->pipe;
  5105. int dpll_reg = DPLL(pipe);
  5106. int dpll;
  5107. if (HAS_PCH_SPLIT(dev))
  5108. return;
  5109. if (!dev_priv->lvds_downclock_avail)
  5110. return;
  5111. dpll = I915_READ(dpll_reg);
  5112. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  5113. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  5114. assert_panel_unlocked(dev_priv, pipe);
  5115. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  5116. I915_WRITE(dpll_reg, dpll);
  5117. intel_wait_for_vblank(dev, pipe);
  5118. dpll = I915_READ(dpll_reg);
  5119. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  5120. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  5121. }
  5122. }
  5123. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  5124. {
  5125. struct drm_device *dev = crtc->dev;
  5126. drm_i915_private_t *dev_priv = dev->dev_private;
  5127. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5128. if (HAS_PCH_SPLIT(dev))
  5129. return;
  5130. if (!dev_priv->lvds_downclock_avail)
  5131. return;
  5132. /*
  5133. * Since this is called by a timer, we should never get here in
  5134. * the manual case.
  5135. */
  5136. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  5137. int pipe = intel_crtc->pipe;
  5138. int dpll_reg = DPLL(pipe);
  5139. int dpll;
  5140. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  5141. assert_panel_unlocked(dev_priv, pipe);
  5142. dpll = I915_READ(dpll_reg);
  5143. dpll |= DISPLAY_RATE_SELECT_FPA1;
  5144. I915_WRITE(dpll_reg, dpll);
  5145. intel_wait_for_vblank(dev, pipe);
  5146. dpll = I915_READ(dpll_reg);
  5147. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  5148. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  5149. }
  5150. }
  5151. void intel_mark_busy(struct drm_device *dev)
  5152. {
  5153. i915_update_gfx_val(dev->dev_private);
  5154. }
  5155. void intel_mark_idle(struct drm_device *dev)
  5156. {
  5157. }
  5158. void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
  5159. {
  5160. struct drm_device *dev = obj->base.dev;
  5161. struct drm_crtc *crtc;
  5162. if (!i915_powersave)
  5163. return;
  5164. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5165. if (!crtc->fb)
  5166. continue;
  5167. if (to_intel_framebuffer(crtc->fb)->obj == obj)
  5168. intel_increase_pllclock(crtc);
  5169. }
  5170. }
  5171. void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
  5172. {
  5173. struct drm_device *dev = obj->base.dev;
  5174. struct drm_crtc *crtc;
  5175. if (!i915_powersave)
  5176. return;
  5177. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5178. if (!crtc->fb)
  5179. continue;
  5180. if (to_intel_framebuffer(crtc->fb)->obj == obj)
  5181. intel_decrease_pllclock(crtc);
  5182. }
  5183. }
  5184. static void intel_crtc_destroy(struct drm_crtc *crtc)
  5185. {
  5186. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5187. struct drm_device *dev = crtc->dev;
  5188. struct intel_unpin_work *work;
  5189. unsigned long flags;
  5190. spin_lock_irqsave(&dev->event_lock, flags);
  5191. work = intel_crtc->unpin_work;
  5192. intel_crtc->unpin_work = NULL;
  5193. spin_unlock_irqrestore(&dev->event_lock, flags);
  5194. if (work) {
  5195. cancel_work_sync(&work->work);
  5196. kfree(work);
  5197. }
  5198. drm_crtc_cleanup(crtc);
  5199. kfree(intel_crtc);
  5200. }
  5201. static void intel_unpin_work_fn(struct work_struct *__work)
  5202. {
  5203. struct intel_unpin_work *work =
  5204. container_of(__work, struct intel_unpin_work, work);
  5205. mutex_lock(&work->dev->struct_mutex);
  5206. intel_unpin_fb_obj(work->old_fb_obj);
  5207. drm_gem_object_unreference(&work->pending_flip_obj->base);
  5208. drm_gem_object_unreference(&work->old_fb_obj->base);
  5209. intel_update_fbc(work->dev);
  5210. mutex_unlock(&work->dev->struct_mutex);
  5211. kfree(work);
  5212. }
  5213. static void do_intel_finish_page_flip(struct drm_device *dev,
  5214. struct drm_crtc *crtc)
  5215. {
  5216. drm_i915_private_t *dev_priv = dev->dev_private;
  5217. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5218. struct intel_unpin_work *work;
  5219. struct drm_i915_gem_object *obj;
  5220. struct drm_pending_vblank_event *e;
  5221. struct timeval tnow, tvbl;
  5222. unsigned long flags;
  5223. /* Ignore early vblank irqs */
  5224. if (intel_crtc == NULL)
  5225. return;
  5226. do_gettimeofday(&tnow);
  5227. spin_lock_irqsave(&dev->event_lock, flags);
  5228. work = intel_crtc->unpin_work;
  5229. if (work == NULL || !work->pending) {
  5230. spin_unlock_irqrestore(&dev->event_lock, flags);
  5231. return;
  5232. }
  5233. intel_crtc->unpin_work = NULL;
  5234. if (work->event) {
  5235. e = work->event;
  5236. e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
  5237. /* Called before vblank count and timestamps have
  5238. * been updated for the vblank interval of flip
  5239. * completion? Need to increment vblank count and
  5240. * add one videorefresh duration to returned timestamp
  5241. * to account for this. We assume this happened if we
  5242. * get called over 0.9 frame durations after the last
  5243. * timestamped vblank.
  5244. *
  5245. * This calculation can not be used with vrefresh rates
  5246. * below 5Hz (10Hz to be on the safe side) without
  5247. * promoting to 64 integers.
  5248. */
  5249. if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
  5250. 9 * crtc->framedur_ns) {
  5251. e->event.sequence++;
  5252. tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
  5253. crtc->framedur_ns);
  5254. }
  5255. e->event.tv_sec = tvbl.tv_sec;
  5256. e->event.tv_usec = tvbl.tv_usec;
  5257. list_add_tail(&e->base.link,
  5258. &e->base.file_priv->event_list);
  5259. wake_up_interruptible(&e->base.file_priv->event_wait);
  5260. }
  5261. drm_vblank_put(dev, intel_crtc->pipe);
  5262. spin_unlock_irqrestore(&dev->event_lock, flags);
  5263. obj = work->old_fb_obj;
  5264. atomic_clear_mask(1 << intel_crtc->plane,
  5265. &obj->pending_flip.counter);
  5266. if (atomic_read(&obj->pending_flip) == 0)
  5267. wake_up(&dev_priv->pending_flip_queue);
  5268. schedule_work(&work->work);
  5269. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  5270. }
  5271. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  5272. {
  5273. drm_i915_private_t *dev_priv = dev->dev_private;
  5274. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  5275. do_intel_finish_page_flip(dev, crtc);
  5276. }
  5277. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  5278. {
  5279. drm_i915_private_t *dev_priv = dev->dev_private;
  5280. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  5281. do_intel_finish_page_flip(dev, crtc);
  5282. }
  5283. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  5284. {
  5285. drm_i915_private_t *dev_priv = dev->dev_private;
  5286. struct intel_crtc *intel_crtc =
  5287. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  5288. unsigned long flags;
  5289. spin_lock_irqsave(&dev->event_lock, flags);
  5290. if (intel_crtc->unpin_work) {
  5291. if ((++intel_crtc->unpin_work->pending) > 1)
  5292. DRM_ERROR("Prepared flip multiple times\n");
  5293. } else {
  5294. DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
  5295. }
  5296. spin_unlock_irqrestore(&dev->event_lock, flags);
  5297. }
  5298. static int intel_gen2_queue_flip(struct drm_device *dev,
  5299. struct drm_crtc *crtc,
  5300. struct drm_framebuffer *fb,
  5301. struct drm_i915_gem_object *obj)
  5302. {
  5303. struct drm_i915_private *dev_priv = dev->dev_private;
  5304. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5305. u32 flip_mask;
  5306. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  5307. int ret;
  5308. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5309. if (ret)
  5310. goto err;
  5311. ret = intel_ring_begin(ring, 6);
  5312. if (ret)
  5313. goto err_unpin;
  5314. /* Can't queue multiple flips, so wait for the previous
  5315. * one to finish before executing the next.
  5316. */
  5317. if (intel_crtc->plane)
  5318. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  5319. else
  5320. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  5321. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  5322. intel_ring_emit(ring, MI_NOOP);
  5323. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  5324. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5325. intel_ring_emit(ring, fb->pitches[0]);
  5326. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  5327. intel_ring_emit(ring, 0); /* aux display base address, unused */
  5328. intel_ring_advance(ring);
  5329. return 0;
  5330. err_unpin:
  5331. intel_unpin_fb_obj(obj);
  5332. err:
  5333. return ret;
  5334. }
  5335. static int intel_gen3_queue_flip(struct drm_device *dev,
  5336. struct drm_crtc *crtc,
  5337. struct drm_framebuffer *fb,
  5338. struct drm_i915_gem_object *obj)
  5339. {
  5340. struct drm_i915_private *dev_priv = dev->dev_private;
  5341. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5342. u32 flip_mask;
  5343. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  5344. int ret;
  5345. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5346. if (ret)
  5347. goto err;
  5348. ret = intel_ring_begin(ring, 6);
  5349. if (ret)
  5350. goto err_unpin;
  5351. if (intel_crtc->plane)
  5352. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  5353. else
  5354. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  5355. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  5356. intel_ring_emit(ring, MI_NOOP);
  5357. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
  5358. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5359. intel_ring_emit(ring, fb->pitches[0]);
  5360. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  5361. intel_ring_emit(ring, MI_NOOP);
  5362. intel_ring_advance(ring);
  5363. return 0;
  5364. err_unpin:
  5365. intel_unpin_fb_obj(obj);
  5366. err:
  5367. return ret;
  5368. }
  5369. static int intel_gen4_queue_flip(struct drm_device *dev,
  5370. struct drm_crtc *crtc,
  5371. struct drm_framebuffer *fb,
  5372. struct drm_i915_gem_object *obj)
  5373. {
  5374. struct drm_i915_private *dev_priv = dev->dev_private;
  5375. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5376. uint32_t pf, pipesrc;
  5377. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  5378. int ret;
  5379. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5380. if (ret)
  5381. goto err;
  5382. ret = intel_ring_begin(ring, 4);
  5383. if (ret)
  5384. goto err_unpin;
  5385. /* i965+ uses the linear or tiled offsets from the
  5386. * Display Registers (which do not change across a page-flip)
  5387. * so we need only reprogram the base address.
  5388. */
  5389. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  5390. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5391. intel_ring_emit(ring, fb->pitches[0]);
  5392. intel_ring_emit(ring,
  5393. (obj->gtt_offset + intel_crtc->dspaddr_offset) |
  5394. obj->tiling_mode);
  5395. /* XXX Enabling the panel-fitter across page-flip is so far
  5396. * untested on non-native modes, so ignore it for now.
  5397. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  5398. */
  5399. pf = 0;
  5400. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  5401. intel_ring_emit(ring, pf | pipesrc);
  5402. intel_ring_advance(ring);
  5403. return 0;
  5404. err_unpin:
  5405. intel_unpin_fb_obj(obj);
  5406. err:
  5407. return ret;
  5408. }
  5409. static int intel_gen6_queue_flip(struct drm_device *dev,
  5410. struct drm_crtc *crtc,
  5411. struct drm_framebuffer *fb,
  5412. struct drm_i915_gem_object *obj)
  5413. {
  5414. struct drm_i915_private *dev_priv = dev->dev_private;
  5415. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5416. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  5417. uint32_t pf, pipesrc;
  5418. int ret;
  5419. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5420. if (ret)
  5421. goto err;
  5422. ret = intel_ring_begin(ring, 4);
  5423. if (ret)
  5424. goto err_unpin;
  5425. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  5426. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5427. intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
  5428. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  5429. /* Contrary to the suggestions in the documentation,
  5430. * "Enable Panel Fitter" does not seem to be required when page
  5431. * flipping with a non-native mode, and worse causes a normal
  5432. * modeset to fail.
  5433. * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  5434. */
  5435. pf = 0;
  5436. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  5437. intel_ring_emit(ring, pf | pipesrc);
  5438. intel_ring_advance(ring);
  5439. return 0;
  5440. err_unpin:
  5441. intel_unpin_fb_obj(obj);
  5442. err:
  5443. return ret;
  5444. }
  5445. /*
  5446. * On gen7 we currently use the blit ring because (in early silicon at least)
  5447. * the render ring doesn't give us interrpts for page flip completion, which
  5448. * means clients will hang after the first flip is queued. Fortunately the
  5449. * blit ring generates interrupts properly, so use it instead.
  5450. */
  5451. static int intel_gen7_queue_flip(struct drm_device *dev,
  5452. struct drm_crtc *crtc,
  5453. struct drm_framebuffer *fb,
  5454. struct drm_i915_gem_object *obj)
  5455. {
  5456. struct drm_i915_private *dev_priv = dev->dev_private;
  5457. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5458. struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
  5459. uint32_t plane_bit = 0;
  5460. int ret;
  5461. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5462. if (ret)
  5463. goto err;
  5464. switch(intel_crtc->plane) {
  5465. case PLANE_A:
  5466. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
  5467. break;
  5468. case PLANE_B:
  5469. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
  5470. break;
  5471. case PLANE_C:
  5472. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
  5473. break;
  5474. default:
  5475. WARN_ONCE(1, "unknown plane in flip command\n");
  5476. ret = -ENODEV;
  5477. goto err_unpin;
  5478. }
  5479. ret = intel_ring_begin(ring, 4);
  5480. if (ret)
  5481. goto err_unpin;
  5482. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
  5483. intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
  5484. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  5485. intel_ring_emit(ring, (MI_NOOP));
  5486. intel_ring_advance(ring);
  5487. return 0;
  5488. err_unpin:
  5489. intel_unpin_fb_obj(obj);
  5490. err:
  5491. return ret;
  5492. }
  5493. static int intel_default_queue_flip(struct drm_device *dev,
  5494. struct drm_crtc *crtc,
  5495. struct drm_framebuffer *fb,
  5496. struct drm_i915_gem_object *obj)
  5497. {
  5498. return -ENODEV;
  5499. }
  5500. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  5501. struct drm_framebuffer *fb,
  5502. struct drm_pending_vblank_event *event)
  5503. {
  5504. struct drm_device *dev = crtc->dev;
  5505. struct drm_i915_private *dev_priv = dev->dev_private;
  5506. struct intel_framebuffer *intel_fb;
  5507. struct drm_i915_gem_object *obj;
  5508. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5509. struct intel_unpin_work *work;
  5510. unsigned long flags;
  5511. int ret;
  5512. /* Can't change pixel format via MI display flips. */
  5513. if (fb->pixel_format != crtc->fb->pixel_format)
  5514. return -EINVAL;
  5515. /*
  5516. * TILEOFF/LINOFF registers can't be changed via MI display flips.
  5517. * Note that pitch changes could also affect these register.
  5518. */
  5519. if (INTEL_INFO(dev)->gen > 3 &&
  5520. (fb->offsets[0] != crtc->fb->offsets[0] ||
  5521. fb->pitches[0] != crtc->fb->pitches[0]))
  5522. return -EINVAL;
  5523. work = kzalloc(sizeof *work, GFP_KERNEL);
  5524. if (work == NULL)
  5525. return -ENOMEM;
  5526. work->event = event;
  5527. work->dev = crtc->dev;
  5528. intel_fb = to_intel_framebuffer(crtc->fb);
  5529. work->old_fb_obj = intel_fb->obj;
  5530. INIT_WORK(&work->work, intel_unpin_work_fn);
  5531. ret = drm_vblank_get(dev, intel_crtc->pipe);
  5532. if (ret)
  5533. goto free_work;
  5534. /* We borrow the event spin lock for protecting unpin_work */
  5535. spin_lock_irqsave(&dev->event_lock, flags);
  5536. if (intel_crtc->unpin_work) {
  5537. spin_unlock_irqrestore(&dev->event_lock, flags);
  5538. kfree(work);
  5539. drm_vblank_put(dev, intel_crtc->pipe);
  5540. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  5541. return -EBUSY;
  5542. }
  5543. intel_crtc->unpin_work = work;
  5544. spin_unlock_irqrestore(&dev->event_lock, flags);
  5545. intel_fb = to_intel_framebuffer(fb);
  5546. obj = intel_fb->obj;
  5547. ret = i915_mutex_lock_interruptible(dev);
  5548. if (ret)
  5549. goto cleanup;
  5550. /* Reference the objects for the scheduled work. */
  5551. drm_gem_object_reference(&work->old_fb_obj->base);
  5552. drm_gem_object_reference(&obj->base);
  5553. crtc->fb = fb;
  5554. work->pending_flip_obj = obj;
  5555. work->enable_stall_check = true;
  5556. /* Block clients from rendering to the new back buffer until
  5557. * the flip occurs and the object is no longer visible.
  5558. */
  5559. atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
  5560. ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
  5561. if (ret)
  5562. goto cleanup_pending;
  5563. intel_disable_fbc(dev);
  5564. intel_mark_fb_busy(obj);
  5565. mutex_unlock(&dev->struct_mutex);
  5566. trace_i915_flip_request(intel_crtc->plane, obj);
  5567. return 0;
  5568. cleanup_pending:
  5569. atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
  5570. drm_gem_object_unreference(&work->old_fb_obj->base);
  5571. drm_gem_object_unreference(&obj->base);
  5572. mutex_unlock(&dev->struct_mutex);
  5573. cleanup:
  5574. spin_lock_irqsave(&dev->event_lock, flags);
  5575. intel_crtc->unpin_work = NULL;
  5576. spin_unlock_irqrestore(&dev->event_lock, flags);
  5577. drm_vblank_put(dev, intel_crtc->pipe);
  5578. free_work:
  5579. kfree(work);
  5580. return ret;
  5581. }
  5582. static void intel_sanitize_modesetting(struct drm_device *dev,
  5583. int pipe, int plane)
  5584. {
  5585. struct drm_i915_private *dev_priv = dev->dev_private;
  5586. u32 reg, val;
  5587. int i;
  5588. /* Clear any frame start delays used for debugging left by the BIOS */
  5589. for_each_pipe(i) {
  5590. reg = PIPECONF(i);
  5591. I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
  5592. }
  5593. if (HAS_PCH_SPLIT(dev))
  5594. return;
  5595. /* Who knows what state these registers were left in by the BIOS or
  5596. * grub?
  5597. *
  5598. * If we leave the registers in a conflicting state (e.g. with the
  5599. * display plane reading from the other pipe than the one we intend
  5600. * to use) then when we attempt to teardown the active mode, we will
  5601. * not disable the pipes and planes in the correct order -- leaving
  5602. * a plane reading from a disabled pipe and possibly leading to
  5603. * undefined behaviour.
  5604. */
  5605. reg = DSPCNTR(plane);
  5606. val = I915_READ(reg);
  5607. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  5608. return;
  5609. if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
  5610. return;
  5611. /* This display plane is active and attached to the other CPU pipe. */
  5612. pipe = !pipe;
  5613. /* Disable the plane and wait for it to stop reading from the pipe. */
  5614. intel_disable_plane(dev_priv, plane, pipe);
  5615. intel_disable_pipe(dev_priv, pipe);
  5616. }
  5617. static void intel_crtc_reset(struct drm_crtc *crtc)
  5618. {
  5619. struct drm_device *dev = crtc->dev;
  5620. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5621. /* Reset flags back to the 'unknown' status so that they
  5622. * will be correctly set on the initial modeset.
  5623. */
  5624. intel_crtc->dpms_mode = -1;
  5625. /* We need to fix up any BIOS configuration that conflicts with
  5626. * our expectations.
  5627. */
  5628. intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
  5629. }
  5630. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  5631. .mode_fixup = intel_crtc_mode_fixup,
  5632. .mode_set = intel_crtc_mode_set,
  5633. .mode_set_base = intel_pipe_set_base,
  5634. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  5635. .load_lut = intel_crtc_load_lut,
  5636. .disable = intel_crtc_disable,
  5637. };
  5638. static const struct drm_crtc_funcs intel_crtc_funcs = {
  5639. .reset = intel_crtc_reset,
  5640. .cursor_set = intel_crtc_cursor_set,
  5641. .cursor_move = intel_crtc_cursor_move,
  5642. .gamma_set = intel_crtc_gamma_set,
  5643. .set_config = drm_crtc_helper_set_config,
  5644. .destroy = intel_crtc_destroy,
  5645. .page_flip = intel_crtc_page_flip,
  5646. };
  5647. static void intel_pch_pll_init(struct drm_device *dev)
  5648. {
  5649. drm_i915_private_t *dev_priv = dev->dev_private;
  5650. int i;
  5651. if (dev_priv->num_pch_pll == 0) {
  5652. DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
  5653. return;
  5654. }
  5655. for (i = 0; i < dev_priv->num_pch_pll; i++) {
  5656. dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
  5657. dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
  5658. dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
  5659. }
  5660. }
  5661. static void intel_crtc_init(struct drm_device *dev, int pipe)
  5662. {
  5663. drm_i915_private_t *dev_priv = dev->dev_private;
  5664. struct intel_crtc *intel_crtc;
  5665. int i;
  5666. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  5667. if (intel_crtc == NULL)
  5668. return;
  5669. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  5670. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  5671. for (i = 0; i < 256; i++) {
  5672. intel_crtc->lut_r[i] = i;
  5673. intel_crtc->lut_g[i] = i;
  5674. intel_crtc->lut_b[i] = i;
  5675. }
  5676. /* Swap pipes & planes for FBC on pre-965 */
  5677. intel_crtc->pipe = pipe;
  5678. intel_crtc->plane = pipe;
  5679. if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  5680. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  5681. intel_crtc->plane = !pipe;
  5682. }
  5683. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  5684. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  5685. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  5686. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  5687. intel_crtc_reset(&intel_crtc->base);
  5688. intel_crtc->active = true; /* force the pipe off on setup_init_config */
  5689. intel_crtc->bpp = 24; /* default for pre-Ironlake */
  5690. intel_helper_funcs.prepare = dev_priv->display.crtc_disable;
  5691. intel_helper_funcs.commit = dev_priv->display.crtc_enable;
  5692. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  5693. }
  5694. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  5695. struct drm_file *file)
  5696. {
  5697. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  5698. struct drm_mode_object *drmmode_obj;
  5699. struct intel_crtc *crtc;
  5700. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  5701. return -ENODEV;
  5702. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  5703. DRM_MODE_OBJECT_CRTC);
  5704. if (!drmmode_obj) {
  5705. DRM_ERROR("no such CRTC id\n");
  5706. return -EINVAL;
  5707. }
  5708. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  5709. pipe_from_crtc_id->pipe = crtc->pipe;
  5710. return 0;
  5711. }
  5712. static int intel_encoder_clones(struct intel_encoder *encoder)
  5713. {
  5714. struct drm_device *dev = encoder->base.dev;
  5715. struct intel_encoder *source_encoder;
  5716. int index_mask = 0;
  5717. int entry = 0;
  5718. list_for_each_entry(source_encoder,
  5719. &dev->mode_config.encoder_list, base.head) {
  5720. if (encoder == source_encoder)
  5721. index_mask |= (1 << entry);
  5722. /* Intel hw has only one MUX where enocoders could be cloned. */
  5723. if (encoder->cloneable && source_encoder->cloneable)
  5724. index_mask |= (1 << entry);
  5725. entry++;
  5726. }
  5727. return index_mask;
  5728. }
  5729. static bool has_edp_a(struct drm_device *dev)
  5730. {
  5731. struct drm_i915_private *dev_priv = dev->dev_private;
  5732. if (!IS_MOBILE(dev))
  5733. return false;
  5734. if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  5735. return false;
  5736. if (IS_GEN5(dev) &&
  5737. (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
  5738. return false;
  5739. return true;
  5740. }
  5741. static void intel_setup_outputs(struct drm_device *dev)
  5742. {
  5743. struct drm_i915_private *dev_priv = dev->dev_private;
  5744. struct intel_encoder *encoder;
  5745. bool dpd_is_edp = false;
  5746. bool has_lvds;
  5747. has_lvds = intel_lvds_init(dev);
  5748. if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
  5749. /* disable the panel fitter on everything but LVDS */
  5750. I915_WRITE(PFIT_CONTROL, 0);
  5751. }
  5752. if (HAS_PCH_SPLIT(dev)) {
  5753. dpd_is_edp = intel_dpd_is_edp(dev);
  5754. if (has_edp_a(dev))
  5755. intel_dp_init(dev, DP_A, PORT_A);
  5756. if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  5757. intel_dp_init(dev, PCH_DP_D, PORT_D);
  5758. }
  5759. intel_crt_init(dev);
  5760. if (IS_HASWELL(dev)) {
  5761. int found;
  5762. /* Haswell uses DDI functions to detect digital outputs */
  5763. found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
  5764. /* DDI A only supports eDP */
  5765. if (found)
  5766. intel_ddi_init(dev, PORT_A);
  5767. /* DDI B, C and D detection is indicated by the SFUSE_STRAP
  5768. * register */
  5769. found = I915_READ(SFUSE_STRAP);
  5770. if (found & SFUSE_STRAP_DDIB_DETECTED)
  5771. intel_ddi_init(dev, PORT_B);
  5772. if (found & SFUSE_STRAP_DDIC_DETECTED)
  5773. intel_ddi_init(dev, PORT_C);
  5774. if (found & SFUSE_STRAP_DDID_DETECTED)
  5775. intel_ddi_init(dev, PORT_D);
  5776. } else if (HAS_PCH_SPLIT(dev)) {
  5777. int found;
  5778. if (I915_READ(HDMIB) & PORT_DETECTED) {
  5779. /* PCH SDVOB multiplex with HDMIB */
  5780. found = intel_sdvo_init(dev, PCH_SDVOB, true);
  5781. if (!found)
  5782. intel_hdmi_init(dev, HDMIB, PORT_B);
  5783. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  5784. intel_dp_init(dev, PCH_DP_B, PORT_B);
  5785. }
  5786. if (I915_READ(HDMIC) & PORT_DETECTED)
  5787. intel_hdmi_init(dev, HDMIC, PORT_C);
  5788. if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
  5789. intel_hdmi_init(dev, HDMID, PORT_D);
  5790. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  5791. intel_dp_init(dev, PCH_DP_C, PORT_C);
  5792. if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  5793. intel_dp_init(dev, PCH_DP_D, PORT_D);
  5794. } else if (IS_VALLEYVIEW(dev)) {
  5795. int found;
  5796. if (I915_READ(SDVOB) & PORT_DETECTED) {
  5797. /* SDVOB multiplex with HDMIB */
  5798. found = intel_sdvo_init(dev, SDVOB, true);
  5799. if (!found)
  5800. intel_hdmi_init(dev, SDVOB, PORT_B);
  5801. if (!found && (I915_READ(DP_B) & DP_DETECTED))
  5802. intel_dp_init(dev, DP_B, PORT_B);
  5803. }
  5804. if (I915_READ(SDVOC) & PORT_DETECTED)
  5805. intel_hdmi_init(dev, SDVOC, PORT_C);
  5806. /* Shares lanes with HDMI on SDVOC */
  5807. if (I915_READ(DP_C) & DP_DETECTED)
  5808. intel_dp_init(dev, DP_C, PORT_C);
  5809. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  5810. bool found = false;
  5811. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  5812. DRM_DEBUG_KMS("probing SDVOB\n");
  5813. found = intel_sdvo_init(dev, SDVOB, true);
  5814. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  5815. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  5816. intel_hdmi_init(dev, SDVOB, PORT_B);
  5817. }
  5818. if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
  5819. DRM_DEBUG_KMS("probing DP_B\n");
  5820. intel_dp_init(dev, DP_B, PORT_B);
  5821. }
  5822. }
  5823. /* Before G4X SDVOC doesn't have its own detect register */
  5824. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  5825. DRM_DEBUG_KMS("probing SDVOC\n");
  5826. found = intel_sdvo_init(dev, SDVOC, false);
  5827. }
  5828. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  5829. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  5830. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  5831. intel_hdmi_init(dev, SDVOC, PORT_C);
  5832. }
  5833. if (SUPPORTS_INTEGRATED_DP(dev)) {
  5834. DRM_DEBUG_KMS("probing DP_C\n");
  5835. intel_dp_init(dev, DP_C, PORT_C);
  5836. }
  5837. }
  5838. if (SUPPORTS_INTEGRATED_DP(dev) &&
  5839. (I915_READ(DP_D) & DP_DETECTED)) {
  5840. DRM_DEBUG_KMS("probing DP_D\n");
  5841. intel_dp_init(dev, DP_D, PORT_D);
  5842. }
  5843. } else if (IS_GEN2(dev))
  5844. intel_dvo_init(dev);
  5845. if (SUPPORTS_TV(dev))
  5846. intel_tv_init(dev);
  5847. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  5848. encoder->base.possible_crtcs = encoder->crtc_mask;
  5849. encoder->base.possible_clones =
  5850. intel_encoder_clones(encoder);
  5851. }
  5852. /* disable all the possible outputs/crtcs before entering KMS mode */
  5853. drm_helper_disable_unused_functions(dev);
  5854. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  5855. ironlake_init_pch_refclk(dev);
  5856. }
  5857. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  5858. {
  5859. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  5860. drm_framebuffer_cleanup(fb);
  5861. drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
  5862. kfree(intel_fb);
  5863. }
  5864. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  5865. struct drm_file *file,
  5866. unsigned int *handle)
  5867. {
  5868. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  5869. struct drm_i915_gem_object *obj = intel_fb->obj;
  5870. return drm_gem_handle_create(file, &obj->base, handle);
  5871. }
  5872. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  5873. .destroy = intel_user_framebuffer_destroy,
  5874. .create_handle = intel_user_framebuffer_create_handle,
  5875. };
  5876. int intel_framebuffer_init(struct drm_device *dev,
  5877. struct intel_framebuffer *intel_fb,
  5878. struct drm_mode_fb_cmd2 *mode_cmd,
  5879. struct drm_i915_gem_object *obj)
  5880. {
  5881. int ret;
  5882. if (obj->tiling_mode == I915_TILING_Y)
  5883. return -EINVAL;
  5884. if (mode_cmd->pitches[0] & 63)
  5885. return -EINVAL;
  5886. switch (mode_cmd->pixel_format) {
  5887. case DRM_FORMAT_RGB332:
  5888. case DRM_FORMAT_RGB565:
  5889. case DRM_FORMAT_XRGB8888:
  5890. case DRM_FORMAT_XBGR8888:
  5891. case DRM_FORMAT_ARGB8888:
  5892. case DRM_FORMAT_XRGB2101010:
  5893. case DRM_FORMAT_ARGB2101010:
  5894. /* RGB formats are common across chipsets */
  5895. break;
  5896. case DRM_FORMAT_YUYV:
  5897. case DRM_FORMAT_UYVY:
  5898. case DRM_FORMAT_YVYU:
  5899. case DRM_FORMAT_VYUY:
  5900. break;
  5901. default:
  5902. DRM_DEBUG_KMS("unsupported pixel format %u\n",
  5903. mode_cmd->pixel_format);
  5904. return -EINVAL;
  5905. }
  5906. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  5907. if (ret) {
  5908. DRM_ERROR("framebuffer init failed %d\n", ret);
  5909. return ret;
  5910. }
  5911. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  5912. intel_fb->obj = obj;
  5913. return 0;
  5914. }
  5915. static struct drm_framebuffer *
  5916. intel_user_framebuffer_create(struct drm_device *dev,
  5917. struct drm_file *filp,
  5918. struct drm_mode_fb_cmd2 *mode_cmd)
  5919. {
  5920. struct drm_i915_gem_object *obj;
  5921. obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
  5922. mode_cmd->handles[0]));
  5923. if (&obj->base == NULL)
  5924. return ERR_PTR(-ENOENT);
  5925. return intel_framebuffer_create(dev, mode_cmd, obj);
  5926. }
  5927. static const struct drm_mode_config_funcs intel_mode_funcs = {
  5928. .fb_create = intel_user_framebuffer_create,
  5929. .output_poll_changed = intel_fb_output_poll_changed,
  5930. };
  5931. /* Set up chip specific display functions */
  5932. static void intel_init_display(struct drm_device *dev)
  5933. {
  5934. struct drm_i915_private *dev_priv = dev->dev_private;
  5935. /* We always want a DPMS function */
  5936. if (HAS_PCH_SPLIT(dev)) {
  5937. dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
  5938. dev_priv->display.crtc_enable = ironlake_crtc_enable;
  5939. dev_priv->display.crtc_disable = ironlake_crtc_disable;
  5940. dev_priv->display.off = ironlake_crtc_off;
  5941. dev_priv->display.update_plane = ironlake_update_plane;
  5942. } else {
  5943. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  5944. dev_priv->display.crtc_enable = i9xx_crtc_enable;
  5945. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  5946. dev_priv->display.off = i9xx_crtc_off;
  5947. dev_priv->display.update_plane = i9xx_update_plane;
  5948. }
  5949. /* Returns the core display clock speed */
  5950. if (IS_VALLEYVIEW(dev))
  5951. dev_priv->display.get_display_clock_speed =
  5952. valleyview_get_display_clock_speed;
  5953. else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
  5954. dev_priv->display.get_display_clock_speed =
  5955. i945_get_display_clock_speed;
  5956. else if (IS_I915G(dev))
  5957. dev_priv->display.get_display_clock_speed =
  5958. i915_get_display_clock_speed;
  5959. else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
  5960. dev_priv->display.get_display_clock_speed =
  5961. i9xx_misc_get_display_clock_speed;
  5962. else if (IS_I915GM(dev))
  5963. dev_priv->display.get_display_clock_speed =
  5964. i915gm_get_display_clock_speed;
  5965. else if (IS_I865G(dev))
  5966. dev_priv->display.get_display_clock_speed =
  5967. i865_get_display_clock_speed;
  5968. else if (IS_I85X(dev))
  5969. dev_priv->display.get_display_clock_speed =
  5970. i855_get_display_clock_speed;
  5971. else /* 852, 830 */
  5972. dev_priv->display.get_display_clock_speed =
  5973. i830_get_display_clock_speed;
  5974. if (HAS_PCH_SPLIT(dev)) {
  5975. if (IS_GEN5(dev)) {
  5976. dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  5977. dev_priv->display.write_eld = ironlake_write_eld;
  5978. } else if (IS_GEN6(dev)) {
  5979. dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  5980. dev_priv->display.write_eld = ironlake_write_eld;
  5981. } else if (IS_IVYBRIDGE(dev)) {
  5982. /* FIXME: detect B0+ stepping and use auto training */
  5983. dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  5984. dev_priv->display.write_eld = ironlake_write_eld;
  5985. } else if (IS_HASWELL(dev)) {
  5986. dev_priv->display.fdi_link_train = hsw_fdi_link_train;
  5987. dev_priv->display.write_eld = haswell_write_eld;
  5988. } else
  5989. dev_priv->display.update_wm = NULL;
  5990. } else if (IS_G4X(dev)) {
  5991. dev_priv->display.write_eld = g4x_write_eld;
  5992. }
  5993. /* Default just returns -ENODEV to indicate unsupported */
  5994. dev_priv->display.queue_flip = intel_default_queue_flip;
  5995. switch (INTEL_INFO(dev)->gen) {
  5996. case 2:
  5997. dev_priv->display.queue_flip = intel_gen2_queue_flip;
  5998. break;
  5999. case 3:
  6000. dev_priv->display.queue_flip = intel_gen3_queue_flip;
  6001. break;
  6002. case 4:
  6003. case 5:
  6004. dev_priv->display.queue_flip = intel_gen4_queue_flip;
  6005. break;
  6006. case 6:
  6007. dev_priv->display.queue_flip = intel_gen6_queue_flip;
  6008. break;
  6009. case 7:
  6010. dev_priv->display.queue_flip = intel_gen7_queue_flip;
  6011. break;
  6012. }
  6013. }
  6014. /*
  6015. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  6016. * resume, or other times. This quirk makes sure that's the case for
  6017. * affected systems.
  6018. */
  6019. static void quirk_pipea_force(struct drm_device *dev)
  6020. {
  6021. struct drm_i915_private *dev_priv = dev->dev_private;
  6022. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  6023. DRM_INFO("applying pipe a force quirk\n");
  6024. }
  6025. /*
  6026. * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  6027. */
  6028. static void quirk_ssc_force_disable(struct drm_device *dev)
  6029. {
  6030. struct drm_i915_private *dev_priv = dev->dev_private;
  6031. dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  6032. DRM_INFO("applying lvds SSC disable quirk\n");
  6033. }
  6034. /*
  6035. * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  6036. * brightness value
  6037. */
  6038. static void quirk_invert_brightness(struct drm_device *dev)
  6039. {
  6040. struct drm_i915_private *dev_priv = dev->dev_private;
  6041. dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
  6042. DRM_INFO("applying inverted panel brightness quirk\n");
  6043. }
  6044. struct intel_quirk {
  6045. int device;
  6046. int subsystem_vendor;
  6047. int subsystem_device;
  6048. void (*hook)(struct drm_device *dev);
  6049. };
  6050. static struct intel_quirk intel_quirks[] = {
  6051. /* HP Mini needs pipe A force quirk (LP: #322104) */
  6052. { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
  6053. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  6054. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  6055. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  6056. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  6057. /* 855 & before need to leave pipe A & dpll A up */
  6058. { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  6059. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  6060. { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  6061. /* Lenovo U160 cannot use SSC on LVDS */
  6062. { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  6063. /* Sony Vaio Y cannot use SSC on LVDS */
  6064. { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  6065. /* Acer Aspire 5734Z must invert backlight brightness */
  6066. { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
  6067. };
  6068. static void intel_init_quirks(struct drm_device *dev)
  6069. {
  6070. struct pci_dev *d = dev->pdev;
  6071. int i;
  6072. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  6073. struct intel_quirk *q = &intel_quirks[i];
  6074. if (d->device == q->device &&
  6075. (d->subsystem_vendor == q->subsystem_vendor ||
  6076. q->subsystem_vendor == PCI_ANY_ID) &&
  6077. (d->subsystem_device == q->subsystem_device ||
  6078. q->subsystem_device == PCI_ANY_ID))
  6079. q->hook(dev);
  6080. }
  6081. }
  6082. /* Disable the VGA plane that we never use */
  6083. static void i915_disable_vga(struct drm_device *dev)
  6084. {
  6085. struct drm_i915_private *dev_priv = dev->dev_private;
  6086. u8 sr1;
  6087. u32 vga_reg;
  6088. if (HAS_PCH_SPLIT(dev))
  6089. vga_reg = CPU_VGACNTRL;
  6090. else
  6091. vga_reg = VGACNTRL;
  6092. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  6093. outb(SR01, VGA_SR_INDEX);
  6094. sr1 = inb(VGA_SR_DATA);
  6095. outb(sr1 | 1<<5, VGA_SR_DATA);
  6096. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  6097. udelay(300);
  6098. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  6099. POSTING_READ(vga_reg);
  6100. }
  6101. void intel_modeset_init_hw(struct drm_device *dev)
  6102. {
  6103. /* We attempt to init the necessary power wells early in the initialization
  6104. * time, so the subsystems that expect power to be enabled can work.
  6105. */
  6106. intel_init_power_wells(dev);
  6107. intel_prepare_ddi(dev);
  6108. intel_init_clock_gating(dev);
  6109. mutex_lock(&dev->struct_mutex);
  6110. intel_enable_gt_powersave(dev);
  6111. mutex_unlock(&dev->struct_mutex);
  6112. }
  6113. void intel_modeset_init(struct drm_device *dev)
  6114. {
  6115. struct drm_i915_private *dev_priv = dev->dev_private;
  6116. int i, ret;
  6117. drm_mode_config_init(dev);
  6118. dev->mode_config.min_width = 0;
  6119. dev->mode_config.min_height = 0;
  6120. dev->mode_config.preferred_depth = 24;
  6121. dev->mode_config.prefer_shadow = 1;
  6122. dev->mode_config.funcs = &intel_mode_funcs;
  6123. intel_init_quirks(dev);
  6124. intel_init_pm(dev);
  6125. intel_init_display(dev);
  6126. if (IS_GEN2(dev)) {
  6127. dev->mode_config.max_width = 2048;
  6128. dev->mode_config.max_height = 2048;
  6129. } else if (IS_GEN3(dev)) {
  6130. dev->mode_config.max_width = 4096;
  6131. dev->mode_config.max_height = 4096;
  6132. } else {
  6133. dev->mode_config.max_width = 8192;
  6134. dev->mode_config.max_height = 8192;
  6135. }
  6136. dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
  6137. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  6138. dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
  6139. for (i = 0; i < dev_priv->num_pipe; i++) {
  6140. intel_crtc_init(dev, i);
  6141. ret = intel_plane_init(dev, i);
  6142. if (ret)
  6143. DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
  6144. }
  6145. intel_pch_pll_init(dev);
  6146. /* Just disable it once at startup */
  6147. i915_disable_vga(dev);
  6148. intel_setup_outputs(dev);
  6149. }
  6150. void intel_modeset_gem_init(struct drm_device *dev)
  6151. {
  6152. intel_modeset_init_hw(dev);
  6153. intel_setup_overlay(dev);
  6154. }
  6155. void intel_modeset_cleanup(struct drm_device *dev)
  6156. {
  6157. struct drm_i915_private *dev_priv = dev->dev_private;
  6158. struct drm_crtc *crtc;
  6159. struct intel_crtc *intel_crtc;
  6160. drm_kms_helper_poll_fini(dev);
  6161. mutex_lock(&dev->struct_mutex);
  6162. intel_unregister_dsm_handler();
  6163. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6164. /* Skip inactive CRTCs */
  6165. if (!crtc->fb)
  6166. continue;
  6167. intel_crtc = to_intel_crtc(crtc);
  6168. intel_increase_pllclock(crtc);
  6169. }
  6170. intel_disable_fbc(dev);
  6171. intel_disable_gt_powersave(dev);
  6172. ironlake_teardown_rc6(dev);
  6173. if (IS_VALLEYVIEW(dev))
  6174. vlv_init_dpio(dev);
  6175. mutex_unlock(&dev->struct_mutex);
  6176. /* Disable the irq before mode object teardown, for the irq might
  6177. * enqueue unpin/hotplug work. */
  6178. drm_irq_uninstall(dev);
  6179. cancel_work_sync(&dev_priv->hotplug_work);
  6180. cancel_work_sync(&dev_priv->rps.work);
  6181. /* flush any delayed tasks or pending work */
  6182. flush_scheduled_work();
  6183. drm_mode_config_cleanup(dev);
  6184. }
  6185. /*
  6186. * Return which encoder is currently attached for connector.
  6187. */
  6188. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  6189. {
  6190. return &intel_attached_encoder(connector)->base;
  6191. }
  6192. void intel_connector_attach_encoder(struct intel_connector *connector,
  6193. struct intel_encoder *encoder)
  6194. {
  6195. connector->encoder = encoder;
  6196. drm_mode_connector_attach_encoder(&connector->base,
  6197. &encoder->base);
  6198. }
  6199. /*
  6200. * set vga decode state - true == enable VGA decode
  6201. */
  6202. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  6203. {
  6204. struct drm_i915_private *dev_priv = dev->dev_private;
  6205. u16 gmch_ctrl;
  6206. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  6207. if (state)
  6208. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  6209. else
  6210. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  6211. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  6212. return 0;
  6213. }
  6214. #ifdef CONFIG_DEBUG_FS
  6215. #include <linux/seq_file.h>
  6216. struct intel_display_error_state {
  6217. struct intel_cursor_error_state {
  6218. u32 control;
  6219. u32 position;
  6220. u32 base;
  6221. u32 size;
  6222. } cursor[I915_MAX_PIPES];
  6223. struct intel_pipe_error_state {
  6224. u32 conf;
  6225. u32 source;
  6226. u32 htotal;
  6227. u32 hblank;
  6228. u32 hsync;
  6229. u32 vtotal;
  6230. u32 vblank;
  6231. u32 vsync;
  6232. } pipe[I915_MAX_PIPES];
  6233. struct intel_plane_error_state {
  6234. u32 control;
  6235. u32 stride;
  6236. u32 size;
  6237. u32 pos;
  6238. u32 addr;
  6239. u32 surface;
  6240. u32 tile_offset;
  6241. } plane[I915_MAX_PIPES];
  6242. };
  6243. struct intel_display_error_state *
  6244. intel_display_capture_error_state(struct drm_device *dev)
  6245. {
  6246. drm_i915_private_t *dev_priv = dev->dev_private;
  6247. struct intel_display_error_state *error;
  6248. int i;
  6249. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  6250. if (error == NULL)
  6251. return NULL;
  6252. for_each_pipe(i) {
  6253. error->cursor[i].control = I915_READ(CURCNTR(i));
  6254. error->cursor[i].position = I915_READ(CURPOS(i));
  6255. error->cursor[i].base = I915_READ(CURBASE(i));
  6256. error->plane[i].control = I915_READ(DSPCNTR(i));
  6257. error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  6258. error->plane[i].size = I915_READ(DSPSIZE(i));
  6259. error->plane[i].pos = I915_READ(DSPPOS(i));
  6260. error->plane[i].addr = I915_READ(DSPADDR(i));
  6261. if (INTEL_INFO(dev)->gen >= 4) {
  6262. error->plane[i].surface = I915_READ(DSPSURF(i));
  6263. error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  6264. }
  6265. error->pipe[i].conf = I915_READ(PIPECONF(i));
  6266. error->pipe[i].source = I915_READ(PIPESRC(i));
  6267. error->pipe[i].htotal = I915_READ(HTOTAL(i));
  6268. error->pipe[i].hblank = I915_READ(HBLANK(i));
  6269. error->pipe[i].hsync = I915_READ(HSYNC(i));
  6270. error->pipe[i].vtotal = I915_READ(VTOTAL(i));
  6271. error->pipe[i].vblank = I915_READ(VBLANK(i));
  6272. error->pipe[i].vsync = I915_READ(VSYNC(i));
  6273. }
  6274. return error;
  6275. }
  6276. void
  6277. intel_display_print_error_state(struct seq_file *m,
  6278. struct drm_device *dev,
  6279. struct intel_display_error_state *error)
  6280. {
  6281. drm_i915_private_t *dev_priv = dev->dev_private;
  6282. int i;
  6283. seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
  6284. for_each_pipe(i) {
  6285. seq_printf(m, "Pipe [%d]:\n", i);
  6286. seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
  6287. seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
  6288. seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
  6289. seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
  6290. seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
  6291. seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
  6292. seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
  6293. seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
  6294. seq_printf(m, "Plane [%d]:\n", i);
  6295. seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
  6296. seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
  6297. seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
  6298. seq_printf(m, " POS: %08x\n", error->plane[i].pos);
  6299. seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
  6300. if (INTEL_INFO(dev)->gen >= 4) {
  6301. seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
  6302. seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
  6303. }
  6304. seq_printf(m, "Cursor [%d]:\n", i);
  6305. seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
  6306. seq_printf(m, " POS: %08x\n", error->cursor[i].position);
  6307. seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
  6308. }
  6309. }
  6310. #endif