ehci-hcd.c 31 KB

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  1. /*
  2. * Copyright (c) 2000-2004 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the
  6. * Free Software Foundation; either version 2 of the License, or (at your
  7. * option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software Foundation,
  16. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. #include <linux/module.h>
  19. #include <linux/pci.h>
  20. #include <linux/dmapool.h>
  21. #include <linux/kernel.h>
  22. #include <linux/delay.h>
  23. #include <linux/ioport.h>
  24. #include <linux/sched.h>
  25. #include <linux/slab.h>
  26. #include <linux/errno.h>
  27. #include <linux/init.h>
  28. #include <linux/timer.h>
  29. #include <linux/list.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/reboot.h>
  32. #include <linux/usb.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/debugfs.h>
  36. #include "../core/hcd.h"
  37. #include <asm/byteorder.h>
  38. #include <asm/io.h>
  39. #include <asm/irq.h>
  40. #include <asm/system.h>
  41. #include <asm/unaligned.h>
  42. /*-------------------------------------------------------------------------*/
  43. /*
  44. * EHCI hc_driver implementation ... experimental, incomplete.
  45. * Based on the final 1.0 register interface specification.
  46. *
  47. * USB 2.0 shows up in upcoming www.pcmcia.org technology.
  48. * First was PCMCIA, like ISA; then CardBus, which is PCI.
  49. * Next comes "CardBay", using USB 2.0 signals.
  50. *
  51. * Contains additional contributions by Brad Hards, Rory Bolt, and others.
  52. * Special thanks to Intel and VIA for providing host controllers to
  53. * test this driver on, and Cypress (including In-System Design) for
  54. * providing early devices for those host controllers to talk to!
  55. */
  56. #define DRIVER_VERSION "10 Dec 2004"
  57. #define DRIVER_AUTHOR "David Brownell"
  58. #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
  59. static const char hcd_name [] = "ehci_hcd";
  60. #undef VERBOSE_DEBUG
  61. #undef EHCI_URB_TRACE
  62. #ifdef DEBUG
  63. #define EHCI_STATS
  64. #endif
  65. /* magic numbers that can affect system performance */
  66. #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
  67. #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
  68. #define EHCI_TUNE_RL_TT 0
  69. #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
  70. #define EHCI_TUNE_MULT_TT 1
  71. #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
  72. #define EHCI_IAA_MSECS 10 /* arbitrary */
  73. #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
  74. #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
  75. #define EHCI_SHRINK_JIFFIES (HZ/100) /* async qh unlink delay */
  76. #define EHCI_SHRINK_UFRAMES (10*8) /* same value in uframes */
  77. /* Initial IRQ latency: faster than hw default */
  78. static int log2_irq_thresh = 0; // 0 to 6
  79. module_param (log2_irq_thresh, int, S_IRUGO);
  80. MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
  81. /* initial park setting: slower than hw default */
  82. static unsigned park = 0;
  83. module_param (park, uint, S_IRUGO);
  84. MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
  85. /* for flakey hardware, ignore overcurrent indicators */
  86. static int ignore_oc = 0;
  87. module_param (ignore_oc, bool, S_IRUGO);
  88. MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
  89. #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
  90. /*-------------------------------------------------------------------------*/
  91. #include "ehci.h"
  92. #include "ehci-dbg.c"
  93. /*-------------------------------------------------------------------------*/
  94. /*
  95. * handshake - spin reading hc until handshake completes or fails
  96. * @ptr: address of hc register to be read
  97. * @mask: bits to look at in result of read
  98. * @done: value of those bits when handshake succeeds
  99. * @usec: timeout in microseconds
  100. *
  101. * Returns negative errno, or zero on success
  102. *
  103. * Success happens when the "mask" bits have the specified value (hardware
  104. * handshake done). There are two failure modes: "usec" have passed (major
  105. * hardware flakeout), or the register reads as all-ones (hardware removed).
  106. *
  107. * That last failure should_only happen in cases like physical cardbus eject
  108. * before driver shutdown. But it also seems to be caused by bugs in cardbus
  109. * bridge shutdown: shutting down the bridge before the devices using it.
  110. */
  111. static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
  112. u32 mask, u32 done, int usec)
  113. {
  114. u32 result;
  115. do {
  116. result = ehci_readl(ehci, ptr);
  117. if (result == ~(u32)0) /* card removed */
  118. return -ENODEV;
  119. result &= mask;
  120. if (result == done)
  121. return 0;
  122. udelay (1);
  123. usec--;
  124. } while (usec > 0);
  125. return -ETIMEDOUT;
  126. }
  127. static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
  128. u32 mask, u32 done, int usec)
  129. {
  130. int error = handshake(ehci, ptr, mask, done, usec);
  131. if (error)
  132. ehci_to_hcd(ehci)->state = HC_STATE_HALT;
  133. return error;
  134. }
  135. /* force HC to halt state from unknown (EHCI spec section 2.3) */
  136. static int ehci_halt (struct ehci_hcd *ehci)
  137. {
  138. u32 temp = ehci_readl(ehci, &ehci->regs->status);
  139. /* disable any irqs left enabled by previous code */
  140. ehci_writel(ehci, 0, &ehci->regs->intr_enable);
  141. if ((temp & STS_HALT) != 0)
  142. return 0;
  143. temp = ehci_readl(ehci, &ehci->regs->command);
  144. temp &= ~CMD_RUN;
  145. ehci_writel(ehci, temp, &ehci->regs->command);
  146. return handshake (ehci, &ehci->regs->status,
  147. STS_HALT, STS_HALT, 16 * 125);
  148. }
  149. /* put TDI/ARC silicon into EHCI mode */
  150. static void tdi_reset (struct ehci_hcd *ehci)
  151. {
  152. u32 __iomem *reg_ptr;
  153. u32 tmp;
  154. reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
  155. tmp = ehci_readl(ehci, reg_ptr);
  156. tmp |= USBMODE_CM_HC;
  157. /* The default byte access to MMR space is LE after
  158. * controller reset. Set the required endian mode
  159. * for transfer buffers to match the host microprocessor
  160. */
  161. if (ehci_big_endian_mmio(ehci))
  162. tmp |= USBMODE_BE;
  163. ehci_writel(ehci, tmp, reg_ptr);
  164. }
  165. /* reset a non-running (STS_HALT == 1) controller */
  166. static int ehci_reset (struct ehci_hcd *ehci)
  167. {
  168. int retval;
  169. u32 command = ehci_readl(ehci, &ehci->regs->command);
  170. command |= CMD_RESET;
  171. dbg_cmd (ehci, "reset", command);
  172. ehci_writel(ehci, command, &ehci->regs->command);
  173. ehci_to_hcd(ehci)->state = HC_STATE_HALT;
  174. ehci->next_statechange = jiffies;
  175. retval = handshake (ehci, &ehci->regs->command,
  176. CMD_RESET, 0, 250 * 1000);
  177. if (retval)
  178. return retval;
  179. if (ehci_is_TDI(ehci))
  180. tdi_reset (ehci);
  181. return retval;
  182. }
  183. /* idle the controller (from running) */
  184. static void ehci_quiesce (struct ehci_hcd *ehci)
  185. {
  186. u32 temp;
  187. #ifdef DEBUG
  188. if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
  189. BUG ();
  190. #endif
  191. /* wait for any schedule enables/disables to take effect */
  192. temp = ehci_readl(ehci, &ehci->regs->command) << 10;
  193. temp &= STS_ASS | STS_PSS;
  194. if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
  195. STS_ASS | STS_PSS, temp, 16 * 125))
  196. return;
  197. /* then disable anything that's still active */
  198. temp = ehci_readl(ehci, &ehci->regs->command);
  199. temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
  200. ehci_writel(ehci, temp, &ehci->regs->command);
  201. /* hardware can take 16 microframes to turn off ... */
  202. handshake_on_error_set_halt(ehci, &ehci->regs->status,
  203. STS_ASS | STS_PSS, 0, 16 * 125);
  204. }
  205. /*-------------------------------------------------------------------------*/
  206. static void end_unlink_async(struct ehci_hcd *ehci);
  207. static void ehci_work(struct ehci_hcd *ehci);
  208. #include "ehci-hub.c"
  209. #include "ehci-mem.c"
  210. #include "ehci-q.c"
  211. #include "ehci-sched.c"
  212. /*-------------------------------------------------------------------------*/
  213. static void ehci_iaa_watchdog(unsigned long param)
  214. {
  215. struct ehci_hcd *ehci = (struct ehci_hcd *) param;
  216. unsigned long flags;
  217. spin_lock_irqsave (&ehci->lock, flags);
  218. /* Lost IAA irqs wedge things badly; seen first with a vt8235.
  219. * So we need this watchdog, but must protect it against both
  220. * (a) SMP races against real IAA firing and retriggering, and
  221. * (b) clean HC shutdown, when IAA watchdog was pending.
  222. */
  223. if (ehci->reclaim
  224. && !timer_pending(&ehci->iaa_watchdog)
  225. && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
  226. u32 cmd, status;
  227. /* If we get here, IAA is *REALLY* late. It's barely
  228. * conceivable that the system is so busy that CMD_IAAD
  229. * is still legitimately set, so let's be sure it's
  230. * clear before we read STS_IAA. (The HC should clear
  231. * CMD_IAAD when it sets STS_IAA.)
  232. */
  233. cmd = ehci_readl(ehci, &ehci->regs->command);
  234. if (cmd & CMD_IAAD)
  235. ehci_writel(ehci, cmd & ~CMD_IAAD,
  236. &ehci->regs->command);
  237. /* If IAA is set here it either legitimately triggered
  238. * before we cleared IAAD above (but _way_ late, so we'll
  239. * still count it as lost) ... or a silicon erratum:
  240. * - VIA seems to set IAA without triggering the IRQ;
  241. * - IAAD potentially cleared without setting IAA.
  242. */
  243. status = ehci_readl(ehci, &ehci->regs->status);
  244. if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
  245. COUNT (ehci->stats.lost_iaa);
  246. ehci_writel(ehci, STS_IAA, &ehci->regs->status);
  247. }
  248. ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
  249. status, cmd);
  250. end_unlink_async(ehci);
  251. }
  252. spin_unlock_irqrestore(&ehci->lock, flags);
  253. }
  254. static void ehci_watchdog(unsigned long param)
  255. {
  256. struct ehci_hcd *ehci = (struct ehci_hcd *) param;
  257. unsigned long flags;
  258. spin_lock_irqsave(&ehci->lock, flags);
  259. /* stop async processing after it's idled a bit */
  260. if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
  261. start_unlink_async (ehci, ehci->async);
  262. /* ehci could run by timer, without IRQs ... */
  263. ehci_work (ehci);
  264. spin_unlock_irqrestore (&ehci->lock, flags);
  265. }
  266. /* On some systems, leaving remote wakeup enabled prevents system shutdown.
  267. * The firmware seems to think that powering off is a wakeup event!
  268. * This routine turns off remote wakeup and everything else, on all ports.
  269. */
  270. static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
  271. {
  272. int port = HCS_N_PORTS(ehci->hcs_params);
  273. while (port--)
  274. ehci_writel(ehci, PORT_RWC_BITS,
  275. &ehci->regs->port_status[port]);
  276. }
  277. /*
  278. * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
  279. * Should be called with ehci->lock held.
  280. */
  281. static void ehci_silence_controller(struct ehci_hcd *ehci)
  282. {
  283. ehci_halt(ehci);
  284. ehci_turn_off_all_ports(ehci);
  285. /* make BIOS/etc use companion controller during reboot */
  286. ehci_writel(ehci, 0, &ehci->regs->configured_flag);
  287. /* unblock posted writes */
  288. ehci_readl(ehci, &ehci->regs->configured_flag);
  289. }
  290. /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
  291. * This forcibly disables dma and IRQs, helping kexec and other cases
  292. * where the next system software may expect clean state.
  293. */
  294. static void ehci_shutdown(struct usb_hcd *hcd)
  295. {
  296. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  297. del_timer_sync(&ehci->watchdog);
  298. del_timer_sync(&ehci->iaa_watchdog);
  299. spin_lock_irq(&ehci->lock);
  300. ehci_silence_controller(ehci);
  301. spin_unlock_irq(&ehci->lock);
  302. }
  303. static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
  304. {
  305. unsigned port;
  306. if (!HCS_PPC (ehci->hcs_params))
  307. return;
  308. ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
  309. for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
  310. (void) ehci_hub_control(ehci_to_hcd(ehci),
  311. is_on ? SetPortFeature : ClearPortFeature,
  312. USB_PORT_FEAT_POWER,
  313. port--, NULL, 0);
  314. /* Flush those writes */
  315. ehci_readl(ehci, &ehci->regs->command);
  316. msleep(20);
  317. }
  318. /*-------------------------------------------------------------------------*/
  319. /*
  320. * ehci_work is called from some interrupts, timers, and so on.
  321. * it calls driver completion functions, after dropping ehci->lock.
  322. */
  323. static void ehci_work (struct ehci_hcd *ehci)
  324. {
  325. timer_action_done (ehci, TIMER_IO_WATCHDOG);
  326. /* another CPU may drop ehci->lock during a schedule scan while
  327. * it reports urb completions. this flag guards against bogus
  328. * attempts at re-entrant schedule scanning.
  329. */
  330. if (ehci->scanning)
  331. return;
  332. ehci->scanning = 1;
  333. scan_async (ehci);
  334. if (ehci->next_uframe != -1)
  335. scan_periodic (ehci);
  336. ehci->scanning = 0;
  337. /* the IO watchdog guards against hardware or driver bugs that
  338. * misplace IRQs, and should let us run completely without IRQs.
  339. * such lossage has been observed on both VT6202 and VT8235.
  340. */
  341. if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
  342. (ehci->async->qh_next.ptr != NULL ||
  343. ehci->periodic_sched != 0))
  344. timer_action (ehci, TIMER_IO_WATCHDOG);
  345. }
  346. /*
  347. * Called when the ehci_hcd module is removed.
  348. */
  349. static void ehci_stop (struct usb_hcd *hcd)
  350. {
  351. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  352. ehci_dbg (ehci, "stop\n");
  353. /* no more interrupts ... */
  354. del_timer_sync (&ehci->watchdog);
  355. del_timer_sync(&ehci->iaa_watchdog);
  356. spin_lock_irq(&ehci->lock);
  357. if (HC_IS_RUNNING (hcd->state))
  358. ehci_quiesce (ehci);
  359. ehci_silence_controller(ehci);
  360. ehci_reset (ehci);
  361. spin_unlock_irq(&ehci->lock);
  362. remove_companion_file(ehci);
  363. remove_debug_files (ehci);
  364. /* root hub is shut down separately (first, when possible) */
  365. spin_lock_irq (&ehci->lock);
  366. if (ehci->async)
  367. ehci_work (ehci);
  368. spin_unlock_irq (&ehci->lock);
  369. ehci_mem_cleanup (ehci);
  370. #ifdef EHCI_STATS
  371. ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
  372. ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
  373. ehci->stats.lost_iaa);
  374. ehci_dbg (ehci, "complete %ld unlink %ld\n",
  375. ehci->stats.complete, ehci->stats.unlink);
  376. #endif
  377. dbg_status (ehci, "ehci_stop completed",
  378. ehci_readl(ehci, &ehci->regs->status));
  379. }
  380. /* one-time init, only for memory state */
  381. static int ehci_init(struct usb_hcd *hcd)
  382. {
  383. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  384. u32 temp;
  385. int retval;
  386. u32 hcc_params;
  387. spin_lock_init(&ehci->lock);
  388. init_timer(&ehci->watchdog);
  389. ehci->watchdog.function = ehci_watchdog;
  390. ehci->watchdog.data = (unsigned long) ehci;
  391. init_timer(&ehci->iaa_watchdog);
  392. ehci->iaa_watchdog.function = ehci_iaa_watchdog;
  393. ehci->iaa_watchdog.data = (unsigned long) ehci;
  394. /*
  395. * hw default: 1K periodic list heads, one per frame.
  396. * periodic_size can shrink by USBCMD update if hcc_params allows.
  397. */
  398. ehci->periodic_size = DEFAULT_I_TDPS;
  399. if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
  400. return retval;
  401. /* controllers may cache some of the periodic schedule ... */
  402. hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
  403. if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
  404. ehci->i_thresh = 8;
  405. else // N microframes cached
  406. ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
  407. ehci->reclaim = NULL;
  408. ehci->next_uframe = -1;
  409. /*
  410. * dedicate a qh for the async ring head, since we couldn't unlink
  411. * a 'real' qh without stopping the async schedule [4.8]. use it
  412. * as the 'reclamation list head' too.
  413. * its dummy is used in hw_alt_next of many tds, to prevent the qh
  414. * from automatically advancing to the next td after short reads.
  415. */
  416. ehci->async->qh_next.qh = NULL;
  417. ehci->async->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
  418. ehci->async->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
  419. ehci->async->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
  420. ehci->async->hw_qtd_next = EHCI_LIST_END(ehci);
  421. ehci->async->qh_state = QH_STATE_LINKED;
  422. ehci->async->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
  423. /* clear interrupt enables, set irq latency */
  424. if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
  425. log2_irq_thresh = 0;
  426. temp = 1 << (16 + log2_irq_thresh);
  427. if (HCC_CANPARK(hcc_params)) {
  428. /* HW default park == 3, on hardware that supports it (like
  429. * NVidia and ALI silicon), maximizes throughput on the async
  430. * schedule by avoiding QH fetches between transfers.
  431. *
  432. * With fast usb storage devices and NForce2, "park" seems to
  433. * make problems: throughput reduction (!), data errors...
  434. */
  435. if (park) {
  436. park = min(park, (unsigned) 3);
  437. temp |= CMD_PARK;
  438. temp |= park << 8;
  439. }
  440. ehci_dbg(ehci, "park %d\n", park);
  441. }
  442. if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
  443. /* periodic schedule size can be smaller than default */
  444. temp &= ~(3 << 2);
  445. temp |= (EHCI_TUNE_FLS << 2);
  446. switch (EHCI_TUNE_FLS) {
  447. case 0: ehci->periodic_size = 1024; break;
  448. case 1: ehci->periodic_size = 512; break;
  449. case 2: ehci->periodic_size = 256; break;
  450. default: BUG();
  451. }
  452. }
  453. ehci->command = temp;
  454. return 0;
  455. }
  456. /* start HC running; it's halted, ehci_init() has been run (once) */
  457. static int ehci_run (struct usb_hcd *hcd)
  458. {
  459. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  460. int retval;
  461. u32 temp;
  462. u32 hcc_params;
  463. hcd->uses_new_polling = 1;
  464. hcd->poll_rh = 0;
  465. /* EHCI spec section 4.1 */
  466. if ((retval = ehci_reset(ehci)) != 0) {
  467. ehci_mem_cleanup(ehci);
  468. return retval;
  469. }
  470. ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
  471. ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
  472. /*
  473. * hcc_params controls whether ehci->regs->segment must (!!!)
  474. * be used; it constrains QH/ITD/SITD and QTD locations.
  475. * pci_pool consistent memory always uses segment zero.
  476. * streaming mappings for I/O buffers, like pci_map_single(),
  477. * can return segments above 4GB, if the device allows.
  478. *
  479. * NOTE: the dma mask is visible through dma_supported(), so
  480. * drivers can pass this info along ... like NETIF_F_HIGHDMA,
  481. * Scsi_Host.highmem_io, and so forth. It's readonly to all
  482. * host side drivers though.
  483. */
  484. hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
  485. if (HCC_64BIT_ADDR(hcc_params)) {
  486. ehci_writel(ehci, 0, &ehci->regs->segment);
  487. #if 0
  488. // this is deeply broken on almost all architectures
  489. if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK))
  490. ehci_info(ehci, "enabled 64bit DMA\n");
  491. #endif
  492. }
  493. // Philips, Intel, and maybe others need CMD_RUN before the
  494. // root hub will detect new devices (why?); NEC doesn't
  495. ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
  496. ehci->command |= CMD_RUN;
  497. ehci_writel(ehci, ehci->command, &ehci->regs->command);
  498. dbg_cmd (ehci, "init", ehci->command);
  499. /*
  500. * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
  501. * are explicitly handed to companion controller(s), so no TT is
  502. * involved with the root hub. (Except where one is integrated,
  503. * and there's no companion controller unless maybe for USB OTG.)
  504. *
  505. * Turning on the CF flag will transfer ownership of all ports
  506. * from the companions to the EHCI controller. If any of the
  507. * companions are in the middle of a port reset at the time, it
  508. * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
  509. * guarantees that no resets are in progress. After we set CF,
  510. * a short delay lets the hardware catch up; new resets shouldn't
  511. * be started before the port switching actions could complete.
  512. */
  513. down_write(&ehci_cf_port_reset_rwsem);
  514. hcd->state = HC_STATE_RUNNING;
  515. ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
  516. ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
  517. msleep(5);
  518. up_write(&ehci_cf_port_reset_rwsem);
  519. temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
  520. ehci_info (ehci,
  521. "USB %x.%x started, EHCI %x.%02x, driver %s%s\n",
  522. ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
  523. temp >> 8, temp & 0xff, DRIVER_VERSION,
  524. ignore_oc ? ", overcurrent ignored" : "");
  525. ehci_writel(ehci, INTR_MASK,
  526. &ehci->regs->intr_enable); /* Turn On Interrupts */
  527. /* GRR this is run-once init(), being done every time the HC starts.
  528. * So long as they're part of class devices, we can't do it init()
  529. * since the class device isn't created that early.
  530. */
  531. create_debug_files(ehci);
  532. create_companion_file(ehci);
  533. return 0;
  534. }
  535. /*-------------------------------------------------------------------------*/
  536. static irqreturn_t ehci_irq (struct usb_hcd *hcd)
  537. {
  538. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  539. u32 status, pcd_status = 0, cmd;
  540. int bh;
  541. spin_lock (&ehci->lock);
  542. status = ehci_readl(ehci, &ehci->regs->status);
  543. /* e.g. cardbus physical eject */
  544. if (status == ~(u32) 0) {
  545. ehci_dbg (ehci, "device removed\n");
  546. goto dead;
  547. }
  548. status &= INTR_MASK;
  549. if (!status) { /* irq sharing? */
  550. spin_unlock(&ehci->lock);
  551. return IRQ_NONE;
  552. }
  553. /* clear (just) interrupts */
  554. ehci_writel(ehci, status, &ehci->regs->status);
  555. cmd = ehci_readl(ehci, &ehci->regs->command);
  556. bh = 0;
  557. #ifdef VERBOSE_DEBUG
  558. /* unrequested/ignored: Frame List Rollover */
  559. dbg_status (ehci, "irq", status);
  560. #endif
  561. /* INT, ERR, and IAA interrupt rates can be throttled */
  562. /* normal [4.15.1.2] or error [4.15.1.1] completion */
  563. if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
  564. if (likely ((status & STS_ERR) == 0))
  565. COUNT (ehci->stats.normal);
  566. else
  567. COUNT (ehci->stats.error);
  568. bh = 1;
  569. }
  570. /* complete the unlinking of some qh [4.15.2.3] */
  571. if (status & STS_IAA) {
  572. /* guard against (alleged) silicon errata */
  573. if (cmd & CMD_IAAD) {
  574. ehci_writel(ehci, cmd & ~CMD_IAAD,
  575. &ehci->regs->command);
  576. ehci_dbg(ehci, "IAA with IAAD still set?\n");
  577. }
  578. if (ehci->reclaim) {
  579. COUNT(ehci->stats.reclaim);
  580. end_unlink_async(ehci);
  581. } else
  582. ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
  583. }
  584. /* remote wakeup [4.3.1] */
  585. if (status & STS_PCD) {
  586. unsigned i = HCS_N_PORTS (ehci->hcs_params);
  587. /* kick root hub later */
  588. pcd_status = status;
  589. /* resume root hub? */
  590. if (!(ehci_readl(ehci, &ehci->regs->command) & CMD_RUN))
  591. usb_hcd_resume_root_hub(hcd);
  592. while (i--) {
  593. int pstatus = ehci_readl(ehci,
  594. &ehci->regs->port_status [i]);
  595. if (pstatus & PORT_OWNER)
  596. continue;
  597. if (!(pstatus & PORT_RESUME)
  598. || ehci->reset_done [i] != 0)
  599. continue;
  600. /* start 20 msec resume signaling from this port,
  601. * and make khubd collect PORT_STAT_C_SUSPEND to
  602. * stop that signaling.
  603. */
  604. ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
  605. ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
  606. mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
  607. }
  608. }
  609. /* PCI errors [4.15.2.4] */
  610. if (unlikely ((status & STS_FATAL) != 0)) {
  611. dbg_cmd (ehci, "fatal", ehci_readl(ehci,
  612. &ehci->regs->command));
  613. dbg_status (ehci, "fatal", status);
  614. if (status & STS_HALT) {
  615. ehci_err (ehci, "fatal error\n");
  616. dead:
  617. ehci_reset (ehci);
  618. ehci_writel(ehci, 0, &ehci->regs->configured_flag);
  619. /* generic layer kills/unlinks all urbs, then
  620. * uses ehci_stop to clean up the rest
  621. */
  622. bh = 1;
  623. }
  624. }
  625. if (bh)
  626. ehci_work (ehci);
  627. spin_unlock (&ehci->lock);
  628. if (pcd_status)
  629. usb_hcd_poll_rh_status(hcd);
  630. return IRQ_HANDLED;
  631. }
  632. /*-------------------------------------------------------------------------*/
  633. /*
  634. * non-error returns are a promise to giveback() the urb later
  635. * we drop ownership so next owner (or urb unlink) can get it
  636. *
  637. * urb + dev is in hcd.self.controller.urb_list
  638. * we're queueing TDs onto software and hardware lists
  639. *
  640. * hcd-specific init for hcpriv hasn't been done yet
  641. *
  642. * NOTE: control, bulk, and interrupt share the same code to append TDs
  643. * to a (possibly active) QH, and the same QH scanning code.
  644. */
  645. static int ehci_urb_enqueue (
  646. struct usb_hcd *hcd,
  647. struct urb *urb,
  648. gfp_t mem_flags
  649. ) {
  650. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  651. struct list_head qtd_list;
  652. INIT_LIST_HEAD (&qtd_list);
  653. switch (usb_pipetype (urb->pipe)) {
  654. case PIPE_CONTROL:
  655. /* qh_completions() code doesn't handle all the fault cases
  656. * in multi-TD control transfers. Even 1KB is rare anyway.
  657. */
  658. if (urb->transfer_buffer_length > (16 * 1024))
  659. return -EMSGSIZE;
  660. /* FALLTHROUGH */
  661. /* case PIPE_BULK: */
  662. default:
  663. if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
  664. return -ENOMEM;
  665. return submit_async(ehci, urb, &qtd_list, mem_flags);
  666. case PIPE_INTERRUPT:
  667. if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
  668. return -ENOMEM;
  669. return intr_submit(ehci, urb, &qtd_list, mem_flags);
  670. case PIPE_ISOCHRONOUS:
  671. if (urb->dev->speed == USB_SPEED_HIGH)
  672. return itd_submit (ehci, urb, mem_flags);
  673. else
  674. return sitd_submit (ehci, urb, mem_flags);
  675. }
  676. }
  677. static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
  678. {
  679. /* failfast */
  680. if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim)
  681. end_unlink_async(ehci);
  682. /* if it's not linked then there's nothing to do */
  683. if (qh->qh_state != QH_STATE_LINKED)
  684. ;
  685. /* defer till later if busy */
  686. else if (ehci->reclaim) {
  687. struct ehci_qh *last;
  688. for (last = ehci->reclaim;
  689. last->reclaim;
  690. last = last->reclaim)
  691. continue;
  692. qh->qh_state = QH_STATE_UNLINK_WAIT;
  693. last->reclaim = qh;
  694. /* start IAA cycle */
  695. } else
  696. start_unlink_async (ehci, qh);
  697. }
  698. /* remove from hardware lists
  699. * completions normally happen asynchronously
  700. */
  701. static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  702. {
  703. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  704. struct ehci_qh *qh;
  705. unsigned long flags;
  706. int rc;
  707. spin_lock_irqsave (&ehci->lock, flags);
  708. rc = usb_hcd_check_unlink_urb(hcd, urb, status);
  709. if (rc)
  710. goto done;
  711. switch (usb_pipetype (urb->pipe)) {
  712. // case PIPE_CONTROL:
  713. // case PIPE_BULK:
  714. default:
  715. qh = (struct ehci_qh *) urb->hcpriv;
  716. if (!qh)
  717. break;
  718. switch (qh->qh_state) {
  719. case QH_STATE_LINKED:
  720. case QH_STATE_COMPLETING:
  721. unlink_async(ehci, qh);
  722. break;
  723. case QH_STATE_UNLINK:
  724. case QH_STATE_UNLINK_WAIT:
  725. /* already started */
  726. break;
  727. case QH_STATE_IDLE:
  728. WARN_ON(1);
  729. break;
  730. }
  731. break;
  732. case PIPE_INTERRUPT:
  733. qh = (struct ehci_qh *) urb->hcpriv;
  734. if (!qh)
  735. break;
  736. switch (qh->qh_state) {
  737. case QH_STATE_LINKED:
  738. intr_deschedule (ehci, qh);
  739. /* FALL THROUGH */
  740. case QH_STATE_IDLE:
  741. qh_completions (ehci, qh);
  742. break;
  743. default:
  744. ehci_dbg (ehci, "bogus qh %p state %d\n",
  745. qh, qh->qh_state);
  746. goto done;
  747. }
  748. /* reschedule QH iff another request is queued */
  749. if (!list_empty (&qh->qtd_list)
  750. && HC_IS_RUNNING (hcd->state)) {
  751. rc = qh_schedule(ehci, qh);
  752. /* An error here likely indicates handshake failure
  753. * or no space left in the schedule. Neither fault
  754. * should happen often ...
  755. *
  756. * FIXME kill the now-dysfunctional queued urbs
  757. */
  758. if (rc != 0)
  759. ehci_err(ehci,
  760. "can't reschedule qh %p, err %d",
  761. qh, rc);
  762. }
  763. break;
  764. case PIPE_ISOCHRONOUS:
  765. // itd or sitd ...
  766. // wait till next completion, do it then.
  767. // completion irqs can wait up to 1024 msec,
  768. break;
  769. }
  770. done:
  771. spin_unlock_irqrestore (&ehci->lock, flags);
  772. return rc;
  773. }
  774. /*-------------------------------------------------------------------------*/
  775. // bulk qh holds the data toggle
  776. static void
  777. ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
  778. {
  779. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  780. unsigned long flags;
  781. struct ehci_qh *qh, *tmp;
  782. /* ASSERT: any requests/urbs are being unlinked */
  783. /* ASSERT: nobody can be submitting urbs for this any more */
  784. rescan:
  785. spin_lock_irqsave (&ehci->lock, flags);
  786. qh = ep->hcpriv;
  787. if (!qh)
  788. goto done;
  789. /* endpoints can be iso streams. for now, we don't
  790. * accelerate iso completions ... so spin a while.
  791. */
  792. if (qh->hw_info1 == 0) {
  793. ehci_vdbg (ehci, "iso delay\n");
  794. goto idle_timeout;
  795. }
  796. if (!HC_IS_RUNNING (hcd->state))
  797. qh->qh_state = QH_STATE_IDLE;
  798. switch (qh->qh_state) {
  799. case QH_STATE_LINKED:
  800. for (tmp = ehci->async->qh_next.qh;
  801. tmp && tmp != qh;
  802. tmp = tmp->qh_next.qh)
  803. continue;
  804. /* periodic qh self-unlinks on empty */
  805. if (!tmp)
  806. goto nogood;
  807. unlink_async (ehci, qh);
  808. /* FALL THROUGH */
  809. case QH_STATE_UNLINK: /* wait for hw to finish? */
  810. case QH_STATE_UNLINK_WAIT:
  811. idle_timeout:
  812. spin_unlock_irqrestore (&ehci->lock, flags);
  813. schedule_timeout_uninterruptible(1);
  814. goto rescan;
  815. case QH_STATE_IDLE: /* fully unlinked */
  816. if (list_empty (&qh->qtd_list)) {
  817. qh_put (qh);
  818. break;
  819. }
  820. /* else FALL THROUGH */
  821. default:
  822. nogood:
  823. /* caller was supposed to have unlinked any requests;
  824. * that's not our job. just leak this memory.
  825. */
  826. ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
  827. qh, ep->desc.bEndpointAddress, qh->qh_state,
  828. list_empty (&qh->qtd_list) ? "" : "(has tds)");
  829. break;
  830. }
  831. ep->hcpriv = NULL;
  832. done:
  833. spin_unlock_irqrestore (&ehci->lock, flags);
  834. return;
  835. }
  836. static int ehci_get_frame (struct usb_hcd *hcd)
  837. {
  838. struct ehci_hcd *ehci = hcd_to_ehci (hcd);
  839. return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) %
  840. ehci->periodic_size;
  841. }
  842. /*-------------------------------------------------------------------------*/
  843. #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
  844. MODULE_DESCRIPTION (DRIVER_INFO);
  845. MODULE_AUTHOR (DRIVER_AUTHOR);
  846. MODULE_LICENSE ("GPL");
  847. #ifdef CONFIG_PCI
  848. #include "ehci-pci.c"
  849. #define PCI_DRIVER ehci_pci_driver
  850. #endif
  851. #ifdef CONFIG_USB_EHCI_FSL
  852. #include "ehci-fsl.c"
  853. #define PLATFORM_DRIVER ehci_fsl_driver
  854. #endif
  855. #ifdef CONFIG_SOC_AU1200
  856. #include "ehci-au1xxx.c"
  857. #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
  858. #endif
  859. #ifdef CONFIG_PPC_PS3
  860. #include "ehci-ps3.c"
  861. #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
  862. #endif
  863. #if defined(CONFIG_440EPX) && !defined(CONFIG_PPC_MERGE)
  864. #include "ehci-ppc-soc.c"
  865. #define PLATFORM_DRIVER ehci_ppc_soc_driver
  866. #endif
  867. #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
  868. #include "ehci-ppc-of.c"
  869. #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
  870. #endif
  871. #ifdef CONFIG_PLAT_ORION
  872. #include "ehci-orion.c"
  873. #define PLATFORM_DRIVER ehci_orion_driver
  874. #endif
  875. #ifdef CONFIG_ARCH_IXP4XX
  876. #include "ehci-ixp4xx.c"
  877. #define PLATFORM_DRIVER ixp4xx_ehci_driver
  878. #endif
  879. #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
  880. !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
  881. #error "missing bus glue for ehci-hcd"
  882. #endif
  883. static int __init ehci_hcd_init(void)
  884. {
  885. int retval = 0;
  886. pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
  887. hcd_name,
  888. sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
  889. sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
  890. #ifdef DEBUG
  891. ehci_debug_root = debugfs_create_dir("ehci", NULL);
  892. if (!ehci_debug_root)
  893. return -ENOENT;
  894. #endif
  895. #ifdef PLATFORM_DRIVER
  896. retval = platform_driver_register(&PLATFORM_DRIVER);
  897. if (retval < 0)
  898. goto clean0;
  899. #endif
  900. #ifdef PCI_DRIVER
  901. retval = pci_register_driver(&PCI_DRIVER);
  902. if (retval < 0)
  903. goto clean1;
  904. #endif
  905. #ifdef PS3_SYSTEM_BUS_DRIVER
  906. retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
  907. if (retval < 0)
  908. goto clean2;
  909. #endif
  910. #ifdef OF_PLATFORM_DRIVER
  911. retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
  912. if (retval < 0)
  913. goto clean3;
  914. #endif
  915. return retval;
  916. #ifdef OF_PLATFORM_DRIVER
  917. /* of_unregister_platform_driver(&OF_PLATFORM_DRIVER); */
  918. clean3:
  919. #endif
  920. #ifdef PS3_SYSTEM_BUS_DRIVER
  921. ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
  922. clean2:
  923. #endif
  924. #ifdef PCI_DRIVER
  925. pci_unregister_driver(&PCI_DRIVER);
  926. clean1:
  927. #endif
  928. #ifdef PLATFORM_DRIVER
  929. platform_driver_unregister(&PLATFORM_DRIVER);
  930. clean0:
  931. #endif
  932. #ifdef DEBUG
  933. debugfs_remove(ehci_debug_root);
  934. ehci_debug_root = NULL;
  935. #endif
  936. return retval;
  937. }
  938. module_init(ehci_hcd_init);
  939. static void __exit ehci_hcd_cleanup(void)
  940. {
  941. #ifdef OF_PLATFORM_DRIVER
  942. of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
  943. #endif
  944. #ifdef PLATFORM_DRIVER
  945. platform_driver_unregister(&PLATFORM_DRIVER);
  946. #endif
  947. #ifdef PCI_DRIVER
  948. pci_unregister_driver(&PCI_DRIVER);
  949. #endif
  950. #ifdef PS3_SYSTEM_BUS_DRIVER
  951. ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
  952. #endif
  953. #ifdef DEBUG
  954. debugfs_remove(ehci_debug_root);
  955. #endif
  956. }
  957. module_exit(ehci_hcd_cleanup);