tg3.c 455 KB

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  1. /*
  2. * tg3.c: Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. * Copyright (C) 2005-2013 Broadcom Corporation.
  8. *
  9. * Firmware is:
  10. * Derived from proprietary unpublished source code,
  11. * Copyright (C) 2000-2003 Broadcom Corporation.
  12. *
  13. * Permission is hereby granted for the distribution of this firmware
  14. * data in hexadecimal or equivalent format, provided this copyright
  15. * notice is accompanying it.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/stringify.h>
  20. #include <linux/kernel.h>
  21. #include <linux/types.h>
  22. #include <linux/compiler.h>
  23. #include <linux/slab.h>
  24. #include <linux/delay.h>
  25. #include <linux/in.h>
  26. #include <linux/init.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/ioport.h>
  29. #include <linux/pci.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/skbuff.h>
  33. #include <linux/ethtool.h>
  34. #include <linux/mdio.h>
  35. #include <linux/mii.h>
  36. #include <linux/phy.h>
  37. #include <linux/brcmphy.h>
  38. #include <linux/if_vlan.h>
  39. #include <linux/ip.h>
  40. #include <linux/tcp.h>
  41. #include <linux/workqueue.h>
  42. #include <linux/prefetch.h>
  43. #include <linux/dma-mapping.h>
  44. #include <linux/firmware.h>
  45. #include <linux/ssb/ssb_driver_gige.h>
  46. #include <linux/hwmon.h>
  47. #include <linux/hwmon-sysfs.h>
  48. #include <net/checksum.h>
  49. #include <net/ip.h>
  50. #include <linux/io.h>
  51. #include <asm/byteorder.h>
  52. #include <linux/uaccess.h>
  53. #include <uapi/linux/net_tstamp.h>
  54. #include <linux/ptp_clock_kernel.h>
  55. #ifdef CONFIG_SPARC
  56. #include <asm/idprom.h>
  57. #include <asm/prom.h>
  58. #endif
  59. #define BAR_0 0
  60. #define BAR_2 2
  61. #include "tg3.h"
  62. /* Functions & macros to verify TG3_FLAGS types */
  63. static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
  64. {
  65. return test_bit(flag, bits);
  66. }
  67. static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
  68. {
  69. set_bit(flag, bits);
  70. }
  71. static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
  72. {
  73. clear_bit(flag, bits);
  74. }
  75. #define tg3_flag(tp, flag) \
  76. _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
  77. #define tg3_flag_set(tp, flag) \
  78. _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
  79. #define tg3_flag_clear(tp, flag) \
  80. _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
  81. #define DRV_MODULE_NAME "tg3"
  82. #define TG3_MAJ_NUM 3
  83. #define TG3_MIN_NUM 132
  84. #define DRV_MODULE_VERSION \
  85. __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  86. #define DRV_MODULE_RELDATE "May 21, 2013"
  87. #define RESET_KIND_SHUTDOWN 0
  88. #define RESET_KIND_INIT 1
  89. #define RESET_KIND_SUSPEND 2
  90. #define TG3_DEF_RX_MODE 0
  91. #define TG3_DEF_TX_MODE 0
  92. #define TG3_DEF_MSG_ENABLE \
  93. (NETIF_MSG_DRV | \
  94. NETIF_MSG_PROBE | \
  95. NETIF_MSG_LINK | \
  96. NETIF_MSG_TIMER | \
  97. NETIF_MSG_IFDOWN | \
  98. NETIF_MSG_IFUP | \
  99. NETIF_MSG_RX_ERR | \
  100. NETIF_MSG_TX_ERR)
  101. #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
  102. /* length of time before we decide the hardware is borked,
  103. * and dev->tx_timeout() should be called to fix the problem
  104. */
  105. #define TG3_TX_TIMEOUT (5 * HZ)
  106. /* hardware minimum and maximum for a single frame's data payload */
  107. #define TG3_MIN_MTU 60
  108. #define TG3_MAX_MTU(tp) \
  109. (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
  110. /* These numbers seem to be hard coded in the NIC firmware somehow.
  111. * You can't change the ring sizes, but you can change where you place
  112. * them in the NIC onboard memory.
  113. */
  114. #define TG3_RX_STD_RING_SIZE(tp) \
  115. (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
  116. TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
  117. #define TG3_DEF_RX_RING_PENDING 200
  118. #define TG3_RX_JMB_RING_SIZE(tp) \
  119. (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
  120. TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
  121. #define TG3_DEF_RX_JUMBO_RING_PENDING 100
  122. /* Do not place this n-ring entries value into the tp struct itself,
  123. * we really want to expose these constants to GCC so that modulo et
  124. * al. operations are done with shifts and masks instead of with
  125. * hw multiply/modulo instructions. Another solution would be to
  126. * replace things like '% foo' with '& (foo - 1)'.
  127. */
  128. #define TG3_TX_RING_SIZE 512
  129. #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
  130. #define TG3_RX_STD_RING_BYTES(tp) \
  131. (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
  132. #define TG3_RX_JMB_RING_BYTES(tp) \
  133. (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
  134. #define TG3_RX_RCB_RING_BYTES(tp) \
  135. (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
  136. #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
  137. TG3_TX_RING_SIZE)
  138. #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
  139. #define TG3_DMA_BYTE_ENAB 64
  140. #define TG3_RX_STD_DMA_SZ 1536
  141. #define TG3_RX_JMB_DMA_SZ 9046
  142. #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
  143. #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
  144. #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
  145. #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
  146. (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
  147. #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
  148. (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
  149. /* Due to a hardware bug, the 5701 can only DMA to memory addresses
  150. * that are at least dword aligned when used in PCIX mode. The driver
  151. * works around this bug by double copying the packet. This workaround
  152. * is built into the normal double copy length check for efficiency.
  153. *
  154. * However, the double copy is only necessary on those architectures
  155. * where unaligned memory accesses are inefficient. For those architectures
  156. * where unaligned memory accesses incur little penalty, we can reintegrate
  157. * the 5701 in the normal rx path. Doing so saves a device structure
  158. * dereference by hardcoding the double copy threshold in place.
  159. */
  160. #define TG3_RX_COPY_THRESHOLD 256
  161. #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
  162. #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
  163. #else
  164. #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
  165. #endif
  166. #if (NET_IP_ALIGN != 0)
  167. #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
  168. #else
  169. #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
  170. #endif
  171. /* minimum number of free TX descriptors required to wake up TX process */
  172. #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
  173. #define TG3_TX_BD_DMA_MAX_2K 2048
  174. #define TG3_TX_BD_DMA_MAX_4K 4096
  175. #define TG3_RAW_IP_ALIGN 2
  176. #define TG3_FW_UPDATE_TIMEOUT_SEC 5
  177. #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
  178. #define FIRMWARE_TG3 "tigon/tg3.bin"
  179. #define FIRMWARE_TG357766 "tigon/tg357766.bin"
  180. #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
  181. #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
  182. static char version[] =
  183. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
  184. MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
  185. MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
  186. MODULE_LICENSE("GPL");
  187. MODULE_VERSION(DRV_MODULE_VERSION);
  188. MODULE_FIRMWARE(FIRMWARE_TG3);
  189. MODULE_FIRMWARE(FIRMWARE_TG3TSO);
  190. MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
  191. static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
  192. module_param(tg3_debug, int, 0);
  193. MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
  194. #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
  195. #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
  196. static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
  197. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
  198. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
  199. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
  200. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
  201. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
  202. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
  203. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
  204. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
  205. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
  206. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
  207. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
  208. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
  209. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
  210. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
  211. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
  212. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
  213. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
  214. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
  215. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
  216. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
  217. TG3_DRV_DATA_FLAG_5705_10_100},
  218. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
  219. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
  220. TG3_DRV_DATA_FLAG_5705_10_100},
  221. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
  222. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
  223. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
  224. TG3_DRV_DATA_FLAG_5705_10_100},
  225. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  226. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  227. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
  228. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  229. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  230. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
  231. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  232. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
  233. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
  234. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
  235. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
  236. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
  237. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  238. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
  239. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
  240. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
  241. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
  242. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
  243. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
  244. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
  245. {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
  246. PCI_VENDOR_ID_LENOVO,
  247. TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
  248. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  249. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
  250. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
  251. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  252. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
  253. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
  254. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
  255. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
  256. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
  257. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
  258. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
  259. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
  260. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
  261. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
  262. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
  263. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
  264. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
  265. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
  266. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
  267. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
  268. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
  269. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
  270. {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
  271. PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
  272. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  273. {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
  274. PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
  275. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  276. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
  277. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
  278. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
  279. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  280. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
  281. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
  282. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
  283. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
  284. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
  285. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
  286. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
  287. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
  288. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
  289. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  290. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
  291. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  292. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
  293. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
  294. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
  295. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
  296. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
  297. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
  298. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
  299. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
  300. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
  301. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
  302. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
  303. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
  304. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
  305. {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
  306. {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
  307. {}
  308. };
  309. MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
  310. static const struct {
  311. const char string[ETH_GSTRING_LEN];
  312. } ethtool_stats_keys[] = {
  313. { "rx_octets" },
  314. { "rx_fragments" },
  315. { "rx_ucast_packets" },
  316. { "rx_mcast_packets" },
  317. { "rx_bcast_packets" },
  318. { "rx_fcs_errors" },
  319. { "rx_align_errors" },
  320. { "rx_xon_pause_rcvd" },
  321. { "rx_xoff_pause_rcvd" },
  322. { "rx_mac_ctrl_rcvd" },
  323. { "rx_xoff_entered" },
  324. { "rx_frame_too_long_errors" },
  325. { "rx_jabbers" },
  326. { "rx_undersize_packets" },
  327. { "rx_in_length_errors" },
  328. { "rx_out_length_errors" },
  329. { "rx_64_or_less_octet_packets" },
  330. { "rx_65_to_127_octet_packets" },
  331. { "rx_128_to_255_octet_packets" },
  332. { "rx_256_to_511_octet_packets" },
  333. { "rx_512_to_1023_octet_packets" },
  334. { "rx_1024_to_1522_octet_packets" },
  335. { "rx_1523_to_2047_octet_packets" },
  336. { "rx_2048_to_4095_octet_packets" },
  337. { "rx_4096_to_8191_octet_packets" },
  338. { "rx_8192_to_9022_octet_packets" },
  339. { "tx_octets" },
  340. { "tx_collisions" },
  341. { "tx_xon_sent" },
  342. { "tx_xoff_sent" },
  343. { "tx_flow_control" },
  344. { "tx_mac_errors" },
  345. { "tx_single_collisions" },
  346. { "tx_mult_collisions" },
  347. { "tx_deferred" },
  348. { "tx_excessive_collisions" },
  349. { "tx_late_collisions" },
  350. { "tx_collide_2times" },
  351. { "tx_collide_3times" },
  352. { "tx_collide_4times" },
  353. { "tx_collide_5times" },
  354. { "tx_collide_6times" },
  355. { "tx_collide_7times" },
  356. { "tx_collide_8times" },
  357. { "tx_collide_9times" },
  358. { "tx_collide_10times" },
  359. { "tx_collide_11times" },
  360. { "tx_collide_12times" },
  361. { "tx_collide_13times" },
  362. { "tx_collide_14times" },
  363. { "tx_collide_15times" },
  364. { "tx_ucast_packets" },
  365. { "tx_mcast_packets" },
  366. { "tx_bcast_packets" },
  367. { "tx_carrier_sense_errors" },
  368. { "tx_discards" },
  369. { "tx_errors" },
  370. { "dma_writeq_full" },
  371. { "dma_write_prioq_full" },
  372. { "rxbds_empty" },
  373. { "rx_discards" },
  374. { "rx_errors" },
  375. { "rx_threshold_hit" },
  376. { "dma_readq_full" },
  377. { "dma_read_prioq_full" },
  378. { "tx_comp_queue_full" },
  379. { "ring_set_send_prod_index" },
  380. { "ring_status_update" },
  381. { "nic_irqs" },
  382. { "nic_avoided_irqs" },
  383. { "nic_tx_threshold_hit" },
  384. { "mbuf_lwm_thresh_hit" },
  385. };
  386. #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
  387. #define TG3_NVRAM_TEST 0
  388. #define TG3_LINK_TEST 1
  389. #define TG3_REGISTER_TEST 2
  390. #define TG3_MEMORY_TEST 3
  391. #define TG3_MAC_LOOPB_TEST 4
  392. #define TG3_PHY_LOOPB_TEST 5
  393. #define TG3_EXT_LOOPB_TEST 6
  394. #define TG3_INTERRUPT_TEST 7
  395. static const struct {
  396. const char string[ETH_GSTRING_LEN];
  397. } ethtool_test_keys[] = {
  398. [TG3_NVRAM_TEST] = { "nvram test (online) " },
  399. [TG3_LINK_TEST] = { "link test (online) " },
  400. [TG3_REGISTER_TEST] = { "register test (offline)" },
  401. [TG3_MEMORY_TEST] = { "memory test (offline)" },
  402. [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
  403. [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
  404. [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
  405. [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
  406. };
  407. #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
  408. static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
  409. {
  410. writel(val, tp->regs + off);
  411. }
  412. static u32 tg3_read32(struct tg3 *tp, u32 off)
  413. {
  414. return readl(tp->regs + off);
  415. }
  416. static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
  417. {
  418. writel(val, tp->aperegs + off);
  419. }
  420. static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
  421. {
  422. return readl(tp->aperegs + off);
  423. }
  424. static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
  425. {
  426. unsigned long flags;
  427. spin_lock_irqsave(&tp->indirect_lock, flags);
  428. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  429. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  430. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  431. }
  432. static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
  433. {
  434. writel(val, tp->regs + off);
  435. readl(tp->regs + off);
  436. }
  437. static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
  438. {
  439. unsigned long flags;
  440. u32 val;
  441. spin_lock_irqsave(&tp->indirect_lock, flags);
  442. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  443. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  444. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  445. return val;
  446. }
  447. static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
  448. {
  449. unsigned long flags;
  450. if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
  451. pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
  452. TG3_64BIT_REG_LOW, val);
  453. return;
  454. }
  455. if (off == TG3_RX_STD_PROD_IDX_REG) {
  456. pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
  457. TG3_64BIT_REG_LOW, val);
  458. return;
  459. }
  460. spin_lock_irqsave(&tp->indirect_lock, flags);
  461. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  462. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  463. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  464. /* In indirect mode when disabling interrupts, we also need
  465. * to clear the interrupt bit in the GRC local ctrl register.
  466. */
  467. if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
  468. (val == 0x1)) {
  469. pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
  470. tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
  471. }
  472. }
  473. static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
  474. {
  475. unsigned long flags;
  476. u32 val;
  477. spin_lock_irqsave(&tp->indirect_lock, flags);
  478. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  479. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  480. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  481. return val;
  482. }
  483. /* usec_wait specifies the wait time in usec when writing to certain registers
  484. * where it is unsafe to read back the register without some delay.
  485. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
  486. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
  487. */
  488. static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
  489. {
  490. if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
  491. /* Non-posted methods */
  492. tp->write32(tp, off, val);
  493. else {
  494. /* Posted method */
  495. tg3_write32(tp, off, val);
  496. if (usec_wait)
  497. udelay(usec_wait);
  498. tp->read32(tp, off);
  499. }
  500. /* Wait again after the read for the posted method to guarantee that
  501. * the wait time is met.
  502. */
  503. if (usec_wait)
  504. udelay(usec_wait);
  505. }
  506. static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  507. {
  508. tp->write32_mbox(tp, off, val);
  509. if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
  510. (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
  511. !tg3_flag(tp, ICH_WORKAROUND)))
  512. tp->read32_mbox(tp, off);
  513. }
  514. static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
  515. {
  516. void __iomem *mbox = tp->regs + off;
  517. writel(val, mbox);
  518. if (tg3_flag(tp, TXD_MBOX_HWBUG))
  519. writel(val, mbox);
  520. if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
  521. tg3_flag(tp, FLUSH_POSTED_WRITES))
  522. readl(mbox);
  523. }
  524. static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
  525. {
  526. return readl(tp->regs + off + GRCMBOX_BASE);
  527. }
  528. static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
  529. {
  530. writel(val, tp->regs + off + GRCMBOX_BASE);
  531. }
  532. #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
  533. #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
  534. #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
  535. #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
  536. #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
  537. #define tw32(reg, val) tp->write32(tp, reg, val)
  538. #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
  539. #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
  540. #define tr32(reg) tp->read32(tp, reg)
  541. static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
  542. {
  543. unsigned long flags;
  544. if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
  545. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
  546. return;
  547. spin_lock_irqsave(&tp->indirect_lock, flags);
  548. if (tg3_flag(tp, SRAM_USE_CONFIG)) {
  549. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  550. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  551. /* Always leave this as zero. */
  552. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  553. } else {
  554. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  555. tw32_f(TG3PCI_MEM_WIN_DATA, val);
  556. /* Always leave this as zero. */
  557. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  558. }
  559. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  560. }
  561. static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
  562. {
  563. unsigned long flags;
  564. if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
  565. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
  566. *val = 0;
  567. return;
  568. }
  569. spin_lock_irqsave(&tp->indirect_lock, flags);
  570. if (tg3_flag(tp, SRAM_USE_CONFIG)) {
  571. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  572. pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  573. /* Always leave this as zero. */
  574. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  575. } else {
  576. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  577. *val = tr32(TG3PCI_MEM_WIN_DATA);
  578. /* Always leave this as zero. */
  579. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  580. }
  581. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  582. }
  583. static void tg3_ape_lock_init(struct tg3 *tp)
  584. {
  585. int i;
  586. u32 regbase, bit;
  587. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  588. regbase = TG3_APE_LOCK_GRANT;
  589. else
  590. regbase = TG3_APE_PER_LOCK_GRANT;
  591. /* Make sure the driver hasn't any stale locks. */
  592. for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
  593. switch (i) {
  594. case TG3_APE_LOCK_PHY0:
  595. case TG3_APE_LOCK_PHY1:
  596. case TG3_APE_LOCK_PHY2:
  597. case TG3_APE_LOCK_PHY3:
  598. bit = APE_LOCK_GRANT_DRIVER;
  599. break;
  600. default:
  601. if (!tp->pci_fn)
  602. bit = APE_LOCK_GRANT_DRIVER;
  603. else
  604. bit = 1 << tp->pci_fn;
  605. }
  606. tg3_ape_write32(tp, regbase + 4 * i, bit);
  607. }
  608. }
  609. static int tg3_ape_lock(struct tg3 *tp, int locknum)
  610. {
  611. int i, off;
  612. int ret = 0;
  613. u32 status, req, gnt, bit;
  614. if (!tg3_flag(tp, ENABLE_APE))
  615. return 0;
  616. switch (locknum) {
  617. case TG3_APE_LOCK_GPIO:
  618. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  619. return 0;
  620. case TG3_APE_LOCK_GRC:
  621. case TG3_APE_LOCK_MEM:
  622. if (!tp->pci_fn)
  623. bit = APE_LOCK_REQ_DRIVER;
  624. else
  625. bit = 1 << tp->pci_fn;
  626. break;
  627. case TG3_APE_LOCK_PHY0:
  628. case TG3_APE_LOCK_PHY1:
  629. case TG3_APE_LOCK_PHY2:
  630. case TG3_APE_LOCK_PHY3:
  631. bit = APE_LOCK_REQ_DRIVER;
  632. break;
  633. default:
  634. return -EINVAL;
  635. }
  636. if (tg3_asic_rev(tp) == ASIC_REV_5761) {
  637. req = TG3_APE_LOCK_REQ;
  638. gnt = TG3_APE_LOCK_GRANT;
  639. } else {
  640. req = TG3_APE_PER_LOCK_REQ;
  641. gnt = TG3_APE_PER_LOCK_GRANT;
  642. }
  643. off = 4 * locknum;
  644. tg3_ape_write32(tp, req + off, bit);
  645. /* Wait for up to 1 millisecond to acquire lock. */
  646. for (i = 0; i < 100; i++) {
  647. status = tg3_ape_read32(tp, gnt + off);
  648. if (status == bit)
  649. break;
  650. udelay(10);
  651. }
  652. if (status != bit) {
  653. /* Revoke the lock request. */
  654. tg3_ape_write32(tp, gnt + off, bit);
  655. ret = -EBUSY;
  656. }
  657. return ret;
  658. }
  659. static void tg3_ape_unlock(struct tg3 *tp, int locknum)
  660. {
  661. u32 gnt, bit;
  662. if (!tg3_flag(tp, ENABLE_APE))
  663. return;
  664. switch (locknum) {
  665. case TG3_APE_LOCK_GPIO:
  666. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  667. return;
  668. case TG3_APE_LOCK_GRC:
  669. case TG3_APE_LOCK_MEM:
  670. if (!tp->pci_fn)
  671. bit = APE_LOCK_GRANT_DRIVER;
  672. else
  673. bit = 1 << tp->pci_fn;
  674. break;
  675. case TG3_APE_LOCK_PHY0:
  676. case TG3_APE_LOCK_PHY1:
  677. case TG3_APE_LOCK_PHY2:
  678. case TG3_APE_LOCK_PHY3:
  679. bit = APE_LOCK_GRANT_DRIVER;
  680. break;
  681. default:
  682. return;
  683. }
  684. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  685. gnt = TG3_APE_LOCK_GRANT;
  686. else
  687. gnt = TG3_APE_PER_LOCK_GRANT;
  688. tg3_ape_write32(tp, gnt + 4 * locknum, bit);
  689. }
  690. static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
  691. {
  692. u32 apedata;
  693. while (timeout_us) {
  694. if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
  695. return -EBUSY;
  696. apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
  697. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  698. break;
  699. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  700. udelay(10);
  701. timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
  702. }
  703. return timeout_us ? 0 : -EBUSY;
  704. }
  705. static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
  706. {
  707. u32 i, apedata;
  708. for (i = 0; i < timeout_us / 10; i++) {
  709. apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
  710. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  711. break;
  712. udelay(10);
  713. }
  714. return i == timeout_us / 10;
  715. }
  716. static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
  717. u32 len)
  718. {
  719. int err;
  720. u32 i, bufoff, msgoff, maxlen, apedata;
  721. if (!tg3_flag(tp, APE_HAS_NCSI))
  722. return 0;
  723. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  724. if (apedata != APE_SEG_SIG_MAGIC)
  725. return -ENODEV;
  726. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  727. if (!(apedata & APE_FW_STATUS_READY))
  728. return -EAGAIN;
  729. bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
  730. TG3_APE_SHMEM_BASE;
  731. msgoff = bufoff + 2 * sizeof(u32);
  732. maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
  733. while (len) {
  734. u32 length;
  735. /* Cap xfer sizes to scratchpad limits. */
  736. length = (len > maxlen) ? maxlen : len;
  737. len -= length;
  738. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  739. if (!(apedata & APE_FW_STATUS_READY))
  740. return -EAGAIN;
  741. /* Wait for up to 1 msec for APE to service previous event. */
  742. err = tg3_ape_event_lock(tp, 1000);
  743. if (err)
  744. return err;
  745. apedata = APE_EVENT_STATUS_DRIVER_EVNT |
  746. APE_EVENT_STATUS_SCRTCHPD_READ |
  747. APE_EVENT_STATUS_EVENT_PENDING;
  748. tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
  749. tg3_ape_write32(tp, bufoff, base_off);
  750. tg3_ape_write32(tp, bufoff + sizeof(u32), length);
  751. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  752. tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
  753. base_off += length;
  754. if (tg3_ape_wait_for_event(tp, 30000))
  755. return -EAGAIN;
  756. for (i = 0; length; i += 4, length -= 4) {
  757. u32 val = tg3_ape_read32(tp, msgoff + i);
  758. memcpy(data, &val, sizeof(u32));
  759. data++;
  760. }
  761. }
  762. return 0;
  763. }
  764. static int tg3_ape_send_event(struct tg3 *tp, u32 event)
  765. {
  766. int err;
  767. u32 apedata;
  768. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  769. if (apedata != APE_SEG_SIG_MAGIC)
  770. return -EAGAIN;
  771. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  772. if (!(apedata & APE_FW_STATUS_READY))
  773. return -EAGAIN;
  774. /* Wait for up to 1 millisecond for APE to service previous event. */
  775. err = tg3_ape_event_lock(tp, 1000);
  776. if (err)
  777. return err;
  778. tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
  779. event | APE_EVENT_STATUS_EVENT_PENDING);
  780. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  781. tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
  782. return 0;
  783. }
  784. static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
  785. {
  786. u32 event;
  787. u32 apedata;
  788. if (!tg3_flag(tp, ENABLE_APE))
  789. return;
  790. switch (kind) {
  791. case RESET_KIND_INIT:
  792. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
  793. APE_HOST_SEG_SIG_MAGIC);
  794. tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
  795. APE_HOST_SEG_LEN_MAGIC);
  796. apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
  797. tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
  798. tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
  799. APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
  800. tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
  801. APE_HOST_BEHAV_NO_PHYLOCK);
  802. tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
  803. TG3_APE_HOST_DRVR_STATE_START);
  804. event = APE_EVENT_STATUS_STATE_START;
  805. break;
  806. case RESET_KIND_SHUTDOWN:
  807. /* With the interface we are currently using,
  808. * APE does not track driver state. Wiping
  809. * out the HOST SEGMENT SIGNATURE forces
  810. * the APE to assume OS absent status.
  811. */
  812. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
  813. if (device_may_wakeup(&tp->pdev->dev) &&
  814. tg3_flag(tp, WOL_ENABLE)) {
  815. tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
  816. TG3_APE_HOST_WOL_SPEED_AUTO);
  817. apedata = TG3_APE_HOST_DRVR_STATE_WOL;
  818. } else
  819. apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
  820. tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
  821. event = APE_EVENT_STATUS_STATE_UNLOAD;
  822. break;
  823. default:
  824. return;
  825. }
  826. event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
  827. tg3_ape_send_event(tp, event);
  828. }
  829. static void tg3_disable_ints(struct tg3 *tp)
  830. {
  831. int i;
  832. tw32(TG3PCI_MISC_HOST_CTRL,
  833. (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
  834. for (i = 0; i < tp->irq_max; i++)
  835. tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
  836. }
  837. static void tg3_enable_ints(struct tg3 *tp)
  838. {
  839. int i;
  840. tp->irq_sync = 0;
  841. wmb();
  842. tw32(TG3PCI_MISC_HOST_CTRL,
  843. (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
  844. tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
  845. for (i = 0; i < tp->irq_cnt; i++) {
  846. struct tg3_napi *tnapi = &tp->napi[i];
  847. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  848. if (tg3_flag(tp, 1SHOT_MSI))
  849. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  850. tp->coal_now |= tnapi->coal_now;
  851. }
  852. /* Force an initial interrupt */
  853. if (!tg3_flag(tp, TAGGED_STATUS) &&
  854. (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
  855. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  856. else
  857. tw32(HOSTCC_MODE, tp->coal_now);
  858. tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
  859. }
  860. static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
  861. {
  862. struct tg3 *tp = tnapi->tp;
  863. struct tg3_hw_status *sblk = tnapi->hw_status;
  864. unsigned int work_exists = 0;
  865. /* check for phy events */
  866. if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
  867. if (sblk->status & SD_STATUS_LINK_CHG)
  868. work_exists = 1;
  869. }
  870. /* check for TX work to do */
  871. if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
  872. work_exists = 1;
  873. /* check for RX work to do */
  874. if (tnapi->rx_rcb_prod_idx &&
  875. *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
  876. work_exists = 1;
  877. return work_exists;
  878. }
  879. /* tg3_int_reenable
  880. * similar to tg3_enable_ints, but it accurately determines whether there
  881. * is new work pending and can return without flushing the PIO write
  882. * which reenables interrupts
  883. */
  884. static void tg3_int_reenable(struct tg3_napi *tnapi)
  885. {
  886. struct tg3 *tp = tnapi->tp;
  887. tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
  888. mmiowb();
  889. /* When doing tagged status, this work check is unnecessary.
  890. * The last_tag we write above tells the chip which piece of
  891. * work we've completed.
  892. */
  893. if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
  894. tw32(HOSTCC_MODE, tp->coalesce_mode |
  895. HOSTCC_MODE_ENABLE | tnapi->coal_now);
  896. }
  897. static void tg3_switch_clocks(struct tg3 *tp)
  898. {
  899. u32 clock_ctrl;
  900. u32 orig_clock_ctrl;
  901. if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
  902. return;
  903. clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
  904. orig_clock_ctrl = clock_ctrl;
  905. clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
  906. CLOCK_CTRL_CLKRUN_OENABLE |
  907. 0x1f);
  908. tp->pci_clock_ctrl = clock_ctrl;
  909. if (tg3_flag(tp, 5705_PLUS)) {
  910. if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
  911. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  912. clock_ctrl | CLOCK_CTRL_625_CORE, 40);
  913. }
  914. } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
  915. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  916. clock_ctrl |
  917. (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
  918. 40);
  919. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  920. clock_ctrl | (CLOCK_CTRL_ALTCLK),
  921. 40);
  922. }
  923. tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
  924. }
  925. #define PHY_BUSY_LOOPS 5000
  926. static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
  927. u32 *val)
  928. {
  929. u32 frame_val;
  930. unsigned int loops;
  931. int ret;
  932. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  933. tw32_f(MAC_MI_MODE,
  934. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  935. udelay(80);
  936. }
  937. tg3_ape_lock(tp, tp->phy_ape_lock);
  938. *val = 0x0;
  939. frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  940. MI_COM_PHY_ADDR_MASK);
  941. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  942. MI_COM_REG_ADDR_MASK);
  943. frame_val |= (MI_COM_CMD_READ | MI_COM_START);
  944. tw32_f(MAC_MI_COM, frame_val);
  945. loops = PHY_BUSY_LOOPS;
  946. while (loops != 0) {
  947. udelay(10);
  948. frame_val = tr32(MAC_MI_COM);
  949. if ((frame_val & MI_COM_BUSY) == 0) {
  950. udelay(5);
  951. frame_val = tr32(MAC_MI_COM);
  952. break;
  953. }
  954. loops -= 1;
  955. }
  956. ret = -EBUSY;
  957. if (loops != 0) {
  958. *val = frame_val & MI_COM_DATA_MASK;
  959. ret = 0;
  960. }
  961. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  962. tw32_f(MAC_MI_MODE, tp->mi_mode);
  963. udelay(80);
  964. }
  965. tg3_ape_unlock(tp, tp->phy_ape_lock);
  966. return ret;
  967. }
  968. static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  969. {
  970. return __tg3_readphy(tp, tp->phy_addr, reg, val);
  971. }
  972. static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
  973. u32 val)
  974. {
  975. u32 frame_val;
  976. unsigned int loops;
  977. int ret;
  978. if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  979. (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
  980. return 0;
  981. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  982. tw32_f(MAC_MI_MODE,
  983. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  984. udelay(80);
  985. }
  986. tg3_ape_lock(tp, tp->phy_ape_lock);
  987. frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  988. MI_COM_PHY_ADDR_MASK);
  989. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  990. MI_COM_REG_ADDR_MASK);
  991. frame_val |= (val & MI_COM_DATA_MASK);
  992. frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
  993. tw32_f(MAC_MI_COM, frame_val);
  994. loops = PHY_BUSY_LOOPS;
  995. while (loops != 0) {
  996. udelay(10);
  997. frame_val = tr32(MAC_MI_COM);
  998. if ((frame_val & MI_COM_BUSY) == 0) {
  999. udelay(5);
  1000. frame_val = tr32(MAC_MI_COM);
  1001. break;
  1002. }
  1003. loops -= 1;
  1004. }
  1005. ret = -EBUSY;
  1006. if (loops != 0)
  1007. ret = 0;
  1008. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  1009. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1010. udelay(80);
  1011. }
  1012. tg3_ape_unlock(tp, tp->phy_ape_lock);
  1013. return ret;
  1014. }
  1015. static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  1016. {
  1017. return __tg3_writephy(tp, tp->phy_addr, reg, val);
  1018. }
  1019. static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
  1020. {
  1021. int err;
  1022. err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
  1023. if (err)
  1024. goto done;
  1025. err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
  1026. if (err)
  1027. goto done;
  1028. err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
  1029. MII_TG3_MMD_CTRL_DATA_NOINC | devad);
  1030. if (err)
  1031. goto done;
  1032. err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
  1033. done:
  1034. return err;
  1035. }
  1036. static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
  1037. {
  1038. int err;
  1039. err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
  1040. if (err)
  1041. goto done;
  1042. err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
  1043. if (err)
  1044. goto done;
  1045. err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
  1046. MII_TG3_MMD_CTRL_DATA_NOINC | devad);
  1047. if (err)
  1048. goto done;
  1049. err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
  1050. done:
  1051. return err;
  1052. }
  1053. static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
  1054. {
  1055. int err;
  1056. err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
  1057. if (!err)
  1058. err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
  1059. return err;
  1060. }
  1061. static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
  1062. {
  1063. int err;
  1064. err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
  1065. if (!err)
  1066. err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
  1067. return err;
  1068. }
  1069. static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
  1070. {
  1071. int err;
  1072. err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
  1073. (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
  1074. MII_TG3_AUXCTL_SHDWSEL_MISC);
  1075. if (!err)
  1076. err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
  1077. return err;
  1078. }
  1079. static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
  1080. {
  1081. if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
  1082. set |= MII_TG3_AUXCTL_MISC_WREN;
  1083. return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
  1084. }
  1085. static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
  1086. {
  1087. u32 val;
  1088. int err;
  1089. err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
  1090. if (err)
  1091. return err;
  1092. if (enable)
  1093. val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
  1094. else
  1095. val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
  1096. err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
  1097. val | MII_TG3_AUXCTL_ACTL_TX_6DB);
  1098. return err;
  1099. }
  1100. static int tg3_bmcr_reset(struct tg3 *tp)
  1101. {
  1102. u32 phy_control;
  1103. int limit, err;
  1104. /* OK, reset it, and poll the BMCR_RESET bit until it
  1105. * clears or we time out.
  1106. */
  1107. phy_control = BMCR_RESET;
  1108. err = tg3_writephy(tp, MII_BMCR, phy_control);
  1109. if (err != 0)
  1110. return -EBUSY;
  1111. limit = 5000;
  1112. while (limit--) {
  1113. err = tg3_readphy(tp, MII_BMCR, &phy_control);
  1114. if (err != 0)
  1115. return -EBUSY;
  1116. if ((phy_control & BMCR_RESET) == 0) {
  1117. udelay(40);
  1118. break;
  1119. }
  1120. udelay(10);
  1121. }
  1122. if (limit < 0)
  1123. return -EBUSY;
  1124. return 0;
  1125. }
  1126. static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
  1127. {
  1128. struct tg3 *tp = bp->priv;
  1129. u32 val;
  1130. spin_lock_bh(&tp->lock);
  1131. if (tg3_readphy(tp, reg, &val))
  1132. val = -EIO;
  1133. spin_unlock_bh(&tp->lock);
  1134. return val;
  1135. }
  1136. static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
  1137. {
  1138. struct tg3 *tp = bp->priv;
  1139. u32 ret = 0;
  1140. spin_lock_bh(&tp->lock);
  1141. if (tg3_writephy(tp, reg, val))
  1142. ret = -EIO;
  1143. spin_unlock_bh(&tp->lock);
  1144. return ret;
  1145. }
  1146. static int tg3_mdio_reset(struct mii_bus *bp)
  1147. {
  1148. return 0;
  1149. }
  1150. static void tg3_mdio_config_5785(struct tg3 *tp)
  1151. {
  1152. u32 val;
  1153. struct phy_device *phydev;
  1154. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1155. switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
  1156. case PHY_ID_BCM50610:
  1157. case PHY_ID_BCM50610M:
  1158. val = MAC_PHYCFG2_50610_LED_MODES;
  1159. break;
  1160. case PHY_ID_BCMAC131:
  1161. val = MAC_PHYCFG2_AC131_LED_MODES;
  1162. break;
  1163. case PHY_ID_RTL8211C:
  1164. val = MAC_PHYCFG2_RTL8211C_LED_MODES;
  1165. break;
  1166. case PHY_ID_RTL8201E:
  1167. val = MAC_PHYCFG2_RTL8201E_LED_MODES;
  1168. break;
  1169. default:
  1170. return;
  1171. }
  1172. if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
  1173. tw32(MAC_PHYCFG2, val);
  1174. val = tr32(MAC_PHYCFG1);
  1175. val &= ~(MAC_PHYCFG1_RGMII_INT |
  1176. MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
  1177. val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
  1178. tw32(MAC_PHYCFG1, val);
  1179. return;
  1180. }
  1181. if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
  1182. val |= MAC_PHYCFG2_EMODE_MASK_MASK |
  1183. MAC_PHYCFG2_FMODE_MASK_MASK |
  1184. MAC_PHYCFG2_GMODE_MASK_MASK |
  1185. MAC_PHYCFG2_ACT_MASK_MASK |
  1186. MAC_PHYCFG2_QUAL_MASK_MASK |
  1187. MAC_PHYCFG2_INBAND_ENABLE;
  1188. tw32(MAC_PHYCFG2, val);
  1189. val = tr32(MAC_PHYCFG1);
  1190. val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
  1191. MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
  1192. if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
  1193. if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
  1194. val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
  1195. if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
  1196. val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
  1197. }
  1198. val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
  1199. MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
  1200. tw32(MAC_PHYCFG1, val);
  1201. val = tr32(MAC_EXT_RGMII_MODE);
  1202. val &= ~(MAC_RGMII_MODE_RX_INT_B |
  1203. MAC_RGMII_MODE_RX_QUALITY |
  1204. MAC_RGMII_MODE_RX_ACTIVITY |
  1205. MAC_RGMII_MODE_RX_ENG_DET |
  1206. MAC_RGMII_MODE_TX_ENABLE |
  1207. MAC_RGMII_MODE_TX_LOWPWR |
  1208. MAC_RGMII_MODE_TX_RESET);
  1209. if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
  1210. if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
  1211. val |= MAC_RGMII_MODE_RX_INT_B |
  1212. MAC_RGMII_MODE_RX_QUALITY |
  1213. MAC_RGMII_MODE_RX_ACTIVITY |
  1214. MAC_RGMII_MODE_RX_ENG_DET;
  1215. if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
  1216. val |= MAC_RGMII_MODE_TX_ENABLE |
  1217. MAC_RGMII_MODE_TX_LOWPWR |
  1218. MAC_RGMII_MODE_TX_RESET;
  1219. }
  1220. tw32(MAC_EXT_RGMII_MODE, val);
  1221. }
  1222. static void tg3_mdio_start(struct tg3 *tp)
  1223. {
  1224. tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
  1225. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1226. udelay(80);
  1227. if (tg3_flag(tp, MDIOBUS_INITED) &&
  1228. tg3_asic_rev(tp) == ASIC_REV_5785)
  1229. tg3_mdio_config_5785(tp);
  1230. }
  1231. static int tg3_mdio_init(struct tg3 *tp)
  1232. {
  1233. int i;
  1234. u32 reg;
  1235. struct phy_device *phydev;
  1236. if (tg3_flag(tp, 5717_PLUS)) {
  1237. u32 is_serdes;
  1238. tp->phy_addr = tp->pci_fn + 1;
  1239. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
  1240. is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
  1241. else
  1242. is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
  1243. TG3_CPMU_PHY_STRAP_IS_SERDES;
  1244. if (is_serdes)
  1245. tp->phy_addr += 7;
  1246. } else
  1247. tp->phy_addr = TG3_PHY_MII_ADDR;
  1248. tg3_mdio_start(tp);
  1249. if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
  1250. return 0;
  1251. tp->mdio_bus = mdiobus_alloc();
  1252. if (tp->mdio_bus == NULL)
  1253. return -ENOMEM;
  1254. tp->mdio_bus->name = "tg3 mdio bus";
  1255. snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
  1256. (tp->pdev->bus->number << 8) | tp->pdev->devfn);
  1257. tp->mdio_bus->priv = tp;
  1258. tp->mdio_bus->parent = &tp->pdev->dev;
  1259. tp->mdio_bus->read = &tg3_mdio_read;
  1260. tp->mdio_bus->write = &tg3_mdio_write;
  1261. tp->mdio_bus->reset = &tg3_mdio_reset;
  1262. tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
  1263. tp->mdio_bus->irq = &tp->mdio_irq[0];
  1264. for (i = 0; i < PHY_MAX_ADDR; i++)
  1265. tp->mdio_bus->irq[i] = PHY_POLL;
  1266. /* The bus registration will look for all the PHYs on the mdio bus.
  1267. * Unfortunately, it does not ensure the PHY is powered up before
  1268. * accessing the PHY ID registers. A chip reset is the
  1269. * quickest way to bring the device back to an operational state..
  1270. */
  1271. if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
  1272. tg3_bmcr_reset(tp);
  1273. i = mdiobus_register(tp->mdio_bus);
  1274. if (i) {
  1275. dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
  1276. mdiobus_free(tp->mdio_bus);
  1277. return i;
  1278. }
  1279. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1280. if (!phydev || !phydev->drv) {
  1281. dev_warn(&tp->pdev->dev, "No PHY devices\n");
  1282. mdiobus_unregister(tp->mdio_bus);
  1283. mdiobus_free(tp->mdio_bus);
  1284. return -ENODEV;
  1285. }
  1286. switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
  1287. case PHY_ID_BCM57780:
  1288. phydev->interface = PHY_INTERFACE_MODE_GMII;
  1289. phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
  1290. break;
  1291. case PHY_ID_BCM50610:
  1292. case PHY_ID_BCM50610M:
  1293. phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
  1294. PHY_BRCM_RX_REFCLK_UNUSED |
  1295. PHY_BRCM_DIS_TXCRXC_NOENRGY |
  1296. PHY_BRCM_AUTO_PWRDWN_ENABLE;
  1297. if (tg3_flag(tp, RGMII_INBAND_DISABLE))
  1298. phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
  1299. if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
  1300. phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
  1301. if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
  1302. phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
  1303. /* fallthru */
  1304. case PHY_ID_RTL8211C:
  1305. phydev->interface = PHY_INTERFACE_MODE_RGMII;
  1306. break;
  1307. case PHY_ID_RTL8201E:
  1308. case PHY_ID_BCMAC131:
  1309. phydev->interface = PHY_INTERFACE_MODE_MII;
  1310. phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
  1311. tp->phy_flags |= TG3_PHYFLG_IS_FET;
  1312. break;
  1313. }
  1314. tg3_flag_set(tp, MDIOBUS_INITED);
  1315. if (tg3_asic_rev(tp) == ASIC_REV_5785)
  1316. tg3_mdio_config_5785(tp);
  1317. return 0;
  1318. }
  1319. static void tg3_mdio_fini(struct tg3 *tp)
  1320. {
  1321. if (tg3_flag(tp, MDIOBUS_INITED)) {
  1322. tg3_flag_clear(tp, MDIOBUS_INITED);
  1323. mdiobus_unregister(tp->mdio_bus);
  1324. mdiobus_free(tp->mdio_bus);
  1325. }
  1326. }
  1327. /* tp->lock is held. */
  1328. static inline void tg3_generate_fw_event(struct tg3 *tp)
  1329. {
  1330. u32 val;
  1331. val = tr32(GRC_RX_CPU_EVENT);
  1332. val |= GRC_RX_CPU_DRIVER_EVENT;
  1333. tw32_f(GRC_RX_CPU_EVENT, val);
  1334. tp->last_event_jiffies = jiffies;
  1335. }
  1336. #define TG3_FW_EVENT_TIMEOUT_USEC 2500
  1337. /* tp->lock is held. */
  1338. static void tg3_wait_for_event_ack(struct tg3 *tp)
  1339. {
  1340. int i;
  1341. unsigned int delay_cnt;
  1342. long time_remain;
  1343. /* If enough time has passed, no wait is necessary. */
  1344. time_remain = (long)(tp->last_event_jiffies + 1 +
  1345. usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
  1346. (long)jiffies;
  1347. if (time_remain < 0)
  1348. return;
  1349. /* Check if we can shorten the wait time. */
  1350. delay_cnt = jiffies_to_usecs(time_remain);
  1351. if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
  1352. delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
  1353. delay_cnt = (delay_cnt >> 3) + 1;
  1354. for (i = 0; i < delay_cnt; i++) {
  1355. if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
  1356. break;
  1357. udelay(8);
  1358. }
  1359. }
  1360. /* tp->lock is held. */
  1361. static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
  1362. {
  1363. u32 reg, val;
  1364. val = 0;
  1365. if (!tg3_readphy(tp, MII_BMCR, &reg))
  1366. val = reg << 16;
  1367. if (!tg3_readphy(tp, MII_BMSR, &reg))
  1368. val |= (reg & 0xffff);
  1369. *data++ = val;
  1370. val = 0;
  1371. if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
  1372. val = reg << 16;
  1373. if (!tg3_readphy(tp, MII_LPA, &reg))
  1374. val |= (reg & 0xffff);
  1375. *data++ = val;
  1376. val = 0;
  1377. if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
  1378. if (!tg3_readphy(tp, MII_CTRL1000, &reg))
  1379. val = reg << 16;
  1380. if (!tg3_readphy(tp, MII_STAT1000, &reg))
  1381. val |= (reg & 0xffff);
  1382. }
  1383. *data++ = val;
  1384. if (!tg3_readphy(tp, MII_PHYADDR, &reg))
  1385. val = reg << 16;
  1386. else
  1387. val = 0;
  1388. *data++ = val;
  1389. }
  1390. /* tp->lock is held. */
  1391. static void tg3_ump_link_report(struct tg3 *tp)
  1392. {
  1393. u32 data[4];
  1394. if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
  1395. return;
  1396. tg3_phy_gather_ump_data(tp, data);
  1397. tg3_wait_for_event_ack(tp);
  1398. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
  1399. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
  1400. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
  1401. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
  1402. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
  1403. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
  1404. tg3_generate_fw_event(tp);
  1405. }
  1406. /* tp->lock is held. */
  1407. static void tg3_stop_fw(struct tg3 *tp)
  1408. {
  1409. if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
  1410. /* Wait for RX cpu to ACK the previous event. */
  1411. tg3_wait_for_event_ack(tp);
  1412. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
  1413. tg3_generate_fw_event(tp);
  1414. /* Wait for RX cpu to ACK this event. */
  1415. tg3_wait_for_event_ack(tp);
  1416. }
  1417. }
  1418. /* tp->lock is held. */
  1419. static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
  1420. {
  1421. tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
  1422. NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  1423. if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
  1424. switch (kind) {
  1425. case RESET_KIND_INIT:
  1426. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1427. DRV_STATE_START);
  1428. break;
  1429. case RESET_KIND_SHUTDOWN:
  1430. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1431. DRV_STATE_UNLOAD);
  1432. break;
  1433. case RESET_KIND_SUSPEND:
  1434. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1435. DRV_STATE_SUSPEND);
  1436. break;
  1437. default:
  1438. break;
  1439. }
  1440. }
  1441. }
  1442. /* tp->lock is held. */
  1443. static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
  1444. {
  1445. if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
  1446. switch (kind) {
  1447. case RESET_KIND_INIT:
  1448. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1449. DRV_STATE_START_DONE);
  1450. break;
  1451. case RESET_KIND_SHUTDOWN:
  1452. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1453. DRV_STATE_UNLOAD_DONE);
  1454. break;
  1455. default:
  1456. break;
  1457. }
  1458. }
  1459. }
  1460. /* tp->lock is held. */
  1461. static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
  1462. {
  1463. if (tg3_flag(tp, ENABLE_ASF)) {
  1464. switch (kind) {
  1465. case RESET_KIND_INIT:
  1466. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1467. DRV_STATE_START);
  1468. break;
  1469. case RESET_KIND_SHUTDOWN:
  1470. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1471. DRV_STATE_UNLOAD);
  1472. break;
  1473. case RESET_KIND_SUSPEND:
  1474. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1475. DRV_STATE_SUSPEND);
  1476. break;
  1477. default:
  1478. break;
  1479. }
  1480. }
  1481. }
  1482. static int tg3_poll_fw(struct tg3 *tp)
  1483. {
  1484. int i;
  1485. u32 val;
  1486. if (tg3_flag(tp, NO_FWARE_REPORTED))
  1487. return 0;
  1488. if (tg3_flag(tp, IS_SSB_CORE)) {
  1489. /* We don't use firmware. */
  1490. return 0;
  1491. }
  1492. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  1493. /* Wait up to 20ms for init done. */
  1494. for (i = 0; i < 200; i++) {
  1495. if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
  1496. return 0;
  1497. udelay(100);
  1498. }
  1499. return -ENODEV;
  1500. }
  1501. /* Wait for firmware initialization to complete. */
  1502. for (i = 0; i < 100000; i++) {
  1503. tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  1504. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  1505. break;
  1506. udelay(10);
  1507. }
  1508. /* Chip might not be fitted with firmware. Some Sun onboard
  1509. * parts are configured like that. So don't signal the timeout
  1510. * of the above loop as an error, but do report the lack of
  1511. * running firmware once.
  1512. */
  1513. if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
  1514. tg3_flag_set(tp, NO_FWARE_REPORTED);
  1515. netdev_info(tp->dev, "No firmware running\n");
  1516. }
  1517. if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
  1518. /* The 57765 A0 needs a little more
  1519. * time to do some important work.
  1520. */
  1521. mdelay(10);
  1522. }
  1523. return 0;
  1524. }
  1525. static void tg3_link_report(struct tg3 *tp)
  1526. {
  1527. if (!netif_carrier_ok(tp->dev)) {
  1528. netif_info(tp, link, tp->dev, "Link is down\n");
  1529. tg3_ump_link_report(tp);
  1530. } else if (netif_msg_link(tp)) {
  1531. netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
  1532. (tp->link_config.active_speed == SPEED_1000 ?
  1533. 1000 :
  1534. (tp->link_config.active_speed == SPEED_100 ?
  1535. 100 : 10)),
  1536. (tp->link_config.active_duplex == DUPLEX_FULL ?
  1537. "full" : "half"));
  1538. netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
  1539. (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
  1540. "on" : "off",
  1541. (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
  1542. "on" : "off");
  1543. if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
  1544. netdev_info(tp->dev, "EEE is %s\n",
  1545. tp->setlpicnt ? "enabled" : "disabled");
  1546. tg3_ump_link_report(tp);
  1547. }
  1548. tp->link_up = netif_carrier_ok(tp->dev);
  1549. }
  1550. static u32 tg3_decode_flowctrl_1000T(u32 adv)
  1551. {
  1552. u32 flowctrl = 0;
  1553. if (adv & ADVERTISE_PAUSE_CAP) {
  1554. flowctrl |= FLOW_CTRL_RX;
  1555. if (!(adv & ADVERTISE_PAUSE_ASYM))
  1556. flowctrl |= FLOW_CTRL_TX;
  1557. } else if (adv & ADVERTISE_PAUSE_ASYM)
  1558. flowctrl |= FLOW_CTRL_TX;
  1559. return flowctrl;
  1560. }
  1561. static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
  1562. {
  1563. u16 miireg;
  1564. if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
  1565. miireg = ADVERTISE_1000XPAUSE;
  1566. else if (flow_ctrl & FLOW_CTRL_TX)
  1567. miireg = ADVERTISE_1000XPSE_ASYM;
  1568. else if (flow_ctrl & FLOW_CTRL_RX)
  1569. miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  1570. else
  1571. miireg = 0;
  1572. return miireg;
  1573. }
  1574. static u32 tg3_decode_flowctrl_1000X(u32 adv)
  1575. {
  1576. u32 flowctrl = 0;
  1577. if (adv & ADVERTISE_1000XPAUSE) {
  1578. flowctrl |= FLOW_CTRL_RX;
  1579. if (!(adv & ADVERTISE_1000XPSE_ASYM))
  1580. flowctrl |= FLOW_CTRL_TX;
  1581. } else if (adv & ADVERTISE_1000XPSE_ASYM)
  1582. flowctrl |= FLOW_CTRL_TX;
  1583. return flowctrl;
  1584. }
  1585. static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
  1586. {
  1587. u8 cap = 0;
  1588. if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
  1589. cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
  1590. } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
  1591. if (lcladv & ADVERTISE_1000XPAUSE)
  1592. cap = FLOW_CTRL_RX;
  1593. if (rmtadv & ADVERTISE_1000XPAUSE)
  1594. cap = FLOW_CTRL_TX;
  1595. }
  1596. return cap;
  1597. }
  1598. static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
  1599. {
  1600. u8 autoneg;
  1601. u8 flowctrl = 0;
  1602. u32 old_rx_mode = tp->rx_mode;
  1603. u32 old_tx_mode = tp->tx_mode;
  1604. if (tg3_flag(tp, USE_PHYLIB))
  1605. autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
  1606. else
  1607. autoneg = tp->link_config.autoneg;
  1608. if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
  1609. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  1610. flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
  1611. else
  1612. flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  1613. } else
  1614. flowctrl = tp->link_config.flowctrl;
  1615. tp->link_config.active_flowctrl = flowctrl;
  1616. if (flowctrl & FLOW_CTRL_RX)
  1617. tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
  1618. else
  1619. tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
  1620. if (old_rx_mode != tp->rx_mode)
  1621. tw32_f(MAC_RX_MODE, tp->rx_mode);
  1622. if (flowctrl & FLOW_CTRL_TX)
  1623. tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
  1624. else
  1625. tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
  1626. if (old_tx_mode != tp->tx_mode)
  1627. tw32_f(MAC_TX_MODE, tp->tx_mode);
  1628. }
  1629. static void tg3_adjust_link(struct net_device *dev)
  1630. {
  1631. u8 oldflowctrl, linkmesg = 0;
  1632. u32 mac_mode, lcl_adv, rmt_adv;
  1633. struct tg3 *tp = netdev_priv(dev);
  1634. struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1635. spin_lock_bh(&tp->lock);
  1636. mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
  1637. MAC_MODE_HALF_DUPLEX);
  1638. oldflowctrl = tp->link_config.active_flowctrl;
  1639. if (phydev->link) {
  1640. lcl_adv = 0;
  1641. rmt_adv = 0;
  1642. if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
  1643. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1644. else if (phydev->speed == SPEED_1000 ||
  1645. tg3_asic_rev(tp) != ASIC_REV_5785)
  1646. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1647. else
  1648. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1649. if (phydev->duplex == DUPLEX_HALF)
  1650. mac_mode |= MAC_MODE_HALF_DUPLEX;
  1651. else {
  1652. lcl_adv = mii_advertise_flowctrl(
  1653. tp->link_config.flowctrl);
  1654. if (phydev->pause)
  1655. rmt_adv = LPA_PAUSE_CAP;
  1656. if (phydev->asym_pause)
  1657. rmt_adv |= LPA_PAUSE_ASYM;
  1658. }
  1659. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  1660. } else
  1661. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1662. if (mac_mode != tp->mac_mode) {
  1663. tp->mac_mode = mac_mode;
  1664. tw32_f(MAC_MODE, tp->mac_mode);
  1665. udelay(40);
  1666. }
  1667. if (tg3_asic_rev(tp) == ASIC_REV_5785) {
  1668. if (phydev->speed == SPEED_10)
  1669. tw32(MAC_MI_STAT,
  1670. MAC_MI_STAT_10MBPS_MODE |
  1671. MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  1672. else
  1673. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  1674. }
  1675. if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
  1676. tw32(MAC_TX_LENGTHS,
  1677. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1678. (6 << TX_LENGTHS_IPG_SHIFT) |
  1679. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1680. else
  1681. tw32(MAC_TX_LENGTHS,
  1682. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1683. (6 << TX_LENGTHS_IPG_SHIFT) |
  1684. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1685. if (phydev->link != tp->old_link ||
  1686. phydev->speed != tp->link_config.active_speed ||
  1687. phydev->duplex != tp->link_config.active_duplex ||
  1688. oldflowctrl != tp->link_config.active_flowctrl)
  1689. linkmesg = 1;
  1690. tp->old_link = phydev->link;
  1691. tp->link_config.active_speed = phydev->speed;
  1692. tp->link_config.active_duplex = phydev->duplex;
  1693. spin_unlock_bh(&tp->lock);
  1694. if (linkmesg)
  1695. tg3_link_report(tp);
  1696. }
  1697. static int tg3_phy_init(struct tg3 *tp)
  1698. {
  1699. struct phy_device *phydev;
  1700. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
  1701. return 0;
  1702. /* Bring the PHY back to a known state. */
  1703. tg3_bmcr_reset(tp);
  1704. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1705. /* Attach the MAC to the PHY. */
  1706. phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
  1707. tg3_adjust_link, phydev->interface);
  1708. if (IS_ERR(phydev)) {
  1709. dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
  1710. return PTR_ERR(phydev);
  1711. }
  1712. /* Mask with MAC supported features. */
  1713. switch (phydev->interface) {
  1714. case PHY_INTERFACE_MODE_GMII:
  1715. case PHY_INTERFACE_MODE_RGMII:
  1716. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  1717. phydev->supported &= (PHY_GBIT_FEATURES |
  1718. SUPPORTED_Pause |
  1719. SUPPORTED_Asym_Pause);
  1720. break;
  1721. }
  1722. /* fallthru */
  1723. case PHY_INTERFACE_MODE_MII:
  1724. phydev->supported &= (PHY_BASIC_FEATURES |
  1725. SUPPORTED_Pause |
  1726. SUPPORTED_Asym_Pause);
  1727. break;
  1728. default:
  1729. phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1730. return -EINVAL;
  1731. }
  1732. tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
  1733. phydev->advertising = phydev->supported;
  1734. return 0;
  1735. }
  1736. static void tg3_phy_start(struct tg3 *tp)
  1737. {
  1738. struct phy_device *phydev;
  1739. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  1740. return;
  1741. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1742. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
  1743. tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
  1744. phydev->speed = tp->link_config.speed;
  1745. phydev->duplex = tp->link_config.duplex;
  1746. phydev->autoneg = tp->link_config.autoneg;
  1747. phydev->advertising = tp->link_config.advertising;
  1748. }
  1749. phy_start(phydev);
  1750. phy_start_aneg(phydev);
  1751. }
  1752. static void tg3_phy_stop(struct tg3 *tp)
  1753. {
  1754. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  1755. return;
  1756. phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1757. }
  1758. static void tg3_phy_fini(struct tg3 *tp)
  1759. {
  1760. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  1761. phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1762. tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
  1763. }
  1764. }
  1765. static int tg3_phy_set_extloopbk(struct tg3 *tp)
  1766. {
  1767. int err;
  1768. u32 val;
  1769. if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  1770. return 0;
  1771. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  1772. /* Cannot do read-modify-write on 5401 */
  1773. err = tg3_phy_auxctl_write(tp,
  1774. MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
  1775. MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
  1776. 0x4c20);
  1777. goto done;
  1778. }
  1779. err = tg3_phy_auxctl_read(tp,
  1780. MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
  1781. if (err)
  1782. return err;
  1783. val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
  1784. err = tg3_phy_auxctl_write(tp,
  1785. MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
  1786. done:
  1787. return err;
  1788. }
  1789. static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
  1790. {
  1791. u32 phytest;
  1792. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
  1793. u32 phy;
  1794. tg3_writephy(tp, MII_TG3_FET_TEST,
  1795. phytest | MII_TG3_FET_SHADOW_EN);
  1796. if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
  1797. if (enable)
  1798. phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
  1799. else
  1800. phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
  1801. tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
  1802. }
  1803. tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
  1804. }
  1805. }
  1806. static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
  1807. {
  1808. u32 reg;
  1809. if (!tg3_flag(tp, 5705_PLUS) ||
  1810. (tg3_flag(tp, 5717_PLUS) &&
  1811. (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
  1812. return;
  1813. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  1814. tg3_phy_fet_toggle_apd(tp, enable);
  1815. return;
  1816. }
  1817. reg = MII_TG3_MISC_SHDW_WREN |
  1818. MII_TG3_MISC_SHDW_SCR5_SEL |
  1819. MII_TG3_MISC_SHDW_SCR5_LPED |
  1820. MII_TG3_MISC_SHDW_SCR5_DLPTLM |
  1821. MII_TG3_MISC_SHDW_SCR5_SDTL |
  1822. MII_TG3_MISC_SHDW_SCR5_C125OE;
  1823. if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
  1824. reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
  1825. tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
  1826. reg = MII_TG3_MISC_SHDW_WREN |
  1827. MII_TG3_MISC_SHDW_APD_SEL |
  1828. MII_TG3_MISC_SHDW_APD_WKTM_84MS;
  1829. if (enable)
  1830. reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
  1831. tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
  1832. }
  1833. static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
  1834. {
  1835. u32 phy;
  1836. if (!tg3_flag(tp, 5705_PLUS) ||
  1837. (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  1838. return;
  1839. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  1840. u32 ephy;
  1841. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
  1842. u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
  1843. tg3_writephy(tp, MII_TG3_FET_TEST,
  1844. ephy | MII_TG3_FET_SHADOW_EN);
  1845. if (!tg3_readphy(tp, reg, &phy)) {
  1846. if (enable)
  1847. phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
  1848. else
  1849. phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
  1850. tg3_writephy(tp, reg, phy);
  1851. }
  1852. tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
  1853. }
  1854. } else {
  1855. int ret;
  1856. ret = tg3_phy_auxctl_read(tp,
  1857. MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
  1858. if (!ret) {
  1859. if (enable)
  1860. phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1861. else
  1862. phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1863. tg3_phy_auxctl_write(tp,
  1864. MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
  1865. }
  1866. }
  1867. }
  1868. static void tg3_phy_set_wirespeed(struct tg3 *tp)
  1869. {
  1870. int ret;
  1871. u32 val;
  1872. if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
  1873. return;
  1874. ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
  1875. if (!ret)
  1876. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
  1877. val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
  1878. }
  1879. static void tg3_phy_apply_otp(struct tg3 *tp)
  1880. {
  1881. u32 otp, phy;
  1882. if (!tp->phy_otp)
  1883. return;
  1884. otp = tp->phy_otp;
  1885. if (tg3_phy_toggle_auxctl_smdsp(tp, true))
  1886. return;
  1887. phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
  1888. phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
  1889. tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
  1890. phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
  1891. ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
  1892. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
  1893. phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
  1894. phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
  1895. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
  1896. phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
  1897. tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
  1898. phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
  1899. tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
  1900. phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
  1901. ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
  1902. tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
  1903. tg3_phy_toggle_auxctl_smdsp(tp, false);
  1904. }
  1905. static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
  1906. {
  1907. u32 val;
  1908. struct ethtool_eee *dest = &tp->eee;
  1909. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
  1910. return;
  1911. if (eee)
  1912. dest = eee;
  1913. if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
  1914. return;
  1915. /* Pull eee_active */
  1916. if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
  1917. val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
  1918. dest->eee_active = 1;
  1919. } else
  1920. dest->eee_active = 0;
  1921. /* Pull lp advertised settings */
  1922. if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
  1923. return;
  1924. dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
  1925. /* Pull advertised and eee_enabled settings */
  1926. if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
  1927. return;
  1928. dest->eee_enabled = !!val;
  1929. dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
  1930. /* Pull tx_lpi_enabled */
  1931. val = tr32(TG3_CPMU_EEE_MODE);
  1932. dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
  1933. /* Pull lpi timer value */
  1934. dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
  1935. }
  1936. static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
  1937. {
  1938. u32 val;
  1939. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
  1940. return;
  1941. tp->setlpicnt = 0;
  1942. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  1943. current_link_up &&
  1944. tp->link_config.active_duplex == DUPLEX_FULL &&
  1945. (tp->link_config.active_speed == SPEED_100 ||
  1946. tp->link_config.active_speed == SPEED_1000)) {
  1947. u32 eeectl;
  1948. if (tp->link_config.active_speed == SPEED_1000)
  1949. eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
  1950. else
  1951. eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
  1952. tw32(TG3_CPMU_EEE_CTRL, eeectl);
  1953. tg3_eee_pull_config(tp, NULL);
  1954. if (tp->eee.eee_active)
  1955. tp->setlpicnt = 2;
  1956. }
  1957. if (!tp->setlpicnt) {
  1958. if (current_link_up &&
  1959. !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  1960. tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
  1961. tg3_phy_toggle_auxctl_smdsp(tp, false);
  1962. }
  1963. val = tr32(TG3_CPMU_EEE_MODE);
  1964. tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
  1965. }
  1966. }
  1967. static void tg3_phy_eee_enable(struct tg3 *tp)
  1968. {
  1969. u32 val;
  1970. if (tp->link_config.active_speed == SPEED_1000 &&
  1971. (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  1972. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  1973. tg3_flag(tp, 57765_CLASS)) &&
  1974. !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  1975. val = MII_TG3_DSP_TAP26_ALNOKO |
  1976. MII_TG3_DSP_TAP26_RMRXSTO;
  1977. tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
  1978. tg3_phy_toggle_auxctl_smdsp(tp, false);
  1979. }
  1980. val = tr32(TG3_CPMU_EEE_MODE);
  1981. tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
  1982. }
  1983. static int tg3_wait_macro_done(struct tg3 *tp)
  1984. {
  1985. int limit = 100;
  1986. while (limit--) {
  1987. u32 tmp32;
  1988. if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
  1989. if ((tmp32 & 0x1000) == 0)
  1990. break;
  1991. }
  1992. }
  1993. if (limit < 0)
  1994. return -EBUSY;
  1995. return 0;
  1996. }
  1997. static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
  1998. {
  1999. static const u32 test_pat[4][6] = {
  2000. { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
  2001. { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
  2002. { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
  2003. { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
  2004. };
  2005. int chan;
  2006. for (chan = 0; chan < 4; chan++) {
  2007. int i;
  2008. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  2009. (chan * 0x2000) | 0x0200);
  2010. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
  2011. for (i = 0; i < 6; i++)
  2012. tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
  2013. test_pat[chan][i]);
  2014. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
  2015. if (tg3_wait_macro_done(tp)) {
  2016. *resetp = 1;
  2017. return -EBUSY;
  2018. }
  2019. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  2020. (chan * 0x2000) | 0x0200);
  2021. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
  2022. if (tg3_wait_macro_done(tp)) {
  2023. *resetp = 1;
  2024. return -EBUSY;
  2025. }
  2026. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
  2027. if (tg3_wait_macro_done(tp)) {
  2028. *resetp = 1;
  2029. return -EBUSY;
  2030. }
  2031. for (i = 0; i < 6; i += 2) {
  2032. u32 low, high;
  2033. if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
  2034. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
  2035. tg3_wait_macro_done(tp)) {
  2036. *resetp = 1;
  2037. return -EBUSY;
  2038. }
  2039. low &= 0x7fff;
  2040. high &= 0x000f;
  2041. if (low != test_pat[chan][i] ||
  2042. high != test_pat[chan][i+1]) {
  2043. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
  2044. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
  2045. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
  2046. return -EBUSY;
  2047. }
  2048. }
  2049. }
  2050. return 0;
  2051. }
  2052. static int tg3_phy_reset_chanpat(struct tg3 *tp)
  2053. {
  2054. int chan;
  2055. for (chan = 0; chan < 4; chan++) {
  2056. int i;
  2057. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  2058. (chan * 0x2000) | 0x0200);
  2059. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
  2060. for (i = 0; i < 6; i++)
  2061. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
  2062. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
  2063. if (tg3_wait_macro_done(tp))
  2064. return -EBUSY;
  2065. }
  2066. return 0;
  2067. }
  2068. static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
  2069. {
  2070. u32 reg32, phy9_orig;
  2071. int retries, do_phy_reset, err;
  2072. retries = 10;
  2073. do_phy_reset = 1;
  2074. do {
  2075. if (do_phy_reset) {
  2076. err = tg3_bmcr_reset(tp);
  2077. if (err)
  2078. return err;
  2079. do_phy_reset = 0;
  2080. }
  2081. /* Disable transmitter and interrupt. */
  2082. if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
  2083. continue;
  2084. reg32 |= 0x3000;
  2085. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  2086. /* Set full-duplex, 1000 mbps. */
  2087. tg3_writephy(tp, MII_BMCR,
  2088. BMCR_FULLDPLX | BMCR_SPEED1000);
  2089. /* Set to master mode. */
  2090. if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
  2091. continue;
  2092. tg3_writephy(tp, MII_CTRL1000,
  2093. CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
  2094. err = tg3_phy_toggle_auxctl_smdsp(tp, true);
  2095. if (err)
  2096. return err;
  2097. /* Block the PHY control access. */
  2098. tg3_phydsp_write(tp, 0x8005, 0x0800);
  2099. err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
  2100. if (!err)
  2101. break;
  2102. } while (--retries);
  2103. err = tg3_phy_reset_chanpat(tp);
  2104. if (err)
  2105. return err;
  2106. tg3_phydsp_write(tp, 0x8005, 0x0000);
  2107. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
  2108. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
  2109. tg3_phy_toggle_auxctl_smdsp(tp, false);
  2110. tg3_writephy(tp, MII_CTRL1000, phy9_orig);
  2111. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
  2112. reg32 &= ~0x3000;
  2113. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  2114. } else if (!err)
  2115. err = -EBUSY;
  2116. return err;
  2117. }
  2118. static void tg3_carrier_off(struct tg3 *tp)
  2119. {
  2120. netif_carrier_off(tp->dev);
  2121. tp->link_up = false;
  2122. }
  2123. static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
  2124. {
  2125. if (tg3_flag(tp, ENABLE_ASF))
  2126. netdev_warn(tp->dev,
  2127. "Management side-band traffic will be interrupted during phy settings change\n");
  2128. }
  2129. /* This will reset the tigon3 PHY if there is no valid
  2130. * link unless the FORCE argument is non-zero.
  2131. */
  2132. static int tg3_phy_reset(struct tg3 *tp)
  2133. {
  2134. u32 val, cpmuctrl;
  2135. int err;
  2136. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  2137. val = tr32(GRC_MISC_CFG);
  2138. tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
  2139. udelay(40);
  2140. }
  2141. err = tg3_readphy(tp, MII_BMSR, &val);
  2142. err |= tg3_readphy(tp, MII_BMSR, &val);
  2143. if (err != 0)
  2144. return -EBUSY;
  2145. if (netif_running(tp->dev) && tp->link_up) {
  2146. netif_carrier_off(tp->dev);
  2147. tg3_link_report(tp);
  2148. }
  2149. if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
  2150. tg3_asic_rev(tp) == ASIC_REV_5704 ||
  2151. tg3_asic_rev(tp) == ASIC_REV_5705) {
  2152. err = tg3_phy_reset_5703_4_5(tp);
  2153. if (err)
  2154. return err;
  2155. goto out;
  2156. }
  2157. cpmuctrl = 0;
  2158. if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
  2159. tg3_chip_rev(tp) != CHIPREV_5784_AX) {
  2160. cpmuctrl = tr32(TG3_CPMU_CTRL);
  2161. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
  2162. tw32(TG3_CPMU_CTRL,
  2163. cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
  2164. }
  2165. err = tg3_bmcr_reset(tp);
  2166. if (err)
  2167. return err;
  2168. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
  2169. val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
  2170. tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
  2171. tw32(TG3_CPMU_CTRL, cpmuctrl);
  2172. }
  2173. if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
  2174. tg3_chip_rev(tp) == CHIPREV_5761_AX) {
  2175. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  2176. if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
  2177. CPMU_LSPD_1000MB_MACCLK_12_5) {
  2178. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  2179. udelay(40);
  2180. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  2181. }
  2182. }
  2183. if (tg3_flag(tp, 5717_PLUS) &&
  2184. (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
  2185. return 0;
  2186. tg3_phy_apply_otp(tp);
  2187. if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
  2188. tg3_phy_toggle_apd(tp, true);
  2189. else
  2190. tg3_phy_toggle_apd(tp, false);
  2191. out:
  2192. if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
  2193. !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  2194. tg3_phydsp_write(tp, 0x201f, 0x2aaa);
  2195. tg3_phydsp_write(tp, 0x000a, 0x0323);
  2196. tg3_phy_toggle_auxctl_smdsp(tp, false);
  2197. }
  2198. if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
  2199. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  2200. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  2201. }
  2202. if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
  2203. if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  2204. tg3_phydsp_write(tp, 0x000a, 0x310b);
  2205. tg3_phydsp_write(tp, 0x201f, 0x9506);
  2206. tg3_phydsp_write(tp, 0x401f, 0x14e2);
  2207. tg3_phy_toggle_auxctl_smdsp(tp, false);
  2208. }
  2209. } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
  2210. if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  2211. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  2212. if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
  2213. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
  2214. tg3_writephy(tp, MII_TG3_TEST1,
  2215. MII_TG3_TEST1_TRIM_EN | 0x4);
  2216. } else
  2217. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
  2218. tg3_phy_toggle_auxctl_smdsp(tp, false);
  2219. }
  2220. }
  2221. /* Set Extended packet length bit (bit 14) on all chips that */
  2222. /* support jumbo frames */
  2223. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  2224. /* Cannot do read-modify-write on 5401 */
  2225. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
  2226. } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
  2227. /* Set bit 14 with read-modify-write to preserve other bits */
  2228. err = tg3_phy_auxctl_read(tp,
  2229. MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
  2230. if (!err)
  2231. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
  2232. val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
  2233. }
  2234. /* Set phy register 0x10 bit 0 to high fifo elasticity to support
  2235. * jumbo frames transmission.
  2236. */
  2237. if (tg3_flag(tp, JUMBO_CAPABLE)) {
  2238. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
  2239. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  2240. val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
  2241. }
  2242. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  2243. /* adjust output voltage */
  2244. tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
  2245. }
  2246. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
  2247. tg3_phydsp_write(tp, 0xffb, 0x4000);
  2248. tg3_phy_toggle_automdix(tp, true);
  2249. tg3_phy_set_wirespeed(tp);
  2250. return 0;
  2251. }
  2252. #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
  2253. #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
  2254. #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
  2255. TG3_GPIO_MSG_NEED_VAUX)
  2256. #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
  2257. ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
  2258. (TG3_GPIO_MSG_DRVR_PRES << 4) | \
  2259. (TG3_GPIO_MSG_DRVR_PRES << 8) | \
  2260. (TG3_GPIO_MSG_DRVR_PRES << 12))
  2261. #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
  2262. ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
  2263. (TG3_GPIO_MSG_NEED_VAUX << 4) | \
  2264. (TG3_GPIO_MSG_NEED_VAUX << 8) | \
  2265. (TG3_GPIO_MSG_NEED_VAUX << 12))
  2266. static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
  2267. {
  2268. u32 status, shift;
  2269. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  2270. tg3_asic_rev(tp) == ASIC_REV_5719)
  2271. status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
  2272. else
  2273. status = tr32(TG3_CPMU_DRV_STATUS);
  2274. shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
  2275. status &= ~(TG3_GPIO_MSG_MASK << shift);
  2276. status |= (newstat << shift);
  2277. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  2278. tg3_asic_rev(tp) == ASIC_REV_5719)
  2279. tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
  2280. else
  2281. tw32(TG3_CPMU_DRV_STATUS, status);
  2282. return status >> TG3_APE_GPIO_MSG_SHIFT;
  2283. }
  2284. static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
  2285. {
  2286. if (!tg3_flag(tp, IS_NIC))
  2287. return 0;
  2288. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  2289. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  2290. tg3_asic_rev(tp) == ASIC_REV_5720) {
  2291. if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
  2292. return -EIO;
  2293. tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
  2294. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
  2295. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2296. tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
  2297. } else {
  2298. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
  2299. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2300. }
  2301. return 0;
  2302. }
  2303. static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
  2304. {
  2305. u32 grc_local_ctrl;
  2306. if (!tg3_flag(tp, IS_NIC) ||
  2307. tg3_asic_rev(tp) == ASIC_REV_5700 ||
  2308. tg3_asic_rev(tp) == ASIC_REV_5701)
  2309. return;
  2310. grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
  2311. tw32_wait_f(GRC_LOCAL_CTRL,
  2312. grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
  2313. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2314. tw32_wait_f(GRC_LOCAL_CTRL,
  2315. grc_local_ctrl,
  2316. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2317. tw32_wait_f(GRC_LOCAL_CTRL,
  2318. grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
  2319. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2320. }
  2321. static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
  2322. {
  2323. if (!tg3_flag(tp, IS_NIC))
  2324. return;
  2325. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  2326. tg3_asic_rev(tp) == ASIC_REV_5701) {
  2327. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  2328. (GRC_LCLCTRL_GPIO_OE0 |
  2329. GRC_LCLCTRL_GPIO_OE1 |
  2330. GRC_LCLCTRL_GPIO_OE2 |
  2331. GRC_LCLCTRL_GPIO_OUTPUT0 |
  2332. GRC_LCLCTRL_GPIO_OUTPUT1),
  2333. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2334. } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  2335. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
  2336. /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
  2337. u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
  2338. GRC_LCLCTRL_GPIO_OE1 |
  2339. GRC_LCLCTRL_GPIO_OE2 |
  2340. GRC_LCLCTRL_GPIO_OUTPUT0 |
  2341. GRC_LCLCTRL_GPIO_OUTPUT1 |
  2342. tp->grc_local_ctrl;
  2343. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
  2344. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2345. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
  2346. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
  2347. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2348. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
  2349. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
  2350. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2351. } else {
  2352. u32 no_gpio2;
  2353. u32 grc_local_ctrl = 0;
  2354. /* Workaround to prevent overdrawing Amps. */
  2355. if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  2356. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  2357. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  2358. grc_local_ctrl,
  2359. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2360. }
  2361. /* On 5753 and variants, GPIO2 cannot be used. */
  2362. no_gpio2 = tp->nic_sram_data_cfg &
  2363. NIC_SRAM_DATA_CFG_NO_GPIO2;
  2364. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  2365. GRC_LCLCTRL_GPIO_OE1 |
  2366. GRC_LCLCTRL_GPIO_OE2 |
  2367. GRC_LCLCTRL_GPIO_OUTPUT1 |
  2368. GRC_LCLCTRL_GPIO_OUTPUT2;
  2369. if (no_gpio2) {
  2370. grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
  2371. GRC_LCLCTRL_GPIO_OUTPUT2);
  2372. }
  2373. tw32_wait_f(GRC_LOCAL_CTRL,
  2374. tp->grc_local_ctrl | grc_local_ctrl,
  2375. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2376. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
  2377. tw32_wait_f(GRC_LOCAL_CTRL,
  2378. tp->grc_local_ctrl | grc_local_ctrl,
  2379. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2380. if (!no_gpio2) {
  2381. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
  2382. tw32_wait_f(GRC_LOCAL_CTRL,
  2383. tp->grc_local_ctrl | grc_local_ctrl,
  2384. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2385. }
  2386. }
  2387. }
  2388. static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
  2389. {
  2390. u32 msg = 0;
  2391. /* Serialize power state transitions */
  2392. if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
  2393. return;
  2394. if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
  2395. msg = TG3_GPIO_MSG_NEED_VAUX;
  2396. msg = tg3_set_function_status(tp, msg);
  2397. if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
  2398. goto done;
  2399. if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
  2400. tg3_pwrsrc_switch_to_vaux(tp);
  2401. else
  2402. tg3_pwrsrc_die_with_vmain(tp);
  2403. done:
  2404. tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
  2405. }
  2406. static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
  2407. {
  2408. bool need_vaux = false;
  2409. /* The GPIOs do something completely different on 57765. */
  2410. if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
  2411. return;
  2412. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  2413. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  2414. tg3_asic_rev(tp) == ASIC_REV_5720) {
  2415. tg3_frob_aux_power_5717(tp, include_wol ?
  2416. tg3_flag(tp, WOL_ENABLE) != 0 : 0);
  2417. return;
  2418. }
  2419. if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
  2420. struct net_device *dev_peer;
  2421. dev_peer = pci_get_drvdata(tp->pdev_peer);
  2422. /* remove_one() may have been run on the peer. */
  2423. if (dev_peer) {
  2424. struct tg3 *tp_peer = netdev_priv(dev_peer);
  2425. if (tg3_flag(tp_peer, INIT_COMPLETE))
  2426. return;
  2427. if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
  2428. tg3_flag(tp_peer, ENABLE_ASF))
  2429. need_vaux = true;
  2430. }
  2431. }
  2432. if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
  2433. tg3_flag(tp, ENABLE_ASF))
  2434. need_vaux = true;
  2435. if (need_vaux)
  2436. tg3_pwrsrc_switch_to_vaux(tp);
  2437. else
  2438. tg3_pwrsrc_die_with_vmain(tp);
  2439. }
  2440. static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
  2441. {
  2442. if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
  2443. return 1;
  2444. else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
  2445. if (speed != SPEED_10)
  2446. return 1;
  2447. } else if (speed == SPEED_10)
  2448. return 1;
  2449. return 0;
  2450. }
  2451. static bool tg3_phy_power_bug(struct tg3 *tp)
  2452. {
  2453. switch (tg3_asic_rev(tp)) {
  2454. case ASIC_REV_5700:
  2455. case ASIC_REV_5704:
  2456. return true;
  2457. case ASIC_REV_5780:
  2458. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  2459. return true;
  2460. return false;
  2461. case ASIC_REV_5717:
  2462. if (!tp->pci_fn)
  2463. return true;
  2464. return false;
  2465. case ASIC_REV_5719:
  2466. case ASIC_REV_5720:
  2467. if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  2468. !tp->pci_fn)
  2469. return true;
  2470. return false;
  2471. }
  2472. return false;
  2473. }
  2474. static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
  2475. {
  2476. u32 val;
  2477. if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
  2478. return;
  2479. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  2480. if (tg3_asic_rev(tp) == ASIC_REV_5704) {
  2481. u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
  2482. u32 serdes_cfg = tr32(MAC_SERDES_CFG);
  2483. sg_dig_ctrl |=
  2484. SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
  2485. tw32(SG_DIG_CTRL, sg_dig_ctrl);
  2486. tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
  2487. }
  2488. return;
  2489. }
  2490. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  2491. tg3_bmcr_reset(tp);
  2492. val = tr32(GRC_MISC_CFG);
  2493. tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
  2494. udelay(40);
  2495. return;
  2496. } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  2497. u32 phytest;
  2498. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
  2499. u32 phy;
  2500. tg3_writephy(tp, MII_ADVERTISE, 0);
  2501. tg3_writephy(tp, MII_BMCR,
  2502. BMCR_ANENABLE | BMCR_ANRESTART);
  2503. tg3_writephy(tp, MII_TG3_FET_TEST,
  2504. phytest | MII_TG3_FET_SHADOW_EN);
  2505. if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
  2506. phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
  2507. tg3_writephy(tp,
  2508. MII_TG3_FET_SHDW_AUXMODE4,
  2509. phy);
  2510. }
  2511. tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
  2512. }
  2513. return;
  2514. } else if (do_low_power) {
  2515. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  2516. MII_TG3_EXT_CTRL_FORCE_LED_OFF);
  2517. val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
  2518. MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
  2519. MII_TG3_AUXCTL_PCTL_VREG_11V;
  2520. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
  2521. }
  2522. /* The PHY should not be powered down on some chips because
  2523. * of bugs.
  2524. */
  2525. if (tg3_phy_power_bug(tp))
  2526. return;
  2527. if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
  2528. tg3_chip_rev(tp) == CHIPREV_5761_AX) {
  2529. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  2530. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  2531. val |= CPMU_LSPD_1000MB_MACCLK_12_5;
  2532. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  2533. }
  2534. tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
  2535. }
  2536. /* tp->lock is held. */
  2537. static int tg3_nvram_lock(struct tg3 *tp)
  2538. {
  2539. if (tg3_flag(tp, NVRAM)) {
  2540. int i;
  2541. if (tp->nvram_lock_cnt == 0) {
  2542. tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  2543. for (i = 0; i < 8000; i++) {
  2544. if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  2545. break;
  2546. udelay(20);
  2547. }
  2548. if (i == 8000) {
  2549. tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
  2550. return -ENODEV;
  2551. }
  2552. }
  2553. tp->nvram_lock_cnt++;
  2554. }
  2555. return 0;
  2556. }
  2557. /* tp->lock is held. */
  2558. static void tg3_nvram_unlock(struct tg3 *tp)
  2559. {
  2560. if (tg3_flag(tp, NVRAM)) {
  2561. if (tp->nvram_lock_cnt > 0)
  2562. tp->nvram_lock_cnt--;
  2563. if (tp->nvram_lock_cnt == 0)
  2564. tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
  2565. }
  2566. }
  2567. /* tp->lock is held. */
  2568. static void tg3_enable_nvram_access(struct tg3 *tp)
  2569. {
  2570. if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
  2571. u32 nvaccess = tr32(NVRAM_ACCESS);
  2572. tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
  2573. }
  2574. }
  2575. /* tp->lock is held. */
  2576. static void tg3_disable_nvram_access(struct tg3 *tp)
  2577. {
  2578. if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
  2579. u32 nvaccess = tr32(NVRAM_ACCESS);
  2580. tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
  2581. }
  2582. }
  2583. static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
  2584. u32 offset, u32 *val)
  2585. {
  2586. u32 tmp;
  2587. int i;
  2588. if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
  2589. return -EINVAL;
  2590. tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
  2591. EEPROM_ADDR_DEVID_MASK |
  2592. EEPROM_ADDR_READ);
  2593. tw32(GRC_EEPROM_ADDR,
  2594. tmp |
  2595. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  2596. ((offset << EEPROM_ADDR_ADDR_SHIFT) &
  2597. EEPROM_ADDR_ADDR_MASK) |
  2598. EEPROM_ADDR_READ | EEPROM_ADDR_START);
  2599. for (i = 0; i < 1000; i++) {
  2600. tmp = tr32(GRC_EEPROM_ADDR);
  2601. if (tmp & EEPROM_ADDR_COMPLETE)
  2602. break;
  2603. msleep(1);
  2604. }
  2605. if (!(tmp & EEPROM_ADDR_COMPLETE))
  2606. return -EBUSY;
  2607. tmp = tr32(GRC_EEPROM_DATA);
  2608. /*
  2609. * The data will always be opposite the native endian
  2610. * format. Perform a blind byteswap to compensate.
  2611. */
  2612. *val = swab32(tmp);
  2613. return 0;
  2614. }
  2615. #define NVRAM_CMD_TIMEOUT 10000
  2616. static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
  2617. {
  2618. int i;
  2619. tw32(NVRAM_CMD, nvram_cmd);
  2620. for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
  2621. udelay(10);
  2622. if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
  2623. udelay(10);
  2624. break;
  2625. }
  2626. }
  2627. if (i == NVRAM_CMD_TIMEOUT)
  2628. return -EBUSY;
  2629. return 0;
  2630. }
  2631. static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
  2632. {
  2633. if (tg3_flag(tp, NVRAM) &&
  2634. tg3_flag(tp, NVRAM_BUFFERED) &&
  2635. tg3_flag(tp, FLASH) &&
  2636. !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
  2637. (tp->nvram_jedecnum == JEDEC_ATMEL))
  2638. addr = ((addr / tp->nvram_pagesize) <<
  2639. ATMEL_AT45DB0X1B_PAGE_POS) +
  2640. (addr % tp->nvram_pagesize);
  2641. return addr;
  2642. }
  2643. static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
  2644. {
  2645. if (tg3_flag(tp, NVRAM) &&
  2646. tg3_flag(tp, NVRAM_BUFFERED) &&
  2647. tg3_flag(tp, FLASH) &&
  2648. !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
  2649. (tp->nvram_jedecnum == JEDEC_ATMEL))
  2650. addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
  2651. tp->nvram_pagesize) +
  2652. (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
  2653. return addr;
  2654. }
  2655. /* NOTE: Data read in from NVRAM is byteswapped according to
  2656. * the byteswapping settings for all other register accesses.
  2657. * tg3 devices are BE devices, so on a BE machine, the data
  2658. * returned will be exactly as it is seen in NVRAM. On a LE
  2659. * machine, the 32-bit value will be byteswapped.
  2660. */
  2661. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
  2662. {
  2663. int ret;
  2664. if (!tg3_flag(tp, NVRAM))
  2665. return tg3_nvram_read_using_eeprom(tp, offset, val);
  2666. offset = tg3_nvram_phys_addr(tp, offset);
  2667. if (offset > NVRAM_ADDR_MSK)
  2668. return -EINVAL;
  2669. ret = tg3_nvram_lock(tp);
  2670. if (ret)
  2671. return ret;
  2672. tg3_enable_nvram_access(tp);
  2673. tw32(NVRAM_ADDR, offset);
  2674. ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
  2675. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
  2676. if (ret == 0)
  2677. *val = tr32(NVRAM_RDDATA);
  2678. tg3_disable_nvram_access(tp);
  2679. tg3_nvram_unlock(tp);
  2680. return ret;
  2681. }
  2682. /* Ensures NVRAM data is in bytestream format. */
  2683. static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
  2684. {
  2685. u32 v;
  2686. int res = tg3_nvram_read(tp, offset, &v);
  2687. if (!res)
  2688. *val = cpu_to_be32(v);
  2689. return res;
  2690. }
  2691. static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
  2692. u32 offset, u32 len, u8 *buf)
  2693. {
  2694. int i, j, rc = 0;
  2695. u32 val;
  2696. for (i = 0; i < len; i += 4) {
  2697. u32 addr;
  2698. __be32 data;
  2699. addr = offset + i;
  2700. memcpy(&data, buf + i, 4);
  2701. /*
  2702. * The SEEPROM interface expects the data to always be opposite
  2703. * the native endian format. We accomplish this by reversing
  2704. * all the operations that would have been performed on the
  2705. * data from a call to tg3_nvram_read_be32().
  2706. */
  2707. tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
  2708. val = tr32(GRC_EEPROM_ADDR);
  2709. tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
  2710. val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
  2711. EEPROM_ADDR_READ);
  2712. tw32(GRC_EEPROM_ADDR, val |
  2713. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  2714. (addr & EEPROM_ADDR_ADDR_MASK) |
  2715. EEPROM_ADDR_START |
  2716. EEPROM_ADDR_WRITE);
  2717. for (j = 0; j < 1000; j++) {
  2718. val = tr32(GRC_EEPROM_ADDR);
  2719. if (val & EEPROM_ADDR_COMPLETE)
  2720. break;
  2721. msleep(1);
  2722. }
  2723. if (!(val & EEPROM_ADDR_COMPLETE)) {
  2724. rc = -EBUSY;
  2725. break;
  2726. }
  2727. }
  2728. return rc;
  2729. }
  2730. /* offset and length are dword aligned */
  2731. static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
  2732. u8 *buf)
  2733. {
  2734. int ret = 0;
  2735. u32 pagesize = tp->nvram_pagesize;
  2736. u32 pagemask = pagesize - 1;
  2737. u32 nvram_cmd;
  2738. u8 *tmp;
  2739. tmp = kmalloc(pagesize, GFP_KERNEL);
  2740. if (tmp == NULL)
  2741. return -ENOMEM;
  2742. while (len) {
  2743. int j;
  2744. u32 phy_addr, page_off, size;
  2745. phy_addr = offset & ~pagemask;
  2746. for (j = 0; j < pagesize; j += 4) {
  2747. ret = tg3_nvram_read_be32(tp, phy_addr + j,
  2748. (__be32 *) (tmp + j));
  2749. if (ret)
  2750. break;
  2751. }
  2752. if (ret)
  2753. break;
  2754. page_off = offset & pagemask;
  2755. size = pagesize;
  2756. if (len < size)
  2757. size = len;
  2758. len -= size;
  2759. memcpy(tmp + page_off, buf, size);
  2760. offset = offset + (pagesize - page_off);
  2761. tg3_enable_nvram_access(tp);
  2762. /*
  2763. * Before we can erase the flash page, we need
  2764. * to issue a special "write enable" command.
  2765. */
  2766. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  2767. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  2768. break;
  2769. /* Erase the target page */
  2770. tw32(NVRAM_ADDR, phy_addr);
  2771. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
  2772. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
  2773. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  2774. break;
  2775. /* Issue another write enable to start the write. */
  2776. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  2777. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  2778. break;
  2779. for (j = 0; j < pagesize; j += 4) {
  2780. __be32 data;
  2781. data = *((__be32 *) (tmp + j));
  2782. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  2783. tw32(NVRAM_ADDR, phy_addr + j);
  2784. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
  2785. NVRAM_CMD_WR;
  2786. if (j == 0)
  2787. nvram_cmd |= NVRAM_CMD_FIRST;
  2788. else if (j == (pagesize - 4))
  2789. nvram_cmd |= NVRAM_CMD_LAST;
  2790. ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
  2791. if (ret)
  2792. break;
  2793. }
  2794. if (ret)
  2795. break;
  2796. }
  2797. nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  2798. tg3_nvram_exec_cmd(tp, nvram_cmd);
  2799. kfree(tmp);
  2800. return ret;
  2801. }
  2802. /* offset and length are dword aligned */
  2803. static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
  2804. u8 *buf)
  2805. {
  2806. int i, ret = 0;
  2807. for (i = 0; i < len; i += 4, offset += 4) {
  2808. u32 page_off, phy_addr, nvram_cmd;
  2809. __be32 data;
  2810. memcpy(&data, buf + i, 4);
  2811. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  2812. page_off = offset % tp->nvram_pagesize;
  2813. phy_addr = tg3_nvram_phys_addr(tp, offset);
  2814. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
  2815. if (page_off == 0 || i == 0)
  2816. nvram_cmd |= NVRAM_CMD_FIRST;
  2817. if (page_off == (tp->nvram_pagesize - 4))
  2818. nvram_cmd |= NVRAM_CMD_LAST;
  2819. if (i == (len - 4))
  2820. nvram_cmd |= NVRAM_CMD_LAST;
  2821. if ((nvram_cmd & NVRAM_CMD_FIRST) ||
  2822. !tg3_flag(tp, FLASH) ||
  2823. !tg3_flag(tp, 57765_PLUS))
  2824. tw32(NVRAM_ADDR, phy_addr);
  2825. if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
  2826. !tg3_flag(tp, 5755_PLUS) &&
  2827. (tp->nvram_jedecnum == JEDEC_ST) &&
  2828. (nvram_cmd & NVRAM_CMD_FIRST)) {
  2829. u32 cmd;
  2830. cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  2831. ret = tg3_nvram_exec_cmd(tp, cmd);
  2832. if (ret)
  2833. break;
  2834. }
  2835. if (!tg3_flag(tp, FLASH)) {
  2836. /* We always do complete word writes to eeprom. */
  2837. nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
  2838. }
  2839. ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
  2840. if (ret)
  2841. break;
  2842. }
  2843. return ret;
  2844. }
  2845. /* offset and length are dword aligned */
  2846. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
  2847. {
  2848. int ret;
  2849. if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
  2850. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  2851. ~GRC_LCLCTRL_GPIO_OUTPUT1);
  2852. udelay(40);
  2853. }
  2854. if (!tg3_flag(tp, NVRAM)) {
  2855. ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
  2856. } else {
  2857. u32 grc_mode;
  2858. ret = tg3_nvram_lock(tp);
  2859. if (ret)
  2860. return ret;
  2861. tg3_enable_nvram_access(tp);
  2862. if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
  2863. tw32(NVRAM_WRITE1, 0x406);
  2864. grc_mode = tr32(GRC_MODE);
  2865. tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
  2866. if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
  2867. ret = tg3_nvram_write_block_buffered(tp, offset, len,
  2868. buf);
  2869. } else {
  2870. ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
  2871. buf);
  2872. }
  2873. grc_mode = tr32(GRC_MODE);
  2874. tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
  2875. tg3_disable_nvram_access(tp);
  2876. tg3_nvram_unlock(tp);
  2877. }
  2878. if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
  2879. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  2880. udelay(40);
  2881. }
  2882. return ret;
  2883. }
  2884. #define RX_CPU_SCRATCH_BASE 0x30000
  2885. #define RX_CPU_SCRATCH_SIZE 0x04000
  2886. #define TX_CPU_SCRATCH_BASE 0x34000
  2887. #define TX_CPU_SCRATCH_SIZE 0x04000
  2888. /* tp->lock is held. */
  2889. static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
  2890. {
  2891. int i;
  2892. const int iters = 10000;
  2893. for (i = 0; i < iters; i++) {
  2894. tw32(cpu_base + CPU_STATE, 0xffffffff);
  2895. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  2896. if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
  2897. break;
  2898. }
  2899. return (i == iters) ? -EBUSY : 0;
  2900. }
  2901. /* tp->lock is held. */
  2902. static int tg3_rxcpu_pause(struct tg3 *tp)
  2903. {
  2904. int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
  2905. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  2906. tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
  2907. udelay(10);
  2908. return rc;
  2909. }
  2910. /* tp->lock is held. */
  2911. static int tg3_txcpu_pause(struct tg3 *tp)
  2912. {
  2913. return tg3_pause_cpu(tp, TX_CPU_BASE);
  2914. }
  2915. /* tp->lock is held. */
  2916. static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
  2917. {
  2918. tw32(cpu_base + CPU_STATE, 0xffffffff);
  2919. tw32_f(cpu_base + CPU_MODE, 0x00000000);
  2920. }
  2921. /* tp->lock is held. */
  2922. static void tg3_rxcpu_resume(struct tg3 *tp)
  2923. {
  2924. tg3_resume_cpu(tp, RX_CPU_BASE);
  2925. }
  2926. /* tp->lock is held. */
  2927. static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
  2928. {
  2929. int rc;
  2930. BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
  2931. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  2932. u32 val = tr32(GRC_VCPU_EXT_CTRL);
  2933. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
  2934. return 0;
  2935. }
  2936. if (cpu_base == RX_CPU_BASE) {
  2937. rc = tg3_rxcpu_pause(tp);
  2938. } else {
  2939. /*
  2940. * There is only an Rx CPU for the 5750 derivative in the
  2941. * BCM4785.
  2942. */
  2943. if (tg3_flag(tp, IS_SSB_CORE))
  2944. return 0;
  2945. rc = tg3_txcpu_pause(tp);
  2946. }
  2947. if (rc) {
  2948. netdev_err(tp->dev, "%s timed out, %s CPU\n",
  2949. __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
  2950. return -ENODEV;
  2951. }
  2952. /* Clear firmware's nvram arbitration. */
  2953. if (tg3_flag(tp, NVRAM))
  2954. tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
  2955. return 0;
  2956. }
  2957. static int tg3_fw_data_len(struct tg3 *tp,
  2958. const struct tg3_firmware_hdr *fw_hdr)
  2959. {
  2960. int fw_len;
  2961. /* Non fragmented firmware have one firmware header followed by a
  2962. * contiguous chunk of data to be written. The length field in that
  2963. * header is not the length of data to be written but the complete
  2964. * length of the bss. The data length is determined based on
  2965. * tp->fw->size minus headers.
  2966. *
  2967. * Fragmented firmware have a main header followed by multiple
  2968. * fragments. Each fragment is identical to non fragmented firmware
  2969. * with a firmware header followed by a contiguous chunk of data. In
  2970. * the main header, the length field is unused and set to 0xffffffff.
  2971. * In each fragment header the length is the entire size of that
  2972. * fragment i.e. fragment data + header length. Data length is
  2973. * therefore length field in the header minus TG3_FW_HDR_LEN.
  2974. */
  2975. if (tp->fw_len == 0xffffffff)
  2976. fw_len = be32_to_cpu(fw_hdr->len);
  2977. else
  2978. fw_len = tp->fw->size;
  2979. return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
  2980. }
  2981. /* tp->lock is held. */
  2982. static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
  2983. u32 cpu_scratch_base, int cpu_scratch_size,
  2984. const struct tg3_firmware_hdr *fw_hdr)
  2985. {
  2986. int err, i;
  2987. void (*write_op)(struct tg3 *, u32, u32);
  2988. int total_len = tp->fw->size;
  2989. if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
  2990. netdev_err(tp->dev,
  2991. "%s: Trying to load TX cpu firmware which is 5705\n",
  2992. __func__);
  2993. return -EINVAL;
  2994. }
  2995. if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
  2996. write_op = tg3_write_mem;
  2997. else
  2998. write_op = tg3_write_indirect_reg32;
  2999. if (tg3_asic_rev(tp) != ASIC_REV_57766) {
  3000. /* It is possible that bootcode is still loading at this point.
  3001. * Get the nvram lock first before halting the cpu.
  3002. */
  3003. int lock_err = tg3_nvram_lock(tp);
  3004. err = tg3_halt_cpu(tp, cpu_base);
  3005. if (!lock_err)
  3006. tg3_nvram_unlock(tp);
  3007. if (err)
  3008. goto out;
  3009. for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  3010. write_op(tp, cpu_scratch_base + i, 0);
  3011. tw32(cpu_base + CPU_STATE, 0xffffffff);
  3012. tw32(cpu_base + CPU_MODE,
  3013. tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
  3014. } else {
  3015. /* Subtract additional main header for fragmented firmware and
  3016. * advance to the first fragment
  3017. */
  3018. total_len -= TG3_FW_HDR_LEN;
  3019. fw_hdr++;
  3020. }
  3021. do {
  3022. u32 *fw_data = (u32 *)(fw_hdr + 1);
  3023. for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
  3024. write_op(tp, cpu_scratch_base +
  3025. (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
  3026. (i * sizeof(u32)),
  3027. be32_to_cpu(fw_data[i]));
  3028. total_len -= be32_to_cpu(fw_hdr->len);
  3029. /* Advance to next fragment */
  3030. fw_hdr = (struct tg3_firmware_hdr *)
  3031. ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
  3032. } while (total_len > 0);
  3033. err = 0;
  3034. out:
  3035. return err;
  3036. }
  3037. /* tp->lock is held. */
  3038. static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
  3039. {
  3040. int i;
  3041. const int iters = 5;
  3042. tw32(cpu_base + CPU_STATE, 0xffffffff);
  3043. tw32_f(cpu_base + CPU_PC, pc);
  3044. for (i = 0; i < iters; i++) {
  3045. if (tr32(cpu_base + CPU_PC) == pc)
  3046. break;
  3047. tw32(cpu_base + CPU_STATE, 0xffffffff);
  3048. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  3049. tw32_f(cpu_base + CPU_PC, pc);
  3050. udelay(1000);
  3051. }
  3052. return (i == iters) ? -EBUSY : 0;
  3053. }
  3054. /* tp->lock is held. */
  3055. static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
  3056. {
  3057. const struct tg3_firmware_hdr *fw_hdr;
  3058. int err;
  3059. fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
  3060. /* Firmware blob starts with version numbers, followed by
  3061. start address and length. We are setting complete length.
  3062. length = end_address_of_bss - start_address_of_text.
  3063. Remainder is the blob to be loaded contiguously
  3064. from start address. */
  3065. err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
  3066. RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
  3067. fw_hdr);
  3068. if (err)
  3069. return err;
  3070. err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  3071. TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  3072. fw_hdr);
  3073. if (err)
  3074. return err;
  3075. /* Now startup only the RX cpu. */
  3076. err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
  3077. be32_to_cpu(fw_hdr->base_addr));
  3078. if (err) {
  3079. netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
  3080. "should be %08x\n", __func__,
  3081. tr32(RX_CPU_BASE + CPU_PC),
  3082. be32_to_cpu(fw_hdr->base_addr));
  3083. return -ENODEV;
  3084. }
  3085. tg3_rxcpu_resume(tp);
  3086. return 0;
  3087. }
  3088. static int tg3_validate_rxcpu_state(struct tg3 *tp)
  3089. {
  3090. const int iters = 1000;
  3091. int i;
  3092. u32 val;
  3093. /* Wait for boot code to complete initialization and enter service
  3094. * loop. It is then safe to download service patches
  3095. */
  3096. for (i = 0; i < iters; i++) {
  3097. if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
  3098. break;
  3099. udelay(10);
  3100. }
  3101. if (i == iters) {
  3102. netdev_err(tp->dev, "Boot code not ready for service patches\n");
  3103. return -EBUSY;
  3104. }
  3105. val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
  3106. if (val & 0xff) {
  3107. netdev_warn(tp->dev,
  3108. "Other patches exist. Not downloading EEE patch\n");
  3109. return -EEXIST;
  3110. }
  3111. return 0;
  3112. }
  3113. /* tp->lock is held. */
  3114. static void tg3_load_57766_firmware(struct tg3 *tp)
  3115. {
  3116. struct tg3_firmware_hdr *fw_hdr;
  3117. if (!tg3_flag(tp, NO_NVRAM))
  3118. return;
  3119. if (tg3_validate_rxcpu_state(tp))
  3120. return;
  3121. if (!tp->fw)
  3122. return;
  3123. /* This firmware blob has a different format than older firmware
  3124. * releases as given below. The main difference is we have fragmented
  3125. * data to be written to non-contiguous locations.
  3126. *
  3127. * In the beginning we have a firmware header identical to other
  3128. * firmware which consists of version, base addr and length. The length
  3129. * here is unused and set to 0xffffffff.
  3130. *
  3131. * This is followed by a series of firmware fragments which are
  3132. * individually identical to previous firmware. i.e. they have the
  3133. * firmware header and followed by data for that fragment. The version
  3134. * field of the individual fragment header is unused.
  3135. */
  3136. fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
  3137. if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
  3138. return;
  3139. if (tg3_rxcpu_pause(tp))
  3140. return;
  3141. /* tg3_load_firmware_cpu() will always succeed for the 57766 */
  3142. tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
  3143. tg3_rxcpu_resume(tp);
  3144. }
  3145. /* tp->lock is held. */
  3146. static int tg3_load_tso_firmware(struct tg3 *tp)
  3147. {
  3148. const struct tg3_firmware_hdr *fw_hdr;
  3149. unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  3150. int err;
  3151. if (!tg3_flag(tp, FW_TSO))
  3152. return 0;
  3153. fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
  3154. /* Firmware blob starts with version numbers, followed by
  3155. start address and length. We are setting complete length.
  3156. length = end_address_of_bss - start_address_of_text.
  3157. Remainder is the blob to be loaded contiguously
  3158. from start address. */
  3159. cpu_scratch_size = tp->fw_len;
  3160. if (tg3_asic_rev(tp) == ASIC_REV_5705) {
  3161. cpu_base = RX_CPU_BASE;
  3162. cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
  3163. } else {
  3164. cpu_base = TX_CPU_BASE;
  3165. cpu_scratch_base = TX_CPU_SCRATCH_BASE;
  3166. cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
  3167. }
  3168. err = tg3_load_firmware_cpu(tp, cpu_base,
  3169. cpu_scratch_base, cpu_scratch_size,
  3170. fw_hdr);
  3171. if (err)
  3172. return err;
  3173. /* Now startup the cpu. */
  3174. err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
  3175. be32_to_cpu(fw_hdr->base_addr));
  3176. if (err) {
  3177. netdev_err(tp->dev,
  3178. "%s fails to set CPU PC, is %08x should be %08x\n",
  3179. __func__, tr32(cpu_base + CPU_PC),
  3180. be32_to_cpu(fw_hdr->base_addr));
  3181. return -ENODEV;
  3182. }
  3183. tg3_resume_cpu(tp, cpu_base);
  3184. return 0;
  3185. }
  3186. /* tp->lock is held. */
  3187. static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
  3188. {
  3189. u32 addr_high, addr_low;
  3190. int i;
  3191. addr_high = ((tp->dev->dev_addr[0] << 8) |
  3192. tp->dev->dev_addr[1]);
  3193. addr_low = ((tp->dev->dev_addr[2] << 24) |
  3194. (tp->dev->dev_addr[3] << 16) |
  3195. (tp->dev->dev_addr[4] << 8) |
  3196. (tp->dev->dev_addr[5] << 0));
  3197. for (i = 0; i < 4; i++) {
  3198. if (i == 1 && skip_mac_1)
  3199. continue;
  3200. tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
  3201. tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  3202. }
  3203. if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
  3204. tg3_asic_rev(tp) == ASIC_REV_5704) {
  3205. for (i = 0; i < 12; i++) {
  3206. tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
  3207. tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
  3208. }
  3209. }
  3210. addr_high = (tp->dev->dev_addr[0] +
  3211. tp->dev->dev_addr[1] +
  3212. tp->dev->dev_addr[2] +
  3213. tp->dev->dev_addr[3] +
  3214. tp->dev->dev_addr[4] +
  3215. tp->dev->dev_addr[5]) &
  3216. TX_BACKOFF_SEED_MASK;
  3217. tw32(MAC_TX_BACKOFF_SEED, addr_high);
  3218. }
  3219. static void tg3_enable_register_access(struct tg3 *tp)
  3220. {
  3221. /*
  3222. * Make sure register accesses (indirect or otherwise) will function
  3223. * correctly.
  3224. */
  3225. pci_write_config_dword(tp->pdev,
  3226. TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
  3227. }
  3228. static int tg3_power_up(struct tg3 *tp)
  3229. {
  3230. int err;
  3231. tg3_enable_register_access(tp);
  3232. err = pci_set_power_state(tp->pdev, PCI_D0);
  3233. if (!err) {
  3234. /* Switch out of Vaux if it is a NIC */
  3235. tg3_pwrsrc_switch_to_vmain(tp);
  3236. } else {
  3237. netdev_err(tp->dev, "Transition to D0 failed\n");
  3238. }
  3239. return err;
  3240. }
  3241. static int tg3_setup_phy(struct tg3 *, bool);
  3242. static int tg3_power_down_prepare(struct tg3 *tp)
  3243. {
  3244. u32 misc_host_ctrl;
  3245. bool device_should_wake, do_low_power;
  3246. tg3_enable_register_access(tp);
  3247. /* Restore the CLKREQ setting. */
  3248. if (tg3_flag(tp, CLKREQ_BUG))
  3249. pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
  3250. PCI_EXP_LNKCTL_CLKREQ_EN);
  3251. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  3252. tw32(TG3PCI_MISC_HOST_CTRL,
  3253. misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
  3254. device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
  3255. tg3_flag(tp, WOL_ENABLE);
  3256. if (tg3_flag(tp, USE_PHYLIB)) {
  3257. do_low_power = false;
  3258. if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
  3259. !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  3260. struct phy_device *phydev;
  3261. u32 phyid, advertising;
  3262. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  3263. tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
  3264. tp->link_config.speed = phydev->speed;
  3265. tp->link_config.duplex = phydev->duplex;
  3266. tp->link_config.autoneg = phydev->autoneg;
  3267. tp->link_config.advertising = phydev->advertising;
  3268. advertising = ADVERTISED_TP |
  3269. ADVERTISED_Pause |
  3270. ADVERTISED_Autoneg |
  3271. ADVERTISED_10baseT_Half;
  3272. if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
  3273. if (tg3_flag(tp, WOL_SPEED_100MB))
  3274. advertising |=
  3275. ADVERTISED_100baseT_Half |
  3276. ADVERTISED_100baseT_Full |
  3277. ADVERTISED_10baseT_Full;
  3278. else
  3279. advertising |= ADVERTISED_10baseT_Full;
  3280. }
  3281. phydev->advertising = advertising;
  3282. phy_start_aneg(phydev);
  3283. phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
  3284. if (phyid != PHY_ID_BCMAC131) {
  3285. phyid &= PHY_BCM_OUI_MASK;
  3286. if (phyid == PHY_BCM_OUI_1 ||
  3287. phyid == PHY_BCM_OUI_2 ||
  3288. phyid == PHY_BCM_OUI_3)
  3289. do_low_power = true;
  3290. }
  3291. }
  3292. } else {
  3293. do_low_power = true;
  3294. if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
  3295. tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
  3296. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  3297. tg3_setup_phy(tp, false);
  3298. }
  3299. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  3300. u32 val;
  3301. val = tr32(GRC_VCPU_EXT_CTRL);
  3302. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
  3303. } else if (!tg3_flag(tp, ENABLE_ASF)) {
  3304. int i;
  3305. u32 val;
  3306. for (i = 0; i < 200; i++) {
  3307. tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
  3308. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  3309. break;
  3310. msleep(1);
  3311. }
  3312. }
  3313. if (tg3_flag(tp, WOL_CAP))
  3314. tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
  3315. WOL_DRV_STATE_SHUTDOWN |
  3316. WOL_DRV_WOL |
  3317. WOL_SET_MAGIC_PKT);
  3318. if (device_should_wake) {
  3319. u32 mac_mode;
  3320. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  3321. if (do_low_power &&
  3322. !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  3323. tg3_phy_auxctl_write(tp,
  3324. MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
  3325. MII_TG3_AUXCTL_PCTL_WOL_EN |
  3326. MII_TG3_AUXCTL_PCTL_100TX_LPWR |
  3327. MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
  3328. udelay(40);
  3329. }
  3330. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  3331. mac_mode = MAC_MODE_PORT_MODE_GMII;
  3332. else if (tp->phy_flags &
  3333. TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
  3334. if (tp->link_config.active_speed == SPEED_1000)
  3335. mac_mode = MAC_MODE_PORT_MODE_GMII;
  3336. else
  3337. mac_mode = MAC_MODE_PORT_MODE_MII;
  3338. } else
  3339. mac_mode = MAC_MODE_PORT_MODE_MII;
  3340. mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
  3341. if (tg3_asic_rev(tp) == ASIC_REV_5700) {
  3342. u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
  3343. SPEED_100 : SPEED_10;
  3344. if (tg3_5700_link_polarity(tp, speed))
  3345. mac_mode |= MAC_MODE_LINK_POLARITY;
  3346. else
  3347. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  3348. }
  3349. } else {
  3350. mac_mode = MAC_MODE_PORT_MODE_TBI;
  3351. }
  3352. if (!tg3_flag(tp, 5750_PLUS))
  3353. tw32(MAC_LED_CTRL, tp->led_ctrl);
  3354. mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
  3355. if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
  3356. (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
  3357. mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
  3358. if (tg3_flag(tp, ENABLE_APE))
  3359. mac_mode |= MAC_MODE_APE_TX_EN |
  3360. MAC_MODE_APE_RX_EN |
  3361. MAC_MODE_TDE_ENABLE;
  3362. tw32_f(MAC_MODE, mac_mode);
  3363. udelay(100);
  3364. tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
  3365. udelay(10);
  3366. }
  3367. if (!tg3_flag(tp, WOL_SPEED_100MB) &&
  3368. (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  3369. tg3_asic_rev(tp) == ASIC_REV_5701)) {
  3370. u32 base_val;
  3371. base_val = tp->pci_clock_ctrl;
  3372. base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
  3373. CLOCK_CTRL_TXCLK_DISABLE);
  3374. tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
  3375. CLOCK_CTRL_PWRDOWN_PLL133, 40);
  3376. } else if (tg3_flag(tp, 5780_CLASS) ||
  3377. tg3_flag(tp, CPMU_PRESENT) ||
  3378. tg3_asic_rev(tp) == ASIC_REV_5906) {
  3379. /* do nothing */
  3380. } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
  3381. u32 newbits1, newbits2;
  3382. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  3383. tg3_asic_rev(tp) == ASIC_REV_5701) {
  3384. newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
  3385. CLOCK_CTRL_TXCLK_DISABLE |
  3386. CLOCK_CTRL_ALTCLK);
  3387. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  3388. } else if (tg3_flag(tp, 5705_PLUS)) {
  3389. newbits1 = CLOCK_CTRL_625_CORE;
  3390. newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
  3391. } else {
  3392. newbits1 = CLOCK_CTRL_ALTCLK;
  3393. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  3394. }
  3395. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
  3396. 40);
  3397. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
  3398. 40);
  3399. if (!tg3_flag(tp, 5705_PLUS)) {
  3400. u32 newbits3;
  3401. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  3402. tg3_asic_rev(tp) == ASIC_REV_5701) {
  3403. newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
  3404. CLOCK_CTRL_TXCLK_DISABLE |
  3405. CLOCK_CTRL_44MHZ_CORE);
  3406. } else {
  3407. newbits3 = CLOCK_CTRL_44MHZ_CORE;
  3408. }
  3409. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  3410. tp->pci_clock_ctrl | newbits3, 40);
  3411. }
  3412. }
  3413. if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
  3414. tg3_power_down_phy(tp, do_low_power);
  3415. tg3_frob_aux_power(tp, true);
  3416. /* Workaround for unstable PLL clock */
  3417. if ((!tg3_flag(tp, IS_SSB_CORE)) &&
  3418. ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
  3419. (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
  3420. u32 val = tr32(0x7d00);
  3421. val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  3422. tw32(0x7d00, val);
  3423. if (!tg3_flag(tp, ENABLE_ASF)) {
  3424. int err;
  3425. err = tg3_nvram_lock(tp);
  3426. tg3_halt_cpu(tp, RX_CPU_BASE);
  3427. if (!err)
  3428. tg3_nvram_unlock(tp);
  3429. }
  3430. }
  3431. tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
  3432. tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
  3433. return 0;
  3434. }
  3435. static void tg3_power_down(struct tg3 *tp)
  3436. {
  3437. tg3_power_down_prepare(tp);
  3438. pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
  3439. pci_set_power_state(tp->pdev, PCI_D3hot);
  3440. }
  3441. static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
  3442. {
  3443. switch (val & MII_TG3_AUX_STAT_SPDMASK) {
  3444. case MII_TG3_AUX_STAT_10HALF:
  3445. *speed = SPEED_10;
  3446. *duplex = DUPLEX_HALF;
  3447. break;
  3448. case MII_TG3_AUX_STAT_10FULL:
  3449. *speed = SPEED_10;
  3450. *duplex = DUPLEX_FULL;
  3451. break;
  3452. case MII_TG3_AUX_STAT_100HALF:
  3453. *speed = SPEED_100;
  3454. *duplex = DUPLEX_HALF;
  3455. break;
  3456. case MII_TG3_AUX_STAT_100FULL:
  3457. *speed = SPEED_100;
  3458. *duplex = DUPLEX_FULL;
  3459. break;
  3460. case MII_TG3_AUX_STAT_1000HALF:
  3461. *speed = SPEED_1000;
  3462. *duplex = DUPLEX_HALF;
  3463. break;
  3464. case MII_TG3_AUX_STAT_1000FULL:
  3465. *speed = SPEED_1000;
  3466. *duplex = DUPLEX_FULL;
  3467. break;
  3468. default:
  3469. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  3470. *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
  3471. SPEED_10;
  3472. *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
  3473. DUPLEX_HALF;
  3474. break;
  3475. }
  3476. *speed = SPEED_UNKNOWN;
  3477. *duplex = DUPLEX_UNKNOWN;
  3478. break;
  3479. }
  3480. }
  3481. static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
  3482. {
  3483. int err = 0;
  3484. u32 val, new_adv;
  3485. new_adv = ADVERTISE_CSMA;
  3486. new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
  3487. new_adv |= mii_advertise_flowctrl(flowctrl);
  3488. err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
  3489. if (err)
  3490. goto done;
  3491. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3492. new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
  3493. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  3494. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
  3495. new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
  3496. err = tg3_writephy(tp, MII_CTRL1000, new_adv);
  3497. if (err)
  3498. goto done;
  3499. }
  3500. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
  3501. goto done;
  3502. tw32(TG3_CPMU_EEE_MODE,
  3503. tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
  3504. err = tg3_phy_toggle_auxctl_smdsp(tp, true);
  3505. if (!err) {
  3506. u32 err2;
  3507. val = 0;
  3508. /* Advertise 100-BaseTX EEE ability */
  3509. if (advertise & ADVERTISED_100baseT_Full)
  3510. val |= MDIO_AN_EEE_ADV_100TX;
  3511. /* Advertise 1000-BaseT EEE ability */
  3512. if (advertise & ADVERTISED_1000baseT_Full)
  3513. val |= MDIO_AN_EEE_ADV_1000T;
  3514. if (!tp->eee.eee_enabled) {
  3515. val = 0;
  3516. tp->eee.advertised = 0;
  3517. } else {
  3518. tp->eee.advertised = advertise &
  3519. (ADVERTISED_100baseT_Full |
  3520. ADVERTISED_1000baseT_Full);
  3521. }
  3522. err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  3523. if (err)
  3524. val = 0;
  3525. switch (tg3_asic_rev(tp)) {
  3526. case ASIC_REV_5717:
  3527. case ASIC_REV_57765:
  3528. case ASIC_REV_57766:
  3529. case ASIC_REV_5719:
  3530. /* If we advertised any eee advertisements above... */
  3531. if (val)
  3532. val = MII_TG3_DSP_TAP26_ALNOKO |
  3533. MII_TG3_DSP_TAP26_RMRXSTO |
  3534. MII_TG3_DSP_TAP26_OPCSINPT;
  3535. tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
  3536. /* Fall through */
  3537. case ASIC_REV_5720:
  3538. case ASIC_REV_5762:
  3539. if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
  3540. tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
  3541. MII_TG3_DSP_CH34TP2_HIBW01);
  3542. }
  3543. err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
  3544. if (!err)
  3545. err = err2;
  3546. }
  3547. done:
  3548. return err;
  3549. }
  3550. static void tg3_phy_copper_begin(struct tg3 *tp)
  3551. {
  3552. if (tp->link_config.autoneg == AUTONEG_ENABLE ||
  3553. (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  3554. u32 adv, fc;
  3555. if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
  3556. !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
  3557. adv = ADVERTISED_10baseT_Half |
  3558. ADVERTISED_10baseT_Full;
  3559. if (tg3_flag(tp, WOL_SPEED_100MB))
  3560. adv |= ADVERTISED_100baseT_Half |
  3561. ADVERTISED_100baseT_Full;
  3562. if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK)
  3563. adv |= ADVERTISED_1000baseT_Half |
  3564. ADVERTISED_1000baseT_Full;
  3565. fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
  3566. } else {
  3567. adv = tp->link_config.advertising;
  3568. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  3569. adv &= ~(ADVERTISED_1000baseT_Half |
  3570. ADVERTISED_1000baseT_Full);
  3571. fc = tp->link_config.flowctrl;
  3572. }
  3573. tg3_phy_autoneg_cfg(tp, adv, fc);
  3574. if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
  3575. (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
  3576. /* Normally during power down we want to autonegotiate
  3577. * the lowest possible speed for WOL. However, to avoid
  3578. * link flap, we leave it untouched.
  3579. */
  3580. return;
  3581. }
  3582. tg3_writephy(tp, MII_BMCR,
  3583. BMCR_ANENABLE | BMCR_ANRESTART);
  3584. } else {
  3585. int i;
  3586. u32 bmcr, orig_bmcr;
  3587. tp->link_config.active_speed = tp->link_config.speed;
  3588. tp->link_config.active_duplex = tp->link_config.duplex;
  3589. if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  3590. /* With autoneg disabled, 5715 only links up when the
  3591. * advertisement register has the configured speed
  3592. * enabled.
  3593. */
  3594. tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
  3595. }
  3596. bmcr = 0;
  3597. switch (tp->link_config.speed) {
  3598. default:
  3599. case SPEED_10:
  3600. break;
  3601. case SPEED_100:
  3602. bmcr |= BMCR_SPEED100;
  3603. break;
  3604. case SPEED_1000:
  3605. bmcr |= BMCR_SPEED1000;
  3606. break;
  3607. }
  3608. if (tp->link_config.duplex == DUPLEX_FULL)
  3609. bmcr |= BMCR_FULLDPLX;
  3610. if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
  3611. (bmcr != orig_bmcr)) {
  3612. tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
  3613. for (i = 0; i < 1500; i++) {
  3614. u32 tmp;
  3615. udelay(10);
  3616. if (tg3_readphy(tp, MII_BMSR, &tmp) ||
  3617. tg3_readphy(tp, MII_BMSR, &tmp))
  3618. continue;
  3619. if (!(tmp & BMSR_LSTATUS)) {
  3620. udelay(40);
  3621. break;
  3622. }
  3623. }
  3624. tg3_writephy(tp, MII_BMCR, bmcr);
  3625. udelay(40);
  3626. }
  3627. }
  3628. }
  3629. static int tg3_phy_pull_config(struct tg3 *tp)
  3630. {
  3631. int err;
  3632. u32 val;
  3633. err = tg3_readphy(tp, MII_BMCR, &val);
  3634. if (err)
  3635. goto done;
  3636. if (!(val & BMCR_ANENABLE)) {
  3637. tp->link_config.autoneg = AUTONEG_DISABLE;
  3638. tp->link_config.advertising = 0;
  3639. tg3_flag_clear(tp, PAUSE_AUTONEG);
  3640. err = -EIO;
  3641. switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
  3642. case 0:
  3643. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  3644. goto done;
  3645. tp->link_config.speed = SPEED_10;
  3646. break;
  3647. case BMCR_SPEED100:
  3648. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  3649. goto done;
  3650. tp->link_config.speed = SPEED_100;
  3651. break;
  3652. case BMCR_SPEED1000:
  3653. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3654. tp->link_config.speed = SPEED_1000;
  3655. break;
  3656. }
  3657. /* Fall through */
  3658. default:
  3659. goto done;
  3660. }
  3661. if (val & BMCR_FULLDPLX)
  3662. tp->link_config.duplex = DUPLEX_FULL;
  3663. else
  3664. tp->link_config.duplex = DUPLEX_HALF;
  3665. tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
  3666. err = 0;
  3667. goto done;
  3668. }
  3669. tp->link_config.autoneg = AUTONEG_ENABLE;
  3670. tp->link_config.advertising = ADVERTISED_Autoneg;
  3671. tg3_flag_set(tp, PAUSE_AUTONEG);
  3672. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  3673. u32 adv;
  3674. err = tg3_readphy(tp, MII_ADVERTISE, &val);
  3675. if (err)
  3676. goto done;
  3677. adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
  3678. tp->link_config.advertising |= adv | ADVERTISED_TP;
  3679. tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
  3680. } else {
  3681. tp->link_config.advertising |= ADVERTISED_FIBRE;
  3682. }
  3683. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3684. u32 adv;
  3685. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  3686. err = tg3_readphy(tp, MII_CTRL1000, &val);
  3687. if (err)
  3688. goto done;
  3689. adv = mii_ctrl1000_to_ethtool_adv_t(val);
  3690. } else {
  3691. err = tg3_readphy(tp, MII_ADVERTISE, &val);
  3692. if (err)
  3693. goto done;
  3694. adv = tg3_decode_flowctrl_1000X(val);
  3695. tp->link_config.flowctrl = adv;
  3696. val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
  3697. adv = mii_adv_to_ethtool_adv_x(val);
  3698. }
  3699. tp->link_config.advertising |= adv;
  3700. }
  3701. done:
  3702. return err;
  3703. }
  3704. static int tg3_init_5401phy_dsp(struct tg3 *tp)
  3705. {
  3706. int err;
  3707. /* Turn off tap power management. */
  3708. /* Set Extended packet length bit */
  3709. err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
  3710. err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
  3711. err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
  3712. err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
  3713. err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
  3714. err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
  3715. udelay(40);
  3716. return err;
  3717. }
  3718. static bool tg3_phy_eee_config_ok(struct tg3 *tp)
  3719. {
  3720. struct ethtool_eee eee;
  3721. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
  3722. return true;
  3723. tg3_eee_pull_config(tp, &eee);
  3724. if (tp->eee.eee_enabled) {
  3725. if (tp->eee.advertised != eee.advertised ||
  3726. tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
  3727. tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
  3728. return false;
  3729. } else {
  3730. /* EEE is disabled but we're advertising */
  3731. if (eee.advertised)
  3732. return false;
  3733. }
  3734. return true;
  3735. }
  3736. static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
  3737. {
  3738. u32 advmsk, tgtadv, advertising;
  3739. advertising = tp->link_config.advertising;
  3740. tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
  3741. advmsk = ADVERTISE_ALL;
  3742. if (tp->link_config.active_duplex == DUPLEX_FULL) {
  3743. tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
  3744. advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3745. }
  3746. if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
  3747. return false;
  3748. if ((*lcladv & advmsk) != tgtadv)
  3749. return false;
  3750. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3751. u32 tg3_ctrl;
  3752. tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
  3753. if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
  3754. return false;
  3755. if (tgtadv &&
  3756. (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  3757. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
  3758. tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
  3759. tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
  3760. CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
  3761. } else {
  3762. tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
  3763. }
  3764. if (tg3_ctrl != tgtadv)
  3765. return false;
  3766. }
  3767. return true;
  3768. }
  3769. static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
  3770. {
  3771. u32 lpeth = 0;
  3772. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3773. u32 val;
  3774. if (tg3_readphy(tp, MII_STAT1000, &val))
  3775. return false;
  3776. lpeth = mii_stat1000_to_ethtool_lpa_t(val);
  3777. }
  3778. if (tg3_readphy(tp, MII_LPA, rmtadv))
  3779. return false;
  3780. lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
  3781. tp->link_config.rmt_adv = lpeth;
  3782. return true;
  3783. }
  3784. static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
  3785. {
  3786. if (curr_link_up != tp->link_up) {
  3787. if (curr_link_up) {
  3788. netif_carrier_on(tp->dev);
  3789. } else {
  3790. netif_carrier_off(tp->dev);
  3791. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  3792. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3793. }
  3794. tg3_link_report(tp);
  3795. return true;
  3796. }
  3797. return false;
  3798. }
  3799. static void tg3_clear_mac_status(struct tg3 *tp)
  3800. {
  3801. tw32(MAC_EVENT, 0);
  3802. tw32_f(MAC_STATUS,
  3803. MAC_STATUS_SYNC_CHANGED |
  3804. MAC_STATUS_CFG_CHANGED |
  3805. MAC_STATUS_MI_COMPLETION |
  3806. MAC_STATUS_LNKSTATE_CHANGED);
  3807. udelay(40);
  3808. }
  3809. static void tg3_setup_eee(struct tg3 *tp)
  3810. {
  3811. u32 val;
  3812. val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
  3813. TG3_CPMU_EEE_LNKIDL_UART_IDL;
  3814. if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
  3815. val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
  3816. tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
  3817. tw32_f(TG3_CPMU_EEE_CTRL,
  3818. TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
  3819. val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
  3820. (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
  3821. TG3_CPMU_EEEMD_LPI_IN_RX |
  3822. TG3_CPMU_EEEMD_EEE_ENABLE;
  3823. if (tg3_asic_rev(tp) != ASIC_REV_5717)
  3824. val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
  3825. if (tg3_flag(tp, ENABLE_APE))
  3826. val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
  3827. tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
  3828. tw32_f(TG3_CPMU_EEE_DBTMR1,
  3829. TG3_CPMU_DBTMR1_PCIEXIT_2047US |
  3830. (tp->eee.tx_lpi_timer & 0xffff));
  3831. tw32_f(TG3_CPMU_EEE_DBTMR2,
  3832. TG3_CPMU_DBTMR2_APE_TX_2047US |
  3833. TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
  3834. }
  3835. static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
  3836. {
  3837. bool current_link_up;
  3838. u32 bmsr, val;
  3839. u32 lcl_adv, rmt_adv;
  3840. u16 current_speed;
  3841. u8 current_duplex;
  3842. int i, err;
  3843. tg3_clear_mac_status(tp);
  3844. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  3845. tw32_f(MAC_MI_MODE,
  3846. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  3847. udelay(80);
  3848. }
  3849. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
  3850. /* Some third-party PHYs need to be reset on link going
  3851. * down.
  3852. */
  3853. if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
  3854. tg3_asic_rev(tp) == ASIC_REV_5704 ||
  3855. tg3_asic_rev(tp) == ASIC_REV_5705) &&
  3856. tp->link_up) {
  3857. tg3_readphy(tp, MII_BMSR, &bmsr);
  3858. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  3859. !(bmsr & BMSR_LSTATUS))
  3860. force_reset = true;
  3861. }
  3862. if (force_reset)
  3863. tg3_phy_reset(tp);
  3864. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  3865. tg3_readphy(tp, MII_BMSR, &bmsr);
  3866. if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
  3867. !tg3_flag(tp, INIT_COMPLETE))
  3868. bmsr = 0;
  3869. if (!(bmsr & BMSR_LSTATUS)) {
  3870. err = tg3_init_5401phy_dsp(tp);
  3871. if (err)
  3872. return err;
  3873. tg3_readphy(tp, MII_BMSR, &bmsr);
  3874. for (i = 0; i < 1000; i++) {
  3875. udelay(10);
  3876. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  3877. (bmsr & BMSR_LSTATUS)) {
  3878. udelay(40);
  3879. break;
  3880. }
  3881. }
  3882. if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
  3883. TG3_PHY_REV_BCM5401_B0 &&
  3884. !(bmsr & BMSR_LSTATUS) &&
  3885. tp->link_config.active_speed == SPEED_1000) {
  3886. err = tg3_phy_reset(tp);
  3887. if (!err)
  3888. err = tg3_init_5401phy_dsp(tp);
  3889. if (err)
  3890. return err;
  3891. }
  3892. }
  3893. } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  3894. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
  3895. /* 5701 {A0,B0} CRC bug workaround */
  3896. tg3_writephy(tp, 0x15, 0x0a75);
  3897. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
  3898. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  3899. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
  3900. }
  3901. /* Clear pending interrupts... */
  3902. tg3_readphy(tp, MII_TG3_ISTAT, &val);
  3903. tg3_readphy(tp, MII_TG3_ISTAT, &val);
  3904. if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
  3905. tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
  3906. else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
  3907. tg3_writephy(tp, MII_TG3_IMASK, ~0);
  3908. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  3909. tg3_asic_rev(tp) == ASIC_REV_5701) {
  3910. if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
  3911. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  3912. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  3913. else
  3914. tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
  3915. }
  3916. current_link_up = false;
  3917. current_speed = SPEED_UNKNOWN;
  3918. current_duplex = DUPLEX_UNKNOWN;
  3919. tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
  3920. tp->link_config.rmt_adv = 0;
  3921. if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
  3922. err = tg3_phy_auxctl_read(tp,
  3923. MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
  3924. &val);
  3925. if (!err && !(val & (1 << 10))) {
  3926. tg3_phy_auxctl_write(tp,
  3927. MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
  3928. val | (1 << 10));
  3929. goto relink;
  3930. }
  3931. }
  3932. bmsr = 0;
  3933. for (i = 0; i < 100; i++) {
  3934. tg3_readphy(tp, MII_BMSR, &bmsr);
  3935. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  3936. (bmsr & BMSR_LSTATUS))
  3937. break;
  3938. udelay(40);
  3939. }
  3940. if (bmsr & BMSR_LSTATUS) {
  3941. u32 aux_stat, bmcr;
  3942. tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
  3943. for (i = 0; i < 2000; i++) {
  3944. udelay(10);
  3945. if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
  3946. aux_stat)
  3947. break;
  3948. }
  3949. tg3_aux_stat_to_speed_duplex(tp, aux_stat,
  3950. &current_speed,
  3951. &current_duplex);
  3952. bmcr = 0;
  3953. for (i = 0; i < 200; i++) {
  3954. tg3_readphy(tp, MII_BMCR, &bmcr);
  3955. if (tg3_readphy(tp, MII_BMCR, &bmcr))
  3956. continue;
  3957. if (bmcr && bmcr != 0x7fff)
  3958. break;
  3959. udelay(10);
  3960. }
  3961. lcl_adv = 0;
  3962. rmt_adv = 0;
  3963. tp->link_config.active_speed = current_speed;
  3964. tp->link_config.active_duplex = current_duplex;
  3965. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  3966. bool eee_config_ok = tg3_phy_eee_config_ok(tp);
  3967. if ((bmcr & BMCR_ANENABLE) &&
  3968. eee_config_ok &&
  3969. tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
  3970. tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
  3971. current_link_up = true;
  3972. /* EEE settings changes take effect only after a phy
  3973. * reset. If we have skipped a reset due to Link Flap
  3974. * Avoidance being enabled, do it now.
  3975. */
  3976. if (!eee_config_ok &&
  3977. (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
  3978. !force_reset) {
  3979. tg3_setup_eee(tp);
  3980. tg3_phy_reset(tp);
  3981. }
  3982. } else {
  3983. if (!(bmcr & BMCR_ANENABLE) &&
  3984. tp->link_config.speed == current_speed &&
  3985. tp->link_config.duplex == current_duplex) {
  3986. current_link_up = true;
  3987. }
  3988. }
  3989. if (current_link_up &&
  3990. tp->link_config.active_duplex == DUPLEX_FULL) {
  3991. u32 reg, bit;
  3992. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  3993. reg = MII_TG3_FET_GEN_STAT;
  3994. bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
  3995. } else {
  3996. reg = MII_TG3_EXT_STAT;
  3997. bit = MII_TG3_EXT_STAT_MDIX;
  3998. }
  3999. if (!tg3_readphy(tp, reg, &val) && (val & bit))
  4000. tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
  4001. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  4002. }
  4003. }
  4004. relink:
  4005. if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  4006. tg3_phy_copper_begin(tp);
  4007. if (tg3_flag(tp, ROBOSWITCH)) {
  4008. current_link_up = true;
  4009. /* FIXME: when BCM5325 switch is used use 100 MBit/s */
  4010. current_speed = SPEED_1000;
  4011. current_duplex = DUPLEX_FULL;
  4012. tp->link_config.active_speed = current_speed;
  4013. tp->link_config.active_duplex = current_duplex;
  4014. }
  4015. tg3_readphy(tp, MII_BMSR, &bmsr);
  4016. if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
  4017. (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
  4018. current_link_up = true;
  4019. }
  4020. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  4021. if (current_link_up) {
  4022. if (tp->link_config.active_speed == SPEED_100 ||
  4023. tp->link_config.active_speed == SPEED_10)
  4024. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  4025. else
  4026. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  4027. } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  4028. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  4029. else
  4030. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  4031. /* In order for the 5750 core in BCM4785 chip to work properly
  4032. * in RGMII mode, the Led Control Register must be set up.
  4033. */
  4034. if (tg3_flag(tp, RGMII_MODE)) {
  4035. u32 led_ctrl = tr32(MAC_LED_CTRL);
  4036. led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
  4037. if (tp->link_config.active_speed == SPEED_10)
  4038. led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
  4039. else if (tp->link_config.active_speed == SPEED_100)
  4040. led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
  4041. LED_CTRL_100MBPS_ON);
  4042. else if (tp->link_config.active_speed == SPEED_1000)
  4043. led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
  4044. LED_CTRL_1000MBPS_ON);
  4045. tw32(MAC_LED_CTRL, led_ctrl);
  4046. udelay(40);
  4047. }
  4048. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  4049. if (tp->link_config.active_duplex == DUPLEX_HALF)
  4050. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  4051. if (tg3_asic_rev(tp) == ASIC_REV_5700) {
  4052. if (current_link_up &&
  4053. tg3_5700_link_polarity(tp, tp->link_config.active_speed))
  4054. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  4055. else
  4056. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  4057. }
  4058. /* ??? Without this setting Netgear GA302T PHY does not
  4059. * ??? send/receive packets...
  4060. */
  4061. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
  4062. tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
  4063. tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
  4064. tw32_f(MAC_MI_MODE, tp->mi_mode);
  4065. udelay(80);
  4066. }
  4067. tw32_f(MAC_MODE, tp->mac_mode);
  4068. udelay(40);
  4069. tg3_phy_eee_adjust(tp, current_link_up);
  4070. if (tg3_flag(tp, USE_LINKCHG_REG)) {
  4071. /* Polled via timer. */
  4072. tw32_f(MAC_EVENT, 0);
  4073. } else {
  4074. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4075. }
  4076. udelay(40);
  4077. if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
  4078. current_link_up &&
  4079. tp->link_config.active_speed == SPEED_1000 &&
  4080. (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
  4081. udelay(120);
  4082. tw32_f(MAC_STATUS,
  4083. (MAC_STATUS_SYNC_CHANGED |
  4084. MAC_STATUS_CFG_CHANGED));
  4085. udelay(40);
  4086. tg3_write_mem(tp,
  4087. NIC_SRAM_FIRMWARE_MBOX,
  4088. NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
  4089. }
  4090. /* Prevent send BD corruption. */
  4091. if (tg3_flag(tp, CLKREQ_BUG)) {
  4092. if (tp->link_config.active_speed == SPEED_100 ||
  4093. tp->link_config.active_speed == SPEED_10)
  4094. pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
  4095. PCI_EXP_LNKCTL_CLKREQ_EN);
  4096. else
  4097. pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
  4098. PCI_EXP_LNKCTL_CLKREQ_EN);
  4099. }
  4100. tg3_test_and_report_link_chg(tp, current_link_up);
  4101. return 0;
  4102. }
  4103. struct tg3_fiber_aneginfo {
  4104. int state;
  4105. #define ANEG_STATE_UNKNOWN 0
  4106. #define ANEG_STATE_AN_ENABLE 1
  4107. #define ANEG_STATE_RESTART_INIT 2
  4108. #define ANEG_STATE_RESTART 3
  4109. #define ANEG_STATE_DISABLE_LINK_OK 4
  4110. #define ANEG_STATE_ABILITY_DETECT_INIT 5
  4111. #define ANEG_STATE_ABILITY_DETECT 6
  4112. #define ANEG_STATE_ACK_DETECT_INIT 7
  4113. #define ANEG_STATE_ACK_DETECT 8
  4114. #define ANEG_STATE_COMPLETE_ACK_INIT 9
  4115. #define ANEG_STATE_COMPLETE_ACK 10
  4116. #define ANEG_STATE_IDLE_DETECT_INIT 11
  4117. #define ANEG_STATE_IDLE_DETECT 12
  4118. #define ANEG_STATE_LINK_OK 13
  4119. #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
  4120. #define ANEG_STATE_NEXT_PAGE_WAIT 15
  4121. u32 flags;
  4122. #define MR_AN_ENABLE 0x00000001
  4123. #define MR_RESTART_AN 0x00000002
  4124. #define MR_AN_COMPLETE 0x00000004
  4125. #define MR_PAGE_RX 0x00000008
  4126. #define MR_NP_LOADED 0x00000010
  4127. #define MR_TOGGLE_TX 0x00000020
  4128. #define MR_LP_ADV_FULL_DUPLEX 0x00000040
  4129. #define MR_LP_ADV_HALF_DUPLEX 0x00000080
  4130. #define MR_LP_ADV_SYM_PAUSE 0x00000100
  4131. #define MR_LP_ADV_ASYM_PAUSE 0x00000200
  4132. #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
  4133. #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
  4134. #define MR_LP_ADV_NEXT_PAGE 0x00001000
  4135. #define MR_TOGGLE_RX 0x00002000
  4136. #define MR_NP_RX 0x00004000
  4137. #define MR_LINK_OK 0x80000000
  4138. unsigned long link_time, cur_time;
  4139. u32 ability_match_cfg;
  4140. int ability_match_count;
  4141. char ability_match, idle_match, ack_match;
  4142. u32 txconfig, rxconfig;
  4143. #define ANEG_CFG_NP 0x00000080
  4144. #define ANEG_CFG_ACK 0x00000040
  4145. #define ANEG_CFG_RF2 0x00000020
  4146. #define ANEG_CFG_RF1 0x00000010
  4147. #define ANEG_CFG_PS2 0x00000001
  4148. #define ANEG_CFG_PS1 0x00008000
  4149. #define ANEG_CFG_HD 0x00004000
  4150. #define ANEG_CFG_FD 0x00002000
  4151. #define ANEG_CFG_INVAL 0x00001f06
  4152. };
  4153. #define ANEG_OK 0
  4154. #define ANEG_DONE 1
  4155. #define ANEG_TIMER_ENAB 2
  4156. #define ANEG_FAILED -1
  4157. #define ANEG_STATE_SETTLE_TIME 10000
  4158. static int tg3_fiber_aneg_smachine(struct tg3 *tp,
  4159. struct tg3_fiber_aneginfo *ap)
  4160. {
  4161. u16 flowctrl;
  4162. unsigned long delta;
  4163. u32 rx_cfg_reg;
  4164. int ret;
  4165. if (ap->state == ANEG_STATE_UNKNOWN) {
  4166. ap->rxconfig = 0;
  4167. ap->link_time = 0;
  4168. ap->cur_time = 0;
  4169. ap->ability_match_cfg = 0;
  4170. ap->ability_match_count = 0;
  4171. ap->ability_match = 0;
  4172. ap->idle_match = 0;
  4173. ap->ack_match = 0;
  4174. }
  4175. ap->cur_time++;
  4176. if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
  4177. rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
  4178. if (rx_cfg_reg != ap->ability_match_cfg) {
  4179. ap->ability_match_cfg = rx_cfg_reg;
  4180. ap->ability_match = 0;
  4181. ap->ability_match_count = 0;
  4182. } else {
  4183. if (++ap->ability_match_count > 1) {
  4184. ap->ability_match = 1;
  4185. ap->ability_match_cfg = rx_cfg_reg;
  4186. }
  4187. }
  4188. if (rx_cfg_reg & ANEG_CFG_ACK)
  4189. ap->ack_match = 1;
  4190. else
  4191. ap->ack_match = 0;
  4192. ap->idle_match = 0;
  4193. } else {
  4194. ap->idle_match = 1;
  4195. ap->ability_match_cfg = 0;
  4196. ap->ability_match_count = 0;
  4197. ap->ability_match = 0;
  4198. ap->ack_match = 0;
  4199. rx_cfg_reg = 0;
  4200. }
  4201. ap->rxconfig = rx_cfg_reg;
  4202. ret = ANEG_OK;
  4203. switch (ap->state) {
  4204. case ANEG_STATE_UNKNOWN:
  4205. if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
  4206. ap->state = ANEG_STATE_AN_ENABLE;
  4207. /* fallthru */
  4208. case ANEG_STATE_AN_ENABLE:
  4209. ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
  4210. if (ap->flags & MR_AN_ENABLE) {
  4211. ap->link_time = 0;
  4212. ap->cur_time = 0;
  4213. ap->ability_match_cfg = 0;
  4214. ap->ability_match_count = 0;
  4215. ap->ability_match = 0;
  4216. ap->idle_match = 0;
  4217. ap->ack_match = 0;
  4218. ap->state = ANEG_STATE_RESTART_INIT;
  4219. } else {
  4220. ap->state = ANEG_STATE_DISABLE_LINK_OK;
  4221. }
  4222. break;
  4223. case ANEG_STATE_RESTART_INIT:
  4224. ap->link_time = ap->cur_time;
  4225. ap->flags &= ~(MR_NP_LOADED);
  4226. ap->txconfig = 0;
  4227. tw32(MAC_TX_AUTO_NEG, 0);
  4228. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  4229. tw32_f(MAC_MODE, tp->mac_mode);
  4230. udelay(40);
  4231. ret = ANEG_TIMER_ENAB;
  4232. ap->state = ANEG_STATE_RESTART;
  4233. /* fallthru */
  4234. case ANEG_STATE_RESTART:
  4235. delta = ap->cur_time - ap->link_time;
  4236. if (delta > ANEG_STATE_SETTLE_TIME)
  4237. ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
  4238. else
  4239. ret = ANEG_TIMER_ENAB;
  4240. break;
  4241. case ANEG_STATE_DISABLE_LINK_OK:
  4242. ret = ANEG_DONE;
  4243. break;
  4244. case ANEG_STATE_ABILITY_DETECT_INIT:
  4245. ap->flags &= ~(MR_TOGGLE_TX);
  4246. ap->txconfig = ANEG_CFG_FD;
  4247. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  4248. if (flowctrl & ADVERTISE_1000XPAUSE)
  4249. ap->txconfig |= ANEG_CFG_PS1;
  4250. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  4251. ap->txconfig |= ANEG_CFG_PS2;
  4252. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  4253. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  4254. tw32_f(MAC_MODE, tp->mac_mode);
  4255. udelay(40);
  4256. ap->state = ANEG_STATE_ABILITY_DETECT;
  4257. break;
  4258. case ANEG_STATE_ABILITY_DETECT:
  4259. if (ap->ability_match != 0 && ap->rxconfig != 0)
  4260. ap->state = ANEG_STATE_ACK_DETECT_INIT;
  4261. break;
  4262. case ANEG_STATE_ACK_DETECT_INIT:
  4263. ap->txconfig |= ANEG_CFG_ACK;
  4264. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  4265. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  4266. tw32_f(MAC_MODE, tp->mac_mode);
  4267. udelay(40);
  4268. ap->state = ANEG_STATE_ACK_DETECT;
  4269. /* fallthru */
  4270. case ANEG_STATE_ACK_DETECT:
  4271. if (ap->ack_match != 0) {
  4272. if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
  4273. (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
  4274. ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
  4275. } else {
  4276. ap->state = ANEG_STATE_AN_ENABLE;
  4277. }
  4278. } else if (ap->ability_match != 0 &&
  4279. ap->rxconfig == 0) {
  4280. ap->state = ANEG_STATE_AN_ENABLE;
  4281. }
  4282. break;
  4283. case ANEG_STATE_COMPLETE_ACK_INIT:
  4284. if (ap->rxconfig & ANEG_CFG_INVAL) {
  4285. ret = ANEG_FAILED;
  4286. break;
  4287. }
  4288. ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
  4289. MR_LP_ADV_HALF_DUPLEX |
  4290. MR_LP_ADV_SYM_PAUSE |
  4291. MR_LP_ADV_ASYM_PAUSE |
  4292. MR_LP_ADV_REMOTE_FAULT1 |
  4293. MR_LP_ADV_REMOTE_FAULT2 |
  4294. MR_LP_ADV_NEXT_PAGE |
  4295. MR_TOGGLE_RX |
  4296. MR_NP_RX);
  4297. if (ap->rxconfig & ANEG_CFG_FD)
  4298. ap->flags |= MR_LP_ADV_FULL_DUPLEX;
  4299. if (ap->rxconfig & ANEG_CFG_HD)
  4300. ap->flags |= MR_LP_ADV_HALF_DUPLEX;
  4301. if (ap->rxconfig & ANEG_CFG_PS1)
  4302. ap->flags |= MR_LP_ADV_SYM_PAUSE;
  4303. if (ap->rxconfig & ANEG_CFG_PS2)
  4304. ap->flags |= MR_LP_ADV_ASYM_PAUSE;
  4305. if (ap->rxconfig & ANEG_CFG_RF1)
  4306. ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
  4307. if (ap->rxconfig & ANEG_CFG_RF2)
  4308. ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
  4309. if (ap->rxconfig & ANEG_CFG_NP)
  4310. ap->flags |= MR_LP_ADV_NEXT_PAGE;
  4311. ap->link_time = ap->cur_time;
  4312. ap->flags ^= (MR_TOGGLE_TX);
  4313. if (ap->rxconfig & 0x0008)
  4314. ap->flags |= MR_TOGGLE_RX;
  4315. if (ap->rxconfig & ANEG_CFG_NP)
  4316. ap->flags |= MR_NP_RX;
  4317. ap->flags |= MR_PAGE_RX;
  4318. ap->state = ANEG_STATE_COMPLETE_ACK;
  4319. ret = ANEG_TIMER_ENAB;
  4320. break;
  4321. case ANEG_STATE_COMPLETE_ACK:
  4322. if (ap->ability_match != 0 &&
  4323. ap->rxconfig == 0) {
  4324. ap->state = ANEG_STATE_AN_ENABLE;
  4325. break;
  4326. }
  4327. delta = ap->cur_time - ap->link_time;
  4328. if (delta > ANEG_STATE_SETTLE_TIME) {
  4329. if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
  4330. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  4331. } else {
  4332. if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
  4333. !(ap->flags & MR_NP_RX)) {
  4334. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  4335. } else {
  4336. ret = ANEG_FAILED;
  4337. }
  4338. }
  4339. }
  4340. break;
  4341. case ANEG_STATE_IDLE_DETECT_INIT:
  4342. ap->link_time = ap->cur_time;
  4343. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  4344. tw32_f(MAC_MODE, tp->mac_mode);
  4345. udelay(40);
  4346. ap->state = ANEG_STATE_IDLE_DETECT;
  4347. ret = ANEG_TIMER_ENAB;
  4348. break;
  4349. case ANEG_STATE_IDLE_DETECT:
  4350. if (ap->ability_match != 0 &&
  4351. ap->rxconfig == 0) {
  4352. ap->state = ANEG_STATE_AN_ENABLE;
  4353. break;
  4354. }
  4355. delta = ap->cur_time - ap->link_time;
  4356. if (delta > ANEG_STATE_SETTLE_TIME) {
  4357. /* XXX another gem from the Broadcom driver :( */
  4358. ap->state = ANEG_STATE_LINK_OK;
  4359. }
  4360. break;
  4361. case ANEG_STATE_LINK_OK:
  4362. ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
  4363. ret = ANEG_DONE;
  4364. break;
  4365. case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
  4366. /* ??? unimplemented */
  4367. break;
  4368. case ANEG_STATE_NEXT_PAGE_WAIT:
  4369. /* ??? unimplemented */
  4370. break;
  4371. default:
  4372. ret = ANEG_FAILED;
  4373. break;
  4374. }
  4375. return ret;
  4376. }
  4377. static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
  4378. {
  4379. int res = 0;
  4380. struct tg3_fiber_aneginfo aninfo;
  4381. int status = ANEG_FAILED;
  4382. unsigned int tick;
  4383. u32 tmp;
  4384. tw32_f(MAC_TX_AUTO_NEG, 0);
  4385. tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  4386. tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
  4387. udelay(40);
  4388. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
  4389. udelay(40);
  4390. memset(&aninfo, 0, sizeof(aninfo));
  4391. aninfo.flags |= MR_AN_ENABLE;
  4392. aninfo.state = ANEG_STATE_UNKNOWN;
  4393. aninfo.cur_time = 0;
  4394. tick = 0;
  4395. while (++tick < 195000) {
  4396. status = tg3_fiber_aneg_smachine(tp, &aninfo);
  4397. if (status == ANEG_DONE || status == ANEG_FAILED)
  4398. break;
  4399. udelay(1);
  4400. }
  4401. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  4402. tw32_f(MAC_MODE, tp->mac_mode);
  4403. udelay(40);
  4404. *txflags = aninfo.txconfig;
  4405. *rxflags = aninfo.flags;
  4406. if (status == ANEG_DONE &&
  4407. (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
  4408. MR_LP_ADV_FULL_DUPLEX)))
  4409. res = 1;
  4410. return res;
  4411. }
  4412. static void tg3_init_bcm8002(struct tg3 *tp)
  4413. {
  4414. u32 mac_status = tr32(MAC_STATUS);
  4415. int i;
  4416. /* Reset when initting first time or we have a link. */
  4417. if (tg3_flag(tp, INIT_COMPLETE) &&
  4418. !(mac_status & MAC_STATUS_PCS_SYNCED))
  4419. return;
  4420. /* Set PLL lock range. */
  4421. tg3_writephy(tp, 0x16, 0x8007);
  4422. /* SW reset */
  4423. tg3_writephy(tp, MII_BMCR, BMCR_RESET);
  4424. /* Wait for reset to complete. */
  4425. /* XXX schedule_timeout() ... */
  4426. for (i = 0; i < 500; i++)
  4427. udelay(10);
  4428. /* Config mode; select PMA/Ch 1 regs. */
  4429. tg3_writephy(tp, 0x10, 0x8411);
  4430. /* Enable auto-lock and comdet, select txclk for tx. */
  4431. tg3_writephy(tp, 0x11, 0x0a10);
  4432. tg3_writephy(tp, 0x18, 0x00a0);
  4433. tg3_writephy(tp, 0x16, 0x41ff);
  4434. /* Assert and deassert POR. */
  4435. tg3_writephy(tp, 0x13, 0x0400);
  4436. udelay(40);
  4437. tg3_writephy(tp, 0x13, 0x0000);
  4438. tg3_writephy(tp, 0x11, 0x0a50);
  4439. udelay(40);
  4440. tg3_writephy(tp, 0x11, 0x0a10);
  4441. /* Wait for signal to stabilize */
  4442. /* XXX schedule_timeout() ... */
  4443. for (i = 0; i < 15000; i++)
  4444. udelay(10);
  4445. /* Deselect the channel register so we can read the PHYID
  4446. * later.
  4447. */
  4448. tg3_writephy(tp, 0x10, 0x8011);
  4449. }
  4450. static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
  4451. {
  4452. u16 flowctrl;
  4453. bool current_link_up;
  4454. u32 sg_dig_ctrl, sg_dig_status;
  4455. u32 serdes_cfg, expected_sg_dig_ctrl;
  4456. int workaround, port_a;
  4457. serdes_cfg = 0;
  4458. expected_sg_dig_ctrl = 0;
  4459. workaround = 0;
  4460. port_a = 1;
  4461. current_link_up = false;
  4462. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
  4463. tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
  4464. workaround = 1;
  4465. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  4466. port_a = 0;
  4467. /* preserve bits 0-11,13,14 for signal pre-emphasis */
  4468. /* preserve bits 20-23 for voltage regulator */
  4469. serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
  4470. }
  4471. sg_dig_ctrl = tr32(SG_DIG_CTRL);
  4472. if (tp->link_config.autoneg != AUTONEG_ENABLE) {
  4473. if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
  4474. if (workaround) {
  4475. u32 val = serdes_cfg;
  4476. if (port_a)
  4477. val |= 0xc010000;
  4478. else
  4479. val |= 0x4010000;
  4480. tw32_f(MAC_SERDES_CFG, val);
  4481. }
  4482. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  4483. }
  4484. if (mac_status & MAC_STATUS_PCS_SYNCED) {
  4485. tg3_setup_flow_control(tp, 0, 0);
  4486. current_link_up = true;
  4487. }
  4488. goto out;
  4489. }
  4490. /* Want auto-negotiation. */
  4491. expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
  4492. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  4493. if (flowctrl & ADVERTISE_1000XPAUSE)
  4494. expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
  4495. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  4496. expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
  4497. if (sg_dig_ctrl != expected_sg_dig_ctrl) {
  4498. if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
  4499. tp->serdes_counter &&
  4500. ((mac_status & (MAC_STATUS_PCS_SYNCED |
  4501. MAC_STATUS_RCVD_CFG)) ==
  4502. MAC_STATUS_PCS_SYNCED)) {
  4503. tp->serdes_counter--;
  4504. current_link_up = true;
  4505. goto out;
  4506. }
  4507. restart_autoneg:
  4508. if (workaround)
  4509. tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
  4510. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
  4511. udelay(5);
  4512. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
  4513. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  4514. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4515. } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
  4516. MAC_STATUS_SIGNAL_DET)) {
  4517. sg_dig_status = tr32(SG_DIG_STATUS);
  4518. mac_status = tr32(MAC_STATUS);
  4519. if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
  4520. (mac_status & MAC_STATUS_PCS_SYNCED)) {
  4521. u32 local_adv = 0, remote_adv = 0;
  4522. if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
  4523. local_adv |= ADVERTISE_1000XPAUSE;
  4524. if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
  4525. local_adv |= ADVERTISE_1000XPSE_ASYM;
  4526. if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
  4527. remote_adv |= LPA_1000XPAUSE;
  4528. if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
  4529. remote_adv |= LPA_1000XPAUSE_ASYM;
  4530. tp->link_config.rmt_adv =
  4531. mii_adv_to_ethtool_adv_x(remote_adv);
  4532. tg3_setup_flow_control(tp, local_adv, remote_adv);
  4533. current_link_up = true;
  4534. tp->serdes_counter = 0;
  4535. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4536. } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
  4537. if (tp->serdes_counter)
  4538. tp->serdes_counter--;
  4539. else {
  4540. if (workaround) {
  4541. u32 val = serdes_cfg;
  4542. if (port_a)
  4543. val |= 0xc010000;
  4544. else
  4545. val |= 0x4010000;
  4546. tw32_f(MAC_SERDES_CFG, val);
  4547. }
  4548. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  4549. udelay(40);
  4550. /* Link parallel detection - link is up */
  4551. /* only if we have PCS_SYNC and not */
  4552. /* receiving config code words */
  4553. mac_status = tr32(MAC_STATUS);
  4554. if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
  4555. !(mac_status & MAC_STATUS_RCVD_CFG)) {
  4556. tg3_setup_flow_control(tp, 0, 0);
  4557. current_link_up = true;
  4558. tp->phy_flags |=
  4559. TG3_PHYFLG_PARALLEL_DETECT;
  4560. tp->serdes_counter =
  4561. SERDES_PARALLEL_DET_TIMEOUT;
  4562. } else
  4563. goto restart_autoneg;
  4564. }
  4565. }
  4566. } else {
  4567. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  4568. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4569. }
  4570. out:
  4571. return current_link_up;
  4572. }
  4573. static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
  4574. {
  4575. bool current_link_up = false;
  4576. if (!(mac_status & MAC_STATUS_PCS_SYNCED))
  4577. goto out;
  4578. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  4579. u32 txflags, rxflags;
  4580. int i;
  4581. if (fiber_autoneg(tp, &txflags, &rxflags)) {
  4582. u32 local_adv = 0, remote_adv = 0;
  4583. if (txflags & ANEG_CFG_PS1)
  4584. local_adv |= ADVERTISE_1000XPAUSE;
  4585. if (txflags & ANEG_CFG_PS2)
  4586. local_adv |= ADVERTISE_1000XPSE_ASYM;
  4587. if (rxflags & MR_LP_ADV_SYM_PAUSE)
  4588. remote_adv |= LPA_1000XPAUSE;
  4589. if (rxflags & MR_LP_ADV_ASYM_PAUSE)
  4590. remote_adv |= LPA_1000XPAUSE_ASYM;
  4591. tp->link_config.rmt_adv =
  4592. mii_adv_to_ethtool_adv_x(remote_adv);
  4593. tg3_setup_flow_control(tp, local_adv, remote_adv);
  4594. current_link_up = true;
  4595. }
  4596. for (i = 0; i < 30; i++) {
  4597. udelay(20);
  4598. tw32_f(MAC_STATUS,
  4599. (MAC_STATUS_SYNC_CHANGED |
  4600. MAC_STATUS_CFG_CHANGED));
  4601. udelay(40);
  4602. if ((tr32(MAC_STATUS) &
  4603. (MAC_STATUS_SYNC_CHANGED |
  4604. MAC_STATUS_CFG_CHANGED)) == 0)
  4605. break;
  4606. }
  4607. mac_status = tr32(MAC_STATUS);
  4608. if (!current_link_up &&
  4609. (mac_status & MAC_STATUS_PCS_SYNCED) &&
  4610. !(mac_status & MAC_STATUS_RCVD_CFG))
  4611. current_link_up = true;
  4612. } else {
  4613. tg3_setup_flow_control(tp, 0, 0);
  4614. /* Forcing 1000FD link up. */
  4615. current_link_up = true;
  4616. tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
  4617. udelay(40);
  4618. tw32_f(MAC_MODE, tp->mac_mode);
  4619. udelay(40);
  4620. }
  4621. out:
  4622. return current_link_up;
  4623. }
  4624. static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
  4625. {
  4626. u32 orig_pause_cfg;
  4627. u16 orig_active_speed;
  4628. u8 orig_active_duplex;
  4629. u32 mac_status;
  4630. bool current_link_up;
  4631. int i;
  4632. orig_pause_cfg = tp->link_config.active_flowctrl;
  4633. orig_active_speed = tp->link_config.active_speed;
  4634. orig_active_duplex = tp->link_config.active_duplex;
  4635. if (!tg3_flag(tp, HW_AUTONEG) &&
  4636. tp->link_up &&
  4637. tg3_flag(tp, INIT_COMPLETE)) {
  4638. mac_status = tr32(MAC_STATUS);
  4639. mac_status &= (MAC_STATUS_PCS_SYNCED |
  4640. MAC_STATUS_SIGNAL_DET |
  4641. MAC_STATUS_CFG_CHANGED |
  4642. MAC_STATUS_RCVD_CFG);
  4643. if (mac_status == (MAC_STATUS_PCS_SYNCED |
  4644. MAC_STATUS_SIGNAL_DET)) {
  4645. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  4646. MAC_STATUS_CFG_CHANGED));
  4647. return 0;
  4648. }
  4649. }
  4650. tw32_f(MAC_TX_AUTO_NEG, 0);
  4651. tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  4652. tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
  4653. tw32_f(MAC_MODE, tp->mac_mode);
  4654. udelay(40);
  4655. if (tp->phy_id == TG3_PHY_ID_BCM8002)
  4656. tg3_init_bcm8002(tp);
  4657. /* Enable link change event even when serdes polling. */
  4658. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4659. udelay(40);
  4660. current_link_up = false;
  4661. tp->link_config.rmt_adv = 0;
  4662. mac_status = tr32(MAC_STATUS);
  4663. if (tg3_flag(tp, HW_AUTONEG))
  4664. current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
  4665. else
  4666. current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
  4667. tp->napi[0].hw_status->status =
  4668. (SD_STATUS_UPDATED |
  4669. (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
  4670. for (i = 0; i < 100; i++) {
  4671. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  4672. MAC_STATUS_CFG_CHANGED));
  4673. udelay(5);
  4674. if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
  4675. MAC_STATUS_CFG_CHANGED |
  4676. MAC_STATUS_LNKSTATE_CHANGED)) == 0)
  4677. break;
  4678. }
  4679. mac_status = tr32(MAC_STATUS);
  4680. if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
  4681. current_link_up = false;
  4682. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  4683. tp->serdes_counter == 0) {
  4684. tw32_f(MAC_MODE, (tp->mac_mode |
  4685. MAC_MODE_SEND_CONFIGS));
  4686. udelay(1);
  4687. tw32_f(MAC_MODE, tp->mac_mode);
  4688. }
  4689. }
  4690. if (current_link_up) {
  4691. tp->link_config.active_speed = SPEED_1000;
  4692. tp->link_config.active_duplex = DUPLEX_FULL;
  4693. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  4694. LED_CTRL_LNKLED_OVERRIDE |
  4695. LED_CTRL_1000MBPS_ON));
  4696. } else {
  4697. tp->link_config.active_speed = SPEED_UNKNOWN;
  4698. tp->link_config.active_duplex = DUPLEX_UNKNOWN;
  4699. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  4700. LED_CTRL_LNKLED_OVERRIDE |
  4701. LED_CTRL_TRAFFIC_OVERRIDE));
  4702. }
  4703. if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
  4704. u32 now_pause_cfg = tp->link_config.active_flowctrl;
  4705. if (orig_pause_cfg != now_pause_cfg ||
  4706. orig_active_speed != tp->link_config.active_speed ||
  4707. orig_active_duplex != tp->link_config.active_duplex)
  4708. tg3_link_report(tp);
  4709. }
  4710. return 0;
  4711. }
  4712. static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
  4713. {
  4714. int err = 0;
  4715. u32 bmsr, bmcr;
  4716. u16 current_speed = SPEED_UNKNOWN;
  4717. u8 current_duplex = DUPLEX_UNKNOWN;
  4718. bool current_link_up = false;
  4719. u32 local_adv, remote_adv, sgsr;
  4720. if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
  4721. tg3_asic_rev(tp) == ASIC_REV_5720) &&
  4722. !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
  4723. (sgsr & SERDES_TG3_SGMII_MODE)) {
  4724. if (force_reset)
  4725. tg3_phy_reset(tp);
  4726. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  4727. if (!(sgsr & SERDES_TG3_LINK_UP)) {
  4728. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  4729. } else {
  4730. current_link_up = true;
  4731. if (sgsr & SERDES_TG3_SPEED_1000) {
  4732. current_speed = SPEED_1000;
  4733. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  4734. } else if (sgsr & SERDES_TG3_SPEED_100) {
  4735. current_speed = SPEED_100;
  4736. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  4737. } else {
  4738. current_speed = SPEED_10;
  4739. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  4740. }
  4741. if (sgsr & SERDES_TG3_FULL_DUPLEX)
  4742. current_duplex = DUPLEX_FULL;
  4743. else
  4744. current_duplex = DUPLEX_HALF;
  4745. }
  4746. tw32_f(MAC_MODE, tp->mac_mode);
  4747. udelay(40);
  4748. tg3_clear_mac_status(tp);
  4749. goto fiber_setup_done;
  4750. }
  4751. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  4752. tw32_f(MAC_MODE, tp->mac_mode);
  4753. udelay(40);
  4754. tg3_clear_mac_status(tp);
  4755. if (force_reset)
  4756. tg3_phy_reset(tp);
  4757. tp->link_config.rmt_adv = 0;
  4758. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4759. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4760. if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  4761. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  4762. bmsr |= BMSR_LSTATUS;
  4763. else
  4764. bmsr &= ~BMSR_LSTATUS;
  4765. }
  4766. err |= tg3_readphy(tp, MII_BMCR, &bmcr);
  4767. if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
  4768. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
  4769. /* do nothing, just check for link up at the end */
  4770. } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  4771. u32 adv, newadv;
  4772. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  4773. newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
  4774. ADVERTISE_1000XPAUSE |
  4775. ADVERTISE_1000XPSE_ASYM |
  4776. ADVERTISE_SLCT);
  4777. newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  4778. newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
  4779. if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
  4780. tg3_writephy(tp, MII_ADVERTISE, newadv);
  4781. bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
  4782. tg3_writephy(tp, MII_BMCR, bmcr);
  4783. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4784. tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
  4785. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4786. return err;
  4787. }
  4788. } else {
  4789. u32 new_bmcr;
  4790. bmcr &= ~BMCR_SPEED1000;
  4791. new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
  4792. if (tp->link_config.duplex == DUPLEX_FULL)
  4793. new_bmcr |= BMCR_FULLDPLX;
  4794. if (new_bmcr != bmcr) {
  4795. /* BMCR_SPEED1000 is a reserved bit that needs
  4796. * to be set on write.
  4797. */
  4798. new_bmcr |= BMCR_SPEED1000;
  4799. /* Force a linkdown */
  4800. if (tp->link_up) {
  4801. u32 adv;
  4802. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  4803. adv &= ~(ADVERTISE_1000XFULL |
  4804. ADVERTISE_1000XHALF |
  4805. ADVERTISE_SLCT);
  4806. tg3_writephy(tp, MII_ADVERTISE, adv);
  4807. tg3_writephy(tp, MII_BMCR, bmcr |
  4808. BMCR_ANRESTART |
  4809. BMCR_ANENABLE);
  4810. udelay(10);
  4811. tg3_carrier_off(tp);
  4812. }
  4813. tg3_writephy(tp, MII_BMCR, new_bmcr);
  4814. bmcr = new_bmcr;
  4815. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4816. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4817. if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  4818. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  4819. bmsr |= BMSR_LSTATUS;
  4820. else
  4821. bmsr &= ~BMSR_LSTATUS;
  4822. }
  4823. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4824. }
  4825. }
  4826. if (bmsr & BMSR_LSTATUS) {
  4827. current_speed = SPEED_1000;
  4828. current_link_up = true;
  4829. if (bmcr & BMCR_FULLDPLX)
  4830. current_duplex = DUPLEX_FULL;
  4831. else
  4832. current_duplex = DUPLEX_HALF;
  4833. local_adv = 0;
  4834. remote_adv = 0;
  4835. if (bmcr & BMCR_ANENABLE) {
  4836. u32 common;
  4837. err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
  4838. err |= tg3_readphy(tp, MII_LPA, &remote_adv);
  4839. common = local_adv & remote_adv;
  4840. if (common & (ADVERTISE_1000XHALF |
  4841. ADVERTISE_1000XFULL)) {
  4842. if (common & ADVERTISE_1000XFULL)
  4843. current_duplex = DUPLEX_FULL;
  4844. else
  4845. current_duplex = DUPLEX_HALF;
  4846. tp->link_config.rmt_adv =
  4847. mii_adv_to_ethtool_adv_x(remote_adv);
  4848. } else if (!tg3_flag(tp, 5780_CLASS)) {
  4849. /* Link is up via parallel detect */
  4850. } else {
  4851. current_link_up = false;
  4852. }
  4853. }
  4854. }
  4855. fiber_setup_done:
  4856. if (current_link_up && current_duplex == DUPLEX_FULL)
  4857. tg3_setup_flow_control(tp, local_adv, remote_adv);
  4858. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  4859. if (tp->link_config.active_duplex == DUPLEX_HALF)
  4860. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  4861. tw32_f(MAC_MODE, tp->mac_mode);
  4862. udelay(40);
  4863. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4864. tp->link_config.active_speed = current_speed;
  4865. tp->link_config.active_duplex = current_duplex;
  4866. tg3_test_and_report_link_chg(tp, current_link_up);
  4867. return err;
  4868. }
  4869. static void tg3_serdes_parallel_detect(struct tg3 *tp)
  4870. {
  4871. if (tp->serdes_counter) {
  4872. /* Give autoneg time to complete. */
  4873. tp->serdes_counter--;
  4874. return;
  4875. }
  4876. if (!tp->link_up &&
  4877. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  4878. u32 bmcr;
  4879. tg3_readphy(tp, MII_BMCR, &bmcr);
  4880. if (bmcr & BMCR_ANENABLE) {
  4881. u32 phy1, phy2;
  4882. /* Select shadow register 0x1f */
  4883. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
  4884. tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
  4885. /* Select expansion interrupt status register */
  4886. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  4887. MII_TG3_DSP_EXP1_INT_STAT);
  4888. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  4889. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  4890. if ((phy1 & 0x10) && !(phy2 & 0x20)) {
  4891. /* We have signal detect and not receiving
  4892. * config code words, link is up by parallel
  4893. * detection.
  4894. */
  4895. bmcr &= ~BMCR_ANENABLE;
  4896. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  4897. tg3_writephy(tp, MII_BMCR, bmcr);
  4898. tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
  4899. }
  4900. }
  4901. } else if (tp->link_up &&
  4902. (tp->link_config.autoneg == AUTONEG_ENABLE) &&
  4903. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
  4904. u32 phy2;
  4905. /* Select expansion interrupt status register */
  4906. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  4907. MII_TG3_DSP_EXP1_INT_STAT);
  4908. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  4909. if (phy2 & 0x20) {
  4910. u32 bmcr;
  4911. /* Config code words received, turn on autoneg. */
  4912. tg3_readphy(tp, MII_BMCR, &bmcr);
  4913. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
  4914. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4915. }
  4916. }
  4917. }
  4918. static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
  4919. {
  4920. u32 val;
  4921. int err;
  4922. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  4923. err = tg3_setup_fiber_phy(tp, force_reset);
  4924. else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  4925. err = tg3_setup_fiber_mii_phy(tp, force_reset);
  4926. else
  4927. err = tg3_setup_copper_phy(tp, force_reset);
  4928. if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
  4929. u32 scale;
  4930. val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
  4931. if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
  4932. scale = 65;
  4933. else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
  4934. scale = 6;
  4935. else
  4936. scale = 12;
  4937. val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
  4938. val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
  4939. tw32(GRC_MISC_CFG, val);
  4940. }
  4941. val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  4942. (6 << TX_LENGTHS_IPG_SHIFT);
  4943. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  4944. tg3_asic_rev(tp) == ASIC_REV_5762)
  4945. val |= tr32(MAC_TX_LENGTHS) &
  4946. (TX_LENGTHS_JMB_FRM_LEN_MSK |
  4947. TX_LENGTHS_CNT_DWN_VAL_MSK);
  4948. if (tp->link_config.active_speed == SPEED_1000 &&
  4949. tp->link_config.active_duplex == DUPLEX_HALF)
  4950. tw32(MAC_TX_LENGTHS, val |
  4951. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
  4952. else
  4953. tw32(MAC_TX_LENGTHS, val |
  4954. (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
  4955. if (!tg3_flag(tp, 5705_PLUS)) {
  4956. if (tp->link_up) {
  4957. tw32(HOSTCC_STAT_COAL_TICKS,
  4958. tp->coal.stats_block_coalesce_usecs);
  4959. } else {
  4960. tw32(HOSTCC_STAT_COAL_TICKS, 0);
  4961. }
  4962. }
  4963. if (tg3_flag(tp, ASPM_WORKAROUND)) {
  4964. val = tr32(PCIE_PWR_MGMT_THRESH);
  4965. if (!tp->link_up)
  4966. val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
  4967. tp->pwrmgmt_thresh;
  4968. else
  4969. val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
  4970. tw32(PCIE_PWR_MGMT_THRESH, val);
  4971. }
  4972. return err;
  4973. }
  4974. /* tp->lock must be held */
  4975. static u64 tg3_refclk_read(struct tg3 *tp)
  4976. {
  4977. u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
  4978. return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
  4979. }
  4980. /* tp->lock must be held */
  4981. static void tg3_refclk_write(struct tg3 *tp, u64 newval)
  4982. {
  4983. tw32(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_STOP);
  4984. tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
  4985. tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
  4986. tw32_f(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_RESUME);
  4987. }
  4988. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
  4989. static inline void tg3_full_unlock(struct tg3 *tp);
  4990. static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
  4991. {
  4992. struct tg3 *tp = netdev_priv(dev);
  4993. info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
  4994. SOF_TIMESTAMPING_RX_SOFTWARE |
  4995. SOF_TIMESTAMPING_SOFTWARE;
  4996. if (tg3_flag(tp, PTP_CAPABLE)) {
  4997. info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
  4998. SOF_TIMESTAMPING_RX_HARDWARE |
  4999. SOF_TIMESTAMPING_RAW_HARDWARE;
  5000. }
  5001. if (tp->ptp_clock)
  5002. info->phc_index = ptp_clock_index(tp->ptp_clock);
  5003. else
  5004. info->phc_index = -1;
  5005. info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
  5006. info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
  5007. (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
  5008. (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
  5009. (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
  5010. return 0;
  5011. }
  5012. static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
  5013. {
  5014. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  5015. bool neg_adj = false;
  5016. u32 correction = 0;
  5017. if (ppb < 0) {
  5018. neg_adj = true;
  5019. ppb = -ppb;
  5020. }
  5021. /* Frequency adjustment is performed using hardware with a 24 bit
  5022. * accumulator and a programmable correction value. On each clk, the
  5023. * correction value gets added to the accumulator and when it
  5024. * overflows, the time counter is incremented/decremented.
  5025. *
  5026. * So conversion from ppb to correction value is
  5027. * ppb * (1 << 24) / 1000000000
  5028. */
  5029. correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
  5030. TG3_EAV_REF_CLK_CORRECT_MASK;
  5031. tg3_full_lock(tp, 0);
  5032. if (correction)
  5033. tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
  5034. TG3_EAV_REF_CLK_CORRECT_EN |
  5035. (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
  5036. else
  5037. tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
  5038. tg3_full_unlock(tp);
  5039. return 0;
  5040. }
  5041. static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
  5042. {
  5043. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  5044. tg3_full_lock(tp, 0);
  5045. tp->ptp_adjust += delta;
  5046. tg3_full_unlock(tp);
  5047. return 0;
  5048. }
  5049. static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
  5050. {
  5051. u64 ns;
  5052. u32 remainder;
  5053. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  5054. tg3_full_lock(tp, 0);
  5055. ns = tg3_refclk_read(tp);
  5056. ns += tp->ptp_adjust;
  5057. tg3_full_unlock(tp);
  5058. ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
  5059. ts->tv_nsec = remainder;
  5060. return 0;
  5061. }
  5062. static int tg3_ptp_settime(struct ptp_clock_info *ptp,
  5063. const struct timespec *ts)
  5064. {
  5065. u64 ns;
  5066. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  5067. ns = timespec_to_ns(ts);
  5068. tg3_full_lock(tp, 0);
  5069. tg3_refclk_write(tp, ns);
  5070. tp->ptp_adjust = 0;
  5071. tg3_full_unlock(tp);
  5072. return 0;
  5073. }
  5074. static int tg3_ptp_enable(struct ptp_clock_info *ptp,
  5075. struct ptp_clock_request *rq, int on)
  5076. {
  5077. return -EOPNOTSUPP;
  5078. }
  5079. static const struct ptp_clock_info tg3_ptp_caps = {
  5080. .owner = THIS_MODULE,
  5081. .name = "tg3 clock",
  5082. .max_adj = 250000000,
  5083. .n_alarm = 0,
  5084. .n_ext_ts = 0,
  5085. .n_per_out = 0,
  5086. .pps = 0,
  5087. .adjfreq = tg3_ptp_adjfreq,
  5088. .adjtime = tg3_ptp_adjtime,
  5089. .gettime = tg3_ptp_gettime,
  5090. .settime = tg3_ptp_settime,
  5091. .enable = tg3_ptp_enable,
  5092. };
  5093. static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
  5094. struct skb_shared_hwtstamps *timestamp)
  5095. {
  5096. memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
  5097. timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
  5098. tp->ptp_adjust);
  5099. }
  5100. /* tp->lock must be held */
  5101. static void tg3_ptp_init(struct tg3 *tp)
  5102. {
  5103. if (!tg3_flag(tp, PTP_CAPABLE))
  5104. return;
  5105. /* Initialize the hardware clock to the system time. */
  5106. tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
  5107. tp->ptp_adjust = 0;
  5108. tp->ptp_info = tg3_ptp_caps;
  5109. }
  5110. /* tp->lock must be held */
  5111. static void tg3_ptp_resume(struct tg3 *tp)
  5112. {
  5113. if (!tg3_flag(tp, PTP_CAPABLE))
  5114. return;
  5115. tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
  5116. tp->ptp_adjust = 0;
  5117. }
  5118. static void tg3_ptp_fini(struct tg3 *tp)
  5119. {
  5120. if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
  5121. return;
  5122. ptp_clock_unregister(tp->ptp_clock);
  5123. tp->ptp_clock = NULL;
  5124. tp->ptp_adjust = 0;
  5125. }
  5126. static inline int tg3_irq_sync(struct tg3 *tp)
  5127. {
  5128. return tp->irq_sync;
  5129. }
  5130. static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
  5131. {
  5132. int i;
  5133. dst = (u32 *)((u8 *)dst + off);
  5134. for (i = 0; i < len; i += sizeof(u32))
  5135. *dst++ = tr32(off + i);
  5136. }
  5137. static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
  5138. {
  5139. tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
  5140. tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
  5141. tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
  5142. tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
  5143. tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
  5144. tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
  5145. tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
  5146. tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
  5147. tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
  5148. tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
  5149. tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
  5150. tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
  5151. tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
  5152. tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
  5153. tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
  5154. tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
  5155. tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
  5156. tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
  5157. tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
  5158. if (tg3_flag(tp, SUPPORT_MSIX))
  5159. tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
  5160. tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
  5161. tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
  5162. tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
  5163. tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
  5164. tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
  5165. tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
  5166. tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
  5167. tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
  5168. if (!tg3_flag(tp, 5705_PLUS)) {
  5169. tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
  5170. tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
  5171. tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
  5172. }
  5173. tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
  5174. tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
  5175. tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
  5176. tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
  5177. tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
  5178. if (tg3_flag(tp, NVRAM))
  5179. tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
  5180. }
  5181. static void tg3_dump_state(struct tg3 *tp)
  5182. {
  5183. int i;
  5184. u32 *regs;
  5185. regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
  5186. if (!regs)
  5187. return;
  5188. if (tg3_flag(tp, PCI_EXPRESS)) {
  5189. /* Read up to but not including private PCI registers */
  5190. for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
  5191. regs[i / sizeof(u32)] = tr32(i);
  5192. } else
  5193. tg3_dump_legacy_regs(tp, regs);
  5194. for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
  5195. if (!regs[i + 0] && !regs[i + 1] &&
  5196. !regs[i + 2] && !regs[i + 3])
  5197. continue;
  5198. netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
  5199. i * 4,
  5200. regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
  5201. }
  5202. kfree(regs);
  5203. for (i = 0; i < tp->irq_cnt; i++) {
  5204. struct tg3_napi *tnapi = &tp->napi[i];
  5205. /* SW status block */
  5206. netdev_err(tp->dev,
  5207. "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
  5208. i,
  5209. tnapi->hw_status->status,
  5210. tnapi->hw_status->status_tag,
  5211. tnapi->hw_status->rx_jumbo_consumer,
  5212. tnapi->hw_status->rx_consumer,
  5213. tnapi->hw_status->rx_mini_consumer,
  5214. tnapi->hw_status->idx[0].rx_producer,
  5215. tnapi->hw_status->idx[0].tx_consumer);
  5216. netdev_err(tp->dev,
  5217. "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
  5218. i,
  5219. tnapi->last_tag, tnapi->last_irq_tag,
  5220. tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
  5221. tnapi->rx_rcb_ptr,
  5222. tnapi->prodring.rx_std_prod_idx,
  5223. tnapi->prodring.rx_std_cons_idx,
  5224. tnapi->prodring.rx_jmb_prod_idx,
  5225. tnapi->prodring.rx_jmb_cons_idx);
  5226. }
  5227. }
  5228. /* This is called whenever we suspect that the system chipset is re-
  5229. * ordering the sequence of MMIO to the tx send mailbox. The symptom
  5230. * is bogus tx completions. We try to recover by setting the
  5231. * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
  5232. * in the workqueue.
  5233. */
  5234. static void tg3_tx_recover(struct tg3 *tp)
  5235. {
  5236. BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
  5237. tp->write32_tx_mbox == tg3_write_indirect_mbox);
  5238. netdev_warn(tp->dev,
  5239. "The system may be re-ordering memory-mapped I/O "
  5240. "cycles to the network device, attempting to recover. "
  5241. "Please report the problem to the driver maintainer "
  5242. "and include system chipset information.\n");
  5243. tg3_flag_set(tp, TX_RECOVERY_PENDING);
  5244. }
  5245. static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
  5246. {
  5247. /* Tell compiler to fetch tx indices from memory. */
  5248. barrier();
  5249. return tnapi->tx_pending -
  5250. ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
  5251. }
  5252. /* Tigon3 never reports partial packet sends. So we do not
  5253. * need special logic to handle SKBs that have not had all
  5254. * of their frags sent yet, like SunGEM does.
  5255. */
  5256. static void tg3_tx(struct tg3_napi *tnapi)
  5257. {
  5258. struct tg3 *tp = tnapi->tp;
  5259. u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
  5260. u32 sw_idx = tnapi->tx_cons;
  5261. struct netdev_queue *txq;
  5262. int index = tnapi - tp->napi;
  5263. unsigned int pkts_compl = 0, bytes_compl = 0;
  5264. if (tg3_flag(tp, ENABLE_TSS))
  5265. index--;
  5266. txq = netdev_get_tx_queue(tp->dev, index);
  5267. while (sw_idx != hw_idx) {
  5268. struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
  5269. struct sk_buff *skb = ri->skb;
  5270. int i, tx_bug = 0;
  5271. if (unlikely(skb == NULL)) {
  5272. tg3_tx_recover(tp);
  5273. return;
  5274. }
  5275. if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
  5276. struct skb_shared_hwtstamps timestamp;
  5277. u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
  5278. hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
  5279. tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
  5280. skb_tstamp_tx(skb, &timestamp);
  5281. }
  5282. pci_unmap_single(tp->pdev,
  5283. dma_unmap_addr(ri, mapping),
  5284. skb_headlen(skb),
  5285. PCI_DMA_TODEVICE);
  5286. ri->skb = NULL;
  5287. while (ri->fragmented) {
  5288. ri->fragmented = false;
  5289. sw_idx = NEXT_TX(sw_idx);
  5290. ri = &tnapi->tx_buffers[sw_idx];
  5291. }
  5292. sw_idx = NEXT_TX(sw_idx);
  5293. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  5294. ri = &tnapi->tx_buffers[sw_idx];
  5295. if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
  5296. tx_bug = 1;
  5297. pci_unmap_page(tp->pdev,
  5298. dma_unmap_addr(ri, mapping),
  5299. skb_frag_size(&skb_shinfo(skb)->frags[i]),
  5300. PCI_DMA_TODEVICE);
  5301. while (ri->fragmented) {
  5302. ri->fragmented = false;
  5303. sw_idx = NEXT_TX(sw_idx);
  5304. ri = &tnapi->tx_buffers[sw_idx];
  5305. }
  5306. sw_idx = NEXT_TX(sw_idx);
  5307. }
  5308. pkts_compl++;
  5309. bytes_compl += skb->len;
  5310. dev_kfree_skb(skb);
  5311. if (unlikely(tx_bug)) {
  5312. tg3_tx_recover(tp);
  5313. return;
  5314. }
  5315. }
  5316. netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
  5317. tnapi->tx_cons = sw_idx;
  5318. /* Need to make the tx_cons update visible to tg3_start_xmit()
  5319. * before checking for netif_queue_stopped(). Without the
  5320. * memory barrier, there is a small possibility that tg3_start_xmit()
  5321. * will miss it and cause the queue to be stopped forever.
  5322. */
  5323. smp_mb();
  5324. if (unlikely(netif_tx_queue_stopped(txq) &&
  5325. (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
  5326. __netif_tx_lock(txq, smp_processor_id());
  5327. if (netif_tx_queue_stopped(txq) &&
  5328. (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
  5329. netif_tx_wake_queue(txq);
  5330. __netif_tx_unlock(txq);
  5331. }
  5332. }
  5333. static void tg3_frag_free(bool is_frag, void *data)
  5334. {
  5335. if (is_frag)
  5336. put_page(virt_to_head_page(data));
  5337. else
  5338. kfree(data);
  5339. }
  5340. static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
  5341. {
  5342. unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
  5343. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  5344. if (!ri->data)
  5345. return;
  5346. pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
  5347. map_sz, PCI_DMA_FROMDEVICE);
  5348. tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
  5349. ri->data = NULL;
  5350. }
  5351. /* Returns size of skb allocated or < 0 on error.
  5352. *
  5353. * We only need to fill in the address because the other members
  5354. * of the RX descriptor are invariant, see tg3_init_rings.
  5355. *
  5356. * Note the purposeful assymetry of cpu vs. chip accesses. For
  5357. * posting buffers we only dirty the first cache line of the RX
  5358. * descriptor (containing the address). Whereas for the RX status
  5359. * buffers the cpu only reads the last cacheline of the RX descriptor
  5360. * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
  5361. */
  5362. static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
  5363. u32 opaque_key, u32 dest_idx_unmasked,
  5364. unsigned int *frag_size)
  5365. {
  5366. struct tg3_rx_buffer_desc *desc;
  5367. struct ring_info *map;
  5368. u8 *data;
  5369. dma_addr_t mapping;
  5370. int skb_size, data_size, dest_idx;
  5371. switch (opaque_key) {
  5372. case RXD_OPAQUE_RING_STD:
  5373. dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
  5374. desc = &tpr->rx_std[dest_idx];
  5375. map = &tpr->rx_std_buffers[dest_idx];
  5376. data_size = tp->rx_pkt_map_sz;
  5377. break;
  5378. case RXD_OPAQUE_RING_JUMBO:
  5379. dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
  5380. desc = &tpr->rx_jmb[dest_idx].std;
  5381. map = &tpr->rx_jmb_buffers[dest_idx];
  5382. data_size = TG3_RX_JMB_MAP_SZ;
  5383. break;
  5384. default:
  5385. return -EINVAL;
  5386. }
  5387. /* Do not overwrite any of the map or rp information
  5388. * until we are sure we can commit to a new buffer.
  5389. *
  5390. * Callers depend upon this behavior and assume that
  5391. * we leave everything unchanged if we fail.
  5392. */
  5393. skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
  5394. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  5395. if (skb_size <= PAGE_SIZE) {
  5396. data = netdev_alloc_frag(skb_size);
  5397. *frag_size = skb_size;
  5398. } else {
  5399. data = kmalloc(skb_size, GFP_ATOMIC);
  5400. *frag_size = 0;
  5401. }
  5402. if (!data)
  5403. return -ENOMEM;
  5404. mapping = pci_map_single(tp->pdev,
  5405. data + TG3_RX_OFFSET(tp),
  5406. data_size,
  5407. PCI_DMA_FROMDEVICE);
  5408. if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
  5409. tg3_frag_free(skb_size <= PAGE_SIZE, data);
  5410. return -EIO;
  5411. }
  5412. map->data = data;
  5413. dma_unmap_addr_set(map, mapping, mapping);
  5414. desc->addr_hi = ((u64)mapping >> 32);
  5415. desc->addr_lo = ((u64)mapping & 0xffffffff);
  5416. return data_size;
  5417. }
  5418. /* We only need to move over in the address because the other
  5419. * members of the RX descriptor are invariant. See notes above
  5420. * tg3_alloc_rx_data for full details.
  5421. */
  5422. static void tg3_recycle_rx(struct tg3_napi *tnapi,
  5423. struct tg3_rx_prodring_set *dpr,
  5424. u32 opaque_key, int src_idx,
  5425. u32 dest_idx_unmasked)
  5426. {
  5427. struct tg3 *tp = tnapi->tp;
  5428. struct tg3_rx_buffer_desc *src_desc, *dest_desc;
  5429. struct ring_info *src_map, *dest_map;
  5430. struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
  5431. int dest_idx;
  5432. switch (opaque_key) {
  5433. case RXD_OPAQUE_RING_STD:
  5434. dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
  5435. dest_desc = &dpr->rx_std[dest_idx];
  5436. dest_map = &dpr->rx_std_buffers[dest_idx];
  5437. src_desc = &spr->rx_std[src_idx];
  5438. src_map = &spr->rx_std_buffers[src_idx];
  5439. break;
  5440. case RXD_OPAQUE_RING_JUMBO:
  5441. dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
  5442. dest_desc = &dpr->rx_jmb[dest_idx].std;
  5443. dest_map = &dpr->rx_jmb_buffers[dest_idx];
  5444. src_desc = &spr->rx_jmb[src_idx].std;
  5445. src_map = &spr->rx_jmb_buffers[src_idx];
  5446. break;
  5447. default:
  5448. return;
  5449. }
  5450. dest_map->data = src_map->data;
  5451. dma_unmap_addr_set(dest_map, mapping,
  5452. dma_unmap_addr(src_map, mapping));
  5453. dest_desc->addr_hi = src_desc->addr_hi;
  5454. dest_desc->addr_lo = src_desc->addr_lo;
  5455. /* Ensure that the update to the skb happens after the physical
  5456. * addresses have been transferred to the new BD location.
  5457. */
  5458. smp_wmb();
  5459. src_map->data = NULL;
  5460. }
  5461. /* The RX ring scheme is composed of multiple rings which post fresh
  5462. * buffers to the chip, and one special ring the chip uses to report
  5463. * status back to the host.
  5464. *
  5465. * The special ring reports the status of received packets to the
  5466. * host. The chip does not write into the original descriptor the
  5467. * RX buffer was obtained from. The chip simply takes the original
  5468. * descriptor as provided by the host, updates the status and length
  5469. * field, then writes this into the next status ring entry.
  5470. *
  5471. * Each ring the host uses to post buffers to the chip is described
  5472. * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
  5473. * it is first placed into the on-chip ram. When the packet's length
  5474. * is known, it walks down the TG3_BDINFO entries to select the ring.
  5475. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
  5476. * which is within the range of the new packet's length is chosen.
  5477. *
  5478. * The "separate ring for rx status" scheme may sound queer, but it makes
  5479. * sense from a cache coherency perspective. If only the host writes
  5480. * to the buffer post rings, and only the chip writes to the rx status
  5481. * rings, then cache lines never move beyond shared-modified state.
  5482. * If both the host and chip were to write into the same ring, cache line
  5483. * eviction could occur since both entities want it in an exclusive state.
  5484. */
  5485. static int tg3_rx(struct tg3_napi *tnapi, int budget)
  5486. {
  5487. struct tg3 *tp = tnapi->tp;
  5488. u32 work_mask, rx_std_posted = 0;
  5489. u32 std_prod_idx, jmb_prod_idx;
  5490. u32 sw_idx = tnapi->rx_rcb_ptr;
  5491. u16 hw_idx;
  5492. int received;
  5493. struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
  5494. hw_idx = *(tnapi->rx_rcb_prod_idx);
  5495. /*
  5496. * We need to order the read of hw_idx and the read of
  5497. * the opaque cookie.
  5498. */
  5499. rmb();
  5500. work_mask = 0;
  5501. received = 0;
  5502. std_prod_idx = tpr->rx_std_prod_idx;
  5503. jmb_prod_idx = tpr->rx_jmb_prod_idx;
  5504. while (sw_idx != hw_idx && budget > 0) {
  5505. struct ring_info *ri;
  5506. struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
  5507. unsigned int len;
  5508. struct sk_buff *skb;
  5509. dma_addr_t dma_addr;
  5510. u32 opaque_key, desc_idx, *post_ptr;
  5511. u8 *data;
  5512. u64 tstamp = 0;
  5513. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  5514. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  5515. if (opaque_key == RXD_OPAQUE_RING_STD) {
  5516. ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
  5517. dma_addr = dma_unmap_addr(ri, mapping);
  5518. data = ri->data;
  5519. post_ptr = &std_prod_idx;
  5520. rx_std_posted++;
  5521. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  5522. ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
  5523. dma_addr = dma_unmap_addr(ri, mapping);
  5524. data = ri->data;
  5525. post_ptr = &jmb_prod_idx;
  5526. } else
  5527. goto next_pkt_nopost;
  5528. work_mask |= opaque_key;
  5529. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  5530. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
  5531. drop_it:
  5532. tg3_recycle_rx(tnapi, tpr, opaque_key,
  5533. desc_idx, *post_ptr);
  5534. drop_it_no_recycle:
  5535. /* Other statistics kept track of by card. */
  5536. tp->rx_dropped++;
  5537. goto next_pkt;
  5538. }
  5539. prefetch(data + TG3_RX_OFFSET(tp));
  5540. len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
  5541. ETH_FCS_LEN;
  5542. if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
  5543. RXD_FLAG_PTPSTAT_PTPV1 ||
  5544. (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
  5545. RXD_FLAG_PTPSTAT_PTPV2) {
  5546. tstamp = tr32(TG3_RX_TSTAMP_LSB);
  5547. tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
  5548. }
  5549. if (len > TG3_RX_COPY_THRESH(tp)) {
  5550. int skb_size;
  5551. unsigned int frag_size;
  5552. skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
  5553. *post_ptr, &frag_size);
  5554. if (skb_size < 0)
  5555. goto drop_it;
  5556. pci_unmap_single(tp->pdev, dma_addr, skb_size,
  5557. PCI_DMA_FROMDEVICE);
  5558. skb = build_skb(data, frag_size);
  5559. if (!skb) {
  5560. tg3_frag_free(frag_size != 0, data);
  5561. goto drop_it_no_recycle;
  5562. }
  5563. skb_reserve(skb, TG3_RX_OFFSET(tp));
  5564. /* Ensure that the update to the data happens
  5565. * after the usage of the old DMA mapping.
  5566. */
  5567. smp_wmb();
  5568. ri->data = NULL;
  5569. } else {
  5570. tg3_recycle_rx(tnapi, tpr, opaque_key,
  5571. desc_idx, *post_ptr);
  5572. skb = netdev_alloc_skb(tp->dev,
  5573. len + TG3_RAW_IP_ALIGN);
  5574. if (skb == NULL)
  5575. goto drop_it_no_recycle;
  5576. skb_reserve(skb, TG3_RAW_IP_ALIGN);
  5577. pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  5578. memcpy(skb->data,
  5579. data + TG3_RX_OFFSET(tp),
  5580. len);
  5581. pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  5582. }
  5583. skb_put(skb, len);
  5584. if (tstamp)
  5585. tg3_hwclock_to_timestamp(tp, tstamp,
  5586. skb_hwtstamps(skb));
  5587. if ((tp->dev->features & NETIF_F_RXCSUM) &&
  5588. (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  5589. (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  5590. >> RXD_TCPCSUM_SHIFT) == 0xffff))
  5591. skb->ip_summed = CHECKSUM_UNNECESSARY;
  5592. else
  5593. skb_checksum_none_assert(skb);
  5594. skb->protocol = eth_type_trans(skb, tp->dev);
  5595. if (len > (tp->dev->mtu + ETH_HLEN) &&
  5596. skb->protocol != htons(ETH_P_8021Q)) {
  5597. dev_kfree_skb(skb);
  5598. goto drop_it_no_recycle;
  5599. }
  5600. if (desc->type_flags & RXD_FLAG_VLAN &&
  5601. !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
  5602. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  5603. desc->err_vlan & RXD_VLAN_MASK);
  5604. napi_gro_receive(&tnapi->napi, skb);
  5605. received++;
  5606. budget--;
  5607. next_pkt:
  5608. (*post_ptr)++;
  5609. if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
  5610. tpr->rx_std_prod_idx = std_prod_idx &
  5611. tp->rx_std_ring_mask;
  5612. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  5613. tpr->rx_std_prod_idx);
  5614. work_mask &= ~RXD_OPAQUE_RING_STD;
  5615. rx_std_posted = 0;
  5616. }
  5617. next_pkt_nopost:
  5618. sw_idx++;
  5619. sw_idx &= tp->rx_ret_ring_mask;
  5620. /* Refresh hw_idx to see if there is new work */
  5621. if (sw_idx == hw_idx) {
  5622. hw_idx = *(tnapi->rx_rcb_prod_idx);
  5623. rmb();
  5624. }
  5625. }
  5626. /* ACK the status ring. */
  5627. tnapi->rx_rcb_ptr = sw_idx;
  5628. tw32_rx_mbox(tnapi->consmbox, sw_idx);
  5629. /* Refill RX ring(s). */
  5630. if (!tg3_flag(tp, ENABLE_RSS)) {
  5631. /* Sync BD data before updating mailbox */
  5632. wmb();
  5633. if (work_mask & RXD_OPAQUE_RING_STD) {
  5634. tpr->rx_std_prod_idx = std_prod_idx &
  5635. tp->rx_std_ring_mask;
  5636. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  5637. tpr->rx_std_prod_idx);
  5638. }
  5639. if (work_mask & RXD_OPAQUE_RING_JUMBO) {
  5640. tpr->rx_jmb_prod_idx = jmb_prod_idx &
  5641. tp->rx_jmb_ring_mask;
  5642. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
  5643. tpr->rx_jmb_prod_idx);
  5644. }
  5645. mmiowb();
  5646. } else if (work_mask) {
  5647. /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
  5648. * updated before the producer indices can be updated.
  5649. */
  5650. smp_wmb();
  5651. tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
  5652. tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
  5653. if (tnapi != &tp->napi[1]) {
  5654. tp->rx_refill = true;
  5655. napi_schedule(&tp->napi[1].napi);
  5656. }
  5657. }
  5658. return received;
  5659. }
  5660. static void tg3_poll_link(struct tg3 *tp)
  5661. {
  5662. /* handle link change and other phy events */
  5663. if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
  5664. struct tg3_hw_status *sblk = tp->napi[0].hw_status;
  5665. if (sblk->status & SD_STATUS_LINK_CHG) {
  5666. sblk->status = SD_STATUS_UPDATED |
  5667. (sblk->status & ~SD_STATUS_LINK_CHG);
  5668. spin_lock(&tp->lock);
  5669. if (tg3_flag(tp, USE_PHYLIB)) {
  5670. tw32_f(MAC_STATUS,
  5671. (MAC_STATUS_SYNC_CHANGED |
  5672. MAC_STATUS_CFG_CHANGED |
  5673. MAC_STATUS_MI_COMPLETION |
  5674. MAC_STATUS_LNKSTATE_CHANGED));
  5675. udelay(40);
  5676. } else
  5677. tg3_setup_phy(tp, false);
  5678. spin_unlock(&tp->lock);
  5679. }
  5680. }
  5681. }
  5682. static int tg3_rx_prodring_xfer(struct tg3 *tp,
  5683. struct tg3_rx_prodring_set *dpr,
  5684. struct tg3_rx_prodring_set *spr)
  5685. {
  5686. u32 si, di, cpycnt, src_prod_idx;
  5687. int i, err = 0;
  5688. while (1) {
  5689. src_prod_idx = spr->rx_std_prod_idx;
  5690. /* Make sure updates to the rx_std_buffers[] entries and the
  5691. * standard producer index are seen in the correct order.
  5692. */
  5693. smp_rmb();
  5694. if (spr->rx_std_cons_idx == src_prod_idx)
  5695. break;
  5696. if (spr->rx_std_cons_idx < src_prod_idx)
  5697. cpycnt = src_prod_idx - spr->rx_std_cons_idx;
  5698. else
  5699. cpycnt = tp->rx_std_ring_mask + 1 -
  5700. spr->rx_std_cons_idx;
  5701. cpycnt = min(cpycnt,
  5702. tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
  5703. si = spr->rx_std_cons_idx;
  5704. di = dpr->rx_std_prod_idx;
  5705. for (i = di; i < di + cpycnt; i++) {
  5706. if (dpr->rx_std_buffers[i].data) {
  5707. cpycnt = i - di;
  5708. err = -ENOSPC;
  5709. break;
  5710. }
  5711. }
  5712. if (!cpycnt)
  5713. break;
  5714. /* Ensure that updates to the rx_std_buffers ring and the
  5715. * shadowed hardware producer ring from tg3_recycle_skb() are
  5716. * ordered correctly WRT the skb check above.
  5717. */
  5718. smp_rmb();
  5719. memcpy(&dpr->rx_std_buffers[di],
  5720. &spr->rx_std_buffers[si],
  5721. cpycnt * sizeof(struct ring_info));
  5722. for (i = 0; i < cpycnt; i++, di++, si++) {
  5723. struct tg3_rx_buffer_desc *sbd, *dbd;
  5724. sbd = &spr->rx_std[si];
  5725. dbd = &dpr->rx_std[di];
  5726. dbd->addr_hi = sbd->addr_hi;
  5727. dbd->addr_lo = sbd->addr_lo;
  5728. }
  5729. spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
  5730. tp->rx_std_ring_mask;
  5731. dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
  5732. tp->rx_std_ring_mask;
  5733. }
  5734. while (1) {
  5735. src_prod_idx = spr->rx_jmb_prod_idx;
  5736. /* Make sure updates to the rx_jmb_buffers[] entries and
  5737. * the jumbo producer index are seen in the correct order.
  5738. */
  5739. smp_rmb();
  5740. if (spr->rx_jmb_cons_idx == src_prod_idx)
  5741. break;
  5742. if (spr->rx_jmb_cons_idx < src_prod_idx)
  5743. cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
  5744. else
  5745. cpycnt = tp->rx_jmb_ring_mask + 1 -
  5746. spr->rx_jmb_cons_idx;
  5747. cpycnt = min(cpycnt,
  5748. tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
  5749. si = spr->rx_jmb_cons_idx;
  5750. di = dpr->rx_jmb_prod_idx;
  5751. for (i = di; i < di + cpycnt; i++) {
  5752. if (dpr->rx_jmb_buffers[i].data) {
  5753. cpycnt = i - di;
  5754. err = -ENOSPC;
  5755. break;
  5756. }
  5757. }
  5758. if (!cpycnt)
  5759. break;
  5760. /* Ensure that updates to the rx_jmb_buffers ring and the
  5761. * shadowed hardware producer ring from tg3_recycle_skb() are
  5762. * ordered correctly WRT the skb check above.
  5763. */
  5764. smp_rmb();
  5765. memcpy(&dpr->rx_jmb_buffers[di],
  5766. &spr->rx_jmb_buffers[si],
  5767. cpycnt * sizeof(struct ring_info));
  5768. for (i = 0; i < cpycnt; i++, di++, si++) {
  5769. struct tg3_rx_buffer_desc *sbd, *dbd;
  5770. sbd = &spr->rx_jmb[si].std;
  5771. dbd = &dpr->rx_jmb[di].std;
  5772. dbd->addr_hi = sbd->addr_hi;
  5773. dbd->addr_lo = sbd->addr_lo;
  5774. }
  5775. spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
  5776. tp->rx_jmb_ring_mask;
  5777. dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
  5778. tp->rx_jmb_ring_mask;
  5779. }
  5780. return err;
  5781. }
  5782. static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
  5783. {
  5784. struct tg3 *tp = tnapi->tp;
  5785. /* run TX completion thread */
  5786. if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
  5787. tg3_tx(tnapi);
  5788. if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
  5789. return work_done;
  5790. }
  5791. if (!tnapi->rx_rcb_prod_idx)
  5792. return work_done;
  5793. /* run RX thread, within the bounds set by NAPI.
  5794. * All RX "locking" is done by ensuring outside
  5795. * code synchronizes with tg3->napi.poll()
  5796. */
  5797. if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
  5798. work_done += tg3_rx(tnapi, budget - work_done);
  5799. if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
  5800. struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
  5801. int i, err = 0;
  5802. u32 std_prod_idx = dpr->rx_std_prod_idx;
  5803. u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
  5804. tp->rx_refill = false;
  5805. for (i = 1; i <= tp->rxq_cnt; i++)
  5806. err |= tg3_rx_prodring_xfer(tp, dpr,
  5807. &tp->napi[i].prodring);
  5808. wmb();
  5809. if (std_prod_idx != dpr->rx_std_prod_idx)
  5810. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  5811. dpr->rx_std_prod_idx);
  5812. if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
  5813. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
  5814. dpr->rx_jmb_prod_idx);
  5815. mmiowb();
  5816. if (err)
  5817. tw32_f(HOSTCC_MODE, tp->coal_now);
  5818. }
  5819. return work_done;
  5820. }
  5821. static inline void tg3_reset_task_schedule(struct tg3 *tp)
  5822. {
  5823. if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
  5824. schedule_work(&tp->reset_task);
  5825. }
  5826. static inline void tg3_reset_task_cancel(struct tg3 *tp)
  5827. {
  5828. cancel_work_sync(&tp->reset_task);
  5829. tg3_flag_clear(tp, RESET_TASK_PENDING);
  5830. tg3_flag_clear(tp, TX_RECOVERY_PENDING);
  5831. }
  5832. static int tg3_poll_msix(struct napi_struct *napi, int budget)
  5833. {
  5834. struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
  5835. struct tg3 *tp = tnapi->tp;
  5836. int work_done = 0;
  5837. struct tg3_hw_status *sblk = tnapi->hw_status;
  5838. while (1) {
  5839. work_done = tg3_poll_work(tnapi, work_done, budget);
  5840. if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
  5841. goto tx_recovery;
  5842. if (unlikely(work_done >= budget))
  5843. break;
  5844. /* tp->last_tag is used in tg3_int_reenable() below
  5845. * to tell the hw how much work has been processed,
  5846. * so we must read it before checking for more work.
  5847. */
  5848. tnapi->last_tag = sblk->status_tag;
  5849. tnapi->last_irq_tag = tnapi->last_tag;
  5850. rmb();
  5851. /* check for RX/TX work to do */
  5852. if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
  5853. *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
  5854. /* This test here is not race free, but will reduce
  5855. * the number of interrupts by looping again.
  5856. */
  5857. if (tnapi == &tp->napi[1] && tp->rx_refill)
  5858. continue;
  5859. napi_complete(napi);
  5860. /* Reenable interrupts. */
  5861. tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
  5862. /* This test here is synchronized by napi_schedule()
  5863. * and napi_complete() to close the race condition.
  5864. */
  5865. if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
  5866. tw32(HOSTCC_MODE, tp->coalesce_mode |
  5867. HOSTCC_MODE_ENABLE |
  5868. tnapi->coal_now);
  5869. }
  5870. mmiowb();
  5871. break;
  5872. }
  5873. }
  5874. return work_done;
  5875. tx_recovery:
  5876. /* work_done is guaranteed to be less than budget. */
  5877. napi_complete(napi);
  5878. tg3_reset_task_schedule(tp);
  5879. return work_done;
  5880. }
  5881. static void tg3_process_error(struct tg3 *tp)
  5882. {
  5883. u32 val;
  5884. bool real_error = false;
  5885. if (tg3_flag(tp, ERROR_PROCESSED))
  5886. return;
  5887. /* Check Flow Attention register */
  5888. val = tr32(HOSTCC_FLOW_ATTN);
  5889. if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
  5890. netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
  5891. real_error = true;
  5892. }
  5893. if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
  5894. netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
  5895. real_error = true;
  5896. }
  5897. if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
  5898. netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
  5899. real_error = true;
  5900. }
  5901. if (!real_error)
  5902. return;
  5903. tg3_dump_state(tp);
  5904. tg3_flag_set(tp, ERROR_PROCESSED);
  5905. tg3_reset_task_schedule(tp);
  5906. }
  5907. static int tg3_poll(struct napi_struct *napi, int budget)
  5908. {
  5909. struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
  5910. struct tg3 *tp = tnapi->tp;
  5911. int work_done = 0;
  5912. struct tg3_hw_status *sblk = tnapi->hw_status;
  5913. while (1) {
  5914. if (sblk->status & SD_STATUS_ERROR)
  5915. tg3_process_error(tp);
  5916. tg3_poll_link(tp);
  5917. work_done = tg3_poll_work(tnapi, work_done, budget);
  5918. if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
  5919. goto tx_recovery;
  5920. if (unlikely(work_done >= budget))
  5921. break;
  5922. if (tg3_flag(tp, TAGGED_STATUS)) {
  5923. /* tp->last_tag is used in tg3_int_reenable() below
  5924. * to tell the hw how much work has been processed,
  5925. * so we must read it before checking for more work.
  5926. */
  5927. tnapi->last_tag = sblk->status_tag;
  5928. tnapi->last_irq_tag = tnapi->last_tag;
  5929. rmb();
  5930. } else
  5931. sblk->status &= ~SD_STATUS_UPDATED;
  5932. if (likely(!tg3_has_work(tnapi))) {
  5933. napi_complete(napi);
  5934. tg3_int_reenable(tnapi);
  5935. break;
  5936. }
  5937. }
  5938. return work_done;
  5939. tx_recovery:
  5940. /* work_done is guaranteed to be less than budget. */
  5941. napi_complete(napi);
  5942. tg3_reset_task_schedule(tp);
  5943. return work_done;
  5944. }
  5945. static void tg3_napi_disable(struct tg3 *tp)
  5946. {
  5947. int i;
  5948. for (i = tp->irq_cnt - 1; i >= 0; i--)
  5949. napi_disable(&tp->napi[i].napi);
  5950. }
  5951. static void tg3_napi_enable(struct tg3 *tp)
  5952. {
  5953. int i;
  5954. for (i = 0; i < tp->irq_cnt; i++)
  5955. napi_enable(&tp->napi[i].napi);
  5956. }
  5957. static void tg3_napi_init(struct tg3 *tp)
  5958. {
  5959. int i;
  5960. netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
  5961. for (i = 1; i < tp->irq_cnt; i++)
  5962. netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
  5963. }
  5964. static void tg3_napi_fini(struct tg3 *tp)
  5965. {
  5966. int i;
  5967. for (i = 0; i < tp->irq_cnt; i++)
  5968. netif_napi_del(&tp->napi[i].napi);
  5969. }
  5970. static inline void tg3_netif_stop(struct tg3 *tp)
  5971. {
  5972. tp->dev->trans_start = jiffies; /* prevent tx timeout */
  5973. tg3_napi_disable(tp);
  5974. netif_carrier_off(tp->dev);
  5975. netif_tx_disable(tp->dev);
  5976. }
  5977. /* tp->lock must be held */
  5978. static inline void tg3_netif_start(struct tg3 *tp)
  5979. {
  5980. tg3_ptp_resume(tp);
  5981. /* NOTE: unconditional netif_tx_wake_all_queues is only
  5982. * appropriate so long as all callers are assured to
  5983. * have free tx slots (such as after tg3_init_hw)
  5984. */
  5985. netif_tx_wake_all_queues(tp->dev);
  5986. if (tp->link_up)
  5987. netif_carrier_on(tp->dev);
  5988. tg3_napi_enable(tp);
  5989. tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
  5990. tg3_enable_ints(tp);
  5991. }
  5992. static void tg3_irq_quiesce(struct tg3 *tp)
  5993. {
  5994. int i;
  5995. BUG_ON(tp->irq_sync);
  5996. tp->irq_sync = 1;
  5997. smp_mb();
  5998. for (i = 0; i < tp->irq_cnt; i++)
  5999. synchronize_irq(tp->napi[i].irq_vec);
  6000. }
  6001. /* Fully shutdown all tg3 driver activity elsewhere in the system.
  6002. * If irq_sync is non-zero, then the IRQ handler must be synchronized
  6003. * with as well. Most of the time, this is not necessary except when
  6004. * shutting down the device.
  6005. */
  6006. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
  6007. {
  6008. spin_lock_bh(&tp->lock);
  6009. if (irq_sync)
  6010. tg3_irq_quiesce(tp);
  6011. }
  6012. static inline void tg3_full_unlock(struct tg3 *tp)
  6013. {
  6014. spin_unlock_bh(&tp->lock);
  6015. }
  6016. /* One-shot MSI handler - Chip automatically disables interrupt
  6017. * after sending MSI so driver doesn't have to do it.
  6018. */
  6019. static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
  6020. {
  6021. struct tg3_napi *tnapi = dev_id;
  6022. struct tg3 *tp = tnapi->tp;
  6023. prefetch(tnapi->hw_status);
  6024. if (tnapi->rx_rcb)
  6025. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  6026. if (likely(!tg3_irq_sync(tp)))
  6027. napi_schedule(&tnapi->napi);
  6028. return IRQ_HANDLED;
  6029. }
  6030. /* MSI ISR - No need to check for interrupt sharing and no need to
  6031. * flush status block and interrupt mailbox. PCI ordering rules
  6032. * guarantee that MSI will arrive after the status block.
  6033. */
  6034. static irqreturn_t tg3_msi(int irq, void *dev_id)
  6035. {
  6036. struct tg3_napi *tnapi = dev_id;
  6037. struct tg3 *tp = tnapi->tp;
  6038. prefetch(tnapi->hw_status);
  6039. if (tnapi->rx_rcb)
  6040. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  6041. /*
  6042. * Writing any value to intr-mbox-0 clears PCI INTA# and
  6043. * chip-internal interrupt pending events.
  6044. * Writing non-zero to intr-mbox-0 additional tells the
  6045. * NIC to stop sending us irqs, engaging "in-intr-handler"
  6046. * event coalescing.
  6047. */
  6048. tw32_mailbox(tnapi->int_mbox, 0x00000001);
  6049. if (likely(!tg3_irq_sync(tp)))
  6050. napi_schedule(&tnapi->napi);
  6051. return IRQ_RETVAL(1);
  6052. }
  6053. static irqreturn_t tg3_interrupt(int irq, void *dev_id)
  6054. {
  6055. struct tg3_napi *tnapi = dev_id;
  6056. struct tg3 *tp = tnapi->tp;
  6057. struct tg3_hw_status *sblk = tnapi->hw_status;
  6058. unsigned int handled = 1;
  6059. /* In INTx mode, it is possible for the interrupt to arrive at
  6060. * the CPU before the status block posted prior to the interrupt.
  6061. * Reading the PCI State register will confirm whether the
  6062. * interrupt is ours and will flush the status block.
  6063. */
  6064. if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
  6065. if (tg3_flag(tp, CHIP_RESETTING) ||
  6066. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  6067. handled = 0;
  6068. goto out;
  6069. }
  6070. }
  6071. /*
  6072. * Writing any value to intr-mbox-0 clears PCI INTA# and
  6073. * chip-internal interrupt pending events.
  6074. * Writing non-zero to intr-mbox-0 additional tells the
  6075. * NIC to stop sending us irqs, engaging "in-intr-handler"
  6076. * event coalescing.
  6077. *
  6078. * Flush the mailbox to de-assert the IRQ immediately to prevent
  6079. * spurious interrupts. The flush impacts performance but
  6080. * excessive spurious interrupts can be worse in some cases.
  6081. */
  6082. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  6083. if (tg3_irq_sync(tp))
  6084. goto out;
  6085. sblk->status &= ~SD_STATUS_UPDATED;
  6086. if (likely(tg3_has_work(tnapi))) {
  6087. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  6088. napi_schedule(&tnapi->napi);
  6089. } else {
  6090. /* No work, shared interrupt perhaps? re-enable
  6091. * interrupts, and flush that PCI write
  6092. */
  6093. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  6094. 0x00000000);
  6095. }
  6096. out:
  6097. return IRQ_RETVAL(handled);
  6098. }
  6099. static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
  6100. {
  6101. struct tg3_napi *tnapi = dev_id;
  6102. struct tg3 *tp = tnapi->tp;
  6103. struct tg3_hw_status *sblk = tnapi->hw_status;
  6104. unsigned int handled = 1;
  6105. /* In INTx mode, it is possible for the interrupt to arrive at
  6106. * the CPU before the status block posted prior to the interrupt.
  6107. * Reading the PCI State register will confirm whether the
  6108. * interrupt is ours and will flush the status block.
  6109. */
  6110. if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
  6111. if (tg3_flag(tp, CHIP_RESETTING) ||
  6112. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  6113. handled = 0;
  6114. goto out;
  6115. }
  6116. }
  6117. /*
  6118. * writing any value to intr-mbox-0 clears PCI INTA# and
  6119. * chip-internal interrupt pending events.
  6120. * writing non-zero to intr-mbox-0 additional tells the
  6121. * NIC to stop sending us irqs, engaging "in-intr-handler"
  6122. * event coalescing.
  6123. *
  6124. * Flush the mailbox to de-assert the IRQ immediately to prevent
  6125. * spurious interrupts. The flush impacts performance but
  6126. * excessive spurious interrupts can be worse in some cases.
  6127. */
  6128. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  6129. /*
  6130. * In a shared interrupt configuration, sometimes other devices'
  6131. * interrupts will scream. We record the current status tag here
  6132. * so that the above check can report that the screaming interrupts
  6133. * are unhandled. Eventually they will be silenced.
  6134. */
  6135. tnapi->last_irq_tag = sblk->status_tag;
  6136. if (tg3_irq_sync(tp))
  6137. goto out;
  6138. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  6139. napi_schedule(&tnapi->napi);
  6140. out:
  6141. return IRQ_RETVAL(handled);
  6142. }
  6143. /* ISR for interrupt test */
  6144. static irqreturn_t tg3_test_isr(int irq, void *dev_id)
  6145. {
  6146. struct tg3_napi *tnapi = dev_id;
  6147. struct tg3 *tp = tnapi->tp;
  6148. struct tg3_hw_status *sblk = tnapi->hw_status;
  6149. if ((sblk->status & SD_STATUS_UPDATED) ||
  6150. !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  6151. tg3_disable_ints(tp);
  6152. return IRQ_RETVAL(1);
  6153. }
  6154. return IRQ_RETVAL(0);
  6155. }
  6156. #ifdef CONFIG_NET_POLL_CONTROLLER
  6157. static void tg3_poll_controller(struct net_device *dev)
  6158. {
  6159. int i;
  6160. struct tg3 *tp = netdev_priv(dev);
  6161. if (tg3_irq_sync(tp))
  6162. return;
  6163. for (i = 0; i < tp->irq_cnt; i++)
  6164. tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
  6165. }
  6166. #endif
  6167. static void tg3_tx_timeout(struct net_device *dev)
  6168. {
  6169. struct tg3 *tp = netdev_priv(dev);
  6170. if (netif_msg_tx_err(tp)) {
  6171. netdev_err(dev, "transmit timed out, resetting\n");
  6172. tg3_dump_state(tp);
  6173. }
  6174. tg3_reset_task_schedule(tp);
  6175. }
  6176. /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
  6177. static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
  6178. {
  6179. u32 base = (u32) mapping & 0xffffffff;
  6180. return (base > 0xffffdcc0) && (base + len + 8 < base);
  6181. }
  6182. /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
  6183. * of any 4GB boundaries: 4G, 8G, etc
  6184. */
  6185. static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  6186. u32 len, u32 mss)
  6187. {
  6188. if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
  6189. u32 base = (u32) mapping & 0xffffffff;
  6190. return ((base + len + (mss & 0x3fff)) < base);
  6191. }
  6192. return 0;
  6193. }
  6194. /* Test for DMA addresses > 40-bit */
  6195. static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  6196. int len)
  6197. {
  6198. #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
  6199. if (tg3_flag(tp, 40BIT_DMA_BUG))
  6200. return ((u64) mapping + len) > DMA_BIT_MASK(40);
  6201. return 0;
  6202. #else
  6203. return 0;
  6204. #endif
  6205. }
  6206. static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
  6207. dma_addr_t mapping, u32 len, u32 flags,
  6208. u32 mss, u32 vlan)
  6209. {
  6210. txbd->addr_hi = ((u64) mapping >> 32);
  6211. txbd->addr_lo = ((u64) mapping & 0xffffffff);
  6212. txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
  6213. txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
  6214. }
  6215. static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
  6216. dma_addr_t map, u32 len, u32 flags,
  6217. u32 mss, u32 vlan)
  6218. {
  6219. struct tg3 *tp = tnapi->tp;
  6220. bool hwbug = false;
  6221. if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
  6222. hwbug = true;
  6223. if (tg3_4g_overflow_test(map, len))
  6224. hwbug = true;
  6225. if (tg3_4g_tso_overflow_test(tp, map, len, mss))
  6226. hwbug = true;
  6227. if (tg3_40bit_overflow_test(tp, map, len))
  6228. hwbug = true;
  6229. if (tp->dma_limit) {
  6230. u32 prvidx = *entry;
  6231. u32 tmp_flag = flags & ~TXD_FLAG_END;
  6232. while (len > tp->dma_limit && *budget) {
  6233. u32 frag_len = tp->dma_limit;
  6234. len -= tp->dma_limit;
  6235. /* Avoid the 8byte DMA problem */
  6236. if (len <= 8) {
  6237. len += tp->dma_limit / 2;
  6238. frag_len = tp->dma_limit / 2;
  6239. }
  6240. tnapi->tx_buffers[*entry].fragmented = true;
  6241. tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
  6242. frag_len, tmp_flag, mss, vlan);
  6243. *budget -= 1;
  6244. prvidx = *entry;
  6245. *entry = NEXT_TX(*entry);
  6246. map += frag_len;
  6247. }
  6248. if (len) {
  6249. if (*budget) {
  6250. tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
  6251. len, flags, mss, vlan);
  6252. *budget -= 1;
  6253. *entry = NEXT_TX(*entry);
  6254. } else {
  6255. hwbug = true;
  6256. tnapi->tx_buffers[prvidx].fragmented = false;
  6257. }
  6258. }
  6259. } else {
  6260. tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
  6261. len, flags, mss, vlan);
  6262. *entry = NEXT_TX(*entry);
  6263. }
  6264. return hwbug;
  6265. }
  6266. static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
  6267. {
  6268. int i;
  6269. struct sk_buff *skb;
  6270. struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
  6271. skb = txb->skb;
  6272. txb->skb = NULL;
  6273. pci_unmap_single(tnapi->tp->pdev,
  6274. dma_unmap_addr(txb, mapping),
  6275. skb_headlen(skb),
  6276. PCI_DMA_TODEVICE);
  6277. while (txb->fragmented) {
  6278. txb->fragmented = false;
  6279. entry = NEXT_TX(entry);
  6280. txb = &tnapi->tx_buffers[entry];
  6281. }
  6282. for (i = 0; i <= last; i++) {
  6283. const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  6284. entry = NEXT_TX(entry);
  6285. txb = &tnapi->tx_buffers[entry];
  6286. pci_unmap_page(tnapi->tp->pdev,
  6287. dma_unmap_addr(txb, mapping),
  6288. skb_frag_size(frag), PCI_DMA_TODEVICE);
  6289. while (txb->fragmented) {
  6290. txb->fragmented = false;
  6291. entry = NEXT_TX(entry);
  6292. txb = &tnapi->tx_buffers[entry];
  6293. }
  6294. }
  6295. }
  6296. /* Workaround 4GB and 40-bit hardware DMA bugs. */
  6297. static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
  6298. struct sk_buff **pskb,
  6299. u32 *entry, u32 *budget,
  6300. u32 base_flags, u32 mss, u32 vlan)
  6301. {
  6302. struct tg3 *tp = tnapi->tp;
  6303. struct sk_buff *new_skb, *skb = *pskb;
  6304. dma_addr_t new_addr = 0;
  6305. int ret = 0;
  6306. if (tg3_asic_rev(tp) != ASIC_REV_5701)
  6307. new_skb = skb_copy(skb, GFP_ATOMIC);
  6308. else {
  6309. int more_headroom = 4 - ((unsigned long)skb->data & 3);
  6310. new_skb = skb_copy_expand(skb,
  6311. skb_headroom(skb) + more_headroom,
  6312. skb_tailroom(skb), GFP_ATOMIC);
  6313. }
  6314. if (!new_skb) {
  6315. ret = -1;
  6316. } else {
  6317. /* New SKB is guaranteed to be linear. */
  6318. new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
  6319. PCI_DMA_TODEVICE);
  6320. /* Make sure the mapping succeeded */
  6321. if (pci_dma_mapping_error(tp->pdev, new_addr)) {
  6322. dev_kfree_skb(new_skb);
  6323. ret = -1;
  6324. } else {
  6325. u32 save_entry = *entry;
  6326. base_flags |= TXD_FLAG_END;
  6327. tnapi->tx_buffers[*entry].skb = new_skb;
  6328. dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
  6329. mapping, new_addr);
  6330. if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
  6331. new_skb->len, base_flags,
  6332. mss, vlan)) {
  6333. tg3_tx_skb_unmap(tnapi, save_entry, -1);
  6334. dev_kfree_skb(new_skb);
  6335. ret = -1;
  6336. }
  6337. }
  6338. }
  6339. dev_kfree_skb(skb);
  6340. *pskb = new_skb;
  6341. return ret;
  6342. }
  6343. static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
  6344. /* Use GSO to workaround a rare TSO bug that may be triggered when the
  6345. * TSO header is greater than 80 bytes.
  6346. */
  6347. static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
  6348. {
  6349. struct sk_buff *segs, *nskb;
  6350. u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
  6351. /* Estimate the number of fragments in the worst case */
  6352. if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
  6353. netif_stop_queue(tp->dev);
  6354. /* netif_tx_stop_queue() must be done before checking
  6355. * checking tx index in tg3_tx_avail() below, because in
  6356. * tg3_tx(), we update tx index before checking for
  6357. * netif_tx_queue_stopped().
  6358. */
  6359. smp_mb();
  6360. if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
  6361. return NETDEV_TX_BUSY;
  6362. netif_wake_queue(tp->dev);
  6363. }
  6364. segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
  6365. if (IS_ERR(segs))
  6366. goto tg3_tso_bug_end;
  6367. do {
  6368. nskb = segs;
  6369. segs = segs->next;
  6370. nskb->next = NULL;
  6371. tg3_start_xmit(nskb, tp->dev);
  6372. } while (segs);
  6373. tg3_tso_bug_end:
  6374. dev_kfree_skb(skb);
  6375. return NETDEV_TX_OK;
  6376. }
  6377. /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
  6378. * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
  6379. */
  6380. static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
  6381. {
  6382. struct tg3 *tp = netdev_priv(dev);
  6383. u32 len, entry, base_flags, mss, vlan = 0;
  6384. u32 budget;
  6385. int i = -1, would_hit_hwbug;
  6386. dma_addr_t mapping;
  6387. struct tg3_napi *tnapi;
  6388. struct netdev_queue *txq;
  6389. unsigned int last;
  6390. txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
  6391. tnapi = &tp->napi[skb_get_queue_mapping(skb)];
  6392. if (tg3_flag(tp, ENABLE_TSS))
  6393. tnapi++;
  6394. budget = tg3_tx_avail(tnapi);
  6395. /* We are running in BH disabled context with netif_tx_lock
  6396. * and TX reclaim runs via tp->napi.poll inside of a software
  6397. * interrupt. Furthermore, IRQ processing runs lockless so we have
  6398. * no IRQ context deadlocks to worry about either. Rejoice!
  6399. */
  6400. if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
  6401. if (!netif_tx_queue_stopped(txq)) {
  6402. netif_tx_stop_queue(txq);
  6403. /* This is a hard error, log it. */
  6404. netdev_err(dev,
  6405. "BUG! Tx Ring full when queue awake!\n");
  6406. }
  6407. return NETDEV_TX_BUSY;
  6408. }
  6409. entry = tnapi->tx_prod;
  6410. base_flags = 0;
  6411. if (skb->ip_summed == CHECKSUM_PARTIAL)
  6412. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  6413. mss = skb_shinfo(skb)->gso_size;
  6414. if (mss) {
  6415. struct iphdr *iph;
  6416. u32 tcp_opt_len, hdr_len;
  6417. if (skb_header_cloned(skb) &&
  6418. pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
  6419. goto drop;
  6420. iph = ip_hdr(skb);
  6421. tcp_opt_len = tcp_optlen(skb);
  6422. hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
  6423. if (!skb_is_gso_v6(skb)) {
  6424. iph->check = 0;
  6425. iph->tot_len = htons(mss + hdr_len);
  6426. }
  6427. if (unlikely((ETH_HLEN + hdr_len) > 80) &&
  6428. tg3_flag(tp, TSO_BUG))
  6429. return tg3_tso_bug(tp, skb);
  6430. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  6431. TXD_FLAG_CPU_POST_DMA);
  6432. if (tg3_flag(tp, HW_TSO_1) ||
  6433. tg3_flag(tp, HW_TSO_2) ||
  6434. tg3_flag(tp, HW_TSO_3)) {
  6435. tcp_hdr(skb)->check = 0;
  6436. base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
  6437. } else
  6438. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  6439. iph->daddr, 0,
  6440. IPPROTO_TCP,
  6441. 0);
  6442. if (tg3_flag(tp, HW_TSO_3)) {
  6443. mss |= (hdr_len & 0xc) << 12;
  6444. if (hdr_len & 0x10)
  6445. base_flags |= 0x00000010;
  6446. base_flags |= (hdr_len & 0x3e0) << 5;
  6447. } else if (tg3_flag(tp, HW_TSO_2))
  6448. mss |= hdr_len << 9;
  6449. else if (tg3_flag(tp, HW_TSO_1) ||
  6450. tg3_asic_rev(tp) == ASIC_REV_5705) {
  6451. if (tcp_opt_len || iph->ihl > 5) {
  6452. int tsflags;
  6453. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  6454. mss |= (tsflags << 11);
  6455. }
  6456. } else {
  6457. if (tcp_opt_len || iph->ihl > 5) {
  6458. int tsflags;
  6459. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  6460. base_flags |= tsflags << 12;
  6461. }
  6462. }
  6463. }
  6464. if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
  6465. !mss && skb->len > VLAN_ETH_FRAME_LEN)
  6466. base_flags |= TXD_FLAG_JMB_PKT;
  6467. if (vlan_tx_tag_present(skb)) {
  6468. base_flags |= TXD_FLAG_VLAN;
  6469. vlan = vlan_tx_tag_get(skb);
  6470. }
  6471. if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
  6472. tg3_flag(tp, TX_TSTAMP_EN)) {
  6473. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  6474. base_flags |= TXD_FLAG_HWTSTAMP;
  6475. }
  6476. len = skb_headlen(skb);
  6477. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  6478. if (pci_dma_mapping_error(tp->pdev, mapping))
  6479. goto drop;
  6480. tnapi->tx_buffers[entry].skb = skb;
  6481. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
  6482. would_hit_hwbug = 0;
  6483. if (tg3_flag(tp, 5701_DMA_BUG))
  6484. would_hit_hwbug = 1;
  6485. if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
  6486. ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
  6487. mss, vlan)) {
  6488. would_hit_hwbug = 1;
  6489. } else if (skb_shinfo(skb)->nr_frags > 0) {
  6490. u32 tmp_mss = mss;
  6491. if (!tg3_flag(tp, HW_TSO_1) &&
  6492. !tg3_flag(tp, HW_TSO_2) &&
  6493. !tg3_flag(tp, HW_TSO_3))
  6494. tmp_mss = 0;
  6495. /* Now loop through additional data
  6496. * fragments, and queue them.
  6497. */
  6498. last = skb_shinfo(skb)->nr_frags - 1;
  6499. for (i = 0; i <= last; i++) {
  6500. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  6501. len = skb_frag_size(frag);
  6502. mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
  6503. len, DMA_TO_DEVICE);
  6504. tnapi->tx_buffers[entry].skb = NULL;
  6505. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
  6506. mapping);
  6507. if (dma_mapping_error(&tp->pdev->dev, mapping))
  6508. goto dma_error;
  6509. if (!budget ||
  6510. tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
  6511. len, base_flags |
  6512. ((i == last) ? TXD_FLAG_END : 0),
  6513. tmp_mss, vlan)) {
  6514. would_hit_hwbug = 1;
  6515. break;
  6516. }
  6517. }
  6518. }
  6519. if (would_hit_hwbug) {
  6520. tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
  6521. /* If the workaround fails due to memory/mapping
  6522. * failure, silently drop this packet.
  6523. */
  6524. entry = tnapi->tx_prod;
  6525. budget = tg3_tx_avail(tnapi);
  6526. if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
  6527. base_flags, mss, vlan))
  6528. goto drop_nofree;
  6529. }
  6530. skb_tx_timestamp(skb);
  6531. netdev_tx_sent_queue(txq, skb->len);
  6532. /* Sync BD data before updating mailbox */
  6533. wmb();
  6534. /* Packets are ready, update Tx producer idx local and on card. */
  6535. tw32_tx_mbox(tnapi->prodmbox, entry);
  6536. tnapi->tx_prod = entry;
  6537. if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
  6538. netif_tx_stop_queue(txq);
  6539. /* netif_tx_stop_queue() must be done before checking
  6540. * checking tx index in tg3_tx_avail() below, because in
  6541. * tg3_tx(), we update tx index before checking for
  6542. * netif_tx_queue_stopped().
  6543. */
  6544. smp_mb();
  6545. if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
  6546. netif_tx_wake_queue(txq);
  6547. }
  6548. mmiowb();
  6549. return NETDEV_TX_OK;
  6550. dma_error:
  6551. tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
  6552. tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
  6553. drop:
  6554. dev_kfree_skb(skb);
  6555. drop_nofree:
  6556. tp->tx_dropped++;
  6557. return NETDEV_TX_OK;
  6558. }
  6559. static void tg3_mac_loopback(struct tg3 *tp, bool enable)
  6560. {
  6561. if (enable) {
  6562. tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
  6563. MAC_MODE_PORT_MODE_MASK);
  6564. tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
  6565. if (!tg3_flag(tp, 5705_PLUS))
  6566. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  6567. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  6568. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  6569. else
  6570. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  6571. } else {
  6572. tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
  6573. if (tg3_flag(tp, 5705_PLUS) ||
  6574. (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
  6575. tg3_asic_rev(tp) == ASIC_REV_5700)
  6576. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  6577. }
  6578. tw32(MAC_MODE, tp->mac_mode);
  6579. udelay(40);
  6580. }
  6581. static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
  6582. {
  6583. u32 val, bmcr, mac_mode, ptest = 0;
  6584. tg3_phy_toggle_apd(tp, false);
  6585. tg3_phy_toggle_automdix(tp, false);
  6586. if (extlpbk && tg3_phy_set_extloopbk(tp))
  6587. return -EIO;
  6588. bmcr = BMCR_FULLDPLX;
  6589. switch (speed) {
  6590. case SPEED_10:
  6591. break;
  6592. case SPEED_100:
  6593. bmcr |= BMCR_SPEED100;
  6594. break;
  6595. case SPEED_1000:
  6596. default:
  6597. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  6598. speed = SPEED_100;
  6599. bmcr |= BMCR_SPEED100;
  6600. } else {
  6601. speed = SPEED_1000;
  6602. bmcr |= BMCR_SPEED1000;
  6603. }
  6604. }
  6605. if (extlpbk) {
  6606. if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  6607. tg3_readphy(tp, MII_CTRL1000, &val);
  6608. val |= CTL1000_AS_MASTER |
  6609. CTL1000_ENABLE_MASTER;
  6610. tg3_writephy(tp, MII_CTRL1000, val);
  6611. } else {
  6612. ptest = MII_TG3_FET_PTEST_TRIM_SEL |
  6613. MII_TG3_FET_PTEST_TRIM_2;
  6614. tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
  6615. }
  6616. } else
  6617. bmcr |= BMCR_LOOPBACK;
  6618. tg3_writephy(tp, MII_BMCR, bmcr);
  6619. /* The write needs to be flushed for the FETs */
  6620. if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  6621. tg3_readphy(tp, MII_BMCR, &bmcr);
  6622. udelay(40);
  6623. if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  6624. tg3_asic_rev(tp) == ASIC_REV_5785) {
  6625. tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
  6626. MII_TG3_FET_PTEST_FRC_TX_LINK |
  6627. MII_TG3_FET_PTEST_FRC_TX_LOCK);
  6628. /* The write needs to be flushed for the AC131 */
  6629. tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
  6630. }
  6631. /* Reset to prevent losing 1st rx packet intermittently */
  6632. if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  6633. tg3_flag(tp, 5780_CLASS)) {
  6634. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  6635. udelay(10);
  6636. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6637. }
  6638. mac_mode = tp->mac_mode &
  6639. ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  6640. if (speed == SPEED_1000)
  6641. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  6642. else
  6643. mac_mode |= MAC_MODE_PORT_MODE_MII;
  6644. if (tg3_asic_rev(tp) == ASIC_REV_5700) {
  6645. u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
  6646. if (masked_phy_id == TG3_PHY_ID_BCM5401)
  6647. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  6648. else if (masked_phy_id == TG3_PHY_ID_BCM5411)
  6649. mac_mode |= MAC_MODE_LINK_POLARITY;
  6650. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  6651. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  6652. }
  6653. tw32(MAC_MODE, mac_mode);
  6654. udelay(40);
  6655. return 0;
  6656. }
  6657. static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
  6658. {
  6659. struct tg3 *tp = netdev_priv(dev);
  6660. if (features & NETIF_F_LOOPBACK) {
  6661. if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
  6662. return;
  6663. spin_lock_bh(&tp->lock);
  6664. tg3_mac_loopback(tp, true);
  6665. netif_carrier_on(tp->dev);
  6666. spin_unlock_bh(&tp->lock);
  6667. netdev_info(dev, "Internal MAC loopback mode enabled.\n");
  6668. } else {
  6669. if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
  6670. return;
  6671. spin_lock_bh(&tp->lock);
  6672. tg3_mac_loopback(tp, false);
  6673. /* Force link status check */
  6674. tg3_setup_phy(tp, true);
  6675. spin_unlock_bh(&tp->lock);
  6676. netdev_info(dev, "Internal MAC loopback mode disabled.\n");
  6677. }
  6678. }
  6679. static netdev_features_t tg3_fix_features(struct net_device *dev,
  6680. netdev_features_t features)
  6681. {
  6682. struct tg3 *tp = netdev_priv(dev);
  6683. if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
  6684. features &= ~NETIF_F_ALL_TSO;
  6685. return features;
  6686. }
  6687. static int tg3_set_features(struct net_device *dev, netdev_features_t features)
  6688. {
  6689. netdev_features_t changed = dev->features ^ features;
  6690. if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
  6691. tg3_set_loopback(dev, features);
  6692. return 0;
  6693. }
  6694. static void tg3_rx_prodring_free(struct tg3 *tp,
  6695. struct tg3_rx_prodring_set *tpr)
  6696. {
  6697. int i;
  6698. if (tpr != &tp->napi[0].prodring) {
  6699. for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
  6700. i = (i + 1) & tp->rx_std_ring_mask)
  6701. tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
  6702. tp->rx_pkt_map_sz);
  6703. if (tg3_flag(tp, JUMBO_CAPABLE)) {
  6704. for (i = tpr->rx_jmb_cons_idx;
  6705. i != tpr->rx_jmb_prod_idx;
  6706. i = (i + 1) & tp->rx_jmb_ring_mask) {
  6707. tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
  6708. TG3_RX_JMB_MAP_SZ);
  6709. }
  6710. }
  6711. return;
  6712. }
  6713. for (i = 0; i <= tp->rx_std_ring_mask; i++)
  6714. tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
  6715. tp->rx_pkt_map_sz);
  6716. if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
  6717. for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
  6718. tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
  6719. TG3_RX_JMB_MAP_SZ);
  6720. }
  6721. }
  6722. /* Initialize rx rings for packet processing.
  6723. *
  6724. * The chip has been shut down and the driver detached from
  6725. * the networking, so no interrupts or new tx packets will
  6726. * end up in the driver. tp->{tx,}lock are held and thus
  6727. * we may not sleep.
  6728. */
  6729. static int tg3_rx_prodring_alloc(struct tg3 *tp,
  6730. struct tg3_rx_prodring_set *tpr)
  6731. {
  6732. u32 i, rx_pkt_dma_sz;
  6733. tpr->rx_std_cons_idx = 0;
  6734. tpr->rx_std_prod_idx = 0;
  6735. tpr->rx_jmb_cons_idx = 0;
  6736. tpr->rx_jmb_prod_idx = 0;
  6737. if (tpr != &tp->napi[0].prodring) {
  6738. memset(&tpr->rx_std_buffers[0], 0,
  6739. TG3_RX_STD_BUFF_RING_SIZE(tp));
  6740. if (tpr->rx_jmb_buffers)
  6741. memset(&tpr->rx_jmb_buffers[0], 0,
  6742. TG3_RX_JMB_BUFF_RING_SIZE(tp));
  6743. goto done;
  6744. }
  6745. /* Zero out all descriptors. */
  6746. memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
  6747. rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
  6748. if (tg3_flag(tp, 5780_CLASS) &&
  6749. tp->dev->mtu > ETH_DATA_LEN)
  6750. rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
  6751. tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
  6752. /* Initialize invariants of the rings, we only set this
  6753. * stuff once. This works because the card does not
  6754. * write into the rx buffer posting rings.
  6755. */
  6756. for (i = 0; i <= tp->rx_std_ring_mask; i++) {
  6757. struct tg3_rx_buffer_desc *rxd;
  6758. rxd = &tpr->rx_std[i];
  6759. rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
  6760. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
  6761. rxd->opaque = (RXD_OPAQUE_RING_STD |
  6762. (i << RXD_OPAQUE_INDEX_SHIFT));
  6763. }
  6764. /* Now allocate fresh SKBs for each rx ring. */
  6765. for (i = 0; i < tp->rx_pending; i++) {
  6766. unsigned int frag_size;
  6767. if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
  6768. &frag_size) < 0) {
  6769. netdev_warn(tp->dev,
  6770. "Using a smaller RX standard ring. Only "
  6771. "%d out of %d buffers were allocated "
  6772. "successfully\n", i, tp->rx_pending);
  6773. if (i == 0)
  6774. goto initfail;
  6775. tp->rx_pending = i;
  6776. break;
  6777. }
  6778. }
  6779. if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
  6780. goto done;
  6781. memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
  6782. if (!tg3_flag(tp, JUMBO_RING_ENABLE))
  6783. goto done;
  6784. for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
  6785. struct tg3_rx_buffer_desc *rxd;
  6786. rxd = &tpr->rx_jmb[i].std;
  6787. rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
  6788. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
  6789. RXD_FLAG_JUMBO;
  6790. rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
  6791. (i << RXD_OPAQUE_INDEX_SHIFT));
  6792. }
  6793. for (i = 0; i < tp->rx_jumbo_pending; i++) {
  6794. unsigned int frag_size;
  6795. if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
  6796. &frag_size) < 0) {
  6797. netdev_warn(tp->dev,
  6798. "Using a smaller RX jumbo ring. Only %d "
  6799. "out of %d buffers were allocated "
  6800. "successfully\n", i, tp->rx_jumbo_pending);
  6801. if (i == 0)
  6802. goto initfail;
  6803. tp->rx_jumbo_pending = i;
  6804. break;
  6805. }
  6806. }
  6807. done:
  6808. return 0;
  6809. initfail:
  6810. tg3_rx_prodring_free(tp, tpr);
  6811. return -ENOMEM;
  6812. }
  6813. static void tg3_rx_prodring_fini(struct tg3 *tp,
  6814. struct tg3_rx_prodring_set *tpr)
  6815. {
  6816. kfree(tpr->rx_std_buffers);
  6817. tpr->rx_std_buffers = NULL;
  6818. kfree(tpr->rx_jmb_buffers);
  6819. tpr->rx_jmb_buffers = NULL;
  6820. if (tpr->rx_std) {
  6821. dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
  6822. tpr->rx_std, tpr->rx_std_mapping);
  6823. tpr->rx_std = NULL;
  6824. }
  6825. if (tpr->rx_jmb) {
  6826. dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
  6827. tpr->rx_jmb, tpr->rx_jmb_mapping);
  6828. tpr->rx_jmb = NULL;
  6829. }
  6830. }
  6831. static int tg3_rx_prodring_init(struct tg3 *tp,
  6832. struct tg3_rx_prodring_set *tpr)
  6833. {
  6834. tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
  6835. GFP_KERNEL);
  6836. if (!tpr->rx_std_buffers)
  6837. return -ENOMEM;
  6838. tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
  6839. TG3_RX_STD_RING_BYTES(tp),
  6840. &tpr->rx_std_mapping,
  6841. GFP_KERNEL);
  6842. if (!tpr->rx_std)
  6843. goto err_out;
  6844. if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
  6845. tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
  6846. GFP_KERNEL);
  6847. if (!tpr->rx_jmb_buffers)
  6848. goto err_out;
  6849. tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
  6850. TG3_RX_JMB_RING_BYTES(tp),
  6851. &tpr->rx_jmb_mapping,
  6852. GFP_KERNEL);
  6853. if (!tpr->rx_jmb)
  6854. goto err_out;
  6855. }
  6856. return 0;
  6857. err_out:
  6858. tg3_rx_prodring_fini(tp, tpr);
  6859. return -ENOMEM;
  6860. }
  6861. /* Free up pending packets in all rx/tx rings.
  6862. *
  6863. * The chip has been shut down and the driver detached from
  6864. * the networking, so no interrupts or new tx packets will
  6865. * end up in the driver. tp->{tx,}lock is not held and we are not
  6866. * in an interrupt context and thus may sleep.
  6867. */
  6868. static void tg3_free_rings(struct tg3 *tp)
  6869. {
  6870. int i, j;
  6871. for (j = 0; j < tp->irq_cnt; j++) {
  6872. struct tg3_napi *tnapi = &tp->napi[j];
  6873. tg3_rx_prodring_free(tp, &tnapi->prodring);
  6874. if (!tnapi->tx_buffers)
  6875. continue;
  6876. for (i = 0; i < TG3_TX_RING_SIZE; i++) {
  6877. struct sk_buff *skb = tnapi->tx_buffers[i].skb;
  6878. if (!skb)
  6879. continue;
  6880. tg3_tx_skb_unmap(tnapi, i,
  6881. skb_shinfo(skb)->nr_frags - 1);
  6882. dev_kfree_skb_any(skb);
  6883. }
  6884. netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
  6885. }
  6886. }
  6887. /* Initialize tx/rx rings for packet processing.
  6888. *
  6889. * The chip has been shut down and the driver detached from
  6890. * the networking, so no interrupts or new tx packets will
  6891. * end up in the driver. tp->{tx,}lock are held and thus
  6892. * we may not sleep.
  6893. */
  6894. static int tg3_init_rings(struct tg3 *tp)
  6895. {
  6896. int i;
  6897. /* Free up all the SKBs. */
  6898. tg3_free_rings(tp);
  6899. for (i = 0; i < tp->irq_cnt; i++) {
  6900. struct tg3_napi *tnapi = &tp->napi[i];
  6901. tnapi->last_tag = 0;
  6902. tnapi->last_irq_tag = 0;
  6903. tnapi->hw_status->status = 0;
  6904. tnapi->hw_status->status_tag = 0;
  6905. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6906. tnapi->tx_prod = 0;
  6907. tnapi->tx_cons = 0;
  6908. if (tnapi->tx_ring)
  6909. memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
  6910. tnapi->rx_rcb_ptr = 0;
  6911. if (tnapi->rx_rcb)
  6912. memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  6913. if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
  6914. tg3_free_rings(tp);
  6915. return -ENOMEM;
  6916. }
  6917. }
  6918. return 0;
  6919. }
  6920. static void tg3_mem_tx_release(struct tg3 *tp)
  6921. {
  6922. int i;
  6923. for (i = 0; i < tp->irq_max; i++) {
  6924. struct tg3_napi *tnapi = &tp->napi[i];
  6925. if (tnapi->tx_ring) {
  6926. dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
  6927. tnapi->tx_ring, tnapi->tx_desc_mapping);
  6928. tnapi->tx_ring = NULL;
  6929. }
  6930. kfree(tnapi->tx_buffers);
  6931. tnapi->tx_buffers = NULL;
  6932. }
  6933. }
  6934. static int tg3_mem_tx_acquire(struct tg3 *tp)
  6935. {
  6936. int i;
  6937. struct tg3_napi *tnapi = &tp->napi[0];
  6938. /* If multivector TSS is enabled, vector 0 does not handle
  6939. * tx interrupts. Don't allocate any resources for it.
  6940. */
  6941. if (tg3_flag(tp, ENABLE_TSS))
  6942. tnapi++;
  6943. for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
  6944. tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
  6945. TG3_TX_RING_SIZE, GFP_KERNEL);
  6946. if (!tnapi->tx_buffers)
  6947. goto err_out;
  6948. tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
  6949. TG3_TX_RING_BYTES,
  6950. &tnapi->tx_desc_mapping,
  6951. GFP_KERNEL);
  6952. if (!tnapi->tx_ring)
  6953. goto err_out;
  6954. }
  6955. return 0;
  6956. err_out:
  6957. tg3_mem_tx_release(tp);
  6958. return -ENOMEM;
  6959. }
  6960. static void tg3_mem_rx_release(struct tg3 *tp)
  6961. {
  6962. int i;
  6963. for (i = 0; i < tp->irq_max; i++) {
  6964. struct tg3_napi *tnapi = &tp->napi[i];
  6965. tg3_rx_prodring_fini(tp, &tnapi->prodring);
  6966. if (!tnapi->rx_rcb)
  6967. continue;
  6968. dma_free_coherent(&tp->pdev->dev,
  6969. TG3_RX_RCB_RING_BYTES(tp),
  6970. tnapi->rx_rcb,
  6971. tnapi->rx_rcb_mapping);
  6972. tnapi->rx_rcb = NULL;
  6973. }
  6974. }
  6975. static int tg3_mem_rx_acquire(struct tg3 *tp)
  6976. {
  6977. unsigned int i, limit;
  6978. limit = tp->rxq_cnt;
  6979. /* If RSS is enabled, we need a (dummy) producer ring
  6980. * set on vector zero. This is the true hw prodring.
  6981. */
  6982. if (tg3_flag(tp, ENABLE_RSS))
  6983. limit++;
  6984. for (i = 0; i < limit; i++) {
  6985. struct tg3_napi *tnapi = &tp->napi[i];
  6986. if (tg3_rx_prodring_init(tp, &tnapi->prodring))
  6987. goto err_out;
  6988. /* If multivector RSS is enabled, vector 0
  6989. * does not handle rx or tx interrupts.
  6990. * Don't allocate any resources for it.
  6991. */
  6992. if (!i && tg3_flag(tp, ENABLE_RSS))
  6993. continue;
  6994. tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
  6995. TG3_RX_RCB_RING_BYTES(tp),
  6996. &tnapi->rx_rcb_mapping,
  6997. GFP_KERNEL | __GFP_ZERO);
  6998. if (!tnapi->rx_rcb)
  6999. goto err_out;
  7000. }
  7001. return 0;
  7002. err_out:
  7003. tg3_mem_rx_release(tp);
  7004. return -ENOMEM;
  7005. }
  7006. /*
  7007. * Must not be invoked with interrupt sources disabled and
  7008. * the hardware shutdown down.
  7009. */
  7010. static void tg3_free_consistent(struct tg3 *tp)
  7011. {
  7012. int i;
  7013. for (i = 0; i < tp->irq_cnt; i++) {
  7014. struct tg3_napi *tnapi = &tp->napi[i];
  7015. if (tnapi->hw_status) {
  7016. dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
  7017. tnapi->hw_status,
  7018. tnapi->status_mapping);
  7019. tnapi->hw_status = NULL;
  7020. }
  7021. }
  7022. tg3_mem_rx_release(tp);
  7023. tg3_mem_tx_release(tp);
  7024. if (tp->hw_stats) {
  7025. dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
  7026. tp->hw_stats, tp->stats_mapping);
  7027. tp->hw_stats = NULL;
  7028. }
  7029. }
  7030. /*
  7031. * Must not be invoked with interrupt sources disabled and
  7032. * the hardware shutdown down. Can sleep.
  7033. */
  7034. static int tg3_alloc_consistent(struct tg3 *tp)
  7035. {
  7036. int i;
  7037. tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
  7038. sizeof(struct tg3_hw_stats),
  7039. &tp->stats_mapping,
  7040. GFP_KERNEL | __GFP_ZERO);
  7041. if (!tp->hw_stats)
  7042. goto err_out;
  7043. for (i = 0; i < tp->irq_cnt; i++) {
  7044. struct tg3_napi *tnapi = &tp->napi[i];
  7045. struct tg3_hw_status *sblk;
  7046. tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
  7047. TG3_HW_STATUS_SIZE,
  7048. &tnapi->status_mapping,
  7049. GFP_KERNEL | __GFP_ZERO);
  7050. if (!tnapi->hw_status)
  7051. goto err_out;
  7052. sblk = tnapi->hw_status;
  7053. if (tg3_flag(tp, ENABLE_RSS)) {
  7054. u16 *prodptr = NULL;
  7055. /*
  7056. * When RSS is enabled, the status block format changes
  7057. * slightly. The "rx_jumbo_consumer", "reserved",
  7058. * and "rx_mini_consumer" members get mapped to the
  7059. * other three rx return ring producer indexes.
  7060. */
  7061. switch (i) {
  7062. case 1:
  7063. prodptr = &sblk->idx[0].rx_producer;
  7064. break;
  7065. case 2:
  7066. prodptr = &sblk->rx_jumbo_consumer;
  7067. break;
  7068. case 3:
  7069. prodptr = &sblk->reserved;
  7070. break;
  7071. case 4:
  7072. prodptr = &sblk->rx_mini_consumer;
  7073. break;
  7074. }
  7075. tnapi->rx_rcb_prod_idx = prodptr;
  7076. } else {
  7077. tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
  7078. }
  7079. }
  7080. if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
  7081. goto err_out;
  7082. return 0;
  7083. err_out:
  7084. tg3_free_consistent(tp);
  7085. return -ENOMEM;
  7086. }
  7087. #define MAX_WAIT_CNT 1000
  7088. /* To stop a block, clear the enable bit and poll till it
  7089. * clears. tp->lock is held.
  7090. */
  7091. static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
  7092. {
  7093. unsigned int i;
  7094. u32 val;
  7095. if (tg3_flag(tp, 5705_PLUS)) {
  7096. switch (ofs) {
  7097. case RCVLSC_MODE:
  7098. case DMAC_MODE:
  7099. case MBFREE_MODE:
  7100. case BUFMGR_MODE:
  7101. case MEMARB_MODE:
  7102. /* We can't enable/disable these bits of the
  7103. * 5705/5750, just say success.
  7104. */
  7105. return 0;
  7106. default:
  7107. break;
  7108. }
  7109. }
  7110. val = tr32(ofs);
  7111. val &= ~enable_bit;
  7112. tw32_f(ofs, val);
  7113. for (i = 0; i < MAX_WAIT_CNT; i++) {
  7114. udelay(100);
  7115. val = tr32(ofs);
  7116. if ((val & enable_bit) == 0)
  7117. break;
  7118. }
  7119. if (i == MAX_WAIT_CNT && !silent) {
  7120. dev_err(&tp->pdev->dev,
  7121. "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
  7122. ofs, enable_bit);
  7123. return -ENODEV;
  7124. }
  7125. return 0;
  7126. }
  7127. /* tp->lock is held. */
  7128. static int tg3_abort_hw(struct tg3 *tp, bool silent)
  7129. {
  7130. int i, err;
  7131. tg3_disable_ints(tp);
  7132. tp->rx_mode &= ~RX_MODE_ENABLE;
  7133. tw32_f(MAC_RX_MODE, tp->rx_mode);
  7134. udelay(10);
  7135. err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
  7136. err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
  7137. err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
  7138. err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
  7139. err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
  7140. err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
  7141. err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
  7142. err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
  7143. err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
  7144. err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
  7145. err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
  7146. err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
  7147. err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
  7148. tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  7149. tw32_f(MAC_MODE, tp->mac_mode);
  7150. udelay(40);
  7151. tp->tx_mode &= ~TX_MODE_ENABLE;
  7152. tw32_f(MAC_TX_MODE, tp->tx_mode);
  7153. for (i = 0; i < MAX_WAIT_CNT; i++) {
  7154. udelay(100);
  7155. if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
  7156. break;
  7157. }
  7158. if (i >= MAX_WAIT_CNT) {
  7159. dev_err(&tp->pdev->dev,
  7160. "%s timed out, TX_MODE_ENABLE will not clear "
  7161. "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
  7162. err |= -ENODEV;
  7163. }
  7164. err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
  7165. err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
  7166. err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
  7167. tw32(FTQ_RESET, 0xffffffff);
  7168. tw32(FTQ_RESET, 0x00000000);
  7169. err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
  7170. err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
  7171. for (i = 0; i < tp->irq_cnt; i++) {
  7172. struct tg3_napi *tnapi = &tp->napi[i];
  7173. if (tnapi->hw_status)
  7174. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  7175. }
  7176. return err;
  7177. }
  7178. /* Save PCI command register before chip reset */
  7179. static void tg3_save_pci_state(struct tg3 *tp)
  7180. {
  7181. pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
  7182. }
  7183. /* Restore PCI state after chip reset */
  7184. static void tg3_restore_pci_state(struct tg3 *tp)
  7185. {
  7186. u32 val;
  7187. /* Re-enable indirect register accesses. */
  7188. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  7189. tp->misc_host_ctrl);
  7190. /* Set MAX PCI retry to zero. */
  7191. val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
  7192. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
  7193. tg3_flag(tp, PCIX_MODE))
  7194. val |= PCISTATE_RETRY_SAME_DMA;
  7195. /* Allow reads and writes to the APE register and memory space. */
  7196. if (tg3_flag(tp, ENABLE_APE))
  7197. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  7198. PCISTATE_ALLOW_APE_SHMEM_WR |
  7199. PCISTATE_ALLOW_APE_PSPACE_WR;
  7200. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
  7201. pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
  7202. if (!tg3_flag(tp, PCI_EXPRESS)) {
  7203. pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  7204. tp->pci_cacheline_sz);
  7205. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  7206. tp->pci_lat_timer);
  7207. }
  7208. /* Make sure PCI-X relaxed ordering bit is clear. */
  7209. if (tg3_flag(tp, PCIX_MODE)) {
  7210. u16 pcix_cmd;
  7211. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  7212. &pcix_cmd);
  7213. pcix_cmd &= ~PCI_X_CMD_ERO;
  7214. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  7215. pcix_cmd);
  7216. }
  7217. if (tg3_flag(tp, 5780_CLASS)) {
  7218. /* Chip reset on 5780 will reset MSI enable bit,
  7219. * so need to restore it.
  7220. */
  7221. if (tg3_flag(tp, USING_MSI)) {
  7222. u16 ctrl;
  7223. pci_read_config_word(tp->pdev,
  7224. tp->msi_cap + PCI_MSI_FLAGS,
  7225. &ctrl);
  7226. pci_write_config_word(tp->pdev,
  7227. tp->msi_cap + PCI_MSI_FLAGS,
  7228. ctrl | PCI_MSI_FLAGS_ENABLE);
  7229. val = tr32(MSGINT_MODE);
  7230. tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
  7231. }
  7232. }
  7233. }
  7234. /* tp->lock is held. */
  7235. static int tg3_chip_reset(struct tg3 *tp)
  7236. {
  7237. u32 val;
  7238. void (*write_op)(struct tg3 *, u32, u32);
  7239. int i, err;
  7240. tg3_nvram_lock(tp);
  7241. tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
  7242. /* No matching tg3_nvram_unlock() after this because
  7243. * chip reset below will undo the nvram lock.
  7244. */
  7245. tp->nvram_lock_cnt = 0;
  7246. /* GRC_MISC_CFG core clock reset will clear the memory
  7247. * enable bit in PCI register 4 and the MSI enable bit
  7248. * on some chips, so we save relevant registers here.
  7249. */
  7250. tg3_save_pci_state(tp);
  7251. if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
  7252. tg3_flag(tp, 5755_PLUS))
  7253. tw32(GRC_FASTBOOT_PC, 0);
  7254. /*
  7255. * We must avoid the readl() that normally takes place.
  7256. * It locks machines, causes machine checks, and other
  7257. * fun things. So, temporarily disable the 5701
  7258. * hardware workaround, while we do the reset.
  7259. */
  7260. write_op = tp->write32;
  7261. if (write_op == tg3_write_flush_reg32)
  7262. tp->write32 = tg3_write32;
  7263. /* Prevent the irq handler from reading or writing PCI registers
  7264. * during chip reset when the memory enable bit in the PCI command
  7265. * register may be cleared. The chip does not generate interrupt
  7266. * at this time, but the irq handler may still be called due to irq
  7267. * sharing or irqpoll.
  7268. */
  7269. tg3_flag_set(tp, CHIP_RESETTING);
  7270. for (i = 0; i < tp->irq_cnt; i++) {
  7271. struct tg3_napi *tnapi = &tp->napi[i];
  7272. if (tnapi->hw_status) {
  7273. tnapi->hw_status->status = 0;
  7274. tnapi->hw_status->status_tag = 0;
  7275. }
  7276. tnapi->last_tag = 0;
  7277. tnapi->last_irq_tag = 0;
  7278. }
  7279. smp_mb();
  7280. for (i = 0; i < tp->irq_cnt; i++)
  7281. synchronize_irq(tp->napi[i].irq_vec);
  7282. if (tg3_asic_rev(tp) == ASIC_REV_57780) {
  7283. val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
  7284. tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
  7285. }
  7286. /* do the reset */
  7287. val = GRC_MISC_CFG_CORECLK_RESET;
  7288. if (tg3_flag(tp, PCI_EXPRESS)) {
  7289. /* Force PCIe 1.0a mode */
  7290. if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
  7291. !tg3_flag(tp, 57765_PLUS) &&
  7292. tr32(TG3_PCIE_PHY_TSTCTL) ==
  7293. (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
  7294. tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
  7295. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
  7296. tw32(GRC_MISC_CFG, (1 << 29));
  7297. val |= (1 << 29);
  7298. }
  7299. }
  7300. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  7301. tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
  7302. tw32(GRC_VCPU_EXT_CTRL,
  7303. tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
  7304. }
  7305. /* Manage gphy power for all CPMU absent PCIe devices. */
  7306. if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
  7307. val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  7308. tw32(GRC_MISC_CFG, val);
  7309. /* restore 5701 hardware bug workaround write method */
  7310. tp->write32 = write_op;
  7311. /* Unfortunately, we have to delay before the PCI read back.
  7312. * Some 575X chips even will not respond to a PCI cfg access
  7313. * when the reset command is given to the chip.
  7314. *
  7315. * How do these hardware designers expect things to work
  7316. * properly if the PCI write is posted for a long period
  7317. * of time? It is always necessary to have some method by
  7318. * which a register read back can occur to push the write
  7319. * out which does the reset.
  7320. *
  7321. * For most tg3 variants the trick below was working.
  7322. * Ho hum...
  7323. */
  7324. udelay(120);
  7325. /* Flush PCI posted writes. The normal MMIO registers
  7326. * are inaccessible at this time so this is the only
  7327. * way to make this reliably (actually, this is no longer
  7328. * the case, see above). I tried to use indirect
  7329. * register read/write but this upset some 5701 variants.
  7330. */
  7331. pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
  7332. udelay(120);
  7333. if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
  7334. u16 val16;
  7335. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
  7336. int j;
  7337. u32 cfg_val;
  7338. /* Wait for link training to complete. */
  7339. for (j = 0; j < 5000; j++)
  7340. udelay(100);
  7341. pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
  7342. pci_write_config_dword(tp->pdev, 0xc4,
  7343. cfg_val | (1 << 15));
  7344. }
  7345. /* Clear the "no snoop" and "relaxed ordering" bits. */
  7346. val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
  7347. /*
  7348. * Older PCIe devices only support the 128 byte
  7349. * MPS setting. Enforce the restriction.
  7350. */
  7351. if (!tg3_flag(tp, CPMU_PRESENT))
  7352. val16 |= PCI_EXP_DEVCTL_PAYLOAD;
  7353. pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
  7354. /* Clear error status */
  7355. pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
  7356. PCI_EXP_DEVSTA_CED |
  7357. PCI_EXP_DEVSTA_NFED |
  7358. PCI_EXP_DEVSTA_FED |
  7359. PCI_EXP_DEVSTA_URD);
  7360. }
  7361. tg3_restore_pci_state(tp);
  7362. tg3_flag_clear(tp, CHIP_RESETTING);
  7363. tg3_flag_clear(tp, ERROR_PROCESSED);
  7364. val = 0;
  7365. if (tg3_flag(tp, 5780_CLASS))
  7366. val = tr32(MEMARB_MODE);
  7367. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  7368. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
  7369. tg3_stop_fw(tp);
  7370. tw32(0x5000, 0x400);
  7371. }
  7372. if (tg3_flag(tp, IS_SSB_CORE)) {
  7373. /*
  7374. * BCM4785: In order to avoid repercussions from using
  7375. * potentially defective internal ROM, stop the Rx RISC CPU,
  7376. * which is not required.
  7377. */
  7378. tg3_stop_fw(tp);
  7379. tg3_halt_cpu(tp, RX_CPU_BASE);
  7380. }
  7381. err = tg3_poll_fw(tp);
  7382. if (err)
  7383. return err;
  7384. tw32(GRC_MODE, tp->grc_mode);
  7385. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
  7386. val = tr32(0xc4);
  7387. tw32(0xc4, val | (1 << 15));
  7388. }
  7389. if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
  7390. tg3_asic_rev(tp) == ASIC_REV_5705) {
  7391. tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
  7392. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
  7393. tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
  7394. tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  7395. }
  7396. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  7397. tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
  7398. val = tp->mac_mode;
  7399. } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
  7400. tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
  7401. val = tp->mac_mode;
  7402. } else
  7403. val = 0;
  7404. tw32_f(MAC_MODE, val);
  7405. udelay(40);
  7406. tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
  7407. tg3_mdio_start(tp);
  7408. if (tg3_flag(tp, PCI_EXPRESS) &&
  7409. tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
  7410. tg3_asic_rev(tp) != ASIC_REV_5785 &&
  7411. !tg3_flag(tp, 57765_PLUS)) {
  7412. val = tr32(0x7c00);
  7413. tw32(0x7c00, val | (1 << 25));
  7414. }
  7415. if (tg3_asic_rev(tp) == ASIC_REV_5720) {
  7416. val = tr32(TG3_CPMU_CLCK_ORIDE);
  7417. tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
  7418. }
  7419. /* Reprobe ASF enable state. */
  7420. tg3_flag_clear(tp, ENABLE_ASF);
  7421. tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
  7422. TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
  7423. tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
  7424. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  7425. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  7426. u32 nic_cfg;
  7427. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  7428. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  7429. tg3_flag_set(tp, ENABLE_ASF);
  7430. tp->last_event_jiffies = jiffies;
  7431. if (tg3_flag(tp, 5750_PLUS))
  7432. tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
  7433. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
  7434. if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
  7435. tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
  7436. if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
  7437. tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
  7438. }
  7439. }
  7440. return 0;
  7441. }
  7442. static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
  7443. static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
  7444. /* tp->lock is held. */
  7445. static int tg3_halt(struct tg3 *tp, int kind, bool silent)
  7446. {
  7447. int err;
  7448. tg3_stop_fw(tp);
  7449. tg3_write_sig_pre_reset(tp, kind);
  7450. tg3_abort_hw(tp, silent);
  7451. err = tg3_chip_reset(tp);
  7452. __tg3_set_mac_addr(tp, false);
  7453. tg3_write_sig_legacy(tp, kind);
  7454. tg3_write_sig_post_reset(tp, kind);
  7455. if (tp->hw_stats) {
  7456. /* Save the stats across chip resets... */
  7457. tg3_get_nstats(tp, &tp->net_stats_prev);
  7458. tg3_get_estats(tp, &tp->estats_prev);
  7459. /* And make sure the next sample is new data */
  7460. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  7461. }
  7462. if (err)
  7463. return err;
  7464. return 0;
  7465. }
  7466. static int tg3_set_mac_addr(struct net_device *dev, void *p)
  7467. {
  7468. struct tg3 *tp = netdev_priv(dev);
  7469. struct sockaddr *addr = p;
  7470. int err = 0;
  7471. bool skip_mac_1 = false;
  7472. if (!is_valid_ether_addr(addr->sa_data))
  7473. return -EADDRNOTAVAIL;
  7474. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  7475. if (!netif_running(dev))
  7476. return 0;
  7477. if (tg3_flag(tp, ENABLE_ASF)) {
  7478. u32 addr0_high, addr0_low, addr1_high, addr1_low;
  7479. addr0_high = tr32(MAC_ADDR_0_HIGH);
  7480. addr0_low = tr32(MAC_ADDR_0_LOW);
  7481. addr1_high = tr32(MAC_ADDR_1_HIGH);
  7482. addr1_low = tr32(MAC_ADDR_1_LOW);
  7483. /* Skip MAC addr 1 if ASF is using it. */
  7484. if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
  7485. !(addr1_high == 0 && addr1_low == 0))
  7486. skip_mac_1 = true;
  7487. }
  7488. spin_lock_bh(&tp->lock);
  7489. __tg3_set_mac_addr(tp, skip_mac_1);
  7490. spin_unlock_bh(&tp->lock);
  7491. return err;
  7492. }
  7493. /* tp->lock is held. */
  7494. static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
  7495. dma_addr_t mapping, u32 maxlen_flags,
  7496. u32 nic_addr)
  7497. {
  7498. tg3_write_mem(tp,
  7499. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
  7500. ((u64) mapping >> 32));
  7501. tg3_write_mem(tp,
  7502. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
  7503. ((u64) mapping & 0xffffffff));
  7504. tg3_write_mem(tp,
  7505. (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
  7506. maxlen_flags);
  7507. if (!tg3_flag(tp, 5705_PLUS))
  7508. tg3_write_mem(tp,
  7509. (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
  7510. nic_addr);
  7511. }
  7512. static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
  7513. {
  7514. int i = 0;
  7515. if (!tg3_flag(tp, ENABLE_TSS)) {
  7516. tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
  7517. tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
  7518. tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
  7519. } else {
  7520. tw32(HOSTCC_TXCOL_TICKS, 0);
  7521. tw32(HOSTCC_TXMAX_FRAMES, 0);
  7522. tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
  7523. for (; i < tp->txq_cnt; i++) {
  7524. u32 reg;
  7525. reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
  7526. tw32(reg, ec->tx_coalesce_usecs);
  7527. reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
  7528. tw32(reg, ec->tx_max_coalesced_frames);
  7529. reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
  7530. tw32(reg, ec->tx_max_coalesced_frames_irq);
  7531. }
  7532. }
  7533. for (; i < tp->irq_max - 1; i++) {
  7534. tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
  7535. tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
  7536. tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
  7537. }
  7538. }
  7539. static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
  7540. {
  7541. int i = 0;
  7542. u32 limit = tp->rxq_cnt;
  7543. if (!tg3_flag(tp, ENABLE_RSS)) {
  7544. tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
  7545. tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
  7546. tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
  7547. limit--;
  7548. } else {
  7549. tw32(HOSTCC_RXCOL_TICKS, 0);
  7550. tw32(HOSTCC_RXMAX_FRAMES, 0);
  7551. tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
  7552. }
  7553. for (; i < limit; i++) {
  7554. u32 reg;
  7555. reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
  7556. tw32(reg, ec->rx_coalesce_usecs);
  7557. reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
  7558. tw32(reg, ec->rx_max_coalesced_frames);
  7559. reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
  7560. tw32(reg, ec->rx_max_coalesced_frames_irq);
  7561. }
  7562. for (; i < tp->irq_max - 1; i++) {
  7563. tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
  7564. tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
  7565. tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
  7566. }
  7567. }
  7568. static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
  7569. {
  7570. tg3_coal_tx_init(tp, ec);
  7571. tg3_coal_rx_init(tp, ec);
  7572. if (!tg3_flag(tp, 5705_PLUS)) {
  7573. u32 val = ec->stats_block_coalesce_usecs;
  7574. tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
  7575. tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
  7576. if (!tp->link_up)
  7577. val = 0;
  7578. tw32(HOSTCC_STAT_COAL_TICKS, val);
  7579. }
  7580. }
  7581. /* tp->lock is held. */
  7582. static void tg3_tx_rcbs_disable(struct tg3 *tp)
  7583. {
  7584. u32 txrcb, limit;
  7585. /* Disable all transmit rings but the first. */
  7586. if (!tg3_flag(tp, 5705_PLUS))
  7587. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
  7588. else if (tg3_flag(tp, 5717_PLUS))
  7589. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
  7590. else if (tg3_flag(tp, 57765_CLASS) ||
  7591. tg3_asic_rev(tp) == ASIC_REV_5762)
  7592. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
  7593. else
  7594. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
  7595. for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
  7596. txrcb < limit; txrcb += TG3_BDINFO_SIZE)
  7597. tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
  7598. BDINFO_FLAGS_DISABLED);
  7599. }
  7600. /* tp->lock is held. */
  7601. static void tg3_tx_rcbs_init(struct tg3 *tp)
  7602. {
  7603. int i = 0;
  7604. u32 txrcb = NIC_SRAM_SEND_RCB;
  7605. if (tg3_flag(tp, ENABLE_TSS))
  7606. i++;
  7607. for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
  7608. struct tg3_napi *tnapi = &tp->napi[i];
  7609. if (!tnapi->tx_ring)
  7610. continue;
  7611. tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
  7612. (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
  7613. NIC_SRAM_TX_BUFFER_DESC);
  7614. }
  7615. }
  7616. /* tp->lock is held. */
  7617. static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
  7618. {
  7619. u32 rxrcb, limit;
  7620. /* Disable all receive return rings but the first. */
  7621. if (tg3_flag(tp, 5717_PLUS))
  7622. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
  7623. else if (!tg3_flag(tp, 5705_PLUS))
  7624. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
  7625. else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  7626. tg3_asic_rev(tp) == ASIC_REV_5762 ||
  7627. tg3_flag(tp, 57765_CLASS))
  7628. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
  7629. else
  7630. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
  7631. for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
  7632. rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
  7633. tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
  7634. BDINFO_FLAGS_DISABLED);
  7635. }
  7636. /* tp->lock is held. */
  7637. static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
  7638. {
  7639. int i = 0;
  7640. u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
  7641. if (tg3_flag(tp, ENABLE_RSS))
  7642. i++;
  7643. for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
  7644. struct tg3_napi *tnapi = &tp->napi[i];
  7645. if (!tnapi->rx_rcb)
  7646. continue;
  7647. tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
  7648. (tp->rx_ret_ring_mask + 1) <<
  7649. BDINFO_FLAGS_MAXLEN_SHIFT, 0);
  7650. }
  7651. }
  7652. /* tp->lock is held. */
  7653. static void tg3_rings_reset(struct tg3 *tp)
  7654. {
  7655. int i;
  7656. u32 stblk;
  7657. struct tg3_napi *tnapi = &tp->napi[0];
  7658. tg3_tx_rcbs_disable(tp);
  7659. tg3_rx_ret_rcbs_disable(tp);
  7660. /* Disable interrupts */
  7661. tw32_mailbox_f(tp->napi[0].int_mbox, 1);
  7662. tp->napi[0].chk_msi_cnt = 0;
  7663. tp->napi[0].last_rx_cons = 0;
  7664. tp->napi[0].last_tx_cons = 0;
  7665. /* Zero mailbox registers. */
  7666. if (tg3_flag(tp, SUPPORT_MSIX)) {
  7667. for (i = 1; i < tp->irq_max; i++) {
  7668. tp->napi[i].tx_prod = 0;
  7669. tp->napi[i].tx_cons = 0;
  7670. if (tg3_flag(tp, ENABLE_TSS))
  7671. tw32_mailbox(tp->napi[i].prodmbox, 0);
  7672. tw32_rx_mbox(tp->napi[i].consmbox, 0);
  7673. tw32_mailbox_f(tp->napi[i].int_mbox, 1);
  7674. tp->napi[i].chk_msi_cnt = 0;
  7675. tp->napi[i].last_rx_cons = 0;
  7676. tp->napi[i].last_tx_cons = 0;
  7677. }
  7678. if (!tg3_flag(tp, ENABLE_TSS))
  7679. tw32_mailbox(tp->napi[0].prodmbox, 0);
  7680. } else {
  7681. tp->napi[0].tx_prod = 0;
  7682. tp->napi[0].tx_cons = 0;
  7683. tw32_mailbox(tp->napi[0].prodmbox, 0);
  7684. tw32_rx_mbox(tp->napi[0].consmbox, 0);
  7685. }
  7686. /* Make sure the NIC-based send BD rings are disabled. */
  7687. if (!tg3_flag(tp, 5705_PLUS)) {
  7688. u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
  7689. for (i = 0; i < 16; i++)
  7690. tw32_tx_mbox(mbox + i * 8, 0);
  7691. }
  7692. /* Clear status block in ram. */
  7693. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  7694. /* Set status block DMA address */
  7695. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  7696. ((u64) tnapi->status_mapping >> 32));
  7697. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  7698. ((u64) tnapi->status_mapping & 0xffffffff));
  7699. stblk = HOSTCC_STATBLCK_RING1;
  7700. for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
  7701. u64 mapping = (u64)tnapi->status_mapping;
  7702. tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
  7703. tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
  7704. stblk += 8;
  7705. /* Clear status block in ram. */
  7706. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  7707. }
  7708. tg3_tx_rcbs_init(tp);
  7709. tg3_rx_ret_rcbs_init(tp);
  7710. }
  7711. static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
  7712. {
  7713. u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
  7714. if (!tg3_flag(tp, 5750_PLUS) ||
  7715. tg3_flag(tp, 5780_CLASS) ||
  7716. tg3_asic_rev(tp) == ASIC_REV_5750 ||
  7717. tg3_asic_rev(tp) == ASIC_REV_5752 ||
  7718. tg3_flag(tp, 57765_PLUS))
  7719. bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
  7720. else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  7721. tg3_asic_rev(tp) == ASIC_REV_5787)
  7722. bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
  7723. else
  7724. bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
  7725. nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
  7726. host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
  7727. val = min(nic_rep_thresh, host_rep_thresh);
  7728. tw32(RCVBDI_STD_THRESH, val);
  7729. if (tg3_flag(tp, 57765_PLUS))
  7730. tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
  7731. if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
  7732. return;
  7733. bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
  7734. host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
  7735. val = min(bdcache_maxcnt / 2, host_rep_thresh);
  7736. tw32(RCVBDI_JUMBO_THRESH, val);
  7737. if (tg3_flag(tp, 57765_PLUS))
  7738. tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
  7739. }
  7740. static inline u32 calc_crc(unsigned char *buf, int len)
  7741. {
  7742. u32 reg;
  7743. u32 tmp;
  7744. int j, k;
  7745. reg = 0xffffffff;
  7746. for (j = 0; j < len; j++) {
  7747. reg ^= buf[j];
  7748. for (k = 0; k < 8; k++) {
  7749. tmp = reg & 0x01;
  7750. reg >>= 1;
  7751. if (tmp)
  7752. reg ^= 0xedb88320;
  7753. }
  7754. }
  7755. return ~reg;
  7756. }
  7757. static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
  7758. {
  7759. /* accept or reject all multicast frames */
  7760. tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
  7761. tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
  7762. tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
  7763. tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
  7764. }
  7765. static void __tg3_set_rx_mode(struct net_device *dev)
  7766. {
  7767. struct tg3 *tp = netdev_priv(dev);
  7768. u32 rx_mode;
  7769. rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
  7770. RX_MODE_KEEP_VLAN_TAG);
  7771. #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
  7772. /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
  7773. * flag clear.
  7774. */
  7775. if (!tg3_flag(tp, ENABLE_ASF))
  7776. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  7777. #endif
  7778. if (dev->flags & IFF_PROMISC) {
  7779. /* Promiscuous mode. */
  7780. rx_mode |= RX_MODE_PROMISC;
  7781. } else if (dev->flags & IFF_ALLMULTI) {
  7782. /* Accept all multicast. */
  7783. tg3_set_multi(tp, 1);
  7784. } else if (netdev_mc_empty(dev)) {
  7785. /* Reject all multicast. */
  7786. tg3_set_multi(tp, 0);
  7787. } else {
  7788. /* Accept one or more multicast(s). */
  7789. struct netdev_hw_addr *ha;
  7790. u32 mc_filter[4] = { 0, };
  7791. u32 regidx;
  7792. u32 bit;
  7793. u32 crc;
  7794. netdev_for_each_mc_addr(ha, dev) {
  7795. crc = calc_crc(ha->addr, ETH_ALEN);
  7796. bit = ~crc & 0x7f;
  7797. regidx = (bit & 0x60) >> 5;
  7798. bit &= 0x1f;
  7799. mc_filter[regidx] |= (1 << bit);
  7800. }
  7801. tw32(MAC_HASH_REG_0, mc_filter[0]);
  7802. tw32(MAC_HASH_REG_1, mc_filter[1]);
  7803. tw32(MAC_HASH_REG_2, mc_filter[2]);
  7804. tw32(MAC_HASH_REG_3, mc_filter[3]);
  7805. }
  7806. if (rx_mode != tp->rx_mode) {
  7807. tp->rx_mode = rx_mode;
  7808. tw32_f(MAC_RX_MODE, rx_mode);
  7809. udelay(10);
  7810. }
  7811. }
  7812. static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
  7813. {
  7814. int i;
  7815. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
  7816. tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
  7817. }
  7818. static void tg3_rss_check_indir_tbl(struct tg3 *tp)
  7819. {
  7820. int i;
  7821. if (!tg3_flag(tp, SUPPORT_MSIX))
  7822. return;
  7823. if (tp->rxq_cnt == 1) {
  7824. memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
  7825. return;
  7826. }
  7827. /* Validate table against current IRQ count */
  7828. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
  7829. if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
  7830. break;
  7831. }
  7832. if (i != TG3_RSS_INDIR_TBL_SIZE)
  7833. tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
  7834. }
  7835. static void tg3_rss_write_indir_tbl(struct tg3 *tp)
  7836. {
  7837. int i = 0;
  7838. u32 reg = MAC_RSS_INDIR_TBL_0;
  7839. while (i < TG3_RSS_INDIR_TBL_SIZE) {
  7840. u32 val = tp->rss_ind_tbl[i];
  7841. i++;
  7842. for (; i % 8; i++) {
  7843. val <<= 4;
  7844. val |= tp->rss_ind_tbl[i];
  7845. }
  7846. tw32(reg, val);
  7847. reg += 4;
  7848. }
  7849. }
  7850. static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
  7851. {
  7852. if (tg3_asic_rev(tp) == ASIC_REV_5719)
  7853. return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
  7854. else
  7855. return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
  7856. }
  7857. /* tp->lock is held. */
  7858. static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
  7859. {
  7860. u32 val, rdmac_mode;
  7861. int i, err, limit;
  7862. struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
  7863. tg3_disable_ints(tp);
  7864. tg3_stop_fw(tp);
  7865. tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
  7866. if (tg3_flag(tp, INIT_COMPLETE))
  7867. tg3_abort_hw(tp, 1);
  7868. if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
  7869. !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
  7870. tg3_phy_pull_config(tp);
  7871. tg3_eee_pull_config(tp, NULL);
  7872. tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
  7873. }
  7874. /* Enable MAC control of LPI */
  7875. if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
  7876. tg3_setup_eee(tp);
  7877. if (reset_phy)
  7878. tg3_phy_reset(tp);
  7879. err = tg3_chip_reset(tp);
  7880. if (err)
  7881. return err;
  7882. tg3_write_sig_legacy(tp, RESET_KIND_INIT);
  7883. if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
  7884. val = tr32(TG3_CPMU_CTRL);
  7885. val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
  7886. tw32(TG3_CPMU_CTRL, val);
  7887. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  7888. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  7889. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  7890. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  7891. val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
  7892. val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
  7893. val |= CPMU_LNK_AWARE_MACCLK_6_25;
  7894. tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
  7895. val = tr32(TG3_CPMU_HST_ACC);
  7896. val &= ~CPMU_HST_ACC_MACCLK_MASK;
  7897. val |= CPMU_HST_ACC_MACCLK_6_25;
  7898. tw32(TG3_CPMU_HST_ACC, val);
  7899. }
  7900. if (tg3_asic_rev(tp) == ASIC_REV_57780) {
  7901. val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
  7902. val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
  7903. PCIE_PWR_MGMT_L1_THRESH_4MS;
  7904. tw32(PCIE_PWR_MGMT_THRESH, val);
  7905. val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
  7906. tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
  7907. tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
  7908. val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
  7909. tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
  7910. }
  7911. if (tg3_flag(tp, L1PLLPD_EN)) {
  7912. u32 grc_mode = tr32(GRC_MODE);
  7913. /* Access the lower 1K of PL PCIE block registers. */
  7914. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  7915. tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
  7916. val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
  7917. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
  7918. val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
  7919. tw32(GRC_MODE, grc_mode);
  7920. }
  7921. if (tg3_flag(tp, 57765_CLASS)) {
  7922. if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
  7923. u32 grc_mode = tr32(GRC_MODE);
  7924. /* Access the lower 1K of PL PCIE block registers. */
  7925. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  7926. tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
  7927. val = tr32(TG3_PCIE_TLDLPL_PORT +
  7928. TG3_PCIE_PL_LO_PHYCTL5);
  7929. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
  7930. val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
  7931. tw32(GRC_MODE, grc_mode);
  7932. }
  7933. if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
  7934. u32 grc_mode;
  7935. /* Fix transmit hangs */
  7936. val = tr32(TG3_CPMU_PADRNG_CTL);
  7937. val |= TG3_CPMU_PADRNG_CTL_RDIV2;
  7938. tw32(TG3_CPMU_PADRNG_CTL, val);
  7939. grc_mode = tr32(GRC_MODE);
  7940. /* Access the lower 1K of DL PCIE block registers. */
  7941. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  7942. tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
  7943. val = tr32(TG3_PCIE_TLDLPL_PORT +
  7944. TG3_PCIE_DL_LO_FTSMAX);
  7945. val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
  7946. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
  7947. val | TG3_PCIE_DL_LO_FTSMAX_VAL);
  7948. tw32(GRC_MODE, grc_mode);
  7949. }
  7950. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  7951. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  7952. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  7953. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  7954. }
  7955. /* This works around an issue with Athlon chipsets on
  7956. * B3 tigon3 silicon. This bit has no effect on any
  7957. * other revision. But do not set this on PCI Express
  7958. * chips and don't even touch the clocks if the CPMU is present.
  7959. */
  7960. if (!tg3_flag(tp, CPMU_PRESENT)) {
  7961. if (!tg3_flag(tp, PCI_EXPRESS))
  7962. tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  7963. tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  7964. }
  7965. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
  7966. tg3_flag(tp, PCIX_MODE)) {
  7967. val = tr32(TG3PCI_PCISTATE);
  7968. val |= PCISTATE_RETRY_SAME_DMA;
  7969. tw32(TG3PCI_PCISTATE, val);
  7970. }
  7971. if (tg3_flag(tp, ENABLE_APE)) {
  7972. /* Allow reads and writes to the
  7973. * APE register and memory space.
  7974. */
  7975. val = tr32(TG3PCI_PCISTATE);
  7976. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  7977. PCISTATE_ALLOW_APE_SHMEM_WR |
  7978. PCISTATE_ALLOW_APE_PSPACE_WR;
  7979. tw32(TG3PCI_PCISTATE, val);
  7980. }
  7981. if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
  7982. /* Enable some hw fixes. */
  7983. val = tr32(TG3PCI_MSI_DATA);
  7984. val |= (1 << 26) | (1 << 28) | (1 << 29);
  7985. tw32(TG3PCI_MSI_DATA, val);
  7986. }
  7987. /* Descriptor ring init may make accesses to the
  7988. * NIC SRAM area to setup the TX descriptors, so we
  7989. * can only do this after the hardware has been
  7990. * successfully reset.
  7991. */
  7992. err = tg3_init_rings(tp);
  7993. if (err)
  7994. return err;
  7995. if (tg3_flag(tp, 57765_PLUS)) {
  7996. val = tr32(TG3PCI_DMA_RW_CTRL) &
  7997. ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
  7998. if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
  7999. val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
  8000. if (!tg3_flag(tp, 57765_CLASS) &&
  8001. tg3_asic_rev(tp) != ASIC_REV_5717 &&
  8002. tg3_asic_rev(tp) != ASIC_REV_5762)
  8003. val |= DMA_RWCTRL_TAGGED_STAT_WA;
  8004. tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
  8005. } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
  8006. tg3_asic_rev(tp) != ASIC_REV_5761) {
  8007. /* This value is determined during the probe time DMA
  8008. * engine test, tg3_test_dma.
  8009. */
  8010. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  8011. }
  8012. tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
  8013. GRC_MODE_4X_NIC_SEND_RINGS |
  8014. GRC_MODE_NO_TX_PHDR_CSUM |
  8015. GRC_MODE_NO_RX_PHDR_CSUM);
  8016. tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
  8017. /* Pseudo-header checksum is done by hardware logic and not
  8018. * the offload processers, so make the chip do the pseudo-
  8019. * header checksums on receive. For transmit it is more
  8020. * convenient to do the pseudo-header checksum in software
  8021. * as Linux does that on transmit for us in all cases.
  8022. */
  8023. tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
  8024. val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
  8025. if (tp->rxptpctl)
  8026. tw32(TG3_RX_PTP_CTL,
  8027. tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
  8028. if (tg3_flag(tp, PTP_CAPABLE))
  8029. val |= GRC_MODE_TIME_SYNC_ENABLE;
  8030. tw32(GRC_MODE, tp->grc_mode | val);
  8031. /* Setup the timer prescalar register. Clock is always 66Mhz. */
  8032. val = tr32(GRC_MISC_CFG);
  8033. val &= ~0xff;
  8034. val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
  8035. tw32(GRC_MISC_CFG, val);
  8036. /* Initialize MBUF/DESC pool. */
  8037. if (tg3_flag(tp, 5750_PLUS)) {
  8038. /* Do nothing. */
  8039. } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
  8040. tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  8041. if (tg3_asic_rev(tp) == ASIC_REV_5704)
  8042. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  8043. else
  8044. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  8045. tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  8046. tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  8047. } else if (tg3_flag(tp, TSO_CAPABLE)) {
  8048. int fw_len;
  8049. fw_len = tp->fw_len;
  8050. fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
  8051. tw32(BUFMGR_MB_POOL_ADDR,
  8052. NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
  8053. tw32(BUFMGR_MB_POOL_SIZE,
  8054. NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
  8055. }
  8056. if (tp->dev->mtu <= ETH_DATA_LEN) {
  8057. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  8058. tp->bufmgr_config.mbuf_read_dma_low_water);
  8059. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  8060. tp->bufmgr_config.mbuf_mac_rx_low_water);
  8061. tw32(BUFMGR_MB_HIGH_WATER,
  8062. tp->bufmgr_config.mbuf_high_water);
  8063. } else {
  8064. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  8065. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
  8066. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  8067. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
  8068. tw32(BUFMGR_MB_HIGH_WATER,
  8069. tp->bufmgr_config.mbuf_high_water_jumbo);
  8070. }
  8071. tw32(BUFMGR_DMA_LOW_WATER,
  8072. tp->bufmgr_config.dma_low_water);
  8073. tw32(BUFMGR_DMA_HIGH_WATER,
  8074. tp->bufmgr_config.dma_high_water);
  8075. val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
  8076. if (tg3_asic_rev(tp) == ASIC_REV_5719)
  8077. val |= BUFMGR_MODE_NO_TX_UNDERRUN;
  8078. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  8079. tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
  8080. tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
  8081. val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
  8082. tw32(BUFMGR_MODE, val);
  8083. for (i = 0; i < 2000; i++) {
  8084. if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
  8085. break;
  8086. udelay(10);
  8087. }
  8088. if (i >= 2000) {
  8089. netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
  8090. return -ENODEV;
  8091. }
  8092. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
  8093. tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
  8094. tg3_setup_rxbd_thresholds(tp);
  8095. /* Initialize TG3_BDINFO's at:
  8096. * RCVDBDI_STD_BD: standard eth size rx ring
  8097. * RCVDBDI_JUMBO_BD: jumbo frame rx ring
  8098. * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
  8099. *
  8100. * like so:
  8101. * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
  8102. * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
  8103. * ring attribute flags
  8104. * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
  8105. *
  8106. * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
  8107. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
  8108. *
  8109. * The size of each ring is fixed in the firmware, but the location is
  8110. * configurable.
  8111. */
  8112. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  8113. ((u64) tpr->rx_std_mapping >> 32));
  8114. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  8115. ((u64) tpr->rx_std_mapping & 0xffffffff));
  8116. if (!tg3_flag(tp, 5717_PLUS))
  8117. tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  8118. NIC_SRAM_RX_BUFFER_DESC);
  8119. /* Disable the mini ring */
  8120. if (!tg3_flag(tp, 5705_PLUS))
  8121. tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  8122. BDINFO_FLAGS_DISABLED);
  8123. /* Program the jumbo buffer descriptor ring control
  8124. * blocks on those devices that have them.
  8125. */
  8126. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
  8127. (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
  8128. if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
  8129. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  8130. ((u64) tpr->rx_jmb_mapping >> 32));
  8131. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  8132. ((u64) tpr->rx_jmb_mapping & 0xffffffff));
  8133. val = TG3_RX_JMB_RING_SIZE(tp) <<
  8134. BDINFO_FLAGS_MAXLEN_SHIFT;
  8135. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  8136. val | BDINFO_FLAGS_USE_EXT_RECV);
  8137. if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
  8138. tg3_flag(tp, 57765_CLASS) ||
  8139. tg3_asic_rev(tp) == ASIC_REV_5762)
  8140. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  8141. NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  8142. } else {
  8143. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  8144. BDINFO_FLAGS_DISABLED);
  8145. }
  8146. if (tg3_flag(tp, 57765_PLUS)) {
  8147. val = TG3_RX_STD_RING_SIZE(tp);
  8148. val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
  8149. val |= (TG3_RX_STD_DMA_SZ << 2);
  8150. } else
  8151. val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
  8152. } else
  8153. val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
  8154. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
  8155. tpr->rx_std_prod_idx = tp->rx_pending;
  8156. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
  8157. tpr->rx_jmb_prod_idx =
  8158. tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
  8159. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
  8160. tg3_rings_reset(tp);
  8161. /* Initialize MAC address and backoff seed. */
  8162. __tg3_set_mac_addr(tp, false);
  8163. /* MTU + ethernet header + FCS + optional VLAN tag */
  8164. tw32(MAC_RX_MTU_SIZE,
  8165. tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  8166. /* The slot time is changed by tg3_setup_phy if we
  8167. * run at gigabit with half duplex.
  8168. */
  8169. val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  8170. (6 << TX_LENGTHS_IPG_SHIFT) |
  8171. (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
  8172. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  8173. tg3_asic_rev(tp) == ASIC_REV_5762)
  8174. val |= tr32(MAC_TX_LENGTHS) &
  8175. (TX_LENGTHS_JMB_FRM_LEN_MSK |
  8176. TX_LENGTHS_CNT_DWN_VAL_MSK);
  8177. tw32(MAC_TX_LENGTHS, val);
  8178. /* Receive rules. */
  8179. tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  8180. tw32(RCVLPC_CONFIG, 0x0181);
  8181. /* Calculate RDMAC_MODE setting early, we need it to determine
  8182. * the RCVLPC_STATE_ENABLE mask.
  8183. */
  8184. rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  8185. RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  8186. RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  8187. RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  8188. RDMAC_MODE_LNGREAD_ENAB);
  8189. if (tg3_asic_rev(tp) == ASIC_REV_5717)
  8190. rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
  8191. if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
  8192. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  8193. tg3_asic_rev(tp) == ASIC_REV_57780)
  8194. rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
  8195. RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
  8196. RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
  8197. if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
  8198. tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
  8199. if (tg3_flag(tp, TSO_CAPABLE) &&
  8200. tg3_asic_rev(tp) == ASIC_REV_5705) {
  8201. rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
  8202. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  8203. !tg3_flag(tp, IS_5788)) {
  8204. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  8205. }
  8206. }
  8207. if (tg3_flag(tp, PCI_EXPRESS))
  8208. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  8209. if (tg3_asic_rev(tp) == ASIC_REV_57766) {
  8210. tp->dma_limit = 0;
  8211. if (tp->dev->mtu <= ETH_DATA_LEN) {
  8212. rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
  8213. tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
  8214. }
  8215. }
  8216. if (tg3_flag(tp, HW_TSO_1) ||
  8217. tg3_flag(tp, HW_TSO_2) ||
  8218. tg3_flag(tp, HW_TSO_3))
  8219. rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
  8220. if (tg3_flag(tp, 57765_PLUS) ||
  8221. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  8222. tg3_asic_rev(tp) == ASIC_REV_57780)
  8223. rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
  8224. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  8225. tg3_asic_rev(tp) == ASIC_REV_5762)
  8226. rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
  8227. if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
  8228. tg3_asic_rev(tp) == ASIC_REV_5784 ||
  8229. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  8230. tg3_asic_rev(tp) == ASIC_REV_57780 ||
  8231. tg3_flag(tp, 57765_PLUS)) {
  8232. u32 tgtreg;
  8233. if (tg3_asic_rev(tp) == ASIC_REV_5762)
  8234. tgtreg = TG3_RDMA_RSRVCTRL_REG2;
  8235. else
  8236. tgtreg = TG3_RDMA_RSRVCTRL_REG;
  8237. val = tr32(tgtreg);
  8238. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
  8239. tg3_asic_rev(tp) == ASIC_REV_5762) {
  8240. val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
  8241. TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
  8242. TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
  8243. val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
  8244. TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
  8245. TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
  8246. }
  8247. tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
  8248. }
  8249. if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  8250. tg3_asic_rev(tp) == ASIC_REV_5720 ||
  8251. tg3_asic_rev(tp) == ASIC_REV_5762) {
  8252. u32 tgtreg;
  8253. if (tg3_asic_rev(tp) == ASIC_REV_5762)
  8254. tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
  8255. else
  8256. tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
  8257. val = tr32(tgtreg);
  8258. tw32(tgtreg, val |
  8259. TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
  8260. TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
  8261. }
  8262. /* Receive/send statistics. */
  8263. if (tg3_flag(tp, 5750_PLUS)) {
  8264. val = tr32(RCVLPC_STATS_ENABLE);
  8265. val &= ~RCVLPC_STATSENAB_DACK_FIX;
  8266. tw32(RCVLPC_STATS_ENABLE, val);
  8267. } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
  8268. tg3_flag(tp, TSO_CAPABLE)) {
  8269. val = tr32(RCVLPC_STATS_ENABLE);
  8270. val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
  8271. tw32(RCVLPC_STATS_ENABLE, val);
  8272. } else {
  8273. tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  8274. }
  8275. tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  8276. tw32(SNDDATAI_STATSENAB, 0xffffff);
  8277. tw32(SNDDATAI_STATSCTRL,
  8278. (SNDDATAI_SCTRL_ENABLE |
  8279. SNDDATAI_SCTRL_FASTUPD));
  8280. /* Setup host coalescing engine. */
  8281. tw32(HOSTCC_MODE, 0);
  8282. for (i = 0; i < 2000; i++) {
  8283. if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
  8284. break;
  8285. udelay(10);
  8286. }
  8287. __tg3_set_coalesce(tp, &tp->coal);
  8288. if (!tg3_flag(tp, 5705_PLUS)) {
  8289. /* Status/statistics block address. See tg3_timer,
  8290. * the tg3_periodic_fetch_stats call there, and
  8291. * tg3_get_stats to see how this works for 5705/5750 chips.
  8292. */
  8293. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  8294. ((u64) tp->stats_mapping >> 32));
  8295. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  8296. ((u64) tp->stats_mapping & 0xffffffff));
  8297. tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  8298. tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  8299. /* Clear statistics and status block memory areas */
  8300. for (i = NIC_SRAM_STATS_BLK;
  8301. i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  8302. i += sizeof(u32)) {
  8303. tg3_write_mem(tp, i, 0);
  8304. udelay(40);
  8305. }
  8306. }
  8307. tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  8308. tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  8309. tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  8310. if (!tg3_flag(tp, 5705_PLUS))
  8311. tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  8312. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
  8313. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  8314. /* reset to prevent losing 1st rx packet intermittently */
  8315. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  8316. udelay(10);
  8317. }
  8318. tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  8319. MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
  8320. MAC_MODE_FHDE_ENABLE;
  8321. if (tg3_flag(tp, ENABLE_APE))
  8322. tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  8323. if (!tg3_flag(tp, 5705_PLUS) &&
  8324. !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  8325. tg3_asic_rev(tp) != ASIC_REV_5700)
  8326. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  8327. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
  8328. udelay(40);
  8329. /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
  8330. * If TG3_FLAG_IS_NIC is zero, we should read the
  8331. * register to preserve the GPIO settings for LOMs. The GPIOs,
  8332. * whether used as inputs or outputs, are set by boot code after
  8333. * reset.
  8334. */
  8335. if (!tg3_flag(tp, IS_NIC)) {
  8336. u32 gpio_mask;
  8337. gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
  8338. GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
  8339. GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
  8340. if (tg3_asic_rev(tp) == ASIC_REV_5752)
  8341. gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
  8342. GRC_LCLCTRL_GPIO_OUTPUT3;
  8343. if (tg3_asic_rev(tp) == ASIC_REV_5755)
  8344. gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
  8345. tp->grc_local_ctrl &= ~gpio_mask;
  8346. tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
  8347. /* GPIO1 must be driven high for eeprom write protect */
  8348. if (tg3_flag(tp, EEPROM_WRITE_PROT))
  8349. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  8350. GRC_LCLCTRL_GPIO_OUTPUT1);
  8351. }
  8352. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  8353. udelay(100);
  8354. if (tg3_flag(tp, USING_MSIX)) {
  8355. val = tr32(MSGINT_MODE);
  8356. val |= MSGINT_MODE_ENABLE;
  8357. if (tp->irq_cnt > 1)
  8358. val |= MSGINT_MODE_MULTIVEC_EN;
  8359. if (!tg3_flag(tp, 1SHOT_MSI))
  8360. val |= MSGINT_MODE_ONE_SHOT_DISABLE;
  8361. tw32(MSGINT_MODE, val);
  8362. }
  8363. if (!tg3_flag(tp, 5705_PLUS)) {
  8364. tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
  8365. udelay(40);
  8366. }
  8367. val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  8368. WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  8369. WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  8370. WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  8371. WDMAC_MODE_LNGREAD_ENAB);
  8372. if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
  8373. tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
  8374. if (tg3_flag(tp, TSO_CAPABLE) &&
  8375. (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
  8376. tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
  8377. /* nothing */
  8378. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  8379. !tg3_flag(tp, IS_5788)) {
  8380. val |= WDMAC_MODE_RX_ACCEL;
  8381. }
  8382. }
  8383. /* Enable host coalescing bug fix */
  8384. if (tg3_flag(tp, 5755_PLUS))
  8385. val |= WDMAC_MODE_STATUS_TAG_FIX;
  8386. if (tg3_asic_rev(tp) == ASIC_REV_5785)
  8387. val |= WDMAC_MODE_BURST_ALL_DATA;
  8388. tw32_f(WDMAC_MODE, val);
  8389. udelay(40);
  8390. if (tg3_flag(tp, PCIX_MODE)) {
  8391. u16 pcix_cmd;
  8392. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  8393. &pcix_cmd);
  8394. if (tg3_asic_rev(tp) == ASIC_REV_5703) {
  8395. pcix_cmd &= ~PCI_X_CMD_MAX_READ;
  8396. pcix_cmd |= PCI_X_CMD_READ_2K;
  8397. } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
  8398. pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
  8399. pcix_cmd |= PCI_X_CMD_READ_2K;
  8400. }
  8401. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  8402. pcix_cmd);
  8403. }
  8404. tw32_f(RDMAC_MODE, rdmac_mode);
  8405. udelay(40);
  8406. if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  8407. tg3_asic_rev(tp) == ASIC_REV_5720) {
  8408. for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
  8409. if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
  8410. break;
  8411. }
  8412. if (i < TG3_NUM_RDMA_CHANNELS) {
  8413. val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
  8414. val |= tg3_lso_rd_dma_workaround_bit(tp);
  8415. tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
  8416. tg3_flag_set(tp, 5719_5720_RDMA_BUG);
  8417. }
  8418. }
  8419. tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  8420. if (!tg3_flag(tp, 5705_PLUS))
  8421. tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  8422. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  8423. tw32(SNDDATAC_MODE,
  8424. SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
  8425. else
  8426. tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  8427. tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  8428. tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  8429. val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
  8430. if (tg3_flag(tp, LRG_PROD_RING_CAP))
  8431. val |= RCVDBDI_MODE_LRG_RING_SZ;
  8432. tw32(RCVDBDI_MODE, val);
  8433. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  8434. if (tg3_flag(tp, HW_TSO_1) ||
  8435. tg3_flag(tp, HW_TSO_2) ||
  8436. tg3_flag(tp, HW_TSO_3))
  8437. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
  8438. val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
  8439. if (tg3_flag(tp, ENABLE_TSS))
  8440. val |= SNDBDI_MODE_MULTI_TXQ_EN;
  8441. tw32(SNDBDI_MODE, val);
  8442. tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
  8443. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
  8444. err = tg3_load_5701_a0_firmware_fix(tp);
  8445. if (err)
  8446. return err;
  8447. }
  8448. if (tg3_asic_rev(tp) == ASIC_REV_57766) {
  8449. /* Ignore any errors for the firmware download. If download
  8450. * fails, the device will operate with EEE disabled
  8451. */
  8452. tg3_load_57766_firmware(tp);
  8453. }
  8454. if (tg3_flag(tp, TSO_CAPABLE)) {
  8455. err = tg3_load_tso_firmware(tp);
  8456. if (err)
  8457. return err;
  8458. }
  8459. tp->tx_mode = TX_MODE_ENABLE;
  8460. if (tg3_flag(tp, 5755_PLUS) ||
  8461. tg3_asic_rev(tp) == ASIC_REV_5906)
  8462. tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
  8463. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  8464. tg3_asic_rev(tp) == ASIC_REV_5762) {
  8465. val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
  8466. tp->tx_mode &= ~val;
  8467. tp->tx_mode |= tr32(MAC_TX_MODE) & val;
  8468. }
  8469. tw32_f(MAC_TX_MODE, tp->tx_mode);
  8470. udelay(100);
  8471. if (tg3_flag(tp, ENABLE_RSS)) {
  8472. tg3_rss_write_indir_tbl(tp);
  8473. /* Setup the "secret" hash key. */
  8474. tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
  8475. tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
  8476. tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
  8477. tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
  8478. tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
  8479. tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
  8480. tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
  8481. tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
  8482. tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
  8483. tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
  8484. }
  8485. tp->rx_mode = RX_MODE_ENABLE;
  8486. if (tg3_flag(tp, 5755_PLUS))
  8487. tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
  8488. if (tg3_flag(tp, ENABLE_RSS))
  8489. tp->rx_mode |= RX_MODE_RSS_ENABLE |
  8490. RX_MODE_RSS_ITBL_HASH_BITS_7 |
  8491. RX_MODE_RSS_IPV6_HASH_EN |
  8492. RX_MODE_RSS_TCP_IPV6_HASH_EN |
  8493. RX_MODE_RSS_IPV4_HASH_EN |
  8494. RX_MODE_RSS_TCP_IPV4_HASH_EN;
  8495. tw32_f(MAC_RX_MODE, tp->rx_mode);
  8496. udelay(10);
  8497. tw32(MAC_LED_CTRL, tp->led_ctrl);
  8498. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  8499. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  8500. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  8501. udelay(10);
  8502. }
  8503. tw32_f(MAC_RX_MODE, tp->rx_mode);
  8504. udelay(10);
  8505. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  8506. if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
  8507. !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
  8508. /* Set drive transmission level to 1.2V */
  8509. /* only if the signal pre-emphasis bit is not set */
  8510. val = tr32(MAC_SERDES_CFG);
  8511. val &= 0xfffff000;
  8512. val |= 0x880;
  8513. tw32(MAC_SERDES_CFG, val);
  8514. }
  8515. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
  8516. tw32(MAC_SERDES_CFG, 0x616000);
  8517. }
  8518. /* Prevent chip from dropping frames when flow control
  8519. * is enabled.
  8520. */
  8521. if (tg3_flag(tp, 57765_CLASS))
  8522. val = 1;
  8523. else
  8524. val = 2;
  8525. tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
  8526. if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
  8527. (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  8528. /* Use hardware link auto-negotiation */
  8529. tg3_flag_set(tp, HW_AUTONEG);
  8530. }
  8531. if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  8532. tg3_asic_rev(tp) == ASIC_REV_5714) {
  8533. u32 tmp;
  8534. tmp = tr32(SERDES_RX_CTRL);
  8535. tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
  8536. tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
  8537. tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
  8538. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  8539. }
  8540. if (!tg3_flag(tp, USE_PHYLIB)) {
  8541. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  8542. tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
  8543. err = tg3_setup_phy(tp, false);
  8544. if (err)
  8545. return err;
  8546. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  8547. !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  8548. u32 tmp;
  8549. /* Clear CRC stats. */
  8550. if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
  8551. tg3_writephy(tp, MII_TG3_TEST1,
  8552. tmp | MII_TG3_TEST1_CRC_EN);
  8553. tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
  8554. }
  8555. }
  8556. }
  8557. __tg3_set_rx_mode(tp->dev);
  8558. /* Initialize receive rules. */
  8559. tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
  8560. tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  8561. tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
  8562. tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  8563. if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
  8564. limit = 8;
  8565. else
  8566. limit = 16;
  8567. if (tg3_flag(tp, ENABLE_ASF))
  8568. limit -= 4;
  8569. switch (limit) {
  8570. case 16:
  8571. tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
  8572. case 15:
  8573. tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
  8574. case 14:
  8575. tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
  8576. case 13:
  8577. tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
  8578. case 12:
  8579. tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
  8580. case 11:
  8581. tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
  8582. case 10:
  8583. tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
  8584. case 9:
  8585. tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
  8586. case 8:
  8587. tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
  8588. case 7:
  8589. tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
  8590. case 6:
  8591. tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
  8592. case 5:
  8593. tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
  8594. case 4:
  8595. /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
  8596. case 3:
  8597. /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
  8598. case 2:
  8599. case 1:
  8600. default:
  8601. break;
  8602. }
  8603. if (tg3_flag(tp, ENABLE_APE))
  8604. /* Write our heartbeat update interval to APE. */
  8605. tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
  8606. APE_HOST_HEARTBEAT_INT_DISABLE);
  8607. tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
  8608. return 0;
  8609. }
  8610. /* Called at device open time to get the chip ready for
  8611. * packet processing. Invoked with tp->lock held.
  8612. */
  8613. static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
  8614. {
  8615. /* Chip may have been just powered on. If so, the boot code may still
  8616. * be running initialization. Wait for it to finish to avoid races in
  8617. * accessing the hardware.
  8618. */
  8619. tg3_enable_register_access(tp);
  8620. tg3_poll_fw(tp);
  8621. tg3_switch_clocks(tp);
  8622. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  8623. return tg3_reset_hw(tp, reset_phy);
  8624. }
  8625. static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
  8626. {
  8627. int i;
  8628. for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
  8629. u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
  8630. tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
  8631. off += len;
  8632. if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
  8633. !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
  8634. memset(ocir, 0, TG3_OCIR_LEN);
  8635. }
  8636. }
  8637. /* sysfs attributes for hwmon */
  8638. static ssize_t tg3_show_temp(struct device *dev,
  8639. struct device_attribute *devattr, char *buf)
  8640. {
  8641. struct pci_dev *pdev = to_pci_dev(dev);
  8642. struct net_device *netdev = pci_get_drvdata(pdev);
  8643. struct tg3 *tp = netdev_priv(netdev);
  8644. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  8645. u32 temperature;
  8646. spin_lock_bh(&tp->lock);
  8647. tg3_ape_scratchpad_read(tp, &temperature, attr->index,
  8648. sizeof(temperature));
  8649. spin_unlock_bh(&tp->lock);
  8650. return sprintf(buf, "%u\n", temperature);
  8651. }
  8652. static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
  8653. TG3_TEMP_SENSOR_OFFSET);
  8654. static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
  8655. TG3_TEMP_CAUTION_OFFSET);
  8656. static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
  8657. TG3_TEMP_MAX_OFFSET);
  8658. static struct attribute *tg3_attributes[] = {
  8659. &sensor_dev_attr_temp1_input.dev_attr.attr,
  8660. &sensor_dev_attr_temp1_crit.dev_attr.attr,
  8661. &sensor_dev_attr_temp1_max.dev_attr.attr,
  8662. NULL
  8663. };
  8664. static const struct attribute_group tg3_group = {
  8665. .attrs = tg3_attributes,
  8666. };
  8667. static void tg3_hwmon_close(struct tg3 *tp)
  8668. {
  8669. if (tp->hwmon_dev) {
  8670. hwmon_device_unregister(tp->hwmon_dev);
  8671. tp->hwmon_dev = NULL;
  8672. sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
  8673. }
  8674. }
  8675. static void tg3_hwmon_open(struct tg3 *tp)
  8676. {
  8677. int i, err;
  8678. u32 size = 0;
  8679. struct pci_dev *pdev = tp->pdev;
  8680. struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
  8681. tg3_sd_scan_scratchpad(tp, ocirs);
  8682. for (i = 0; i < TG3_SD_NUM_RECS; i++) {
  8683. if (!ocirs[i].src_data_length)
  8684. continue;
  8685. size += ocirs[i].src_hdr_length;
  8686. size += ocirs[i].src_data_length;
  8687. }
  8688. if (!size)
  8689. return;
  8690. /* Register hwmon sysfs hooks */
  8691. err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
  8692. if (err) {
  8693. dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
  8694. return;
  8695. }
  8696. tp->hwmon_dev = hwmon_device_register(&pdev->dev);
  8697. if (IS_ERR(tp->hwmon_dev)) {
  8698. tp->hwmon_dev = NULL;
  8699. dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
  8700. sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
  8701. }
  8702. }
  8703. #define TG3_STAT_ADD32(PSTAT, REG) \
  8704. do { u32 __val = tr32(REG); \
  8705. (PSTAT)->low += __val; \
  8706. if ((PSTAT)->low < __val) \
  8707. (PSTAT)->high += 1; \
  8708. } while (0)
  8709. static void tg3_periodic_fetch_stats(struct tg3 *tp)
  8710. {
  8711. struct tg3_hw_stats *sp = tp->hw_stats;
  8712. if (!tp->link_up)
  8713. return;
  8714. TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
  8715. TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
  8716. TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
  8717. TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
  8718. TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
  8719. TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
  8720. TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
  8721. TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
  8722. TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
  8723. TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
  8724. TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
  8725. TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
  8726. TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
  8727. if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
  8728. (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
  8729. sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
  8730. u32 val;
  8731. val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
  8732. val &= ~tg3_lso_rd_dma_workaround_bit(tp);
  8733. tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
  8734. tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
  8735. }
  8736. TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
  8737. TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
  8738. TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
  8739. TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
  8740. TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
  8741. TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
  8742. TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
  8743. TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
  8744. TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
  8745. TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
  8746. TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
  8747. TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
  8748. TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
  8749. TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
  8750. TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
  8751. if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
  8752. tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
  8753. tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
  8754. TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
  8755. } else {
  8756. u32 val = tr32(HOSTCC_FLOW_ATTN);
  8757. val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
  8758. if (val) {
  8759. tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
  8760. sp->rx_discards.low += val;
  8761. if (sp->rx_discards.low < val)
  8762. sp->rx_discards.high += 1;
  8763. }
  8764. sp->mbuf_lwm_thresh_hit = sp->rx_discards;
  8765. }
  8766. TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
  8767. }
  8768. static void tg3_chk_missed_msi(struct tg3 *tp)
  8769. {
  8770. u32 i;
  8771. for (i = 0; i < tp->irq_cnt; i++) {
  8772. struct tg3_napi *tnapi = &tp->napi[i];
  8773. if (tg3_has_work(tnapi)) {
  8774. if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
  8775. tnapi->last_tx_cons == tnapi->tx_cons) {
  8776. if (tnapi->chk_msi_cnt < 1) {
  8777. tnapi->chk_msi_cnt++;
  8778. return;
  8779. }
  8780. tg3_msi(0, tnapi);
  8781. }
  8782. }
  8783. tnapi->chk_msi_cnt = 0;
  8784. tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
  8785. tnapi->last_tx_cons = tnapi->tx_cons;
  8786. }
  8787. }
  8788. static void tg3_timer(unsigned long __opaque)
  8789. {
  8790. struct tg3 *tp = (struct tg3 *) __opaque;
  8791. if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
  8792. goto restart_timer;
  8793. spin_lock(&tp->lock);
  8794. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  8795. tg3_flag(tp, 57765_CLASS))
  8796. tg3_chk_missed_msi(tp);
  8797. if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
  8798. /* BCM4785: Flush posted writes from GbE to host memory. */
  8799. tr32(HOSTCC_MODE);
  8800. }
  8801. if (!tg3_flag(tp, TAGGED_STATUS)) {
  8802. /* All of this garbage is because when using non-tagged
  8803. * IRQ status the mailbox/status_block protocol the chip
  8804. * uses with the cpu is race prone.
  8805. */
  8806. if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
  8807. tw32(GRC_LOCAL_CTRL,
  8808. tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  8809. } else {
  8810. tw32(HOSTCC_MODE, tp->coalesce_mode |
  8811. HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
  8812. }
  8813. if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  8814. spin_unlock(&tp->lock);
  8815. tg3_reset_task_schedule(tp);
  8816. goto restart_timer;
  8817. }
  8818. }
  8819. /* This part only runs once per second. */
  8820. if (!--tp->timer_counter) {
  8821. if (tg3_flag(tp, 5705_PLUS))
  8822. tg3_periodic_fetch_stats(tp);
  8823. if (tp->setlpicnt && !--tp->setlpicnt)
  8824. tg3_phy_eee_enable(tp);
  8825. if (tg3_flag(tp, USE_LINKCHG_REG)) {
  8826. u32 mac_stat;
  8827. int phy_event;
  8828. mac_stat = tr32(MAC_STATUS);
  8829. phy_event = 0;
  8830. if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
  8831. if (mac_stat & MAC_STATUS_MI_INTERRUPT)
  8832. phy_event = 1;
  8833. } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
  8834. phy_event = 1;
  8835. if (phy_event)
  8836. tg3_setup_phy(tp, false);
  8837. } else if (tg3_flag(tp, POLL_SERDES)) {
  8838. u32 mac_stat = tr32(MAC_STATUS);
  8839. int need_setup = 0;
  8840. if (tp->link_up &&
  8841. (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
  8842. need_setup = 1;
  8843. }
  8844. if (!tp->link_up &&
  8845. (mac_stat & (MAC_STATUS_PCS_SYNCED |
  8846. MAC_STATUS_SIGNAL_DET))) {
  8847. need_setup = 1;
  8848. }
  8849. if (need_setup) {
  8850. if (!tp->serdes_counter) {
  8851. tw32_f(MAC_MODE,
  8852. (tp->mac_mode &
  8853. ~MAC_MODE_PORT_MODE_MASK));
  8854. udelay(40);
  8855. tw32_f(MAC_MODE, tp->mac_mode);
  8856. udelay(40);
  8857. }
  8858. tg3_setup_phy(tp, false);
  8859. }
  8860. } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  8861. tg3_flag(tp, 5780_CLASS)) {
  8862. tg3_serdes_parallel_detect(tp);
  8863. }
  8864. tp->timer_counter = tp->timer_multiplier;
  8865. }
  8866. /* Heartbeat is only sent once every 2 seconds.
  8867. *
  8868. * The heartbeat is to tell the ASF firmware that the host
  8869. * driver is still alive. In the event that the OS crashes,
  8870. * ASF needs to reset the hardware to free up the FIFO space
  8871. * that may be filled with rx packets destined for the host.
  8872. * If the FIFO is full, ASF will no longer function properly.
  8873. *
  8874. * Unintended resets have been reported on real time kernels
  8875. * where the timer doesn't run on time. Netpoll will also have
  8876. * same problem.
  8877. *
  8878. * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
  8879. * to check the ring condition when the heartbeat is expiring
  8880. * before doing the reset. This will prevent most unintended
  8881. * resets.
  8882. */
  8883. if (!--tp->asf_counter) {
  8884. if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
  8885. tg3_wait_for_event_ack(tp);
  8886. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
  8887. FWCMD_NICDRV_ALIVE3);
  8888. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
  8889. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
  8890. TG3_FW_UPDATE_TIMEOUT_SEC);
  8891. tg3_generate_fw_event(tp);
  8892. }
  8893. tp->asf_counter = tp->asf_multiplier;
  8894. }
  8895. spin_unlock(&tp->lock);
  8896. restart_timer:
  8897. tp->timer.expires = jiffies + tp->timer_offset;
  8898. add_timer(&tp->timer);
  8899. }
  8900. static void tg3_timer_init(struct tg3 *tp)
  8901. {
  8902. if (tg3_flag(tp, TAGGED_STATUS) &&
  8903. tg3_asic_rev(tp) != ASIC_REV_5717 &&
  8904. !tg3_flag(tp, 57765_CLASS))
  8905. tp->timer_offset = HZ;
  8906. else
  8907. tp->timer_offset = HZ / 10;
  8908. BUG_ON(tp->timer_offset > HZ);
  8909. tp->timer_multiplier = (HZ / tp->timer_offset);
  8910. tp->asf_multiplier = (HZ / tp->timer_offset) *
  8911. TG3_FW_UPDATE_FREQ_SEC;
  8912. init_timer(&tp->timer);
  8913. tp->timer.data = (unsigned long) tp;
  8914. tp->timer.function = tg3_timer;
  8915. }
  8916. static void tg3_timer_start(struct tg3 *tp)
  8917. {
  8918. tp->asf_counter = tp->asf_multiplier;
  8919. tp->timer_counter = tp->timer_multiplier;
  8920. tp->timer.expires = jiffies + tp->timer_offset;
  8921. add_timer(&tp->timer);
  8922. }
  8923. static void tg3_timer_stop(struct tg3 *tp)
  8924. {
  8925. del_timer_sync(&tp->timer);
  8926. }
  8927. /* Restart hardware after configuration changes, self-test, etc.
  8928. * Invoked with tp->lock held.
  8929. */
  8930. static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
  8931. __releases(tp->lock)
  8932. __acquires(tp->lock)
  8933. {
  8934. int err;
  8935. err = tg3_init_hw(tp, reset_phy);
  8936. if (err) {
  8937. netdev_err(tp->dev,
  8938. "Failed to re-initialize device, aborting\n");
  8939. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8940. tg3_full_unlock(tp);
  8941. tg3_timer_stop(tp);
  8942. tp->irq_sync = 0;
  8943. tg3_napi_enable(tp);
  8944. dev_close(tp->dev);
  8945. tg3_full_lock(tp, 0);
  8946. }
  8947. return err;
  8948. }
  8949. static void tg3_reset_task(struct work_struct *work)
  8950. {
  8951. struct tg3 *tp = container_of(work, struct tg3, reset_task);
  8952. int err;
  8953. tg3_full_lock(tp, 0);
  8954. if (!netif_running(tp->dev)) {
  8955. tg3_flag_clear(tp, RESET_TASK_PENDING);
  8956. tg3_full_unlock(tp);
  8957. return;
  8958. }
  8959. tg3_full_unlock(tp);
  8960. tg3_phy_stop(tp);
  8961. tg3_netif_stop(tp);
  8962. tg3_full_lock(tp, 1);
  8963. if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
  8964. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  8965. tp->write32_rx_mbox = tg3_write_flush_reg32;
  8966. tg3_flag_set(tp, MBOX_WRITE_REORDER);
  8967. tg3_flag_clear(tp, TX_RECOVERY_PENDING);
  8968. }
  8969. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  8970. err = tg3_init_hw(tp, true);
  8971. if (err)
  8972. goto out;
  8973. tg3_netif_start(tp);
  8974. out:
  8975. tg3_full_unlock(tp);
  8976. if (!err)
  8977. tg3_phy_start(tp);
  8978. tg3_flag_clear(tp, RESET_TASK_PENDING);
  8979. }
  8980. static int tg3_request_irq(struct tg3 *tp, int irq_num)
  8981. {
  8982. irq_handler_t fn;
  8983. unsigned long flags;
  8984. char *name;
  8985. struct tg3_napi *tnapi = &tp->napi[irq_num];
  8986. if (tp->irq_cnt == 1)
  8987. name = tp->dev->name;
  8988. else {
  8989. name = &tnapi->irq_lbl[0];
  8990. snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
  8991. name[IFNAMSIZ-1] = 0;
  8992. }
  8993. if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
  8994. fn = tg3_msi;
  8995. if (tg3_flag(tp, 1SHOT_MSI))
  8996. fn = tg3_msi_1shot;
  8997. flags = 0;
  8998. } else {
  8999. fn = tg3_interrupt;
  9000. if (tg3_flag(tp, TAGGED_STATUS))
  9001. fn = tg3_interrupt_tagged;
  9002. flags = IRQF_SHARED;
  9003. }
  9004. return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
  9005. }
  9006. static int tg3_test_interrupt(struct tg3 *tp)
  9007. {
  9008. struct tg3_napi *tnapi = &tp->napi[0];
  9009. struct net_device *dev = tp->dev;
  9010. int err, i, intr_ok = 0;
  9011. u32 val;
  9012. if (!netif_running(dev))
  9013. return -ENODEV;
  9014. tg3_disable_ints(tp);
  9015. free_irq(tnapi->irq_vec, tnapi);
  9016. /*
  9017. * Turn off MSI one shot mode. Otherwise this test has no
  9018. * observable way to know whether the interrupt was delivered.
  9019. */
  9020. if (tg3_flag(tp, 57765_PLUS)) {
  9021. val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
  9022. tw32(MSGINT_MODE, val);
  9023. }
  9024. err = request_irq(tnapi->irq_vec, tg3_test_isr,
  9025. IRQF_SHARED, dev->name, tnapi);
  9026. if (err)
  9027. return err;
  9028. tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
  9029. tg3_enable_ints(tp);
  9030. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  9031. tnapi->coal_now);
  9032. for (i = 0; i < 5; i++) {
  9033. u32 int_mbox, misc_host_ctrl;
  9034. int_mbox = tr32_mailbox(tnapi->int_mbox);
  9035. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  9036. if ((int_mbox != 0) ||
  9037. (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
  9038. intr_ok = 1;
  9039. break;
  9040. }
  9041. if (tg3_flag(tp, 57765_PLUS) &&
  9042. tnapi->hw_status->status_tag != tnapi->last_tag)
  9043. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  9044. msleep(10);
  9045. }
  9046. tg3_disable_ints(tp);
  9047. free_irq(tnapi->irq_vec, tnapi);
  9048. err = tg3_request_irq(tp, 0);
  9049. if (err)
  9050. return err;
  9051. if (intr_ok) {
  9052. /* Reenable MSI one shot mode. */
  9053. if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
  9054. val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
  9055. tw32(MSGINT_MODE, val);
  9056. }
  9057. return 0;
  9058. }
  9059. return -EIO;
  9060. }
  9061. /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
  9062. * successfully restored
  9063. */
  9064. static int tg3_test_msi(struct tg3 *tp)
  9065. {
  9066. int err;
  9067. u16 pci_cmd;
  9068. if (!tg3_flag(tp, USING_MSI))
  9069. return 0;
  9070. /* Turn off SERR reporting in case MSI terminates with Master
  9071. * Abort.
  9072. */
  9073. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  9074. pci_write_config_word(tp->pdev, PCI_COMMAND,
  9075. pci_cmd & ~PCI_COMMAND_SERR);
  9076. err = tg3_test_interrupt(tp);
  9077. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  9078. if (!err)
  9079. return 0;
  9080. /* other failures */
  9081. if (err != -EIO)
  9082. return err;
  9083. /* MSI test failed, go back to INTx mode */
  9084. netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
  9085. "to INTx mode. Please report this failure to the PCI "
  9086. "maintainer and include system chipset information\n");
  9087. free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
  9088. pci_disable_msi(tp->pdev);
  9089. tg3_flag_clear(tp, USING_MSI);
  9090. tp->napi[0].irq_vec = tp->pdev->irq;
  9091. err = tg3_request_irq(tp, 0);
  9092. if (err)
  9093. return err;
  9094. /* Need to reset the chip because the MSI cycle may have terminated
  9095. * with Master Abort.
  9096. */
  9097. tg3_full_lock(tp, 1);
  9098. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9099. err = tg3_init_hw(tp, true);
  9100. tg3_full_unlock(tp);
  9101. if (err)
  9102. free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
  9103. return err;
  9104. }
  9105. static int tg3_request_firmware(struct tg3 *tp)
  9106. {
  9107. const struct tg3_firmware_hdr *fw_hdr;
  9108. if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
  9109. netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
  9110. tp->fw_needed);
  9111. return -ENOENT;
  9112. }
  9113. fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
  9114. /* Firmware blob starts with version numbers, followed by
  9115. * start address and _full_ length including BSS sections
  9116. * (which must be longer than the actual data, of course
  9117. */
  9118. tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
  9119. if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
  9120. netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
  9121. tp->fw_len, tp->fw_needed);
  9122. release_firmware(tp->fw);
  9123. tp->fw = NULL;
  9124. return -EINVAL;
  9125. }
  9126. /* We no longer need firmware; we have it. */
  9127. tp->fw_needed = NULL;
  9128. return 0;
  9129. }
  9130. static u32 tg3_irq_count(struct tg3 *tp)
  9131. {
  9132. u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
  9133. if (irq_cnt > 1) {
  9134. /* We want as many rx rings enabled as there are cpus.
  9135. * In multiqueue MSI-X mode, the first MSI-X vector
  9136. * only deals with link interrupts, etc, so we add
  9137. * one to the number of vectors we are requesting.
  9138. */
  9139. irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
  9140. }
  9141. return irq_cnt;
  9142. }
  9143. static bool tg3_enable_msix(struct tg3 *tp)
  9144. {
  9145. int i, rc;
  9146. struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
  9147. tp->txq_cnt = tp->txq_req;
  9148. tp->rxq_cnt = tp->rxq_req;
  9149. if (!tp->rxq_cnt)
  9150. tp->rxq_cnt = netif_get_num_default_rss_queues();
  9151. if (tp->rxq_cnt > tp->rxq_max)
  9152. tp->rxq_cnt = tp->rxq_max;
  9153. /* Disable multiple TX rings by default. Simple round-robin hardware
  9154. * scheduling of the TX rings can cause starvation of rings with
  9155. * small packets when other rings have TSO or jumbo packets.
  9156. */
  9157. if (!tp->txq_req)
  9158. tp->txq_cnt = 1;
  9159. tp->irq_cnt = tg3_irq_count(tp);
  9160. for (i = 0; i < tp->irq_max; i++) {
  9161. msix_ent[i].entry = i;
  9162. msix_ent[i].vector = 0;
  9163. }
  9164. rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
  9165. if (rc < 0) {
  9166. return false;
  9167. } else if (rc != 0) {
  9168. if (pci_enable_msix(tp->pdev, msix_ent, rc))
  9169. return false;
  9170. netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
  9171. tp->irq_cnt, rc);
  9172. tp->irq_cnt = rc;
  9173. tp->rxq_cnt = max(rc - 1, 1);
  9174. if (tp->txq_cnt)
  9175. tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
  9176. }
  9177. for (i = 0; i < tp->irq_max; i++)
  9178. tp->napi[i].irq_vec = msix_ent[i].vector;
  9179. if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
  9180. pci_disable_msix(tp->pdev);
  9181. return false;
  9182. }
  9183. if (tp->irq_cnt == 1)
  9184. return true;
  9185. tg3_flag_set(tp, ENABLE_RSS);
  9186. if (tp->txq_cnt > 1)
  9187. tg3_flag_set(tp, ENABLE_TSS);
  9188. netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
  9189. return true;
  9190. }
  9191. static void tg3_ints_init(struct tg3 *tp)
  9192. {
  9193. if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
  9194. !tg3_flag(tp, TAGGED_STATUS)) {
  9195. /* All MSI supporting chips should support tagged
  9196. * status. Assert that this is the case.
  9197. */
  9198. netdev_warn(tp->dev,
  9199. "MSI without TAGGED_STATUS? Not using MSI\n");
  9200. goto defcfg;
  9201. }
  9202. if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
  9203. tg3_flag_set(tp, USING_MSIX);
  9204. else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
  9205. tg3_flag_set(tp, USING_MSI);
  9206. if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
  9207. u32 msi_mode = tr32(MSGINT_MODE);
  9208. if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
  9209. msi_mode |= MSGINT_MODE_MULTIVEC_EN;
  9210. if (!tg3_flag(tp, 1SHOT_MSI))
  9211. msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
  9212. tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
  9213. }
  9214. defcfg:
  9215. if (!tg3_flag(tp, USING_MSIX)) {
  9216. tp->irq_cnt = 1;
  9217. tp->napi[0].irq_vec = tp->pdev->irq;
  9218. }
  9219. if (tp->irq_cnt == 1) {
  9220. tp->txq_cnt = 1;
  9221. tp->rxq_cnt = 1;
  9222. netif_set_real_num_tx_queues(tp->dev, 1);
  9223. netif_set_real_num_rx_queues(tp->dev, 1);
  9224. }
  9225. }
  9226. static void tg3_ints_fini(struct tg3 *tp)
  9227. {
  9228. if (tg3_flag(tp, USING_MSIX))
  9229. pci_disable_msix(tp->pdev);
  9230. else if (tg3_flag(tp, USING_MSI))
  9231. pci_disable_msi(tp->pdev);
  9232. tg3_flag_clear(tp, USING_MSI);
  9233. tg3_flag_clear(tp, USING_MSIX);
  9234. tg3_flag_clear(tp, ENABLE_RSS);
  9235. tg3_flag_clear(tp, ENABLE_TSS);
  9236. }
  9237. static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
  9238. bool init)
  9239. {
  9240. struct net_device *dev = tp->dev;
  9241. int i, err;
  9242. /*
  9243. * Setup interrupts first so we know how
  9244. * many NAPI resources to allocate
  9245. */
  9246. tg3_ints_init(tp);
  9247. tg3_rss_check_indir_tbl(tp);
  9248. /* The placement of this call is tied
  9249. * to the setup and use of Host TX descriptors.
  9250. */
  9251. err = tg3_alloc_consistent(tp);
  9252. if (err)
  9253. goto out_ints_fini;
  9254. tg3_napi_init(tp);
  9255. tg3_napi_enable(tp);
  9256. for (i = 0; i < tp->irq_cnt; i++) {
  9257. struct tg3_napi *tnapi = &tp->napi[i];
  9258. err = tg3_request_irq(tp, i);
  9259. if (err) {
  9260. for (i--; i >= 0; i--) {
  9261. tnapi = &tp->napi[i];
  9262. free_irq(tnapi->irq_vec, tnapi);
  9263. }
  9264. goto out_napi_fini;
  9265. }
  9266. }
  9267. tg3_full_lock(tp, 0);
  9268. if (init)
  9269. tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
  9270. err = tg3_init_hw(tp, reset_phy);
  9271. if (err) {
  9272. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9273. tg3_free_rings(tp);
  9274. }
  9275. tg3_full_unlock(tp);
  9276. if (err)
  9277. goto out_free_irq;
  9278. if (test_irq && tg3_flag(tp, USING_MSI)) {
  9279. err = tg3_test_msi(tp);
  9280. if (err) {
  9281. tg3_full_lock(tp, 0);
  9282. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9283. tg3_free_rings(tp);
  9284. tg3_full_unlock(tp);
  9285. goto out_napi_fini;
  9286. }
  9287. if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
  9288. u32 val = tr32(PCIE_TRANSACTION_CFG);
  9289. tw32(PCIE_TRANSACTION_CFG,
  9290. val | PCIE_TRANS_CFG_1SHOT_MSI);
  9291. }
  9292. }
  9293. tg3_phy_start(tp);
  9294. tg3_hwmon_open(tp);
  9295. tg3_full_lock(tp, 0);
  9296. tg3_timer_start(tp);
  9297. tg3_flag_set(tp, INIT_COMPLETE);
  9298. tg3_enable_ints(tp);
  9299. if (init)
  9300. tg3_ptp_init(tp);
  9301. else
  9302. tg3_ptp_resume(tp);
  9303. tg3_full_unlock(tp);
  9304. netif_tx_start_all_queues(dev);
  9305. /*
  9306. * Reset loopback feature if it was turned on while the device was down
  9307. * make sure that it's installed properly now.
  9308. */
  9309. if (dev->features & NETIF_F_LOOPBACK)
  9310. tg3_set_loopback(dev, dev->features);
  9311. return 0;
  9312. out_free_irq:
  9313. for (i = tp->irq_cnt - 1; i >= 0; i--) {
  9314. struct tg3_napi *tnapi = &tp->napi[i];
  9315. free_irq(tnapi->irq_vec, tnapi);
  9316. }
  9317. out_napi_fini:
  9318. tg3_napi_disable(tp);
  9319. tg3_napi_fini(tp);
  9320. tg3_free_consistent(tp);
  9321. out_ints_fini:
  9322. tg3_ints_fini(tp);
  9323. return err;
  9324. }
  9325. static void tg3_stop(struct tg3 *tp)
  9326. {
  9327. int i;
  9328. tg3_reset_task_cancel(tp);
  9329. tg3_netif_stop(tp);
  9330. tg3_timer_stop(tp);
  9331. tg3_hwmon_close(tp);
  9332. tg3_phy_stop(tp);
  9333. tg3_full_lock(tp, 1);
  9334. tg3_disable_ints(tp);
  9335. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9336. tg3_free_rings(tp);
  9337. tg3_flag_clear(tp, INIT_COMPLETE);
  9338. tg3_full_unlock(tp);
  9339. for (i = tp->irq_cnt - 1; i >= 0; i--) {
  9340. struct tg3_napi *tnapi = &tp->napi[i];
  9341. free_irq(tnapi->irq_vec, tnapi);
  9342. }
  9343. tg3_ints_fini(tp);
  9344. tg3_napi_fini(tp);
  9345. tg3_free_consistent(tp);
  9346. }
  9347. static int tg3_open(struct net_device *dev)
  9348. {
  9349. struct tg3 *tp = netdev_priv(dev);
  9350. int err;
  9351. if (tp->fw_needed) {
  9352. err = tg3_request_firmware(tp);
  9353. if (tg3_asic_rev(tp) == ASIC_REV_57766) {
  9354. if (err) {
  9355. netdev_warn(tp->dev, "EEE capability disabled\n");
  9356. tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
  9357. } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
  9358. netdev_warn(tp->dev, "EEE capability restored\n");
  9359. tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
  9360. }
  9361. } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
  9362. if (err)
  9363. return err;
  9364. } else if (err) {
  9365. netdev_warn(tp->dev, "TSO capability disabled\n");
  9366. tg3_flag_clear(tp, TSO_CAPABLE);
  9367. } else if (!tg3_flag(tp, TSO_CAPABLE)) {
  9368. netdev_notice(tp->dev, "TSO capability restored\n");
  9369. tg3_flag_set(tp, TSO_CAPABLE);
  9370. }
  9371. }
  9372. tg3_carrier_off(tp);
  9373. err = tg3_power_up(tp);
  9374. if (err)
  9375. return err;
  9376. tg3_full_lock(tp, 0);
  9377. tg3_disable_ints(tp);
  9378. tg3_flag_clear(tp, INIT_COMPLETE);
  9379. tg3_full_unlock(tp);
  9380. err = tg3_start(tp,
  9381. !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
  9382. true, true);
  9383. if (err) {
  9384. tg3_frob_aux_power(tp, false);
  9385. pci_set_power_state(tp->pdev, PCI_D3hot);
  9386. }
  9387. if (tg3_flag(tp, PTP_CAPABLE)) {
  9388. tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
  9389. &tp->pdev->dev);
  9390. if (IS_ERR(tp->ptp_clock))
  9391. tp->ptp_clock = NULL;
  9392. }
  9393. return err;
  9394. }
  9395. static int tg3_close(struct net_device *dev)
  9396. {
  9397. struct tg3 *tp = netdev_priv(dev);
  9398. tg3_ptp_fini(tp);
  9399. tg3_stop(tp);
  9400. /* Clear stats across close / open calls */
  9401. memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
  9402. memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
  9403. tg3_power_down(tp);
  9404. tg3_carrier_off(tp);
  9405. return 0;
  9406. }
  9407. static inline u64 get_stat64(tg3_stat64_t *val)
  9408. {
  9409. return ((u64)val->high << 32) | ((u64)val->low);
  9410. }
  9411. static u64 tg3_calc_crc_errors(struct tg3 *tp)
  9412. {
  9413. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  9414. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  9415. (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  9416. tg3_asic_rev(tp) == ASIC_REV_5701)) {
  9417. u32 val;
  9418. if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
  9419. tg3_writephy(tp, MII_TG3_TEST1,
  9420. val | MII_TG3_TEST1_CRC_EN);
  9421. tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
  9422. } else
  9423. val = 0;
  9424. tp->phy_crc_errors += val;
  9425. return tp->phy_crc_errors;
  9426. }
  9427. return get_stat64(&hw_stats->rx_fcs_errors);
  9428. }
  9429. #define ESTAT_ADD(member) \
  9430. estats->member = old_estats->member + \
  9431. get_stat64(&hw_stats->member)
  9432. static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
  9433. {
  9434. struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
  9435. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  9436. ESTAT_ADD(rx_octets);
  9437. ESTAT_ADD(rx_fragments);
  9438. ESTAT_ADD(rx_ucast_packets);
  9439. ESTAT_ADD(rx_mcast_packets);
  9440. ESTAT_ADD(rx_bcast_packets);
  9441. ESTAT_ADD(rx_fcs_errors);
  9442. ESTAT_ADD(rx_align_errors);
  9443. ESTAT_ADD(rx_xon_pause_rcvd);
  9444. ESTAT_ADD(rx_xoff_pause_rcvd);
  9445. ESTAT_ADD(rx_mac_ctrl_rcvd);
  9446. ESTAT_ADD(rx_xoff_entered);
  9447. ESTAT_ADD(rx_frame_too_long_errors);
  9448. ESTAT_ADD(rx_jabbers);
  9449. ESTAT_ADD(rx_undersize_packets);
  9450. ESTAT_ADD(rx_in_length_errors);
  9451. ESTAT_ADD(rx_out_length_errors);
  9452. ESTAT_ADD(rx_64_or_less_octet_packets);
  9453. ESTAT_ADD(rx_65_to_127_octet_packets);
  9454. ESTAT_ADD(rx_128_to_255_octet_packets);
  9455. ESTAT_ADD(rx_256_to_511_octet_packets);
  9456. ESTAT_ADD(rx_512_to_1023_octet_packets);
  9457. ESTAT_ADD(rx_1024_to_1522_octet_packets);
  9458. ESTAT_ADD(rx_1523_to_2047_octet_packets);
  9459. ESTAT_ADD(rx_2048_to_4095_octet_packets);
  9460. ESTAT_ADD(rx_4096_to_8191_octet_packets);
  9461. ESTAT_ADD(rx_8192_to_9022_octet_packets);
  9462. ESTAT_ADD(tx_octets);
  9463. ESTAT_ADD(tx_collisions);
  9464. ESTAT_ADD(tx_xon_sent);
  9465. ESTAT_ADD(tx_xoff_sent);
  9466. ESTAT_ADD(tx_flow_control);
  9467. ESTAT_ADD(tx_mac_errors);
  9468. ESTAT_ADD(tx_single_collisions);
  9469. ESTAT_ADD(tx_mult_collisions);
  9470. ESTAT_ADD(tx_deferred);
  9471. ESTAT_ADD(tx_excessive_collisions);
  9472. ESTAT_ADD(tx_late_collisions);
  9473. ESTAT_ADD(tx_collide_2times);
  9474. ESTAT_ADD(tx_collide_3times);
  9475. ESTAT_ADD(tx_collide_4times);
  9476. ESTAT_ADD(tx_collide_5times);
  9477. ESTAT_ADD(tx_collide_6times);
  9478. ESTAT_ADD(tx_collide_7times);
  9479. ESTAT_ADD(tx_collide_8times);
  9480. ESTAT_ADD(tx_collide_9times);
  9481. ESTAT_ADD(tx_collide_10times);
  9482. ESTAT_ADD(tx_collide_11times);
  9483. ESTAT_ADD(tx_collide_12times);
  9484. ESTAT_ADD(tx_collide_13times);
  9485. ESTAT_ADD(tx_collide_14times);
  9486. ESTAT_ADD(tx_collide_15times);
  9487. ESTAT_ADD(tx_ucast_packets);
  9488. ESTAT_ADD(tx_mcast_packets);
  9489. ESTAT_ADD(tx_bcast_packets);
  9490. ESTAT_ADD(tx_carrier_sense_errors);
  9491. ESTAT_ADD(tx_discards);
  9492. ESTAT_ADD(tx_errors);
  9493. ESTAT_ADD(dma_writeq_full);
  9494. ESTAT_ADD(dma_write_prioq_full);
  9495. ESTAT_ADD(rxbds_empty);
  9496. ESTAT_ADD(rx_discards);
  9497. ESTAT_ADD(rx_errors);
  9498. ESTAT_ADD(rx_threshold_hit);
  9499. ESTAT_ADD(dma_readq_full);
  9500. ESTAT_ADD(dma_read_prioq_full);
  9501. ESTAT_ADD(tx_comp_queue_full);
  9502. ESTAT_ADD(ring_set_send_prod_index);
  9503. ESTAT_ADD(ring_status_update);
  9504. ESTAT_ADD(nic_irqs);
  9505. ESTAT_ADD(nic_avoided_irqs);
  9506. ESTAT_ADD(nic_tx_threshold_hit);
  9507. ESTAT_ADD(mbuf_lwm_thresh_hit);
  9508. }
  9509. static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
  9510. {
  9511. struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
  9512. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  9513. stats->rx_packets = old_stats->rx_packets +
  9514. get_stat64(&hw_stats->rx_ucast_packets) +
  9515. get_stat64(&hw_stats->rx_mcast_packets) +
  9516. get_stat64(&hw_stats->rx_bcast_packets);
  9517. stats->tx_packets = old_stats->tx_packets +
  9518. get_stat64(&hw_stats->tx_ucast_packets) +
  9519. get_stat64(&hw_stats->tx_mcast_packets) +
  9520. get_stat64(&hw_stats->tx_bcast_packets);
  9521. stats->rx_bytes = old_stats->rx_bytes +
  9522. get_stat64(&hw_stats->rx_octets);
  9523. stats->tx_bytes = old_stats->tx_bytes +
  9524. get_stat64(&hw_stats->tx_octets);
  9525. stats->rx_errors = old_stats->rx_errors +
  9526. get_stat64(&hw_stats->rx_errors);
  9527. stats->tx_errors = old_stats->tx_errors +
  9528. get_stat64(&hw_stats->tx_errors) +
  9529. get_stat64(&hw_stats->tx_mac_errors) +
  9530. get_stat64(&hw_stats->tx_carrier_sense_errors) +
  9531. get_stat64(&hw_stats->tx_discards);
  9532. stats->multicast = old_stats->multicast +
  9533. get_stat64(&hw_stats->rx_mcast_packets);
  9534. stats->collisions = old_stats->collisions +
  9535. get_stat64(&hw_stats->tx_collisions);
  9536. stats->rx_length_errors = old_stats->rx_length_errors +
  9537. get_stat64(&hw_stats->rx_frame_too_long_errors) +
  9538. get_stat64(&hw_stats->rx_undersize_packets);
  9539. stats->rx_over_errors = old_stats->rx_over_errors +
  9540. get_stat64(&hw_stats->rxbds_empty);
  9541. stats->rx_frame_errors = old_stats->rx_frame_errors +
  9542. get_stat64(&hw_stats->rx_align_errors);
  9543. stats->tx_aborted_errors = old_stats->tx_aborted_errors +
  9544. get_stat64(&hw_stats->tx_discards);
  9545. stats->tx_carrier_errors = old_stats->tx_carrier_errors +
  9546. get_stat64(&hw_stats->tx_carrier_sense_errors);
  9547. stats->rx_crc_errors = old_stats->rx_crc_errors +
  9548. tg3_calc_crc_errors(tp);
  9549. stats->rx_missed_errors = old_stats->rx_missed_errors +
  9550. get_stat64(&hw_stats->rx_discards);
  9551. stats->rx_dropped = tp->rx_dropped;
  9552. stats->tx_dropped = tp->tx_dropped;
  9553. }
  9554. static int tg3_get_regs_len(struct net_device *dev)
  9555. {
  9556. return TG3_REG_BLK_SIZE;
  9557. }
  9558. static void tg3_get_regs(struct net_device *dev,
  9559. struct ethtool_regs *regs, void *_p)
  9560. {
  9561. struct tg3 *tp = netdev_priv(dev);
  9562. regs->version = 0;
  9563. memset(_p, 0, TG3_REG_BLK_SIZE);
  9564. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  9565. return;
  9566. tg3_full_lock(tp, 0);
  9567. tg3_dump_legacy_regs(tp, (u32 *)_p);
  9568. tg3_full_unlock(tp);
  9569. }
  9570. static int tg3_get_eeprom_len(struct net_device *dev)
  9571. {
  9572. struct tg3 *tp = netdev_priv(dev);
  9573. return tp->nvram_size;
  9574. }
  9575. static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  9576. {
  9577. struct tg3 *tp = netdev_priv(dev);
  9578. int ret;
  9579. u8 *pd;
  9580. u32 i, offset, len, b_offset, b_count;
  9581. __be32 val;
  9582. if (tg3_flag(tp, NO_NVRAM))
  9583. return -EINVAL;
  9584. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  9585. return -EAGAIN;
  9586. offset = eeprom->offset;
  9587. len = eeprom->len;
  9588. eeprom->len = 0;
  9589. eeprom->magic = TG3_EEPROM_MAGIC;
  9590. if (offset & 3) {
  9591. /* adjustments to start on required 4 byte boundary */
  9592. b_offset = offset & 3;
  9593. b_count = 4 - b_offset;
  9594. if (b_count > len) {
  9595. /* i.e. offset=1 len=2 */
  9596. b_count = len;
  9597. }
  9598. ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
  9599. if (ret)
  9600. return ret;
  9601. memcpy(data, ((char *)&val) + b_offset, b_count);
  9602. len -= b_count;
  9603. offset += b_count;
  9604. eeprom->len += b_count;
  9605. }
  9606. /* read bytes up to the last 4 byte boundary */
  9607. pd = &data[eeprom->len];
  9608. for (i = 0; i < (len - (len & 3)); i += 4) {
  9609. ret = tg3_nvram_read_be32(tp, offset + i, &val);
  9610. if (ret) {
  9611. eeprom->len += i;
  9612. return ret;
  9613. }
  9614. memcpy(pd + i, &val, 4);
  9615. }
  9616. eeprom->len += i;
  9617. if (len & 3) {
  9618. /* read last bytes not ending on 4 byte boundary */
  9619. pd = &data[eeprom->len];
  9620. b_count = len & 3;
  9621. b_offset = offset + len - b_count;
  9622. ret = tg3_nvram_read_be32(tp, b_offset, &val);
  9623. if (ret)
  9624. return ret;
  9625. memcpy(pd, &val, b_count);
  9626. eeprom->len += b_count;
  9627. }
  9628. return 0;
  9629. }
  9630. static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  9631. {
  9632. struct tg3 *tp = netdev_priv(dev);
  9633. int ret;
  9634. u32 offset, len, b_offset, odd_len;
  9635. u8 *buf;
  9636. __be32 start, end;
  9637. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  9638. return -EAGAIN;
  9639. if (tg3_flag(tp, NO_NVRAM) ||
  9640. eeprom->magic != TG3_EEPROM_MAGIC)
  9641. return -EINVAL;
  9642. offset = eeprom->offset;
  9643. len = eeprom->len;
  9644. if ((b_offset = (offset & 3))) {
  9645. /* adjustments to start on required 4 byte boundary */
  9646. ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
  9647. if (ret)
  9648. return ret;
  9649. len += b_offset;
  9650. offset &= ~3;
  9651. if (len < 4)
  9652. len = 4;
  9653. }
  9654. odd_len = 0;
  9655. if (len & 3) {
  9656. /* adjustments to end on required 4 byte boundary */
  9657. odd_len = 1;
  9658. len = (len + 3) & ~3;
  9659. ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
  9660. if (ret)
  9661. return ret;
  9662. }
  9663. buf = data;
  9664. if (b_offset || odd_len) {
  9665. buf = kmalloc(len, GFP_KERNEL);
  9666. if (!buf)
  9667. return -ENOMEM;
  9668. if (b_offset)
  9669. memcpy(buf, &start, 4);
  9670. if (odd_len)
  9671. memcpy(buf+len-4, &end, 4);
  9672. memcpy(buf + b_offset, data, eeprom->len);
  9673. }
  9674. ret = tg3_nvram_write_block(tp, offset, len, buf);
  9675. if (buf != data)
  9676. kfree(buf);
  9677. return ret;
  9678. }
  9679. static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  9680. {
  9681. struct tg3 *tp = netdev_priv(dev);
  9682. if (tg3_flag(tp, USE_PHYLIB)) {
  9683. struct phy_device *phydev;
  9684. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  9685. return -EAGAIN;
  9686. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  9687. return phy_ethtool_gset(phydev, cmd);
  9688. }
  9689. cmd->supported = (SUPPORTED_Autoneg);
  9690. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  9691. cmd->supported |= (SUPPORTED_1000baseT_Half |
  9692. SUPPORTED_1000baseT_Full);
  9693. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  9694. cmd->supported |= (SUPPORTED_100baseT_Half |
  9695. SUPPORTED_100baseT_Full |
  9696. SUPPORTED_10baseT_Half |
  9697. SUPPORTED_10baseT_Full |
  9698. SUPPORTED_TP);
  9699. cmd->port = PORT_TP;
  9700. } else {
  9701. cmd->supported |= SUPPORTED_FIBRE;
  9702. cmd->port = PORT_FIBRE;
  9703. }
  9704. cmd->advertising = tp->link_config.advertising;
  9705. if (tg3_flag(tp, PAUSE_AUTONEG)) {
  9706. if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
  9707. if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
  9708. cmd->advertising |= ADVERTISED_Pause;
  9709. } else {
  9710. cmd->advertising |= ADVERTISED_Pause |
  9711. ADVERTISED_Asym_Pause;
  9712. }
  9713. } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
  9714. cmd->advertising |= ADVERTISED_Asym_Pause;
  9715. }
  9716. }
  9717. if (netif_running(dev) && tp->link_up) {
  9718. ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
  9719. cmd->duplex = tp->link_config.active_duplex;
  9720. cmd->lp_advertising = tp->link_config.rmt_adv;
  9721. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  9722. if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
  9723. cmd->eth_tp_mdix = ETH_TP_MDI_X;
  9724. else
  9725. cmd->eth_tp_mdix = ETH_TP_MDI;
  9726. }
  9727. } else {
  9728. ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
  9729. cmd->duplex = DUPLEX_UNKNOWN;
  9730. cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
  9731. }
  9732. cmd->phy_address = tp->phy_addr;
  9733. cmd->transceiver = XCVR_INTERNAL;
  9734. cmd->autoneg = tp->link_config.autoneg;
  9735. cmd->maxtxpkt = 0;
  9736. cmd->maxrxpkt = 0;
  9737. return 0;
  9738. }
  9739. static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  9740. {
  9741. struct tg3 *tp = netdev_priv(dev);
  9742. u32 speed = ethtool_cmd_speed(cmd);
  9743. if (tg3_flag(tp, USE_PHYLIB)) {
  9744. struct phy_device *phydev;
  9745. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  9746. return -EAGAIN;
  9747. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  9748. return phy_ethtool_sset(phydev, cmd);
  9749. }
  9750. if (cmd->autoneg != AUTONEG_ENABLE &&
  9751. cmd->autoneg != AUTONEG_DISABLE)
  9752. return -EINVAL;
  9753. if (cmd->autoneg == AUTONEG_DISABLE &&
  9754. cmd->duplex != DUPLEX_FULL &&
  9755. cmd->duplex != DUPLEX_HALF)
  9756. return -EINVAL;
  9757. if (cmd->autoneg == AUTONEG_ENABLE) {
  9758. u32 mask = ADVERTISED_Autoneg |
  9759. ADVERTISED_Pause |
  9760. ADVERTISED_Asym_Pause;
  9761. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  9762. mask |= ADVERTISED_1000baseT_Half |
  9763. ADVERTISED_1000baseT_Full;
  9764. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  9765. mask |= ADVERTISED_100baseT_Half |
  9766. ADVERTISED_100baseT_Full |
  9767. ADVERTISED_10baseT_Half |
  9768. ADVERTISED_10baseT_Full |
  9769. ADVERTISED_TP;
  9770. else
  9771. mask |= ADVERTISED_FIBRE;
  9772. if (cmd->advertising & ~mask)
  9773. return -EINVAL;
  9774. mask &= (ADVERTISED_1000baseT_Half |
  9775. ADVERTISED_1000baseT_Full |
  9776. ADVERTISED_100baseT_Half |
  9777. ADVERTISED_100baseT_Full |
  9778. ADVERTISED_10baseT_Half |
  9779. ADVERTISED_10baseT_Full);
  9780. cmd->advertising &= mask;
  9781. } else {
  9782. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
  9783. if (speed != SPEED_1000)
  9784. return -EINVAL;
  9785. if (cmd->duplex != DUPLEX_FULL)
  9786. return -EINVAL;
  9787. } else {
  9788. if (speed != SPEED_100 &&
  9789. speed != SPEED_10)
  9790. return -EINVAL;
  9791. }
  9792. }
  9793. tg3_full_lock(tp, 0);
  9794. tp->link_config.autoneg = cmd->autoneg;
  9795. if (cmd->autoneg == AUTONEG_ENABLE) {
  9796. tp->link_config.advertising = (cmd->advertising |
  9797. ADVERTISED_Autoneg);
  9798. tp->link_config.speed = SPEED_UNKNOWN;
  9799. tp->link_config.duplex = DUPLEX_UNKNOWN;
  9800. } else {
  9801. tp->link_config.advertising = 0;
  9802. tp->link_config.speed = speed;
  9803. tp->link_config.duplex = cmd->duplex;
  9804. }
  9805. tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
  9806. tg3_warn_mgmt_link_flap(tp);
  9807. if (netif_running(dev))
  9808. tg3_setup_phy(tp, true);
  9809. tg3_full_unlock(tp);
  9810. return 0;
  9811. }
  9812. static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  9813. {
  9814. struct tg3 *tp = netdev_priv(dev);
  9815. strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
  9816. strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
  9817. strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
  9818. strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
  9819. }
  9820. static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  9821. {
  9822. struct tg3 *tp = netdev_priv(dev);
  9823. if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
  9824. wol->supported = WAKE_MAGIC;
  9825. else
  9826. wol->supported = 0;
  9827. wol->wolopts = 0;
  9828. if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
  9829. wol->wolopts = WAKE_MAGIC;
  9830. memset(&wol->sopass, 0, sizeof(wol->sopass));
  9831. }
  9832. static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  9833. {
  9834. struct tg3 *tp = netdev_priv(dev);
  9835. struct device *dp = &tp->pdev->dev;
  9836. if (wol->wolopts & ~WAKE_MAGIC)
  9837. return -EINVAL;
  9838. if ((wol->wolopts & WAKE_MAGIC) &&
  9839. !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
  9840. return -EINVAL;
  9841. device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
  9842. spin_lock_bh(&tp->lock);
  9843. if (device_may_wakeup(dp))
  9844. tg3_flag_set(tp, WOL_ENABLE);
  9845. else
  9846. tg3_flag_clear(tp, WOL_ENABLE);
  9847. spin_unlock_bh(&tp->lock);
  9848. return 0;
  9849. }
  9850. static u32 tg3_get_msglevel(struct net_device *dev)
  9851. {
  9852. struct tg3 *tp = netdev_priv(dev);
  9853. return tp->msg_enable;
  9854. }
  9855. static void tg3_set_msglevel(struct net_device *dev, u32 value)
  9856. {
  9857. struct tg3 *tp = netdev_priv(dev);
  9858. tp->msg_enable = value;
  9859. }
  9860. static int tg3_nway_reset(struct net_device *dev)
  9861. {
  9862. struct tg3 *tp = netdev_priv(dev);
  9863. int r;
  9864. if (!netif_running(dev))
  9865. return -EAGAIN;
  9866. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  9867. return -EINVAL;
  9868. tg3_warn_mgmt_link_flap(tp);
  9869. if (tg3_flag(tp, USE_PHYLIB)) {
  9870. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  9871. return -EAGAIN;
  9872. r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  9873. } else {
  9874. u32 bmcr;
  9875. spin_lock_bh(&tp->lock);
  9876. r = -EINVAL;
  9877. tg3_readphy(tp, MII_BMCR, &bmcr);
  9878. if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
  9879. ((bmcr & BMCR_ANENABLE) ||
  9880. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
  9881. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
  9882. BMCR_ANENABLE);
  9883. r = 0;
  9884. }
  9885. spin_unlock_bh(&tp->lock);
  9886. }
  9887. return r;
  9888. }
  9889. static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  9890. {
  9891. struct tg3 *tp = netdev_priv(dev);
  9892. ering->rx_max_pending = tp->rx_std_ring_mask;
  9893. if (tg3_flag(tp, JUMBO_RING_ENABLE))
  9894. ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
  9895. else
  9896. ering->rx_jumbo_max_pending = 0;
  9897. ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
  9898. ering->rx_pending = tp->rx_pending;
  9899. if (tg3_flag(tp, JUMBO_RING_ENABLE))
  9900. ering->rx_jumbo_pending = tp->rx_jumbo_pending;
  9901. else
  9902. ering->rx_jumbo_pending = 0;
  9903. ering->tx_pending = tp->napi[0].tx_pending;
  9904. }
  9905. static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  9906. {
  9907. struct tg3 *tp = netdev_priv(dev);
  9908. int i, irq_sync = 0, err = 0;
  9909. if ((ering->rx_pending > tp->rx_std_ring_mask) ||
  9910. (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
  9911. (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
  9912. (ering->tx_pending <= MAX_SKB_FRAGS) ||
  9913. (tg3_flag(tp, TSO_BUG) &&
  9914. (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
  9915. return -EINVAL;
  9916. if (netif_running(dev)) {
  9917. tg3_phy_stop(tp);
  9918. tg3_netif_stop(tp);
  9919. irq_sync = 1;
  9920. }
  9921. tg3_full_lock(tp, irq_sync);
  9922. tp->rx_pending = ering->rx_pending;
  9923. if (tg3_flag(tp, MAX_RXPEND_64) &&
  9924. tp->rx_pending > 63)
  9925. tp->rx_pending = 63;
  9926. tp->rx_jumbo_pending = ering->rx_jumbo_pending;
  9927. for (i = 0; i < tp->irq_max; i++)
  9928. tp->napi[i].tx_pending = ering->tx_pending;
  9929. if (netif_running(dev)) {
  9930. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9931. err = tg3_restart_hw(tp, false);
  9932. if (!err)
  9933. tg3_netif_start(tp);
  9934. }
  9935. tg3_full_unlock(tp);
  9936. if (irq_sync && !err)
  9937. tg3_phy_start(tp);
  9938. return err;
  9939. }
  9940. static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  9941. {
  9942. struct tg3 *tp = netdev_priv(dev);
  9943. epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
  9944. if (tp->link_config.flowctrl & FLOW_CTRL_RX)
  9945. epause->rx_pause = 1;
  9946. else
  9947. epause->rx_pause = 0;
  9948. if (tp->link_config.flowctrl & FLOW_CTRL_TX)
  9949. epause->tx_pause = 1;
  9950. else
  9951. epause->tx_pause = 0;
  9952. }
  9953. static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  9954. {
  9955. struct tg3 *tp = netdev_priv(dev);
  9956. int err = 0;
  9957. if (tp->link_config.autoneg == AUTONEG_ENABLE)
  9958. tg3_warn_mgmt_link_flap(tp);
  9959. if (tg3_flag(tp, USE_PHYLIB)) {
  9960. u32 newadv;
  9961. struct phy_device *phydev;
  9962. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  9963. if (!(phydev->supported & SUPPORTED_Pause) ||
  9964. (!(phydev->supported & SUPPORTED_Asym_Pause) &&
  9965. (epause->rx_pause != epause->tx_pause)))
  9966. return -EINVAL;
  9967. tp->link_config.flowctrl = 0;
  9968. if (epause->rx_pause) {
  9969. tp->link_config.flowctrl |= FLOW_CTRL_RX;
  9970. if (epause->tx_pause) {
  9971. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  9972. newadv = ADVERTISED_Pause;
  9973. } else
  9974. newadv = ADVERTISED_Pause |
  9975. ADVERTISED_Asym_Pause;
  9976. } else if (epause->tx_pause) {
  9977. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  9978. newadv = ADVERTISED_Asym_Pause;
  9979. } else
  9980. newadv = 0;
  9981. if (epause->autoneg)
  9982. tg3_flag_set(tp, PAUSE_AUTONEG);
  9983. else
  9984. tg3_flag_clear(tp, PAUSE_AUTONEG);
  9985. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  9986. u32 oldadv = phydev->advertising &
  9987. (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
  9988. if (oldadv != newadv) {
  9989. phydev->advertising &=
  9990. ~(ADVERTISED_Pause |
  9991. ADVERTISED_Asym_Pause);
  9992. phydev->advertising |= newadv;
  9993. if (phydev->autoneg) {
  9994. /*
  9995. * Always renegotiate the link to
  9996. * inform our link partner of our
  9997. * flow control settings, even if the
  9998. * flow control is forced. Let
  9999. * tg3_adjust_link() do the final
  10000. * flow control setup.
  10001. */
  10002. return phy_start_aneg(phydev);
  10003. }
  10004. }
  10005. if (!epause->autoneg)
  10006. tg3_setup_flow_control(tp, 0, 0);
  10007. } else {
  10008. tp->link_config.advertising &=
  10009. ~(ADVERTISED_Pause |
  10010. ADVERTISED_Asym_Pause);
  10011. tp->link_config.advertising |= newadv;
  10012. }
  10013. } else {
  10014. int irq_sync = 0;
  10015. if (netif_running(dev)) {
  10016. tg3_netif_stop(tp);
  10017. irq_sync = 1;
  10018. }
  10019. tg3_full_lock(tp, irq_sync);
  10020. if (epause->autoneg)
  10021. tg3_flag_set(tp, PAUSE_AUTONEG);
  10022. else
  10023. tg3_flag_clear(tp, PAUSE_AUTONEG);
  10024. if (epause->rx_pause)
  10025. tp->link_config.flowctrl |= FLOW_CTRL_RX;
  10026. else
  10027. tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
  10028. if (epause->tx_pause)
  10029. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  10030. else
  10031. tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
  10032. if (netif_running(dev)) {
  10033. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  10034. err = tg3_restart_hw(tp, false);
  10035. if (!err)
  10036. tg3_netif_start(tp);
  10037. }
  10038. tg3_full_unlock(tp);
  10039. }
  10040. tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
  10041. return err;
  10042. }
  10043. static int tg3_get_sset_count(struct net_device *dev, int sset)
  10044. {
  10045. switch (sset) {
  10046. case ETH_SS_TEST:
  10047. return TG3_NUM_TEST;
  10048. case ETH_SS_STATS:
  10049. return TG3_NUM_STATS;
  10050. default:
  10051. return -EOPNOTSUPP;
  10052. }
  10053. }
  10054. static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
  10055. u32 *rules __always_unused)
  10056. {
  10057. struct tg3 *tp = netdev_priv(dev);
  10058. if (!tg3_flag(tp, SUPPORT_MSIX))
  10059. return -EOPNOTSUPP;
  10060. switch (info->cmd) {
  10061. case ETHTOOL_GRXRINGS:
  10062. if (netif_running(tp->dev))
  10063. info->data = tp->rxq_cnt;
  10064. else {
  10065. info->data = num_online_cpus();
  10066. if (info->data > TG3_RSS_MAX_NUM_QS)
  10067. info->data = TG3_RSS_MAX_NUM_QS;
  10068. }
  10069. /* The first interrupt vector only
  10070. * handles link interrupts.
  10071. */
  10072. info->data -= 1;
  10073. return 0;
  10074. default:
  10075. return -EOPNOTSUPP;
  10076. }
  10077. }
  10078. static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
  10079. {
  10080. u32 size = 0;
  10081. struct tg3 *tp = netdev_priv(dev);
  10082. if (tg3_flag(tp, SUPPORT_MSIX))
  10083. size = TG3_RSS_INDIR_TBL_SIZE;
  10084. return size;
  10085. }
  10086. static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
  10087. {
  10088. struct tg3 *tp = netdev_priv(dev);
  10089. int i;
  10090. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
  10091. indir[i] = tp->rss_ind_tbl[i];
  10092. return 0;
  10093. }
  10094. static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
  10095. {
  10096. struct tg3 *tp = netdev_priv(dev);
  10097. size_t i;
  10098. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
  10099. tp->rss_ind_tbl[i] = indir[i];
  10100. if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
  10101. return 0;
  10102. /* It is legal to write the indirection
  10103. * table while the device is running.
  10104. */
  10105. tg3_full_lock(tp, 0);
  10106. tg3_rss_write_indir_tbl(tp);
  10107. tg3_full_unlock(tp);
  10108. return 0;
  10109. }
  10110. static void tg3_get_channels(struct net_device *dev,
  10111. struct ethtool_channels *channel)
  10112. {
  10113. struct tg3 *tp = netdev_priv(dev);
  10114. u32 deflt_qs = netif_get_num_default_rss_queues();
  10115. channel->max_rx = tp->rxq_max;
  10116. channel->max_tx = tp->txq_max;
  10117. if (netif_running(dev)) {
  10118. channel->rx_count = tp->rxq_cnt;
  10119. channel->tx_count = tp->txq_cnt;
  10120. } else {
  10121. if (tp->rxq_req)
  10122. channel->rx_count = tp->rxq_req;
  10123. else
  10124. channel->rx_count = min(deflt_qs, tp->rxq_max);
  10125. if (tp->txq_req)
  10126. channel->tx_count = tp->txq_req;
  10127. else
  10128. channel->tx_count = min(deflt_qs, tp->txq_max);
  10129. }
  10130. }
  10131. static int tg3_set_channels(struct net_device *dev,
  10132. struct ethtool_channels *channel)
  10133. {
  10134. struct tg3 *tp = netdev_priv(dev);
  10135. if (!tg3_flag(tp, SUPPORT_MSIX))
  10136. return -EOPNOTSUPP;
  10137. if (channel->rx_count > tp->rxq_max ||
  10138. channel->tx_count > tp->txq_max)
  10139. return -EINVAL;
  10140. tp->rxq_req = channel->rx_count;
  10141. tp->txq_req = channel->tx_count;
  10142. if (!netif_running(dev))
  10143. return 0;
  10144. tg3_stop(tp);
  10145. tg3_carrier_off(tp);
  10146. tg3_start(tp, true, false, false);
  10147. return 0;
  10148. }
  10149. static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
  10150. {
  10151. switch (stringset) {
  10152. case ETH_SS_STATS:
  10153. memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
  10154. break;
  10155. case ETH_SS_TEST:
  10156. memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
  10157. break;
  10158. default:
  10159. WARN_ON(1); /* we need a WARN() */
  10160. break;
  10161. }
  10162. }
  10163. static int tg3_set_phys_id(struct net_device *dev,
  10164. enum ethtool_phys_id_state state)
  10165. {
  10166. struct tg3 *tp = netdev_priv(dev);
  10167. if (!netif_running(tp->dev))
  10168. return -EAGAIN;
  10169. switch (state) {
  10170. case ETHTOOL_ID_ACTIVE:
  10171. return 1; /* cycle on/off once per second */
  10172. case ETHTOOL_ID_ON:
  10173. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  10174. LED_CTRL_1000MBPS_ON |
  10175. LED_CTRL_100MBPS_ON |
  10176. LED_CTRL_10MBPS_ON |
  10177. LED_CTRL_TRAFFIC_OVERRIDE |
  10178. LED_CTRL_TRAFFIC_BLINK |
  10179. LED_CTRL_TRAFFIC_LED);
  10180. break;
  10181. case ETHTOOL_ID_OFF:
  10182. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  10183. LED_CTRL_TRAFFIC_OVERRIDE);
  10184. break;
  10185. case ETHTOOL_ID_INACTIVE:
  10186. tw32(MAC_LED_CTRL, tp->led_ctrl);
  10187. break;
  10188. }
  10189. return 0;
  10190. }
  10191. static void tg3_get_ethtool_stats(struct net_device *dev,
  10192. struct ethtool_stats *estats, u64 *tmp_stats)
  10193. {
  10194. struct tg3 *tp = netdev_priv(dev);
  10195. if (tp->hw_stats)
  10196. tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
  10197. else
  10198. memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
  10199. }
  10200. static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
  10201. {
  10202. int i;
  10203. __be32 *buf;
  10204. u32 offset = 0, len = 0;
  10205. u32 magic, val;
  10206. if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
  10207. return NULL;
  10208. if (magic == TG3_EEPROM_MAGIC) {
  10209. for (offset = TG3_NVM_DIR_START;
  10210. offset < TG3_NVM_DIR_END;
  10211. offset += TG3_NVM_DIRENT_SIZE) {
  10212. if (tg3_nvram_read(tp, offset, &val))
  10213. return NULL;
  10214. if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
  10215. TG3_NVM_DIRTYPE_EXTVPD)
  10216. break;
  10217. }
  10218. if (offset != TG3_NVM_DIR_END) {
  10219. len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
  10220. if (tg3_nvram_read(tp, offset + 4, &offset))
  10221. return NULL;
  10222. offset = tg3_nvram_logical_addr(tp, offset);
  10223. }
  10224. }
  10225. if (!offset || !len) {
  10226. offset = TG3_NVM_VPD_OFF;
  10227. len = TG3_NVM_VPD_LEN;
  10228. }
  10229. buf = kmalloc(len, GFP_KERNEL);
  10230. if (buf == NULL)
  10231. return NULL;
  10232. if (magic == TG3_EEPROM_MAGIC) {
  10233. for (i = 0; i < len; i += 4) {
  10234. /* The data is in little-endian format in NVRAM.
  10235. * Use the big-endian read routines to preserve
  10236. * the byte order as it exists in NVRAM.
  10237. */
  10238. if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
  10239. goto error;
  10240. }
  10241. } else {
  10242. u8 *ptr;
  10243. ssize_t cnt;
  10244. unsigned int pos = 0;
  10245. ptr = (u8 *)&buf[0];
  10246. for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
  10247. cnt = pci_read_vpd(tp->pdev, pos,
  10248. len - pos, ptr);
  10249. if (cnt == -ETIMEDOUT || cnt == -EINTR)
  10250. cnt = 0;
  10251. else if (cnt < 0)
  10252. goto error;
  10253. }
  10254. if (pos != len)
  10255. goto error;
  10256. }
  10257. *vpdlen = len;
  10258. return buf;
  10259. error:
  10260. kfree(buf);
  10261. return NULL;
  10262. }
  10263. #define NVRAM_TEST_SIZE 0x100
  10264. #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
  10265. #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
  10266. #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
  10267. #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
  10268. #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
  10269. #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
  10270. #define NVRAM_SELFBOOT_HW_SIZE 0x20
  10271. #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
  10272. static int tg3_test_nvram(struct tg3 *tp)
  10273. {
  10274. u32 csum, magic, len;
  10275. __be32 *buf;
  10276. int i, j, k, err = 0, size;
  10277. if (tg3_flag(tp, NO_NVRAM))
  10278. return 0;
  10279. if (tg3_nvram_read(tp, 0, &magic) != 0)
  10280. return -EIO;
  10281. if (magic == TG3_EEPROM_MAGIC)
  10282. size = NVRAM_TEST_SIZE;
  10283. else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
  10284. if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
  10285. TG3_EEPROM_SB_FORMAT_1) {
  10286. switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
  10287. case TG3_EEPROM_SB_REVISION_0:
  10288. size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
  10289. break;
  10290. case TG3_EEPROM_SB_REVISION_2:
  10291. size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
  10292. break;
  10293. case TG3_EEPROM_SB_REVISION_3:
  10294. size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
  10295. break;
  10296. case TG3_EEPROM_SB_REVISION_4:
  10297. size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
  10298. break;
  10299. case TG3_EEPROM_SB_REVISION_5:
  10300. size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
  10301. break;
  10302. case TG3_EEPROM_SB_REVISION_6:
  10303. size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
  10304. break;
  10305. default:
  10306. return -EIO;
  10307. }
  10308. } else
  10309. return 0;
  10310. } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  10311. size = NVRAM_SELFBOOT_HW_SIZE;
  10312. else
  10313. return -EIO;
  10314. buf = kmalloc(size, GFP_KERNEL);
  10315. if (buf == NULL)
  10316. return -ENOMEM;
  10317. err = -EIO;
  10318. for (i = 0, j = 0; i < size; i += 4, j++) {
  10319. err = tg3_nvram_read_be32(tp, i, &buf[j]);
  10320. if (err)
  10321. break;
  10322. }
  10323. if (i < size)
  10324. goto out;
  10325. /* Selfboot format */
  10326. magic = be32_to_cpu(buf[0]);
  10327. if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
  10328. TG3_EEPROM_MAGIC_FW) {
  10329. u8 *buf8 = (u8 *) buf, csum8 = 0;
  10330. if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
  10331. TG3_EEPROM_SB_REVISION_2) {
  10332. /* For rev 2, the csum doesn't include the MBA. */
  10333. for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
  10334. csum8 += buf8[i];
  10335. for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
  10336. csum8 += buf8[i];
  10337. } else {
  10338. for (i = 0; i < size; i++)
  10339. csum8 += buf8[i];
  10340. }
  10341. if (csum8 == 0) {
  10342. err = 0;
  10343. goto out;
  10344. }
  10345. err = -EIO;
  10346. goto out;
  10347. }
  10348. if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
  10349. TG3_EEPROM_MAGIC_HW) {
  10350. u8 data[NVRAM_SELFBOOT_DATA_SIZE];
  10351. u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
  10352. u8 *buf8 = (u8 *) buf;
  10353. /* Separate the parity bits and the data bytes. */
  10354. for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
  10355. if ((i == 0) || (i == 8)) {
  10356. int l;
  10357. u8 msk;
  10358. for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
  10359. parity[k++] = buf8[i] & msk;
  10360. i++;
  10361. } else if (i == 16) {
  10362. int l;
  10363. u8 msk;
  10364. for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
  10365. parity[k++] = buf8[i] & msk;
  10366. i++;
  10367. for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
  10368. parity[k++] = buf8[i] & msk;
  10369. i++;
  10370. }
  10371. data[j++] = buf8[i];
  10372. }
  10373. err = -EIO;
  10374. for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
  10375. u8 hw8 = hweight8(data[i]);
  10376. if ((hw8 & 0x1) && parity[i])
  10377. goto out;
  10378. else if (!(hw8 & 0x1) && !parity[i])
  10379. goto out;
  10380. }
  10381. err = 0;
  10382. goto out;
  10383. }
  10384. err = -EIO;
  10385. /* Bootstrap checksum at offset 0x10 */
  10386. csum = calc_crc((unsigned char *) buf, 0x10);
  10387. if (csum != le32_to_cpu(buf[0x10/4]))
  10388. goto out;
  10389. /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
  10390. csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
  10391. if (csum != le32_to_cpu(buf[0xfc/4]))
  10392. goto out;
  10393. kfree(buf);
  10394. buf = tg3_vpd_readblock(tp, &len);
  10395. if (!buf)
  10396. return -ENOMEM;
  10397. i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
  10398. if (i > 0) {
  10399. j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
  10400. if (j < 0)
  10401. goto out;
  10402. if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
  10403. goto out;
  10404. i += PCI_VPD_LRDT_TAG_SIZE;
  10405. j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
  10406. PCI_VPD_RO_KEYWORD_CHKSUM);
  10407. if (j > 0) {
  10408. u8 csum8 = 0;
  10409. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  10410. for (i = 0; i <= j; i++)
  10411. csum8 += ((u8 *)buf)[i];
  10412. if (csum8)
  10413. goto out;
  10414. }
  10415. }
  10416. err = 0;
  10417. out:
  10418. kfree(buf);
  10419. return err;
  10420. }
  10421. #define TG3_SERDES_TIMEOUT_SEC 2
  10422. #define TG3_COPPER_TIMEOUT_SEC 6
  10423. static int tg3_test_link(struct tg3 *tp)
  10424. {
  10425. int i, max;
  10426. if (!netif_running(tp->dev))
  10427. return -ENODEV;
  10428. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  10429. max = TG3_SERDES_TIMEOUT_SEC;
  10430. else
  10431. max = TG3_COPPER_TIMEOUT_SEC;
  10432. for (i = 0; i < max; i++) {
  10433. if (tp->link_up)
  10434. return 0;
  10435. if (msleep_interruptible(1000))
  10436. break;
  10437. }
  10438. return -EIO;
  10439. }
  10440. /* Only test the commonly used registers */
  10441. static int tg3_test_registers(struct tg3 *tp)
  10442. {
  10443. int i, is_5705, is_5750;
  10444. u32 offset, read_mask, write_mask, val, save_val, read_val;
  10445. static struct {
  10446. u16 offset;
  10447. u16 flags;
  10448. #define TG3_FL_5705 0x1
  10449. #define TG3_FL_NOT_5705 0x2
  10450. #define TG3_FL_NOT_5788 0x4
  10451. #define TG3_FL_NOT_5750 0x8
  10452. u32 read_mask;
  10453. u32 write_mask;
  10454. } reg_tbl[] = {
  10455. /* MAC Control Registers */
  10456. { MAC_MODE, TG3_FL_NOT_5705,
  10457. 0x00000000, 0x00ef6f8c },
  10458. { MAC_MODE, TG3_FL_5705,
  10459. 0x00000000, 0x01ef6b8c },
  10460. { MAC_STATUS, TG3_FL_NOT_5705,
  10461. 0x03800107, 0x00000000 },
  10462. { MAC_STATUS, TG3_FL_5705,
  10463. 0x03800100, 0x00000000 },
  10464. { MAC_ADDR_0_HIGH, 0x0000,
  10465. 0x00000000, 0x0000ffff },
  10466. { MAC_ADDR_0_LOW, 0x0000,
  10467. 0x00000000, 0xffffffff },
  10468. { MAC_RX_MTU_SIZE, 0x0000,
  10469. 0x00000000, 0x0000ffff },
  10470. { MAC_TX_MODE, 0x0000,
  10471. 0x00000000, 0x00000070 },
  10472. { MAC_TX_LENGTHS, 0x0000,
  10473. 0x00000000, 0x00003fff },
  10474. { MAC_RX_MODE, TG3_FL_NOT_5705,
  10475. 0x00000000, 0x000007fc },
  10476. { MAC_RX_MODE, TG3_FL_5705,
  10477. 0x00000000, 0x000007dc },
  10478. { MAC_HASH_REG_0, 0x0000,
  10479. 0x00000000, 0xffffffff },
  10480. { MAC_HASH_REG_1, 0x0000,
  10481. 0x00000000, 0xffffffff },
  10482. { MAC_HASH_REG_2, 0x0000,
  10483. 0x00000000, 0xffffffff },
  10484. { MAC_HASH_REG_3, 0x0000,
  10485. 0x00000000, 0xffffffff },
  10486. /* Receive Data and Receive BD Initiator Control Registers. */
  10487. { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
  10488. 0x00000000, 0xffffffff },
  10489. { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
  10490. 0x00000000, 0xffffffff },
  10491. { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
  10492. 0x00000000, 0x00000003 },
  10493. { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
  10494. 0x00000000, 0xffffffff },
  10495. { RCVDBDI_STD_BD+0, 0x0000,
  10496. 0x00000000, 0xffffffff },
  10497. { RCVDBDI_STD_BD+4, 0x0000,
  10498. 0x00000000, 0xffffffff },
  10499. { RCVDBDI_STD_BD+8, 0x0000,
  10500. 0x00000000, 0xffff0002 },
  10501. { RCVDBDI_STD_BD+0xc, 0x0000,
  10502. 0x00000000, 0xffffffff },
  10503. /* Receive BD Initiator Control Registers. */
  10504. { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
  10505. 0x00000000, 0xffffffff },
  10506. { RCVBDI_STD_THRESH, TG3_FL_5705,
  10507. 0x00000000, 0x000003ff },
  10508. { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
  10509. 0x00000000, 0xffffffff },
  10510. /* Host Coalescing Control Registers. */
  10511. { HOSTCC_MODE, TG3_FL_NOT_5705,
  10512. 0x00000000, 0x00000004 },
  10513. { HOSTCC_MODE, TG3_FL_5705,
  10514. 0x00000000, 0x000000f6 },
  10515. { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
  10516. 0x00000000, 0xffffffff },
  10517. { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
  10518. 0x00000000, 0x000003ff },
  10519. { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
  10520. 0x00000000, 0xffffffff },
  10521. { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
  10522. 0x00000000, 0x000003ff },
  10523. { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
  10524. 0x00000000, 0xffffffff },
  10525. { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  10526. 0x00000000, 0x000000ff },
  10527. { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
  10528. 0x00000000, 0xffffffff },
  10529. { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  10530. 0x00000000, 0x000000ff },
  10531. { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
  10532. 0x00000000, 0xffffffff },
  10533. { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
  10534. 0x00000000, 0xffffffff },
  10535. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  10536. 0x00000000, 0xffffffff },
  10537. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  10538. 0x00000000, 0x000000ff },
  10539. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  10540. 0x00000000, 0xffffffff },
  10541. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  10542. 0x00000000, 0x000000ff },
  10543. { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
  10544. 0x00000000, 0xffffffff },
  10545. { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
  10546. 0x00000000, 0xffffffff },
  10547. { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
  10548. 0x00000000, 0xffffffff },
  10549. { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
  10550. 0x00000000, 0xffffffff },
  10551. { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
  10552. 0x00000000, 0xffffffff },
  10553. { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
  10554. 0xffffffff, 0x00000000 },
  10555. { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
  10556. 0xffffffff, 0x00000000 },
  10557. /* Buffer Manager Control Registers. */
  10558. { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
  10559. 0x00000000, 0x007fff80 },
  10560. { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
  10561. 0x00000000, 0x007fffff },
  10562. { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
  10563. 0x00000000, 0x0000003f },
  10564. { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
  10565. 0x00000000, 0x000001ff },
  10566. { BUFMGR_MB_HIGH_WATER, 0x0000,
  10567. 0x00000000, 0x000001ff },
  10568. { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
  10569. 0xffffffff, 0x00000000 },
  10570. { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
  10571. 0xffffffff, 0x00000000 },
  10572. /* Mailbox Registers */
  10573. { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
  10574. 0x00000000, 0x000001ff },
  10575. { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
  10576. 0x00000000, 0x000001ff },
  10577. { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
  10578. 0x00000000, 0x000007ff },
  10579. { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
  10580. 0x00000000, 0x000001ff },
  10581. { 0xffff, 0x0000, 0x00000000, 0x00000000 },
  10582. };
  10583. is_5705 = is_5750 = 0;
  10584. if (tg3_flag(tp, 5705_PLUS)) {
  10585. is_5705 = 1;
  10586. if (tg3_flag(tp, 5750_PLUS))
  10587. is_5750 = 1;
  10588. }
  10589. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  10590. if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
  10591. continue;
  10592. if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
  10593. continue;
  10594. if (tg3_flag(tp, IS_5788) &&
  10595. (reg_tbl[i].flags & TG3_FL_NOT_5788))
  10596. continue;
  10597. if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
  10598. continue;
  10599. offset = (u32) reg_tbl[i].offset;
  10600. read_mask = reg_tbl[i].read_mask;
  10601. write_mask = reg_tbl[i].write_mask;
  10602. /* Save the original register content */
  10603. save_val = tr32(offset);
  10604. /* Determine the read-only value. */
  10605. read_val = save_val & read_mask;
  10606. /* Write zero to the register, then make sure the read-only bits
  10607. * are not changed and the read/write bits are all zeros.
  10608. */
  10609. tw32(offset, 0);
  10610. val = tr32(offset);
  10611. /* Test the read-only and read/write bits. */
  10612. if (((val & read_mask) != read_val) || (val & write_mask))
  10613. goto out;
  10614. /* Write ones to all the bits defined by RdMask and WrMask, then
  10615. * make sure the read-only bits are not changed and the
  10616. * read/write bits are all ones.
  10617. */
  10618. tw32(offset, read_mask | write_mask);
  10619. val = tr32(offset);
  10620. /* Test the read-only bits. */
  10621. if ((val & read_mask) != read_val)
  10622. goto out;
  10623. /* Test the read/write bits. */
  10624. if ((val & write_mask) != write_mask)
  10625. goto out;
  10626. tw32(offset, save_val);
  10627. }
  10628. return 0;
  10629. out:
  10630. if (netif_msg_hw(tp))
  10631. netdev_err(tp->dev,
  10632. "Register test failed at offset %x\n", offset);
  10633. tw32(offset, save_val);
  10634. return -EIO;
  10635. }
  10636. static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
  10637. {
  10638. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
  10639. int i;
  10640. u32 j;
  10641. for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
  10642. for (j = 0; j < len; j += 4) {
  10643. u32 val;
  10644. tg3_write_mem(tp, offset + j, test_pattern[i]);
  10645. tg3_read_mem(tp, offset + j, &val);
  10646. if (val != test_pattern[i])
  10647. return -EIO;
  10648. }
  10649. }
  10650. return 0;
  10651. }
  10652. static int tg3_test_memory(struct tg3 *tp)
  10653. {
  10654. static struct mem_entry {
  10655. u32 offset;
  10656. u32 len;
  10657. } mem_tbl_570x[] = {
  10658. { 0x00000000, 0x00b50},
  10659. { 0x00002000, 0x1c000},
  10660. { 0xffffffff, 0x00000}
  10661. }, mem_tbl_5705[] = {
  10662. { 0x00000100, 0x0000c},
  10663. { 0x00000200, 0x00008},
  10664. { 0x00004000, 0x00800},
  10665. { 0x00006000, 0x01000},
  10666. { 0x00008000, 0x02000},
  10667. { 0x00010000, 0x0e000},
  10668. { 0xffffffff, 0x00000}
  10669. }, mem_tbl_5755[] = {
  10670. { 0x00000200, 0x00008},
  10671. { 0x00004000, 0x00800},
  10672. { 0x00006000, 0x00800},
  10673. { 0x00008000, 0x02000},
  10674. { 0x00010000, 0x0c000},
  10675. { 0xffffffff, 0x00000}
  10676. }, mem_tbl_5906[] = {
  10677. { 0x00000200, 0x00008},
  10678. { 0x00004000, 0x00400},
  10679. { 0x00006000, 0x00400},
  10680. { 0x00008000, 0x01000},
  10681. { 0x00010000, 0x01000},
  10682. { 0xffffffff, 0x00000}
  10683. }, mem_tbl_5717[] = {
  10684. { 0x00000200, 0x00008},
  10685. { 0x00010000, 0x0a000},
  10686. { 0x00020000, 0x13c00},
  10687. { 0xffffffff, 0x00000}
  10688. }, mem_tbl_57765[] = {
  10689. { 0x00000200, 0x00008},
  10690. { 0x00004000, 0x00800},
  10691. { 0x00006000, 0x09800},
  10692. { 0x00010000, 0x0a000},
  10693. { 0xffffffff, 0x00000}
  10694. };
  10695. struct mem_entry *mem_tbl;
  10696. int err = 0;
  10697. int i;
  10698. if (tg3_flag(tp, 5717_PLUS))
  10699. mem_tbl = mem_tbl_5717;
  10700. else if (tg3_flag(tp, 57765_CLASS) ||
  10701. tg3_asic_rev(tp) == ASIC_REV_5762)
  10702. mem_tbl = mem_tbl_57765;
  10703. else if (tg3_flag(tp, 5755_PLUS))
  10704. mem_tbl = mem_tbl_5755;
  10705. else if (tg3_asic_rev(tp) == ASIC_REV_5906)
  10706. mem_tbl = mem_tbl_5906;
  10707. else if (tg3_flag(tp, 5705_PLUS))
  10708. mem_tbl = mem_tbl_5705;
  10709. else
  10710. mem_tbl = mem_tbl_570x;
  10711. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  10712. err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
  10713. if (err)
  10714. break;
  10715. }
  10716. return err;
  10717. }
  10718. #define TG3_TSO_MSS 500
  10719. #define TG3_TSO_IP_HDR_LEN 20
  10720. #define TG3_TSO_TCP_HDR_LEN 20
  10721. #define TG3_TSO_TCP_OPT_LEN 12
  10722. static const u8 tg3_tso_header[] = {
  10723. 0x08, 0x00,
  10724. 0x45, 0x00, 0x00, 0x00,
  10725. 0x00, 0x00, 0x40, 0x00,
  10726. 0x40, 0x06, 0x00, 0x00,
  10727. 0x0a, 0x00, 0x00, 0x01,
  10728. 0x0a, 0x00, 0x00, 0x02,
  10729. 0x0d, 0x00, 0xe0, 0x00,
  10730. 0x00, 0x00, 0x01, 0x00,
  10731. 0x00, 0x00, 0x02, 0x00,
  10732. 0x80, 0x10, 0x10, 0x00,
  10733. 0x14, 0x09, 0x00, 0x00,
  10734. 0x01, 0x01, 0x08, 0x0a,
  10735. 0x11, 0x11, 0x11, 0x11,
  10736. 0x11, 0x11, 0x11, 0x11,
  10737. };
  10738. static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
  10739. {
  10740. u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
  10741. u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
  10742. u32 budget;
  10743. struct sk_buff *skb;
  10744. u8 *tx_data, *rx_data;
  10745. dma_addr_t map;
  10746. int num_pkts, tx_len, rx_len, i, err;
  10747. struct tg3_rx_buffer_desc *desc;
  10748. struct tg3_napi *tnapi, *rnapi;
  10749. struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
  10750. tnapi = &tp->napi[0];
  10751. rnapi = &tp->napi[0];
  10752. if (tp->irq_cnt > 1) {
  10753. if (tg3_flag(tp, ENABLE_RSS))
  10754. rnapi = &tp->napi[1];
  10755. if (tg3_flag(tp, ENABLE_TSS))
  10756. tnapi = &tp->napi[1];
  10757. }
  10758. coal_now = tnapi->coal_now | rnapi->coal_now;
  10759. err = -EIO;
  10760. tx_len = pktsz;
  10761. skb = netdev_alloc_skb(tp->dev, tx_len);
  10762. if (!skb)
  10763. return -ENOMEM;
  10764. tx_data = skb_put(skb, tx_len);
  10765. memcpy(tx_data, tp->dev->dev_addr, 6);
  10766. memset(tx_data + 6, 0x0, 8);
  10767. tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
  10768. if (tso_loopback) {
  10769. struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
  10770. u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
  10771. TG3_TSO_TCP_OPT_LEN;
  10772. memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
  10773. sizeof(tg3_tso_header));
  10774. mss = TG3_TSO_MSS;
  10775. val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
  10776. num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
  10777. /* Set the total length field in the IP header */
  10778. iph->tot_len = htons((u16)(mss + hdr_len));
  10779. base_flags = (TXD_FLAG_CPU_PRE_DMA |
  10780. TXD_FLAG_CPU_POST_DMA);
  10781. if (tg3_flag(tp, HW_TSO_1) ||
  10782. tg3_flag(tp, HW_TSO_2) ||
  10783. tg3_flag(tp, HW_TSO_3)) {
  10784. struct tcphdr *th;
  10785. val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
  10786. th = (struct tcphdr *)&tx_data[val];
  10787. th->check = 0;
  10788. } else
  10789. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  10790. if (tg3_flag(tp, HW_TSO_3)) {
  10791. mss |= (hdr_len & 0xc) << 12;
  10792. if (hdr_len & 0x10)
  10793. base_flags |= 0x00000010;
  10794. base_flags |= (hdr_len & 0x3e0) << 5;
  10795. } else if (tg3_flag(tp, HW_TSO_2))
  10796. mss |= hdr_len << 9;
  10797. else if (tg3_flag(tp, HW_TSO_1) ||
  10798. tg3_asic_rev(tp) == ASIC_REV_5705) {
  10799. mss |= (TG3_TSO_TCP_OPT_LEN << 9);
  10800. } else {
  10801. base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
  10802. }
  10803. data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
  10804. } else {
  10805. num_pkts = 1;
  10806. data_off = ETH_HLEN;
  10807. if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
  10808. tx_len > VLAN_ETH_FRAME_LEN)
  10809. base_flags |= TXD_FLAG_JMB_PKT;
  10810. }
  10811. for (i = data_off; i < tx_len; i++)
  10812. tx_data[i] = (u8) (i & 0xff);
  10813. map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
  10814. if (pci_dma_mapping_error(tp->pdev, map)) {
  10815. dev_kfree_skb(skb);
  10816. return -EIO;
  10817. }
  10818. val = tnapi->tx_prod;
  10819. tnapi->tx_buffers[val].skb = skb;
  10820. dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
  10821. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  10822. rnapi->coal_now);
  10823. udelay(10);
  10824. rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
  10825. budget = tg3_tx_avail(tnapi);
  10826. if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
  10827. base_flags | TXD_FLAG_END, mss, 0)) {
  10828. tnapi->tx_buffers[val].skb = NULL;
  10829. dev_kfree_skb(skb);
  10830. return -EIO;
  10831. }
  10832. tnapi->tx_prod++;
  10833. /* Sync BD data before updating mailbox */
  10834. wmb();
  10835. tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
  10836. tr32_mailbox(tnapi->prodmbox);
  10837. udelay(10);
  10838. /* 350 usec to allow enough time on some 10/100 Mbps devices. */
  10839. for (i = 0; i < 35; i++) {
  10840. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  10841. coal_now);
  10842. udelay(10);
  10843. tx_idx = tnapi->hw_status->idx[0].tx_consumer;
  10844. rx_idx = rnapi->hw_status->idx[0].rx_producer;
  10845. if ((tx_idx == tnapi->tx_prod) &&
  10846. (rx_idx == (rx_start_idx + num_pkts)))
  10847. break;
  10848. }
  10849. tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
  10850. dev_kfree_skb(skb);
  10851. if (tx_idx != tnapi->tx_prod)
  10852. goto out;
  10853. if (rx_idx != rx_start_idx + num_pkts)
  10854. goto out;
  10855. val = data_off;
  10856. while (rx_idx != rx_start_idx) {
  10857. desc = &rnapi->rx_rcb[rx_start_idx++];
  10858. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  10859. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  10860. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  10861. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
  10862. goto out;
  10863. rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
  10864. - ETH_FCS_LEN;
  10865. if (!tso_loopback) {
  10866. if (rx_len != tx_len)
  10867. goto out;
  10868. if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
  10869. if (opaque_key != RXD_OPAQUE_RING_STD)
  10870. goto out;
  10871. } else {
  10872. if (opaque_key != RXD_OPAQUE_RING_JUMBO)
  10873. goto out;
  10874. }
  10875. } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  10876. (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  10877. >> RXD_TCPCSUM_SHIFT != 0xffff) {
  10878. goto out;
  10879. }
  10880. if (opaque_key == RXD_OPAQUE_RING_STD) {
  10881. rx_data = tpr->rx_std_buffers[desc_idx].data;
  10882. map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
  10883. mapping);
  10884. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  10885. rx_data = tpr->rx_jmb_buffers[desc_idx].data;
  10886. map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
  10887. mapping);
  10888. } else
  10889. goto out;
  10890. pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
  10891. PCI_DMA_FROMDEVICE);
  10892. rx_data += TG3_RX_OFFSET(tp);
  10893. for (i = data_off; i < rx_len; i++, val++) {
  10894. if (*(rx_data + i) != (u8) (val & 0xff))
  10895. goto out;
  10896. }
  10897. }
  10898. err = 0;
  10899. /* tg3_free_rings will unmap and free the rx_data */
  10900. out:
  10901. return err;
  10902. }
  10903. #define TG3_STD_LOOPBACK_FAILED 1
  10904. #define TG3_JMB_LOOPBACK_FAILED 2
  10905. #define TG3_TSO_LOOPBACK_FAILED 4
  10906. #define TG3_LOOPBACK_FAILED \
  10907. (TG3_STD_LOOPBACK_FAILED | \
  10908. TG3_JMB_LOOPBACK_FAILED | \
  10909. TG3_TSO_LOOPBACK_FAILED)
  10910. static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
  10911. {
  10912. int err = -EIO;
  10913. u32 eee_cap;
  10914. u32 jmb_pkt_sz = 9000;
  10915. if (tp->dma_limit)
  10916. jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
  10917. eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
  10918. tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
  10919. if (!netif_running(tp->dev)) {
  10920. data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10921. data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10922. if (do_extlpbk)
  10923. data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10924. goto done;
  10925. }
  10926. err = tg3_reset_hw(tp, true);
  10927. if (err) {
  10928. data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10929. data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10930. if (do_extlpbk)
  10931. data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10932. goto done;
  10933. }
  10934. if (tg3_flag(tp, ENABLE_RSS)) {
  10935. int i;
  10936. /* Reroute all rx packets to the 1st queue */
  10937. for (i = MAC_RSS_INDIR_TBL_0;
  10938. i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
  10939. tw32(i, 0x0);
  10940. }
  10941. /* HW errata - mac loopback fails in some cases on 5780.
  10942. * Normal traffic and PHY loopback are not affected by
  10943. * errata. Also, the MAC loopback test is deprecated for
  10944. * all newer ASIC revisions.
  10945. */
  10946. if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
  10947. !tg3_flag(tp, CPMU_PRESENT)) {
  10948. tg3_mac_loopback(tp, true);
  10949. if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
  10950. data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
  10951. if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
  10952. tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
  10953. data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
  10954. tg3_mac_loopback(tp, false);
  10955. }
  10956. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  10957. !tg3_flag(tp, USE_PHYLIB)) {
  10958. int i;
  10959. tg3_phy_lpbk_set(tp, 0, false);
  10960. /* Wait for link */
  10961. for (i = 0; i < 100; i++) {
  10962. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  10963. break;
  10964. mdelay(1);
  10965. }
  10966. if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
  10967. data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
  10968. if (tg3_flag(tp, TSO_CAPABLE) &&
  10969. tg3_run_loopback(tp, ETH_FRAME_LEN, true))
  10970. data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
  10971. if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
  10972. tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
  10973. data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
  10974. if (do_extlpbk) {
  10975. tg3_phy_lpbk_set(tp, 0, true);
  10976. /* All link indications report up, but the hardware
  10977. * isn't really ready for about 20 msec. Double it
  10978. * to be sure.
  10979. */
  10980. mdelay(40);
  10981. if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
  10982. data[TG3_EXT_LOOPB_TEST] |=
  10983. TG3_STD_LOOPBACK_FAILED;
  10984. if (tg3_flag(tp, TSO_CAPABLE) &&
  10985. tg3_run_loopback(tp, ETH_FRAME_LEN, true))
  10986. data[TG3_EXT_LOOPB_TEST] |=
  10987. TG3_TSO_LOOPBACK_FAILED;
  10988. if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
  10989. tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
  10990. data[TG3_EXT_LOOPB_TEST] |=
  10991. TG3_JMB_LOOPBACK_FAILED;
  10992. }
  10993. /* Re-enable gphy autopowerdown. */
  10994. if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
  10995. tg3_phy_toggle_apd(tp, true);
  10996. }
  10997. err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
  10998. data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
  10999. done:
  11000. tp->phy_flags |= eee_cap;
  11001. return err;
  11002. }
  11003. static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
  11004. u64 *data)
  11005. {
  11006. struct tg3 *tp = netdev_priv(dev);
  11007. bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
  11008. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
  11009. if (tg3_power_up(tp)) {
  11010. etest->flags |= ETH_TEST_FL_FAILED;
  11011. memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
  11012. return;
  11013. }
  11014. tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
  11015. }
  11016. memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
  11017. if (tg3_test_nvram(tp) != 0) {
  11018. etest->flags |= ETH_TEST_FL_FAILED;
  11019. data[TG3_NVRAM_TEST] = 1;
  11020. }
  11021. if (!doextlpbk && tg3_test_link(tp)) {
  11022. etest->flags |= ETH_TEST_FL_FAILED;
  11023. data[TG3_LINK_TEST] = 1;
  11024. }
  11025. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  11026. int err, err2 = 0, irq_sync = 0;
  11027. if (netif_running(dev)) {
  11028. tg3_phy_stop(tp);
  11029. tg3_netif_stop(tp);
  11030. irq_sync = 1;
  11031. }
  11032. tg3_full_lock(tp, irq_sync);
  11033. tg3_halt(tp, RESET_KIND_SUSPEND, 1);
  11034. err = tg3_nvram_lock(tp);
  11035. tg3_halt_cpu(tp, RX_CPU_BASE);
  11036. if (!tg3_flag(tp, 5705_PLUS))
  11037. tg3_halt_cpu(tp, TX_CPU_BASE);
  11038. if (!err)
  11039. tg3_nvram_unlock(tp);
  11040. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  11041. tg3_phy_reset(tp);
  11042. if (tg3_test_registers(tp) != 0) {
  11043. etest->flags |= ETH_TEST_FL_FAILED;
  11044. data[TG3_REGISTER_TEST] = 1;
  11045. }
  11046. if (tg3_test_memory(tp) != 0) {
  11047. etest->flags |= ETH_TEST_FL_FAILED;
  11048. data[TG3_MEMORY_TEST] = 1;
  11049. }
  11050. if (doextlpbk)
  11051. etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
  11052. if (tg3_test_loopback(tp, data, doextlpbk))
  11053. etest->flags |= ETH_TEST_FL_FAILED;
  11054. tg3_full_unlock(tp);
  11055. if (tg3_test_interrupt(tp) != 0) {
  11056. etest->flags |= ETH_TEST_FL_FAILED;
  11057. data[TG3_INTERRUPT_TEST] = 1;
  11058. }
  11059. tg3_full_lock(tp, 0);
  11060. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  11061. if (netif_running(dev)) {
  11062. tg3_flag_set(tp, INIT_COMPLETE);
  11063. err2 = tg3_restart_hw(tp, true);
  11064. if (!err2)
  11065. tg3_netif_start(tp);
  11066. }
  11067. tg3_full_unlock(tp);
  11068. if (irq_sync && !err2)
  11069. tg3_phy_start(tp);
  11070. }
  11071. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  11072. tg3_power_down(tp);
  11073. }
  11074. static int tg3_hwtstamp_ioctl(struct net_device *dev,
  11075. struct ifreq *ifr, int cmd)
  11076. {
  11077. struct tg3 *tp = netdev_priv(dev);
  11078. struct hwtstamp_config stmpconf;
  11079. if (!tg3_flag(tp, PTP_CAPABLE))
  11080. return -EINVAL;
  11081. if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
  11082. return -EFAULT;
  11083. if (stmpconf.flags)
  11084. return -EINVAL;
  11085. switch (stmpconf.tx_type) {
  11086. case HWTSTAMP_TX_ON:
  11087. tg3_flag_set(tp, TX_TSTAMP_EN);
  11088. break;
  11089. case HWTSTAMP_TX_OFF:
  11090. tg3_flag_clear(tp, TX_TSTAMP_EN);
  11091. break;
  11092. default:
  11093. return -ERANGE;
  11094. }
  11095. switch (stmpconf.rx_filter) {
  11096. case HWTSTAMP_FILTER_NONE:
  11097. tp->rxptpctl = 0;
  11098. break;
  11099. case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
  11100. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
  11101. TG3_RX_PTP_CTL_ALL_V1_EVENTS;
  11102. break;
  11103. case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
  11104. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
  11105. TG3_RX_PTP_CTL_SYNC_EVNT;
  11106. break;
  11107. case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
  11108. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
  11109. TG3_RX_PTP_CTL_DELAY_REQ;
  11110. break;
  11111. case HWTSTAMP_FILTER_PTP_V2_EVENT:
  11112. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
  11113. TG3_RX_PTP_CTL_ALL_V2_EVENTS;
  11114. break;
  11115. case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
  11116. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
  11117. TG3_RX_PTP_CTL_ALL_V2_EVENTS;
  11118. break;
  11119. case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
  11120. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
  11121. TG3_RX_PTP_CTL_ALL_V2_EVENTS;
  11122. break;
  11123. case HWTSTAMP_FILTER_PTP_V2_SYNC:
  11124. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
  11125. TG3_RX_PTP_CTL_SYNC_EVNT;
  11126. break;
  11127. case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
  11128. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
  11129. TG3_RX_PTP_CTL_SYNC_EVNT;
  11130. break;
  11131. case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
  11132. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
  11133. TG3_RX_PTP_CTL_SYNC_EVNT;
  11134. break;
  11135. case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
  11136. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
  11137. TG3_RX_PTP_CTL_DELAY_REQ;
  11138. break;
  11139. case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
  11140. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
  11141. TG3_RX_PTP_CTL_DELAY_REQ;
  11142. break;
  11143. case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
  11144. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
  11145. TG3_RX_PTP_CTL_DELAY_REQ;
  11146. break;
  11147. default:
  11148. return -ERANGE;
  11149. }
  11150. if (netif_running(dev) && tp->rxptpctl)
  11151. tw32(TG3_RX_PTP_CTL,
  11152. tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
  11153. return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
  11154. -EFAULT : 0;
  11155. }
  11156. static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  11157. {
  11158. struct mii_ioctl_data *data = if_mii(ifr);
  11159. struct tg3 *tp = netdev_priv(dev);
  11160. int err;
  11161. if (tg3_flag(tp, USE_PHYLIB)) {
  11162. struct phy_device *phydev;
  11163. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  11164. return -EAGAIN;
  11165. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  11166. return phy_mii_ioctl(phydev, ifr, cmd);
  11167. }
  11168. switch (cmd) {
  11169. case SIOCGMIIPHY:
  11170. data->phy_id = tp->phy_addr;
  11171. /* fallthru */
  11172. case SIOCGMIIREG: {
  11173. u32 mii_regval;
  11174. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  11175. break; /* We have no PHY */
  11176. if (!netif_running(dev))
  11177. return -EAGAIN;
  11178. spin_lock_bh(&tp->lock);
  11179. err = __tg3_readphy(tp, data->phy_id & 0x1f,
  11180. data->reg_num & 0x1f, &mii_regval);
  11181. spin_unlock_bh(&tp->lock);
  11182. data->val_out = mii_regval;
  11183. return err;
  11184. }
  11185. case SIOCSMIIREG:
  11186. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  11187. break; /* We have no PHY */
  11188. if (!netif_running(dev))
  11189. return -EAGAIN;
  11190. spin_lock_bh(&tp->lock);
  11191. err = __tg3_writephy(tp, data->phy_id & 0x1f,
  11192. data->reg_num & 0x1f, data->val_in);
  11193. spin_unlock_bh(&tp->lock);
  11194. return err;
  11195. case SIOCSHWTSTAMP:
  11196. return tg3_hwtstamp_ioctl(dev, ifr, cmd);
  11197. default:
  11198. /* do nothing */
  11199. break;
  11200. }
  11201. return -EOPNOTSUPP;
  11202. }
  11203. static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  11204. {
  11205. struct tg3 *tp = netdev_priv(dev);
  11206. memcpy(ec, &tp->coal, sizeof(*ec));
  11207. return 0;
  11208. }
  11209. static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  11210. {
  11211. struct tg3 *tp = netdev_priv(dev);
  11212. u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
  11213. u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
  11214. if (!tg3_flag(tp, 5705_PLUS)) {
  11215. max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
  11216. max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
  11217. max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
  11218. min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
  11219. }
  11220. if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
  11221. (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
  11222. (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
  11223. (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
  11224. (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
  11225. (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
  11226. (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
  11227. (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
  11228. (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
  11229. (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
  11230. return -EINVAL;
  11231. /* No rx interrupts will be generated if both are zero */
  11232. if ((ec->rx_coalesce_usecs == 0) &&
  11233. (ec->rx_max_coalesced_frames == 0))
  11234. return -EINVAL;
  11235. /* No tx interrupts will be generated if both are zero */
  11236. if ((ec->tx_coalesce_usecs == 0) &&
  11237. (ec->tx_max_coalesced_frames == 0))
  11238. return -EINVAL;
  11239. /* Only copy relevant parameters, ignore all others. */
  11240. tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
  11241. tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
  11242. tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
  11243. tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
  11244. tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
  11245. tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
  11246. tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
  11247. tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
  11248. tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
  11249. if (netif_running(dev)) {
  11250. tg3_full_lock(tp, 0);
  11251. __tg3_set_coalesce(tp, &tp->coal);
  11252. tg3_full_unlock(tp);
  11253. }
  11254. return 0;
  11255. }
  11256. static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
  11257. {
  11258. struct tg3 *tp = netdev_priv(dev);
  11259. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
  11260. netdev_warn(tp->dev, "Board does not support EEE!\n");
  11261. return -EOPNOTSUPP;
  11262. }
  11263. if (edata->advertised != tp->eee.advertised) {
  11264. netdev_warn(tp->dev,
  11265. "Direct manipulation of EEE advertisement is not supported\n");
  11266. return -EINVAL;
  11267. }
  11268. if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
  11269. netdev_warn(tp->dev,
  11270. "Maximal Tx Lpi timer supported is %#x(u)\n",
  11271. TG3_CPMU_DBTMR1_LNKIDLE_MAX);
  11272. return -EINVAL;
  11273. }
  11274. tp->eee = *edata;
  11275. tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
  11276. tg3_warn_mgmt_link_flap(tp);
  11277. if (netif_running(tp->dev)) {
  11278. tg3_full_lock(tp, 0);
  11279. tg3_setup_eee(tp);
  11280. tg3_phy_reset(tp);
  11281. tg3_full_unlock(tp);
  11282. }
  11283. return 0;
  11284. }
  11285. static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
  11286. {
  11287. struct tg3 *tp = netdev_priv(dev);
  11288. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
  11289. netdev_warn(tp->dev,
  11290. "Board does not support EEE!\n");
  11291. return -EOPNOTSUPP;
  11292. }
  11293. *edata = tp->eee;
  11294. return 0;
  11295. }
  11296. static const struct ethtool_ops tg3_ethtool_ops = {
  11297. .get_settings = tg3_get_settings,
  11298. .set_settings = tg3_set_settings,
  11299. .get_drvinfo = tg3_get_drvinfo,
  11300. .get_regs_len = tg3_get_regs_len,
  11301. .get_regs = tg3_get_regs,
  11302. .get_wol = tg3_get_wol,
  11303. .set_wol = tg3_set_wol,
  11304. .get_msglevel = tg3_get_msglevel,
  11305. .set_msglevel = tg3_set_msglevel,
  11306. .nway_reset = tg3_nway_reset,
  11307. .get_link = ethtool_op_get_link,
  11308. .get_eeprom_len = tg3_get_eeprom_len,
  11309. .get_eeprom = tg3_get_eeprom,
  11310. .set_eeprom = tg3_set_eeprom,
  11311. .get_ringparam = tg3_get_ringparam,
  11312. .set_ringparam = tg3_set_ringparam,
  11313. .get_pauseparam = tg3_get_pauseparam,
  11314. .set_pauseparam = tg3_set_pauseparam,
  11315. .self_test = tg3_self_test,
  11316. .get_strings = tg3_get_strings,
  11317. .set_phys_id = tg3_set_phys_id,
  11318. .get_ethtool_stats = tg3_get_ethtool_stats,
  11319. .get_coalesce = tg3_get_coalesce,
  11320. .set_coalesce = tg3_set_coalesce,
  11321. .get_sset_count = tg3_get_sset_count,
  11322. .get_rxnfc = tg3_get_rxnfc,
  11323. .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
  11324. .get_rxfh_indir = tg3_get_rxfh_indir,
  11325. .set_rxfh_indir = tg3_set_rxfh_indir,
  11326. .get_channels = tg3_get_channels,
  11327. .set_channels = tg3_set_channels,
  11328. .get_ts_info = tg3_get_ts_info,
  11329. .get_eee = tg3_get_eee,
  11330. .set_eee = tg3_set_eee,
  11331. };
  11332. static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
  11333. struct rtnl_link_stats64 *stats)
  11334. {
  11335. struct tg3 *tp = netdev_priv(dev);
  11336. spin_lock_bh(&tp->lock);
  11337. if (!tp->hw_stats) {
  11338. spin_unlock_bh(&tp->lock);
  11339. return &tp->net_stats_prev;
  11340. }
  11341. tg3_get_nstats(tp, stats);
  11342. spin_unlock_bh(&tp->lock);
  11343. return stats;
  11344. }
  11345. static void tg3_set_rx_mode(struct net_device *dev)
  11346. {
  11347. struct tg3 *tp = netdev_priv(dev);
  11348. if (!netif_running(dev))
  11349. return;
  11350. tg3_full_lock(tp, 0);
  11351. __tg3_set_rx_mode(dev);
  11352. tg3_full_unlock(tp);
  11353. }
  11354. static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
  11355. int new_mtu)
  11356. {
  11357. dev->mtu = new_mtu;
  11358. if (new_mtu > ETH_DATA_LEN) {
  11359. if (tg3_flag(tp, 5780_CLASS)) {
  11360. netdev_update_features(dev);
  11361. tg3_flag_clear(tp, TSO_CAPABLE);
  11362. } else {
  11363. tg3_flag_set(tp, JUMBO_RING_ENABLE);
  11364. }
  11365. } else {
  11366. if (tg3_flag(tp, 5780_CLASS)) {
  11367. tg3_flag_set(tp, TSO_CAPABLE);
  11368. netdev_update_features(dev);
  11369. }
  11370. tg3_flag_clear(tp, JUMBO_RING_ENABLE);
  11371. }
  11372. }
  11373. static int tg3_change_mtu(struct net_device *dev, int new_mtu)
  11374. {
  11375. struct tg3 *tp = netdev_priv(dev);
  11376. int err;
  11377. bool reset_phy = false;
  11378. if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
  11379. return -EINVAL;
  11380. if (!netif_running(dev)) {
  11381. /* We'll just catch it later when the
  11382. * device is up'd.
  11383. */
  11384. tg3_set_mtu(dev, tp, new_mtu);
  11385. return 0;
  11386. }
  11387. tg3_phy_stop(tp);
  11388. tg3_netif_stop(tp);
  11389. tg3_full_lock(tp, 1);
  11390. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  11391. tg3_set_mtu(dev, tp, new_mtu);
  11392. /* Reset PHY, otherwise the read DMA engine will be in a mode that
  11393. * breaks all requests to 256 bytes.
  11394. */
  11395. if (tg3_asic_rev(tp) == ASIC_REV_57766)
  11396. reset_phy = true;
  11397. err = tg3_restart_hw(tp, reset_phy);
  11398. if (!err)
  11399. tg3_netif_start(tp);
  11400. tg3_full_unlock(tp);
  11401. if (!err)
  11402. tg3_phy_start(tp);
  11403. return err;
  11404. }
  11405. static const struct net_device_ops tg3_netdev_ops = {
  11406. .ndo_open = tg3_open,
  11407. .ndo_stop = tg3_close,
  11408. .ndo_start_xmit = tg3_start_xmit,
  11409. .ndo_get_stats64 = tg3_get_stats64,
  11410. .ndo_validate_addr = eth_validate_addr,
  11411. .ndo_set_rx_mode = tg3_set_rx_mode,
  11412. .ndo_set_mac_address = tg3_set_mac_addr,
  11413. .ndo_do_ioctl = tg3_ioctl,
  11414. .ndo_tx_timeout = tg3_tx_timeout,
  11415. .ndo_change_mtu = tg3_change_mtu,
  11416. .ndo_fix_features = tg3_fix_features,
  11417. .ndo_set_features = tg3_set_features,
  11418. #ifdef CONFIG_NET_POLL_CONTROLLER
  11419. .ndo_poll_controller = tg3_poll_controller,
  11420. #endif
  11421. };
  11422. static void tg3_get_eeprom_size(struct tg3 *tp)
  11423. {
  11424. u32 cursize, val, magic;
  11425. tp->nvram_size = EEPROM_CHIP_SIZE;
  11426. if (tg3_nvram_read(tp, 0, &magic) != 0)
  11427. return;
  11428. if ((magic != TG3_EEPROM_MAGIC) &&
  11429. ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
  11430. ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
  11431. return;
  11432. /*
  11433. * Size the chip by reading offsets at increasing powers of two.
  11434. * When we encounter our validation signature, we know the addressing
  11435. * has wrapped around, and thus have our chip size.
  11436. */
  11437. cursize = 0x10;
  11438. while (cursize < tp->nvram_size) {
  11439. if (tg3_nvram_read(tp, cursize, &val) != 0)
  11440. return;
  11441. if (val == magic)
  11442. break;
  11443. cursize <<= 1;
  11444. }
  11445. tp->nvram_size = cursize;
  11446. }
  11447. static void tg3_get_nvram_size(struct tg3 *tp)
  11448. {
  11449. u32 val;
  11450. if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
  11451. return;
  11452. /* Selfboot format */
  11453. if (val != TG3_EEPROM_MAGIC) {
  11454. tg3_get_eeprom_size(tp);
  11455. return;
  11456. }
  11457. if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
  11458. if (val != 0) {
  11459. /* This is confusing. We want to operate on the
  11460. * 16-bit value at offset 0xf2. The tg3_nvram_read()
  11461. * call will read from NVRAM and byteswap the data
  11462. * according to the byteswapping settings for all
  11463. * other register accesses. This ensures the data we
  11464. * want will always reside in the lower 16-bits.
  11465. * However, the data in NVRAM is in LE format, which
  11466. * means the data from the NVRAM read will always be
  11467. * opposite the endianness of the CPU. The 16-bit
  11468. * byteswap then brings the data to CPU endianness.
  11469. */
  11470. tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
  11471. return;
  11472. }
  11473. }
  11474. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11475. }
  11476. static void tg3_get_nvram_info(struct tg3 *tp)
  11477. {
  11478. u32 nvcfg1;
  11479. nvcfg1 = tr32(NVRAM_CFG1);
  11480. if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
  11481. tg3_flag_set(tp, FLASH);
  11482. } else {
  11483. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11484. tw32(NVRAM_CFG1, nvcfg1);
  11485. }
  11486. if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
  11487. tg3_flag(tp, 5780_CLASS)) {
  11488. switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
  11489. case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
  11490. tp->nvram_jedecnum = JEDEC_ATMEL;
  11491. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  11492. tg3_flag_set(tp, NVRAM_BUFFERED);
  11493. break;
  11494. case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
  11495. tp->nvram_jedecnum = JEDEC_ATMEL;
  11496. tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
  11497. break;
  11498. case FLASH_VENDOR_ATMEL_EEPROM:
  11499. tp->nvram_jedecnum = JEDEC_ATMEL;
  11500. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11501. tg3_flag_set(tp, NVRAM_BUFFERED);
  11502. break;
  11503. case FLASH_VENDOR_ST:
  11504. tp->nvram_jedecnum = JEDEC_ST;
  11505. tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
  11506. tg3_flag_set(tp, NVRAM_BUFFERED);
  11507. break;
  11508. case FLASH_VENDOR_SAIFUN:
  11509. tp->nvram_jedecnum = JEDEC_SAIFUN;
  11510. tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
  11511. break;
  11512. case FLASH_VENDOR_SST_SMALL:
  11513. case FLASH_VENDOR_SST_LARGE:
  11514. tp->nvram_jedecnum = JEDEC_SST;
  11515. tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
  11516. break;
  11517. }
  11518. } else {
  11519. tp->nvram_jedecnum = JEDEC_ATMEL;
  11520. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  11521. tg3_flag_set(tp, NVRAM_BUFFERED);
  11522. }
  11523. }
  11524. static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
  11525. {
  11526. switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
  11527. case FLASH_5752PAGE_SIZE_256:
  11528. tp->nvram_pagesize = 256;
  11529. break;
  11530. case FLASH_5752PAGE_SIZE_512:
  11531. tp->nvram_pagesize = 512;
  11532. break;
  11533. case FLASH_5752PAGE_SIZE_1K:
  11534. tp->nvram_pagesize = 1024;
  11535. break;
  11536. case FLASH_5752PAGE_SIZE_2K:
  11537. tp->nvram_pagesize = 2048;
  11538. break;
  11539. case FLASH_5752PAGE_SIZE_4K:
  11540. tp->nvram_pagesize = 4096;
  11541. break;
  11542. case FLASH_5752PAGE_SIZE_264:
  11543. tp->nvram_pagesize = 264;
  11544. break;
  11545. case FLASH_5752PAGE_SIZE_528:
  11546. tp->nvram_pagesize = 528;
  11547. break;
  11548. }
  11549. }
  11550. static void tg3_get_5752_nvram_info(struct tg3 *tp)
  11551. {
  11552. u32 nvcfg1;
  11553. nvcfg1 = tr32(NVRAM_CFG1);
  11554. /* NVRAM protection for TPM */
  11555. if (nvcfg1 & (1 << 27))
  11556. tg3_flag_set(tp, PROTECTED_NVRAM);
  11557. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11558. case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
  11559. case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
  11560. tp->nvram_jedecnum = JEDEC_ATMEL;
  11561. tg3_flag_set(tp, NVRAM_BUFFERED);
  11562. break;
  11563. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  11564. tp->nvram_jedecnum = JEDEC_ATMEL;
  11565. tg3_flag_set(tp, NVRAM_BUFFERED);
  11566. tg3_flag_set(tp, FLASH);
  11567. break;
  11568. case FLASH_5752VENDOR_ST_M45PE10:
  11569. case FLASH_5752VENDOR_ST_M45PE20:
  11570. case FLASH_5752VENDOR_ST_M45PE40:
  11571. tp->nvram_jedecnum = JEDEC_ST;
  11572. tg3_flag_set(tp, NVRAM_BUFFERED);
  11573. tg3_flag_set(tp, FLASH);
  11574. break;
  11575. }
  11576. if (tg3_flag(tp, FLASH)) {
  11577. tg3_nvram_get_pagesize(tp, nvcfg1);
  11578. } else {
  11579. /* For eeprom, set pagesize to maximum eeprom size */
  11580. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11581. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11582. tw32(NVRAM_CFG1, nvcfg1);
  11583. }
  11584. }
  11585. static void tg3_get_5755_nvram_info(struct tg3 *tp)
  11586. {
  11587. u32 nvcfg1, protect = 0;
  11588. nvcfg1 = tr32(NVRAM_CFG1);
  11589. /* NVRAM protection for TPM */
  11590. if (nvcfg1 & (1 << 27)) {
  11591. tg3_flag_set(tp, PROTECTED_NVRAM);
  11592. protect = 1;
  11593. }
  11594. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  11595. switch (nvcfg1) {
  11596. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  11597. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  11598. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  11599. case FLASH_5755VENDOR_ATMEL_FLASH_5:
  11600. tp->nvram_jedecnum = JEDEC_ATMEL;
  11601. tg3_flag_set(tp, NVRAM_BUFFERED);
  11602. tg3_flag_set(tp, FLASH);
  11603. tp->nvram_pagesize = 264;
  11604. if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
  11605. nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
  11606. tp->nvram_size = (protect ? 0x3e200 :
  11607. TG3_NVRAM_SIZE_512KB);
  11608. else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
  11609. tp->nvram_size = (protect ? 0x1f200 :
  11610. TG3_NVRAM_SIZE_256KB);
  11611. else
  11612. tp->nvram_size = (protect ? 0x1f200 :
  11613. TG3_NVRAM_SIZE_128KB);
  11614. break;
  11615. case FLASH_5752VENDOR_ST_M45PE10:
  11616. case FLASH_5752VENDOR_ST_M45PE20:
  11617. case FLASH_5752VENDOR_ST_M45PE40:
  11618. tp->nvram_jedecnum = JEDEC_ST;
  11619. tg3_flag_set(tp, NVRAM_BUFFERED);
  11620. tg3_flag_set(tp, FLASH);
  11621. tp->nvram_pagesize = 256;
  11622. if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
  11623. tp->nvram_size = (protect ?
  11624. TG3_NVRAM_SIZE_64KB :
  11625. TG3_NVRAM_SIZE_128KB);
  11626. else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
  11627. tp->nvram_size = (protect ?
  11628. TG3_NVRAM_SIZE_64KB :
  11629. TG3_NVRAM_SIZE_256KB);
  11630. else
  11631. tp->nvram_size = (protect ?
  11632. TG3_NVRAM_SIZE_128KB :
  11633. TG3_NVRAM_SIZE_512KB);
  11634. break;
  11635. }
  11636. }
  11637. static void tg3_get_5787_nvram_info(struct tg3 *tp)
  11638. {
  11639. u32 nvcfg1;
  11640. nvcfg1 = tr32(NVRAM_CFG1);
  11641. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11642. case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
  11643. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  11644. case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
  11645. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  11646. tp->nvram_jedecnum = JEDEC_ATMEL;
  11647. tg3_flag_set(tp, NVRAM_BUFFERED);
  11648. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11649. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11650. tw32(NVRAM_CFG1, nvcfg1);
  11651. break;
  11652. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  11653. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  11654. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  11655. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  11656. tp->nvram_jedecnum = JEDEC_ATMEL;
  11657. tg3_flag_set(tp, NVRAM_BUFFERED);
  11658. tg3_flag_set(tp, FLASH);
  11659. tp->nvram_pagesize = 264;
  11660. break;
  11661. case FLASH_5752VENDOR_ST_M45PE10:
  11662. case FLASH_5752VENDOR_ST_M45PE20:
  11663. case FLASH_5752VENDOR_ST_M45PE40:
  11664. tp->nvram_jedecnum = JEDEC_ST;
  11665. tg3_flag_set(tp, NVRAM_BUFFERED);
  11666. tg3_flag_set(tp, FLASH);
  11667. tp->nvram_pagesize = 256;
  11668. break;
  11669. }
  11670. }
  11671. static void tg3_get_5761_nvram_info(struct tg3 *tp)
  11672. {
  11673. u32 nvcfg1, protect = 0;
  11674. nvcfg1 = tr32(NVRAM_CFG1);
  11675. /* NVRAM protection for TPM */
  11676. if (nvcfg1 & (1 << 27)) {
  11677. tg3_flag_set(tp, PROTECTED_NVRAM);
  11678. protect = 1;
  11679. }
  11680. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  11681. switch (nvcfg1) {
  11682. case FLASH_5761VENDOR_ATMEL_ADB021D:
  11683. case FLASH_5761VENDOR_ATMEL_ADB041D:
  11684. case FLASH_5761VENDOR_ATMEL_ADB081D:
  11685. case FLASH_5761VENDOR_ATMEL_ADB161D:
  11686. case FLASH_5761VENDOR_ATMEL_MDB021D:
  11687. case FLASH_5761VENDOR_ATMEL_MDB041D:
  11688. case FLASH_5761VENDOR_ATMEL_MDB081D:
  11689. case FLASH_5761VENDOR_ATMEL_MDB161D:
  11690. tp->nvram_jedecnum = JEDEC_ATMEL;
  11691. tg3_flag_set(tp, NVRAM_BUFFERED);
  11692. tg3_flag_set(tp, FLASH);
  11693. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  11694. tp->nvram_pagesize = 256;
  11695. break;
  11696. case FLASH_5761VENDOR_ST_A_M45PE20:
  11697. case FLASH_5761VENDOR_ST_A_M45PE40:
  11698. case FLASH_5761VENDOR_ST_A_M45PE80:
  11699. case FLASH_5761VENDOR_ST_A_M45PE16:
  11700. case FLASH_5761VENDOR_ST_M_M45PE20:
  11701. case FLASH_5761VENDOR_ST_M_M45PE40:
  11702. case FLASH_5761VENDOR_ST_M_M45PE80:
  11703. case FLASH_5761VENDOR_ST_M_M45PE16:
  11704. tp->nvram_jedecnum = JEDEC_ST;
  11705. tg3_flag_set(tp, NVRAM_BUFFERED);
  11706. tg3_flag_set(tp, FLASH);
  11707. tp->nvram_pagesize = 256;
  11708. break;
  11709. }
  11710. if (protect) {
  11711. tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
  11712. } else {
  11713. switch (nvcfg1) {
  11714. case FLASH_5761VENDOR_ATMEL_ADB161D:
  11715. case FLASH_5761VENDOR_ATMEL_MDB161D:
  11716. case FLASH_5761VENDOR_ST_A_M45PE16:
  11717. case FLASH_5761VENDOR_ST_M_M45PE16:
  11718. tp->nvram_size = TG3_NVRAM_SIZE_2MB;
  11719. break;
  11720. case FLASH_5761VENDOR_ATMEL_ADB081D:
  11721. case FLASH_5761VENDOR_ATMEL_MDB081D:
  11722. case FLASH_5761VENDOR_ST_A_M45PE80:
  11723. case FLASH_5761VENDOR_ST_M_M45PE80:
  11724. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  11725. break;
  11726. case FLASH_5761VENDOR_ATMEL_ADB041D:
  11727. case FLASH_5761VENDOR_ATMEL_MDB041D:
  11728. case FLASH_5761VENDOR_ST_A_M45PE40:
  11729. case FLASH_5761VENDOR_ST_M_M45PE40:
  11730. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11731. break;
  11732. case FLASH_5761VENDOR_ATMEL_ADB021D:
  11733. case FLASH_5761VENDOR_ATMEL_MDB021D:
  11734. case FLASH_5761VENDOR_ST_A_M45PE20:
  11735. case FLASH_5761VENDOR_ST_M_M45PE20:
  11736. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11737. break;
  11738. }
  11739. }
  11740. }
  11741. static void tg3_get_5906_nvram_info(struct tg3 *tp)
  11742. {
  11743. tp->nvram_jedecnum = JEDEC_ATMEL;
  11744. tg3_flag_set(tp, NVRAM_BUFFERED);
  11745. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11746. }
  11747. static void tg3_get_57780_nvram_info(struct tg3 *tp)
  11748. {
  11749. u32 nvcfg1;
  11750. nvcfg1 = tr32(NVRAM_CFG1);
  11751. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11752. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  11753. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  11754. tp->nvram_jedecnum = JEDEC_ATMEL;
  11755. tg3_flag_set(tp, NVRAM_BUFFERED);
  11756. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11757. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11758. tw32(NVRAM_CFG1, nvcfg1);
  11759. return;
  11760. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  11761. case FLASH_57780VENDOR_ATMEL_AT45DB011D:
  11762. case FLASH_57780VENDOR_ATMEL_AT45DB011B:
  11763. case FLASH_57780VENDOR_ATMEL_AT45DB021D:
  11764. case FLASH_57780VENDOR_ATMEL_AT45DB021B:
  11765. case FLASH_57780VENDOR_ATMEL_AT45DB041D:
  11766. case FLASH_57780VENDOR_ATMEL_AT45DB041B:
  11767. tp->nvram_jedecnum = JEDEC_ATMEL;
  11768. tg3_flag_set(tp, NVRAM_BUFFERED);
  11769. tg3_flag_set(tp, FLASH);
  11770. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11771. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  11772. case FLASH_57780VENDOR_ATMEL_AT45DB011D:
  11773. case FLASH_57780VENDOR_ATMEL_AT45DB011B:
  11774. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11775. break;
  11776. case FLASH_57780VENDOR_ATMEL_AT45DB021D:
  11777. case FLASH_57780VENDOR_ATMEL_AT45DB021B:
  11778. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11779. break;
  11780. case FLASH_57780VENDOR_ATMEL_AT45DB041D:
  11781. case FLASH_57780VENDOR_ATMEL_AT45DB041B:
  11782. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11783. break;
  11784. }
  11785. break;
  11786. case FLASH_5752VENDOR_ST_M45PE10:
  11787. case FLASH_5752VENDOR_ST_M45PE20:
  11788. case FLASH_5752VENDOR_ST_M45PE40:
  11789. tp->nvram_jedecnum = JEDEC_ST;
  11790. tg3_flag_set(tp, NVRAM_BUFFERED);
  11791. tg3_flag_set(tp, FLASH);
  11792. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11793. case FLASH_5752VENDOR_ST_M45PE10:
  11794. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11795. break;
  11796. case FLASH_5752VENDOR_ST_M45PE20:
  11797. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11798. break;
  11799. case FLASH_5752VENDOR_ST_M45PE40:
  11800. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11801. break;
  11802. }
  11803. break;
  11804. default:
  11805. tg3_flag_set(tp, NO_NVRAM);
  11806. return;
  11807. }
  11808. tg3_nvram_get_pagesize(tp, nvcfg1);
  11809. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  11810. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  11811. }
  11812. static void tg3_get_5717_nvram_info(struct tg3 *tp)
  11813. {
  11814. u32 nvcfg1;
  11815. nvcfg1 = tr32(NVRAM_CFG1);
  11816. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11817. case FLASH_5717VENDOR_ATMEL_EEPROM:
  11818. case FLASH_5717VENDOR_MICRO_EEPROM:
  11819. tp->nvram_jedecnum = JEDEC_ATMEL;
  11820. tg3_flag_set(tp, NVRAM_BUFFERED);
  11821. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11822. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11823. tw32(NVRAM_CFG1, nvcfg1);
  11824. return;
  11825. case FLASH_5717VENDOR_ATMEL_MDB011D:
  11826. case FLASH_5717VENDOR_ATMEL_ADB011B:
  11827. case FLASH_5717VENDOR_ATMEL_ADB011D:
  11828. case FLASH_5717VENDOR_ATMEL_MDB021D:
  11829. case FLASH_5717VENDOR_ATMEL_ADB021B:
  11830. case FLASH_5717VENDOR_ATMEL_ADB021D:
  11831. case FLASH_5717VENDOR_ATMEL_45USPT:
  11832. tp->nvram_jedecnum = JEDEC_ATMEL;
  11833. tg3_flag_set(tp, NVRAM_BUFFERED);
  11834. tg3_flag_set(tp, FLASH);
  11835. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11836. case FLASH_5717VENDOR_ATMEL_MDB021D:
  11837. /* Detect size with tg3_nvram_get_size() */
  11838. break;
  11839. case FLASH_5717VENDOR_ATMEL_ADB021B:
  11840. case FLASH_5717VENDOR_ATMEL_ADB021D:
  11841. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11842. break;
  11843. default:
  11844. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11845. break;
  11846. }
  11847. break;
  11848. case FLASH_5717VENDOR_ST_M_M25PE10:
  11849. case FLASH_5717VENDOR_ST_A_M25PE10:
  11850. case FLASH_5717VENDOR_ST_M_M45PE10:
  11851. case FLASH_5717VENDOR_ST_A_M45PE10:
  11852. case FLASH_5717VENDOR_ST_M_M25PE20:
  11853. case FLASH_5717VENDOR_ST_A_M25PE20:
  11854. case FLASH_5717VENDOR_ST_M_M45PE20:
  11855. case FLASH_5717VENDOR_ST_A_M45PE20:
  11856. case FLASH_5717VENDOR_ST_25USPT:
  11857. case FLASH_5717VENDOR_ST_45USPT:
  11858. tp->nvram_jedecnum = JEDEC_ST;
  11859. tg3_flag_set(tp, NVRAM_BUFFERED);
  11860. tg3_flag_set(tp, FLASH);
  11861. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11862. case FLASH_5717VENDOR_ST_M_M25PE20:
  11863. case FLASH_5717VENDOR_ST_M_M45PE20:
  11864. /* Detect size with tg3_nvram_get_size() */
  11865. break;
  11866. case FLASH_5717VENDOR_ST_A_M25PE20:
  11867. case FLASH_5717VENDOR_ST_A_M45PE20:
  11868. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11869. break;
  11870. default:
  11871. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11872. break;
  11873. }
  11874. break;
  11875. default:
  11876. tg3_flag_set(tp, NO_NVRAM);
  11877. return;
  11878. }
  11879. tg3_nvram_get_pagesize(tp, nvcfg1);
  11880. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  11881. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  11882. }
  11883. static void tg3_get_5720_nvram_info(struct tg3 *tp)
  11884. {
  11885. u32 nvcfg1, nvmpinstrp;
  11886. nvcfg1 = tr32(NVRAM_CFG1);
  11887. nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
  11888. if (tg3_asic_rev(tp) == ASIC_REV_5762) {
  11889. if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
  11890. tg3_flag_set(tp, NO_NVRAM);
  11891. return;
  11892. }
  11893. switch (nvmpinstrp) {
  11894. case FLASH_5762_EEPROM_HD:
  11895. nvmpinstrp = FLASH_5720_EEPROM_HD;
  11896. break;
  11897. case FLASH_5762_EEPROM_LD:
  11898. nvmpinstrp = FLASH_5720_EEPROM_LD;
  11899. break;
  11900. case FLASH_5720VENDOR_M_ST_M45PE20:
  11901. /* This pinstrap supports multiple sizes, so force it
  11902. * to read the actual size from location 0xf0.
  11903. */
  11904. nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
  11905. break;
  11906. }
  11907. }
  11908. switch (nvmpinstrp) {
  11909. case FLASH_5720_EEPROM_HD:
  11910. case FLASH_5720_EEPROM_LD:
  11911. tp->nvram_jedecnum = JEDEC_ATMEL;
  11912. tg3_flag_set(tp, NVRAM_BUFFERED);
  11913. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11914. tw32(NVRAM_CFG1, nvcfg1);
  11915. if (nvmpinstrp == FLASH_5720_EEPROM_HD)
  11916. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11917. else
  11918. tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
  11919. return;
  11920. case FLASH_5720VENDOR_M_ATMEL_DB011D:
  11921. case FLASH_5720VENDOR_A_ATMEL_DB011B:
  11922. case FLASH_5720VENDOR_A_ATMEL_DB011D:
  11923. case FLASH_5720VENDOR_M_ATMEL_DB021D:
  11924. case FLASH_5720VENDOR_A_ATMEL_DB021B:
  11925. case FLASH_5720VENDOR_A_ATMEL_DB021D:
  11926. case FLASH_5720VENDOR_M_ATMEL_DB041D:
  11927. case FLASH_5720VENDOR_A_ATMEL_DB041B:
  11928. case FLASH_5720VENDOR_A_ATMEL_DB041D:
  11929. case FLASH_5720VENDOR_M_ATMEL_DB081D:
  11930. case FLASH_5720VENDOR_A_ATMEL_DB081D:
  11931. case FLASH_5720VENDOR_ATMEL_45USPT:
  11932. tp->nvram_jedecnum = JEDEC_ATMEL;
  11933. tg3_flag_set(tp, NVRAM_BUFFERED);
  11934. tg3_flag_set(tp, FLASH);
  11935. switch (nvmpinstrp) {
  11936. case FLASH_5720VENDOR_M_ATMEL_DB021D:
  11937. case FLASH_5720VENDOR_A_ATMEL_DB021B:
  11938. case FLASH_5720VENDOR_A_ATMEL_DB021D:
  11939. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11940. break;
  11941. case FLASH_5720VENDOR_M_ATMEL_DB041D:
  11942. case FLASH_5720VENDOR_A_ATMEL_DB041B:
  11943. case FLASH_5720VENDOR_A_ATMEL_DB041D:
  11944. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11945. break;
  11946. case FLASH_5720VENDOR_M_ATMEL_DB081D:
  11947. case FLASH_5720VENDOR_A_ATMEL_DB081D:
  11948. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  11949. break;
  11950. default:
  11951. if (tg3_asic_rev(tp) != ASIC_REV_5762)
  11952. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11953. break;
  11954. }
  11955. break;
  11956. case FLASH_5720VENDOR_M_ST_M25PE10:
  11957. case FLASH_5720VENDOR_M_ST_M45PE10:
  11958. case FLASH_5720VENDOR_A_ST_M25PE10:
  11959. case FLASH_5720VENDOR_A_ST_M45PE10:
  11960. case FLASH_5720VENDOR_M_ST_M25PE20:
  11961. case FLASH_5720VENDOR_M_ST_M45PE20:
  11962. case FLASH_5720VENDOR_A_ST_M25PE20:
  11963. case FLASH_5720VENDOR_A_ST_M45PE20:
  11964. case FLASH_5720VENDOR_M_ST_M25PE40:
  11965. case FLASH_5720VENDOR_M_ST_M45PE40:
  11966. case FLASH_5720VENDOR_A_ST_M25PE40:
  11967. case FLASH_5720VENDOR_A_ST_M45PE40:
  11968. case FLASH_5720VENDOR_M_ST_M25PE80:
  11969. case FLASH_5720VENDOR_M_ST_M45PE80:
  11970. case FLASH_5720VENDOR_A_ST_M25PE80:
  11971. case FLASH_5720VENDOR_A_ST_M45PE80:
  11972. case FLASH_5720VENDOR_ST_25USPT:
  11973. case FLASH_5720VENDOR_ST_45USPT:
  11974. tp->nvram_jedecnum = JEDEC_ST;
  11975. tg3_flag_set(tp, NVRAM_BUFFERED);
  11976. tg3_flag_set(tp, FLASH);
  11977. switch (nvmpinstrp) {
  11978. case FLASH_5720VENDOR_M_ST_M25PE20:
  11979. case FLASH_5720VENDOR_M_ST_M45PE20:
  11980. case FLASH_5720VENDOR_A_ST_M25PE20:
  11981. case FLASH_5720VENDOR_A_ST_M45PE20:
  11982. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11983. break;
  11984. case FLASH_5720VENDOR_M_ST_M25PE40:
  11985. case FLASH_5720VENDOR_M_ST_M45PE40:
  11986. case FLASH_5720VENDOR_A_ST_M25PE40:
  11987. case FLASH_5720VENDOR_A_ST_M45PE40:
  11988. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11989. break;
  11990. case FLASH_5720VENDOR_M_ST_M25PE80:
  11991. case FLASH_5720VENDOR_M_ST_M45PE80:
  11992. case FLASH_5720VENDOR_A_ST_M25PE80:
  11993. case FLASH_5720VENDOR_A_ST_M45PE80:
  11994. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  11995. break;
  11996. default:
  11997. if (tg3_asic_rev(tp) != ASIC_REV_5762)
  11998. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11999. break;
  12000. }
  12001. break;
  12002. default:
  12003. tg3_flag_set(tp, NO_NVRAM);
  12004. return;
  12005. }
  12006. tg3_nvram_get_pagesize(tp, nvcfg1);
  12007. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  12008. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  12009. if (tg3_asic_rev(tp) == ASIC_REV_5762) {
  12010. u32 val;
  12011. if (tg3_nvram_read(tp, 0, &val))
  12012. return;
  12013. if (val != TG3_EEPROM_MAGIC &&
  12014. (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
  12015. tg3_flag_set(tp, NO_NVRAM);
  12016. }
  12017. }
  12018. /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  12019. static void tg3_nvram_init(struct tg3 *tp)
  12020. {
  12021. if (tg3_flag(tp, IS_SSB_CORE)) {
  12022. /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
  12023. tg3_flag_clear(tp, NVRAM);
  12024. tg3_flag_clear(tp, NVRAM_BUFFERED);
  12025. tg3_flag_set(tp, NO_NVRAM);
  12026. return;
  12027. }
  12028. tw32_f(GRC_EEPROM_ADDR,
  12029. (EEPROM_ADDR_FSM_RESET |
  12030. (EEPROM_DEFAULT_CLOCK_PERIOD <<
  12031. EEPROM_ADDR_CLKPERD_SHIFT)));
  12032. msleep(1);
  12033. /* Enable seeprom accesses. */
  12034. tw32_f(GRC_LOCAL_CTRL,
  12035. tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
  12036. udelay(100);
  12037. if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  12038. tg3_asic_rev(tp) != ASIC_REV_5701) {
  12039. tg3_flag_set(tp, NVRAM);
  12040. if (tg3_nvram_lock(tp)) {
  12041. netdev_warn(tp->dev,
  12042. "Cannot get nvram lock, %s failed\n",
  12043. __func__);
  12044. return;
  12045. }
  12046. tg3_enable_nvram_access(tp);
  12047. tp->nvram_size = 0;
  12048. if (tg3_asic_rev(tp) == ASIC_REV_5752)
  12049. tg3_get_5752_nvram_info(tp);
  12050. else if (tg3_asic_rev(tp) == ASIC_REV_5755)
  12051. tg3_get_5755_nvram_info(tp);
  12052. else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
  12053. tg3_asic_rev(tp) == ASIC_REV_5784 ||
  12054. tg3_asic_rev(tp) == ASIC_REV_5785)
  12055. tg3_get_5787_nvram_info(tp);
  12056. else if (tg3_asic_rev(tp) == ASIC_REV_5761)
  12057. tg3_get_5761_nvram_info(tp);
  12058. else if (tg3_asic_rev(tp) == ASIC_REV_5906)
  12059. tg3_get_5906_nvram_info(tp);
  12060. else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
  12061. tg3_flag(tp, 57765_CLASS))
  12062. tg3_get_57780_nvram_info(tp);
  12063. else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  12064. tg3_asic_rev(tp) == ASIC_REV_5719)
  12065. tg3_get_5717_nvram_info(tp);
  12066. else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  12067. tg3_asic_rev(tp) == ASIC_REV_5762)
  12068. tg3_get_5720_nvram_info(tp);
  12069. else
  12070. tg3_get_nvram_info(tp);
  12071. if (tp->nvram_size == 0)
  12072. tg3_get_nvram_size(tp);
  12073. tg3_disable_nvram_access(tp);
  12074. tg3_nvram_unlock(tp);
  12075. } else {
  12076. tg3_flag_clear(tp, NVRAM);
  12077. tg3_flag_clear(tp, NVRAM_BUFFERED);
  12078. tg3_get_eeprom_size(tp);
  12079. }
  12080. }
  12081. struct subsys_tbl_ent {
  12082. u16 subsys_vendor, subsys_devid;
  12083. u32 phy_id;
  12084. };
  12085. static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
  12086. /* Broadcom boards. */
  12087. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12088. TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
  12089. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12090. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
  12091. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12092. TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
  12093. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12094. TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
  12095. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12096. TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
  12097. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12098. TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
  12099. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12100. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
  12101. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12102. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
  12103. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12104. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
  12105. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12106. TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
  12107. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12108. TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
  12109. /* 3com boards. */
  12110. { TG3PCI_SUBVENDOR_ID_3COM,
  12111. TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
  12112. { TG3PCI_SUBVENDOR_ID_3COM,
  12113. TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
  12114. { TG3PCI_SUBVENDOR_ID_3COM,
  12115. TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
  12116. { TG3PCI_SUBVENDOR_ID_3COM,
  12117. TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
  12118. { TG3PCI_SUBVENDOR_ID_3COM,
  12119. TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
  12120. /* DELL boards. */
  12121. { TG3PCI_SUBVENDOR_ID_DELL,
  12122. TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
  12123. { TG3PCI_SUBVENDOR_ID_DELL,
  12124. TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
  12125. { TG3PCI_SUBVENDOR_ID_DELL,
  12126. TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
  12127. { TG3PCI_SUBVENDOR_ID_DELL,
  12128. TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
  12129. /* Compaq boards. */
  12130. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  12131. TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
  12132. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  12133. TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
  12134. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  12135. TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
  12136. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  12137. TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
  12138. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  12139. TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
  12140. /* IBM boards. */
  12141. { TG3PCI_SUBVENDOR_ID_IBM,
  12142. TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
  12143. };
  12144. static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
  12145. {
  12146. int i;
  12147. for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
  12148. if ((subsys_id_to_phy_id[i].subsys_vendor ==
  12149. tp->pdev->subsystem_vendor) &&
  12150. (subsys_id_to_phy_id[i].subsys_devid ==
  12151. tp->pdev->subsystem_device))
  12152. return &subsys_id_to_phy_id[i];
  12153. }
  12154. return NULL;
  12155. }
  12156. static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
  12157. {
  12158. u32 val;
  12159. tp->phy_id = TG3_PHY_ID_INVALID;
  12160. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  12161. /* Assume an onboard device and WOL capable by default. */
  12162. tg3_flag_set(tp, EEPROM_WRITE_PROT);
  12163. tg3_flag_set(tp, WOL_CAP);
  12164. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  12165. if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
  12166. tg3_flag_clear(tp, EEPROM_WRITE_PROT);
  12167. tg3_flag_set(tp, IS_NIC);
  12168. }
  12169. val = tr32(VCPU_CFGSHDW);
  12170. if (val & VCPU_CFGSHDW_ASPM_DBNC)
  12171. tg3_flag_set(tp, ASPM_WORKAROUND);
  12172. if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
  12173. (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
  12174. tg3_flag_set(tp, WOL_ENABLE);
  12175. device_set_wakeup_enable(&tp->pdev->dev, true);
  12176. }
  12177. goto done;
  12178. }
  12179. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  12180. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  12181. u32 nic_cfg, led_cfg;
  12182. u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
  12183. int eeprom_phy_serdes = 0;
  12184. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  12185. tp->nic_sram_data_cfg = nic_cfg;
  12186. tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
  12187. ver >>= NIC_SRAM_DATA_VER_SHIFT;
  12188. if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  12189. tg3_asic_rev(tp) != ASIC_REV_5701 &&
  12190. tg3_asic_rev(tp) != ASIC_REV_5703 &&
  12191. (ver > 0) && (ver < 0x100))
  12192. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
  12193. if (tg3_asic_rev(tp) == ASIC_REV_5785)
  12194. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
  12195. if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
  12196. NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
  12197. eeprom_phy_serdes = 1;
  12198. tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
  12199. if (nic_phy_id != 0) {
  12200. u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
  12201. u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
  12202. eeprom_phy_id = (id1 >> 16) << 10;
  12203. eeprom_phy_id |= (id2 & 0xfc00) << 16;
  12204. eeprom_phy_id |= (id2 & 0x03ff) << 0;
  12205. } else
  12206. eeprom_phy_id = 0;
  12207. tp->phy_id = eeprom_phy_id;
  12208. if (eeprom_phy_serdes) {
  12209. if (!tg3_flag(tp, 5705_PLUS))
  12210. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  12211. else
  12212. tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
  12213. }
  12214. if (tg3_flag(tp, 5750_PLUS))
  12215. led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
  12216. SHASTA_EXT_LED_MODE_MASK);
  12217. else
  12218. led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
  12219. switch (led_cfg) {
  12220. default:
  12221. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
  12222. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  12223. break;
  12224. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
  12225. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  12226. break;
  12227. case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
  12228. tp->led_ctrl = LED_CTRL_MODE_MAC;
  12229. /* Default to PHY_1_MODE if 0 (MAC_MODE) is
  12230. * read on some older 5700/5701 bootcode.
  12231. */
  12232. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  12233. tg3_asic_rev(tp) == ASIC_REV_5701)
  12234. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  12235. break;
  12236. case SHASTA_EXT_LED_SHARED:
  12237. tp->led_ctrl = LED_CTRL_MODE_SHARED;
  12238. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
  12239. tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
  12240. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  12241. LED_CTRL_MODE_PHY_2);
  12242. break;
  12243. case SHASTA_EXT_LED_MAC:
  12244. tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
  12245. break;
  12246. case SHASTA_EXT_LED_COMBO:
  12247. tp->led_ctrl = LED_CTRL_MODE_COMBO;
  12248. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
  12249. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  12250. LED_CTRL_MODE_PHY_2);
  12251. break;
  12252. }
  12253. if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
  12254. tg3_asic_rev(tp) == ASIC_REV_5701) &&
  12255. tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
  12256. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  12257. if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
  12258. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  12259. if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
  12260. tg3_flag_set(tp, EEPROM_WRITE_PROT);
  12261. if ((tp->pdev->subsystem_vendor ==
  12262. PCI_VENDOR_ID_ARIMA) &&
  12263. (tp->pdev->subsystem_device == 0x205a ||
  12264. tp->pdev->subsystem_device == 0x2063))
  12265. tg3_flag_clear(tp, EEPROM_WRITE_PROT);
  12266. } else {
  12267. tg3_flag_clear(tp, EEPROM_WRITE_PROT);
  12268. tg3_flag_set(tp, IS_NIC);
  12269. }
  12270. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  12271. tg3_flag_set(tp, ENABLE_ASF);
  12272. if (tg3_flag(tp, 5750_PLUS))
  12273. tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
  12274. }
  12275. if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
  12276. tg3_flag(tp, 5750_PLUS))
  12277. tg3_flag_set(tp, ENABLE_APE);
  12278. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
  12279. !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
  12280. tg3_flag_clear(tp, WOL_CAP);
  12281. if (tg3_flag(tp, WOL_CAP) &&
  12282. (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
  12283. tg3_flag_set(tp, WOL_ENABLE);
  12284. device_set_wakeup_enable(&tp->pdev->dev, true);
  12285. }
  12286. if (cfg2 & (1 << 17))
  12287. tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
  12288. /* serdes signal pre-emphasis in register 0x590 set by */
  12289. /* bootcode if bit 18 is set */
  12290. if (cfg2 & (1 << 18))
  12291. tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
  12292. if ((tg3_flag(tp, 57765_PLUS) ||
  12293. (tg3_asic_rev(tp) == ASIC_REV_5784 &&
  12294. tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
  12295. (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
  12296. tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
  12297. if (tg3_flag(tp, PCI_EXPRESS)) {
  12298. u32 cfg3;
  12299. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
  12300. if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
  12301. !tg3_flag(tp, 57765_PLUS) &&
  12302. (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
  12303. tg3_flag_set(tp, ASPM_WORKAROUND);
  12304. if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
  12305. tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
  12306. if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
  12307. tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
  12308. }
  12309. if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
  12310. tg3_flag_set(tp, RGMII_INBAND_DISABLE);
  12311. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
  12312. tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
  12313. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
  12314. tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
  12315. }
  12316. done:
  12317. if (tg3_flag(tp, WOL_CAP))
  12318. device_set_wakeup_enable(&tp->pdev->dev,
  12319. tg3_flag(tp, WOL_ENABLE));
  12320. else
  12321. device_set_wakeup_capable(&tp->pdev->dev, false);
  12322. }
  12323. static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
  12324. {
  12325. int i, err;
  12326. u32 val2, off = offset * 8;
  12327. err = tg3_nvram_lock(tp);
  12328. if (err)
  12329. return err;
  12330. tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
  12331. tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
  12332. APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
  12333. tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
  12334. udelay(10);
  12335. for (i = 0; i < 100; i++) {
  12336. val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
  12337. if (val2 & APE_OTP_STATUS_CMD_DONE) {
  12338. *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
  12339. break;
  12340. }
  12341. udelay(10);
  12342. }
  12343. tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
  12344. tg3_nvram_unlock(tp);
  12345. if (val2 & APE_OTP_STATUS_CMD_DONE)
  12346. return 0;
  12347. return -EBUSY;
  12348. }
  12349. static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
  12350. {
  12351. int i;
  12352. u32 val;
  12353. tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
  12354. tw32(OTP_CTRL, cmd);
  12355. /* Wait for up to 1 ms for command to execute. */
  12356. for (i = 0; i < 100; i++) {
  12357. val = tr32(OTP_STATUS);
  12358. if (val & OTP_STATUS_CMD_DONE)
  12359. break;
  12360. udelay(10);
  12361. }
  12362. return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
  12363. }
  12364. /* Read the gphy configuration from the OTP region of the chip. The gphy
  12365. * configuration is a 32-bit value that straddles the alignment boundary.
  12366. * We do two 32-bit reads and then shift and merge the results.
  12367. */
  12368. static u32 tg3_read_otp_phycfg(struct tg3 *tp)
  12369. {
  12370. u32 bhalf_otp, thalf_otp;
  12371. tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
  12372. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
  12373. return 0;
  12374. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
  12375. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  12376. return 0;
  12377. thalf_otp = tr32(OTP_READ_DATA);
  12378. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
  12379. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  12380. return 0;
  12381. bhalf_otp = tr32(OTP_READ_DATA);
  12382. return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
  12383. }
  12384. static void tg3_phy_init_link_config(struct tg3 *tp)
  12385. {
  12386. u32 adv = ADVERTISED_Autoneg;
  12387. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  12388. adv |= ADVERTISED_1000baseT_Half |
  12389. ADVERTISED_1000baseT_Full;
  12390. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  12391. adv |= ADVERTISED_100baseT_Half |
  12392. ADVERTISED_100baseT_Full |
  12393. ADVERTISED_10baseT_Half |
  12394. ADVERTISED_10baseT_Full |
  12395. ADVERTISED_TP;
  12396. else
  12397. adv |= ADVERTISED_FIBRE;
  12398. tp->link_config.advertising = adv;
  12399. tp->link_config.speed = SPEED_UNKNOWN;
  12400. tp->link_config.duplex = DUPLEX_UNKNOWN;
  12401. tp->link_config.autoneg = AUTONEG_ENABLE;
  12402. tp->link_config.active_speed = SPEED_UNKNOWN;
  12403. tp->link_config.active_duplex = DUPLEX_UNKNOWN;
  12404. tp->old_link = -1;
  12405. }
  12406. static int tg3_phy_probe(struct tg3 *tp)
  12407. {
  12408. u32 hw_phy_id_1, hw_phy_id_2;
  12409. u32 hw_phy_id, hw_phy_id_masked;
  12410. int err;
  12411. /* flow control autonegotiation is default behavior */
  12412. tg3_flag_set(tp, PAUSE_AUTONEG);
  12413. tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  12414. if (tg3_flag(tp, ENABLE_APE)) {
  12415. switch (tp->pci_fn) {
  12416. case 0:
  12417. tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
  12418. break;
  12419. case 1:
  12420. tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
  12421. break;
  12422. case 2:
  12423. tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
  12424. break;
  12425. case 3:
  12426. tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
  12427. break;
  12428. }
  12429. }
  12430. if (!tg3_flag(tp, ENABLE_ASF) &&
  12431. !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
  12432. !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  12433. tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
  12434. TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
  12435. if (tg3_flag(tp, USE_PHYLIB))
  12436. return tg3_phy_init(tp);
  12437. /* Reading the PHY ID register can conflict with ASF
  12438. * firmware access to the PHY hardware.
  12439. */
  12440. err = 0;
  12441. if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
  12442. hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
  12443. } else {
  12444. /* Now read the physical PHY_ID from the chip and verify
  12445. * that it is sane. If it doesn't look good, we fall back
  12446. * to either the hard-coded table based PHY_ID and failing
  12447. * that the value found in the eeprom area.
  12448. */
  12449. err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
  12450. err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
  12451. hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
  12452. hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
  12453. hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
  12454. hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
  12455. }
  12456. if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
  12457. tp->phy_id = hw_phy_id;
  12458. if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
  12459. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  12460. else
  12461. tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
  12462. } else {
  12463. if (tp->phy_id != TG3_PHY_ID_INVALID) {
  12464. /* Do nothing, phy ID already set up in
  12465. * tg3_get_eeprom_hw_cfg().
  12466. */
  12467. } else {
  12468. struct subsys_tbl_ent *p;
  12469. /* No eeprom signature? Try the hardcoded
  12470. * subsys device table.
  12471. */
  12472. p = tg3_lookup_by_subsys(tp);
  12473. if (p) {
  12474. tp->phy_id = p->phy_id;
  12475. } else if (!tg3_flag(tp, IS_SSB_CORE)) {
  12476. /* For now we saw the IDs 0xbc050cd0,
  12477. * 0xbc050f80 and 0xbc050c30 on devices
  12478. * connected to an BCM4785 and there are
  12479. * probably more. Just assume that the phy is
  12480. * supported when it is connected to a SSB core
  12481. * for now.
  12482. */
  12483. return -ENODEV;
  12484. }
  12485. if (!tp->phy_id ||
  12486. tp->phy_id == TG3_PHY_ID_BCM8002)
  12487. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  12488. }
  12489. }
  12490. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
  12491. (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  12492. tg3_asic_rev(tp) == ASIC_REV_5720 ||
  12493. tg3_asic_rev(tp) == ASIC_REV_57766 ||
  12494. tg3_asic_rev(tp) == ASIC_REV_5762 ||
  12495. (tg3_asic_rev(tp) == ASIC_REV_5717 &&
  12496. tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
  12497. (tg3_asic_rev(tp) == ASIC_REV_57765 &&
  12498. tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
  12499. tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
  12500. tp->eee.supported = SUPPORTED_100baseT_Full |
  12501. SUPPORTED_1000baseT_Full;
  12502. tp->eee.advertised = ADVERTISED_100baseT_Full |
  12503. ADVERTISED_1000baseT_Full;
  12504. tp->eee.eee_enabled = 1;
  12505. tp->eee.tx_lpi_enabled = 1;
  12506. tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
  12507. }
  12508. tg3_phy_init_link_config(tp);
  12509. if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
  12510. !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
  12511. !tg3_flag(tp, ENABLE_APE) &&
  12512. !tg3_flag(tp, ENABLE_ASF)) {
  12513. u32 bmsr, dummy;
  12514. tg3_readphy(tp, MII_BMSR, &bmsr);
  12515. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  12516. (bmsr & BMSR_LSTATUS))
  12517. goto skip_phy_reset;
  12518. err = tg3_phy_reset(tp);
  12519. if (err)
  12520. return err;
  12521. tg3_phy_set_wirespeed(tp);
  12522. if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
  12523. tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
  12524. tp->link_config.flowctrl);
  12525. tg3_writephy(tp, MII_BMCR,
  12526. BMCR_ANENABLE | BMCR_ANRESTART);
  12527. }
  12528. }
  12529. skip_phy_reset:
  12530. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  12531. err = tg3_init_5401phy_dsp(tp);
  12532. if (err)
  12533. return err;
  12534. err = tg3_init_5401phy_dsp(tp);
  12535. }
  12536. return err;
  12537. }
  12538. static void tg3_read_vpd(struct tg3 *tp)
  12539. {
  12540. u8 *vpd_data;
  12541. unsigned int block_end, rosize, len;
  12542. u32 vpdlen;
  12543. int j, i = 0;
  12544. vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
  12545. if (!vpd_data)
  12546. goto out_no_vpd;
  12547. i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
  12548. if (i < 0)
  12549. goto out_not_found;
  12550. rosize = pci_vpd_lrdt_size(&vpd_data[i]);
  12551. block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
  12552. i += PCI_VPD_LRDT_TAG_SIZE;
  12553. if (block_end > vpdlen)
  12554. goto out_not_found;
  12555. j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  12556. PCI_VPD_RO_KEYWORD_MFR_ID);
  12557. if (j > 0) {
  12558. len = pci_vpd_info_field_size(&vpd_data[j]);
  12559. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  12560. if (j + len > block_end || len != 4 ||
  12561. memcmp(&vpd_data[j], "1028", 4))
  12562. goto partno;
  12563. j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  12564. PCI_VPD_RO_KEYWORD_VENDOR0);
  12565. if (j < 0)
  12566. goto partno;
  12567. len = pci_vpd_info_field_size(&vpd_data[j]);
  12568. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  12569. if (j + len > block_end)
  12570. goto partno;
  12571. if (len >= sizeof(tp->fw_ver))
  12572. len = sizeof(tp->fw_ver) - 1;
  12573. memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
  12574. snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
  12575. &vpd_data[j]);
  12576. }
  12577. partno:
  12578. i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  12579. PCI_VPD_RO_KEYWORD_PARTNO);
  12580. if (i < 0)
  12581. goto out_not_found;
  12582. len = pci_vpd_info_field_size(&vpd_data[i]);
  12583. i += PCI_VPD_INFO_FLD_HDR_SIZE;
  12584. if (len > TG3_BPN_SIZE ||
  12585. (len + i) > vpdlen)
  12586. goto out_not_found;
  12587. memcpy(tp->board_part_number, &vpd_data[i], len);
  12588. out_not_found:
  12589. kfree(vpd_data);
  12590. if (tp->board_part_number[0])
  12591. return;
  12592. out_no_vpd:
  12593. if (tg3_asic_rev(tp) == ASIC_REV_5717) {
  12594. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  12595. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
  12596. strcpy(tp->board_part_number, "BCM5717");
  12597. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
  12598. strcpy(tp->board_part_number, "BCM5718");
  12599. else
  12600. goto nomatch;
  12601. } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
  12602. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
  12603. strcpy(tp->board_part_number, "BCM57780");
  12604. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
  12605. strcpy(tp->board_part_number, "BCM57760");
  12606. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
  12607. strcpy(tp->board_part_number, "BCM57790");
  12608. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
  12609. strcpy(tp->board_part_number, "BCM57788");
  12610. else
  12611. goto nomatch;
  12612. } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
  12613. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
  12614. strcpy(tp->board_part_number, "BCM57761");
  12615. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
  12616. strcpy(tp->board_part_number, "BCM57765");
  12617. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
  12618. strcpy(tp->board_part_number, "BCM57781");
  12619. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
  12620. strcpy(tp->board_part_number, "BCM57785");
  12621. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
  12622. strcpy(tp->board_part_number, "BCM57791");
  12623. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
  12624. strcpy(tp->board_part_number, "BCM57795");
  12625. else
  12626. goto nomatch;
  12627. } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
  12628. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
  12629. strcpy(tp->board_part_number, "BCM57762");
  12630. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
  12631. strcpy(tp->board_part_number, "BCM57766");
  12632. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
  12633. strcpy(tp->board_part_number, "BCM57782");
  12634. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
  12635. strcpy(tp->board_part_number, "BCM57786");
  12636. else
  12637. goto nomatch;
  12638. } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  12639. strcpy(tp->board_part_number, "BCM95906");
  12640. } else {
  12641. nomatch:
  12642. strcpy(tp->board_part_number, "none");
  12643. }
  12644. }
  12645. static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
  12646. {
  12647. u32 val;
  12648. if (tg3_nvram_read(tp, offset, &val) ||
  12649. (val & 0xfc000000) != 0x0c000000 ||
  12650. tg3_nvram_read(tp, offset + 4, &val) ||
  12651. val != 0)
  12652. return 0;
  12653. return 1;
  12654. }
  12655. static void tg3_read_bc_ver(struct tg3 *tp)
  12656. {
  12657. u32 val, offset, start, ver_offset;
  12658. int i, dst_off;
  12659. bool newver = false;
  12660. if (tg3_nvram_read(tp, 0xc, &offset) ||
  12661. tg3_nvram_read(tp, 0x4, &start))
  12662. return;
  12663. offset = tg3_nvram_logical_addr(tp, offset);
  12664. if (tg3_nvram_read(tp, offset, &val))
  12665. return;
  12666. if ((val & 0xfc000000) == 0x0c000000) {
  12667. if (tg3_nvram_read(tp, offset + 4, &val))
  12668. return;
  12669. if (val == 0)
  12670. newver = true;
  12671. }
  12672. dst_off = strlen(tp->fw_ver);
  12673. if (newver) {
  12674. if (TG3_VER_SIZE - dst_off < 16 ||
  12675. tg3_nvram_read(tp, offset + 8, &ver_offset))
  12676. return;
  12677. offset = offset + ver_offset - start;
  12678. for (i = 0; i < 16; i += 4) {
  12679. __be32 v;
  12680. if (tg3_nvram_read_be32(tp, offset + i, &v))
  12681. return;
  12682. memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
  12683. }
  12684. } else {
  12685. u32 major, minor;
  12686. if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
  12687. return;
  12688. major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
  12689. TG3_NVM_BCVER_MAJSFT;
  12690. minor = ver_offset & TG3_NVM_BCVER_MINMSK;
  12691. snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
  12692. "v%d.%02d", major, minor);
  12693. }
  12694. }
  12695. static void tg3_read_hwsb_ver(struct tg3 *tp)
  12696. {
  12697. u32 val, major, minor;
  12698. /* Use native endian representation */
  12699. if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
  12700. return;
  12701. major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
  12702. TG3_NVM_HWSB_CFG1_MAJSFT;
  12703. minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
  12704. TG3_NVM_HWSB_CFG1_MINSFT;
  12705. snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
  12706. }
  12707. static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
  12708. {
  12709. u32 offset, major, minor, build;
  12710. strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
  12711. if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
  12712. return;
  12713. switch (val & TG3_EEPROM_SB_REVISION_MASK) {
  12714. case TG3_EEPROM_SB_REVISION_0:
  12715. offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
  12716. break;
  12717. case TG3_EEPROM_SB_REVISION_2:
  12718. offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
  12719. break;
  12720. case TG3_EEPROM_SB_REVISION_3:
  12721. offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
  12722. break;
  12723. case TG3_EEPROM_SB_REVISION_4:
  12724. offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
  12725. break;
  12726. case TG3_EEPROM_SB_REVISION_5:
  12727. offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
  12728. break;
  12729. case TG3_EEPROM_SB_REVISION_6:
  12730. offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
  12731. break;
  12732. default:
  12733. return;
  12734. }
  12735. if (tg3_nvram_read(tp, offset, &val))
  12736. return;
  12737. build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
  12738. TG3_EEPROM_SB_EDH_BLD_SHFT;
  12739. major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
  12740. TG3_EEPROM_SB_EDH_MAJ_SHFT;
  12741. minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
  12742. if (minor > 99 || build > 26)
  12743. return;
  12744. offset = strlen(tp->fw_ver);
  12745. snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
  12746. " v%d.%02d", major, minor);
  12747. if (build > 0) {
  12748. offset = strlen(tp->fw_ver);
  12749. if (offset < TG3_VER_SIZE - 1)
  12750. tp->fw_ver[offset] = 'a' + build - 1;
  12751. }
  12752. }
  12753. static void tg3_read_mgmtfw_ver(struct tg3 *tp)
  12754. {
  12755. u32 val, offset, start;
  12756. int i, vlen;
  12757. for (offset = TG3_NVM_DIR_START;
  12758. offset < TG3_NVM_DIR_END;
  12759. offset += TG3_NVM_DIRENT_SIZE) {
  12760. if (tg3_nvram_read(tp, offset, &val))
  12761. return;
  12762. if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
  12763. break;
  12764. }
  12765. if (offset == TG3_NVM_DIR_END)
  12766. return;
  12767. if (!tg3_flag(tp, 5705_PLUS))
  12768. start = 0x08000000;
  12769. else if (tg3_nvram_read(tp, offset - 4, &start))
  12770. return;
  12771. if (tg3_nvram_read(tp, offset + 4, &offset) ||
  12772. !tg3_fw_img_is_valid(tp, offset) ||
  12773. tg3_nvram_read(tp, offset + 8, &val))
  12774. return;
  12775. offset += val - start;
  12776. vlen = strlen(tp->fw_ver);
  12777. tp->fw_ver[vlen++] = ',';
  12778. tp->fw_ver[vlen++] = ' ';
  12779. for (i = 0; i < 4; i++) {
  12780. __be32 v;
  12781. if (tg3_nvram_read_be32(tp, offset, &v))
  12782. return;
  12783. offset += sizeof(v);
  12784. if (vlen > TG3_VER_SIZE - sizeof(v)) {
  12785. memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
  12786. break;
  12787. }
  12788. memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
  12789. vlen += sizeof(v);
  12790. }
  12791. }
  12792. static void tg3_probe_ncsi(struct tg3 *tp)
  12793. {
  12794. u32 apedata;
  12795. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  12796. if (apedata != APE_SEG_SIG_MAGIC)
  12797. return;
  12798. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  12799. if (!(apedata & APE_FW_STATUS_READY))
  12800. return;
  12801. if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
  12802. tg3_flag_set(tp, APE_HAS_NCSI);
  12803. }
  12804. static void tg3_read_dash_ver(struct tg3 *tp)
  12805. {
  12806. int vlen;
  12807. u32 apedata;
  12808. char *fwtype;
  12809. apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
  12810. if (tg3_flag(tp, APE_HAS_NCSI))
  12811. fwtype = "NCSI";
  12812. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
  12813. fwtype = "SMASH";
  12814. else
  12815. fwtype = "DASH";
  12816. vlen = strlen(tp->fw_ver);
  12817. snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
  12818. fwtype,
  12819. (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
  12820. (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
  12821. (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
  12822. (apedata & APE_FW_VERSION_BLDMSK));
  12823. }
  12824. static void tg3_read_otp_ver(struct tg3 *tp)
  12825. {
  12826. u32 val, val2;
  12827. if (tg3_asic_rev(tp) != ASIC_REV_5762)
  12828. return;
  12829. if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
  12830. !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
  12831. TG3_OTP_MAGIC0_VALID(val)) {
  12832. u64 val64 = (u64) val << 32 | val2;
  12833. u32 ver = 0;
  12834. int i, vlen;
  12835. for (i = 0; i < 7; i++) {
  12836. if ((val64 & 0xff) == 0)
  12837. break;
  12838. ver = val64 & 0xff;
  12839. val64 >>= 8;
  12840. }
  12841. vlen = strlen(tp->fw_ver);
  12842. snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
  12843. }
  12844. }
  12845. static void tg3_read_fw_ver(struct tg3 *tp)
  12846. {
  12847. u32 val;
  12848. bool vpd_vers = false;
  12849. if (tp->fw_ver[0] != 0)
  12850. vpd_vers = true;
  12851. if (tg3_flag(tp, NO_NVRAM)) {
  12852. strcat(tp->fw_ver, "sb");
  12853. tg3_read_otp_ver(tp);
  12854. return;
  12855. }
  12856. if (tg3_nvram_read(tp, 0, &val))
  12857. return;
  12858. if (val == TG3_EEPROM_MAGIC)
  12859. tg3_read_bc_ver(tp);
  12860. else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
  12861. tg3_read_sb_ver(tp, val);
  12862. else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  12863. tg3_read_hwsb_ver(tp);
  12864. if (tg3_flag(tp, ENABLE_ASF)) {
  12865. if (tg3_flag(tp, ENABLE_APE)) {
  12866. tg3_probe_ncsi(tp);
  12867. if (!vpd_vers)
  12868. tg3_read_dash_ver(tp);
  12869. } else if (!vpd_vers) {
  12870. tg3_read_mgmtfw_ver(tp);
  12871. }
  12872. }
  12873. tp->fw_ver[TG3_VER_SIZE - 1] = 0;
  12874. }
  12875. static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
  12876. {
  12877. if (tg3_flag(tp, LRG_PROD_RING_CAP))
  12878. return TG3_RX_RET_MAX_SIZE_5717;
  12879. else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
  12880. return TG3_RX_RET_MAX_SIZE_5700;
  12881. else
  12882. return TG3_RX_RET_MAX_SIZE_5705;
  12883. }
  12884. static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
  12885. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
  12886. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
  12887. { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
  12888. { },
  12889. };
  12890. static struct pci_dev *tg3_find_peer(struct tg3 *tp)
  12891. {
  12892. struct pci_dev *peer;
  12893. unsigned int func, devnr = tp->pdev->devfn & ~7;
  12894. for (func = 0; func < 8; func++) {
  12895. peer = pci_get_slot(tp->pdev->bus, devnr | func);
  12896. if (peer && peer != tp->pdev)
  12897. break;
  12898. pci_dev_put(peer);
  12899. }
  12900. /* 5704 can be configured in single-port mode, set peer to
  12901. * tp->pdev in that case.
  12902. */
  12903. if (!peer) {
  12904. peer = tp->pdev;
  12905. return peer;
  12906. }
  12907. /*
  12908. * We don't need to keep the refcount elevated; there's no way
  12909. * to remove one half of this device without removing the other
  12910. */
  12911. pci_dev_put(peer);
  12912. return peer;
  12913. }
  12914. static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
  12915. {
  12916. tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
  12917. if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
  12918. u32 reg;
  12919. /* All devices that use the alternate
  12920. * ASIC REV location have a CPMU.
  12921. */
  12922. tg3_flag_set(tp, CPMU_PRESENT);
  12923. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  12924. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
  12925. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
  12926. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
  12927. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
  12928. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
  12929. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
  12930. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727)
  12931. reg = TG3PCI_GEN2_PRODID_ASICREV;
  12932. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
  12933. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
  12934. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
  12935. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
  12936. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
  12937. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
  12938. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
  12939. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
  12940. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
  12941. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
  12942. reg = TG3PCI_GEN15_PRODID_ASICREV;
  12943. else
  12944. reg = TG3PCI_PRODID_ASICREV;
  12945. pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
  12946. }
  12947. /* Wrong chip ID in 5752 A0. This code can be removed later
  12948. * as A0 is not in production.
  12949. */
  12950. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
  12951. tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
  12952. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
  12953. tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
  12954. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  12955. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  12956. tg3_asic_rev(tp) == ASIC_REV_5720)
  12957. tg3_flag_set(tp, 5717_PLUS);
  12958. if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
  12959. tg3_asic_rev(tp) == ASIC_REV_57766)
  12960. tg3_flag_set(tp, 57765_CLASS);
  12961. if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
  12962. tg3_asic_rev(tp) == ASIC_REV_5762)
  12963. tg3_flag_set(tp, 57765_PLUS);
  12964. /* Intentionally exclude ASIC_REV_5906 */
  12965. if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  12966. tg3_asic_rev(tp) == ASIC_REV_5787 ||
  12967. tg3_asic_rev(tp) == ASIC_REV_5784 ||
  12968. tg3_asic_rev(tp) == ASIC_REV_5761 ||
  12969. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  12970. tg3_asic_rev(tp) == ASIC_REV_57780 ||
  12971. tg3_flag(tp, 57765_PLUS))
  12972. tg3_flag_set(tp, 5755_PLUS);
  12973. if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
  12974. tg3_asic_rev(tp) == ASIC_REV_5714)
  12975. tg3_flag_set(tp, 5780_CLASS);
  12976. if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
  12977. tg3_asic_rev(tp) == ASIC_REV_5752 ||
  12978. tg3_asic_rev(tp) == ASIC_REV_5906 ||
  12979. tg3_flag(tp, 5755_PLUS) ||
  12980. tg3_flag(tp, 5780_CLASS))
  12981. tg3_flag_set(tp, 5750_PLUS);
  12982. if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
  12983. tg3_flag(tp, 5750_PLUS))
  12984. tg3_flag_set(tp, 5705_PLUS);
  12985. }
  12986. static bool tg3_10_100_only_device(struct tg3 *tp,
  12987. const struct pci_device_id *ent)
  12988. {
  12989. u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
  12990. if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
  12991. (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
  12992. (tp->phy_flags & TG3_PHYFLG_IS_FET))
  12993. return true;
  12994. if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
  12995. if (tg3_asic_rev(tp) == ASIC_REV_5705) {
  12996. if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
  12997. return true;
  12998. } else {
  12999. return true;
  13000. }
  13001. }
  13002. return false;
  13003. }
  13004. static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
  13005. {
  13006. u32 misc_ctrl_reg;
  13007. u32 pci_state_reg, grc_misc_cfg;
  13008. u32 val;
  13009. u16 pci_cmd;
  13010. int err;
  13011. /* Force memory write invalidate off. If we leave it on,
  13012. * then on 5700_BX chips we have to enable a workaround.
  13013. * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
  13014. * to match the cacheline size. The Broadcom driver have this
  13015. * workaround but turns MWI off all the times so never uses
  13016. * it. This seems to suggest that the workaround is insufficient.
  13017. */
  13018. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  13019. pci_cmd &= ~PCI_COMMAND_INVALIDATE;
  13020. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  13021. /* Important! -- Make sure register accesses are byteswapped
  13022. * correctly. Also, for those chips that require it, make
  13023. * sure that indirect register accesses are enabled before
  13024. * the first operation.
  13025. */
  13026. pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  13027. &misc_ctrl_reg);
  13028. tp->misc_host_ctrl |= (misc_ctrl_reg &
  13029. MISC_HOST_CTRL_CHIPREV);
  13030. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  13031. tp->misc_host_ctrl);
  13032. tg3_detect_asic_rev(tp, misc_ctrl_reg);
  13033. /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
  13034. * we need to disable memory and use config. cycles
  13035. * only to access all registers. The 5702/03 chips
  13036. * can mistakenly decode the special cycles from the
  13037. * ICH chipsets as memory write cycles, causing corruption
  13038. * of register and memory space. Only certain ICH bridges
  13039. * will drive special cycles with non-zero data during the
  13040. * address phase which can fall within the 5703's address
  13041. * range. This is not an ICH bug as the PCI spec allows
  13042. * non-zero address during special cycles. However, only
  13043. * these ICH bridges are known to drive non-zero addresses
  13044. * during special cycles.
  13045. *
  13046. * Since special cycles do not cross PCI bridges, we only
  13047. * enable this workaround if the 5703 is on the secondary
  13048. * bus of these ICH bridges.
  13049. */
  13050. if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
  13051. (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
  13052. static struct tg3_dev_id {
  13053. u32 vendor;
  13054. u32 device;
  13055. u32 rev;
  13056. } ich_chipsets[] = {
  13057. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
  13058. PCI_ANY_ID },
  13059. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
  13060. PCI_ANY_ID },
  13061. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
  13062. 0xa },
  13063. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
  13064. PCI_ANY_ID },
  13065. { },
  13066. };
  13067. struct tg3_dev_id *pci_id = &ich_chipsets[0];
  13068. struct pci_dev *bridge = NULL;
  13069. while (pci_id->vendor != 0) {
  13070. bridge = pci_get_device(pci_id->vendor, pci_id->device,
  13071. bridge);
  13072. if (!bridge) {
  13073. pci_id++;
  13074. continue;
  13075. }
  13076. if (pci_id->rev != PCI_ANY_ID) {
  13077. if (bridge->revision > pci_id->rev)
  13078. continue;
  13079. }
  13080. if (bridge->subordinate &&
  13081. (bridge->subordinate->number ==
  13082. tp->pdev->bus->number)) {
  13083. tg3_flag_set(tp, ICH_WORKAROUND);
  13084. pci_dev_put(bridge);
  13085. break;
  13086. }
  13087. }
  13088. }
  13089. if (tg3_asic_rev(tp) == ASIC_REV_5701) {
  13090. static struct tg3_dev_id {
  13091. u32 vendor;
  13092. u32 device;
  13093. } bridge_chipsets[] = {
  13094. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
  13095. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
  13096. { },
  13097. };
  13098. struct tg3_dev_id *pci_id = &bridge_chipsets[0];
  13099. struct pci_dev *bridge = NULL;
  13100. while (pci_id->vendor != 0) {
  13101. bridge = pci_get_device(pci_id->vendor,
  13102. pci_id->device,
  13103. bridge);
  13104. if (!bridge) {
  13105. pci_id++;
  13106. continue;
  13107. }
  13108. if (bridge->subordinate &&
  13109. (bridge->subordinate->number <=
  13110. tp->pdev->bus->number) &&
  13111. (bridge->subordinate->busn_res.end >=
  13112. tp->pdev->bus->number)) {
  13113. tg3_flag_set(tp, 5701_DMA_BUG);
  13114. pci_dev_put(bridge);
  13115. break;
  13116. }
  13117. }
  13118. }
  13119. /* The EPB bridge inside 5714, 5715, and 5780 cannot support
  13120. * DMA addresses > 40-bit. This bridge may have other additional
  13121. * 57xx devices behind it in some 4-port NIC designs for example.
  13122. * Any tg3 device found behind the bridge will also need the 40-bit
  13123. * DMA workaround.
  13124. */
  13125. if (tg3_flag(tp, 5780_CLASS)) {
  13126. tg3_flag_set(tp, 40BIT_DMA_BUG);
  13127. tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
  13128. } else {
  13129. struct pci_dev *bridge = NULL;
  13130. do {
  13131. bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  13132. PCI_DEVICE_ID_SERVERWORKS_EPB,
  13133. bridge);
  13134. if (bridge && bridge->subordinate &&
  13135. (bridge->subordinate->number <=
  13136. tp->pdev->bus->number) &&
  13137. (bridge->subordinate->busn_res.end >=
  13138. tp->pdev->bus->number)) {
  13139. tg3_flag_set(tp, 40BIT_DMA_BUG);
  13140. pci_dev_put(bridge);
  13141. break;
  13142. }
  13143. } while (bridge);
  13144. }
  13145. if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
  13146. tg3_asic_rev(tp) == ASIC_REV_5714)
  13147. tp->pdev_peer = tg3_find_peer(tp);
  13148. /* Determine TSO capabilities */
  13149. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
  13150. ; /* Do nothing. HW bug. */
  13151. else if (tg3_flag(tp, 57765_PLUS))
  13152. tg3_flag_set(tp, HW_TSO_3);
  13153. else if (tg3_flag(tp, 5755_PLUS) ||
  13154. tg3_asic_rev(tp) == ASIC_REV_5906)
  13155. tg3_flag_set(tp, HW_TSO_2);
  13156. else if (tg3_flag(tp, 5750_PLUS)) {
  13157. tg3_flag_set(tp, HW_TSO_1);
  13158. tg3_flag_set(tp, TSO_BUG);
  13159. if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
  13160. tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
  13161. tg3_flag_clear(tp, TSO_BUG);
  13162. } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  13163. tg3_asic_rev(tp) != ASIC_REV_5701 &&
  13164. tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
  13165. tg3_flag_set(tp, FW_TSO);
  13166. tg3_flag_set(tp, TSO_BUG);
  13167. if (tg3_asic_rev(tp) == ASIC_REV_5705)
  13168. tp->fw_needed = FIRMWARE_TG3TSO5;
  13169. else
  13170. tp->fw_needed = FIRMWARE_TG3TSO;
  13171. }
  13172. /* Selectively allow TSO based on operating conditions */
  13173. if (tg3_flag(tp, HW_TSO_1) ||
  13174. tg3_flag(tp, HW_TSO_2) ||
  13175. tg3_flag(tp, HW_TSO_3) ||
  13176. tg3_flag(tp, FW_TSO)) {
  13177. /* For firmware TSO, assume ASF is disabled.
  13178. * We'll disable TSO later if we discover ASF
  13179. * is enabled in tg3_get_eeprom_hw_cfg().
  13180. */
  13181. tg3_flag_set(tp, TSO_CAPABLE);
  13182. } else {
  13183. tg3_flag_clear(tp, TSO_CAPABLE);
  13184. tg3_flag_clear(tp, TSO_BUG);
  13185. tp->fw_needed = NULL;
  13186. }
  13187. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
  13188. tp->fw_needed = FIRMWARE_TG3;
  13189. if (tg3_asic_rev(tp) == ASIC_REV_57766)
  13190. tp->fw_needed = FIRMWARE_TG357766;
  13191. tp->irq_max = 1;
  13192. if (tg3_flag(tp, 5750_PLUS)) {
  13193. tg3_flag_set(tp, SUPPORT_MSI);
  13194. if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
  13195. tg3_chip_rev(tp) == CHIPREV_5750_BX ||
  13196. (tg3_asic_rev(tp) == ASIC_REV_5714 &&
  13197. tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
  13198. tp->pdev_peer == tp->pdev))
  13199. tg3_flag_clear(tp, SUPPORT_MSI);
  13200. if (tg3_flag(tp, 5755_PLUS) ||
  13201. tg3_asic_rev(tp) == ASIC_REV_5906) {
  13202. tg3_flag_set(tp, 1SHOT_MSI);
  13203. }
  13204. if (tg3_flag(tp, 57765_PLUS)) {
  13205. tg3_flag_set(tp, SUPPORT_MSIX);
  13206. tp->irq_max = TG3_IRQ_MAX_VECS;
  13207. }
  13208. }
  13209. tp->txq_max = 1;
  13210. tp->rxq_max = 1;
  13211. if (tp->irq_max > 1) {
  13212. tp->rxq_max = TG3_RSS_MAX_NUM_QS;
  13213. tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
  13214. if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  13215. tg3_asic_rev(tp) == ASIC_REV_5720)
  13216. tp->txq_max = tp->irq_max - 1;
  13217. }
  13218. if (tg3_flag(tp, 5755_PLUS) ||
  13219. tg3_asic_rev(tp) == ASIC_REV_5906)
  13220. tg3_flag_set(tp, SHORT_DMA_BUG);
  13221. if (tg3_asic_rev(tp) == ASIC_REV_5719)
  13222. tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
  13223. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  13224. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  13225. tg3_asic_rev(tp) == ASIC_REV_5720 ||
  13226. tg3_asic_rev(tp) == ASIC_REV_5762)
  13227. tg3_flag_set(tp, LRG_PROD_RING_CAP);
  13228. if (tg3_flag(tp, 57765_PLUS) &&
  13229. tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
  13230. tg3_flag_set(tp, USE_JUMBO_BDFLAG);
  13231. if (!tg3_flag(tp, 5705_PLUS) ||
  13232. tg3_flag(tp, 5780_CLASS) ||
  13233. tg3_flag(tp, USE_JUMBO_BDFLAG))
  13234. tg3_flag_set(tp, JUMBO_CAPABLE);
  13235. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  13236. &pci_state_reg);
  13237. if (pci_is_pcie(tp->pdev)) {
  13238. u16 lnkctl;
  13239. tg3_flag_set(tp, PCI_EXPRESS);
  13240. pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
  13241. if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
  13242. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  13243. tg3_flag_clear(tp, HW_TSO_2);
  13244. tg3_flag_clear(tp, TSO_CAPABLE);
  13245. }
  13246. if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
  13247. tg3_asic_rev(tp) == ASIC_REV_5761 ||
  13248. tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
  13249. tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
  13250. tg3_flag_set(tp, CLKREQ_BUG);
  13251. } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
  13252. tg3_flag_set(tp, L1PLLPD_EN);
  13253. }
  13254. } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
  13255. /* BCM5785 devices are effectively PCIe devices, and should
  13256. * follow PCIe codepaths, but do not have a PCIe capabilities
  13257. * section.
  13258. */
  13259. tg3_flag_set(tp, PCI_EXPRESS);
  13260. } else if (!tg3_flag(tp, 5705_PLUS) ||
  13261. tg3_flag(tp, 5780_CLASS)) {
  13262. tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
  13263. if (!tp->pcix_cap) {
  13264. dev_err(&tp->pdev->dev,
  13265. "Cannot find PCI-X capability, aborting\n");
  13266. return -EIO;
  13267. }
  13268. if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
  13269. tg3_flag_set(tp, PCIX_MODE);
  13270. }
  13271. /* If we have an AMD 762 or VIA K8T800 chipset, write
  13272. * reordering to the mailbox registers done by the host
  13273. * controller can cause major troubles. We read back from
  13274. * every mailbox register write to force the writes to be
  13275. * posted to the chip in order.
  13276. */
  13277. if (pci_dev_present(tg3_write_reorder_chipsets) &&
  13278. !tg3_flag(tp, PCI_EXPRESS))
  13279. tg3_flag_set(tp, MBOX_WRITE_REORDER);
  13280. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  13281. &tp->pci_cacheline_sz);
  13282. pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  13283. &tp->pci_lat_timer);
  13284. if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
  13285. tp->pci_lat_timer < 64) {
  13286. tp->pci_lat_timer = 64;
  13287. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  13288. tp->pci_lat_timer);
  13289. }
  13290. /* Important! -- It is critical that the PCI-X hw workaround
  13291. * situation is decided before the first MMIO register access.
  13292. */
  13293. if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
  13294. /* 5700 BX chips need to have their TX producer index
  13295. * mailboxes written twice to workaround a bug.
  13296. */
  13297. tg3_flag_set(tp, TXD_MBOX_HWBUG);
  13298. /* If we are in PCI-X mode, enable register write workaround.
  13299. *
  13300. * The workaround is to use indirect register accesses
  13301. * for all chip writes not to mailbox registers.
  13302. */
  13303. if (tg3_flag(tp, PCIX_MODE)) {
  13304. u32 pm_reg;
  13305. tg3_flag_set(tp, PCIX_TARGET_HWBUG);
  13306. /* The chip can have it's power management PCI config
  13307. * space registers clobbered due to this bug.
  13308. * So explicitly force the chip into D0 here.
  13309. */
  13310. pci_read_config_dword(tp->pdev,
  13311. tp->pm_cap + PCI_PM_CTRL,
  13312. &pm_reg);
  13313. pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
  13314. pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
  13315. pci_write_config_dword(tp->pdev,
  13316. tp->pm_cap + PCI_PM_CTRL,
  13317. pm_reg);
  13318. /* Also, force SERR#/PERR# in PCI command. */
  13319. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  13320. pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  13321. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  13322. }
  13323. }
  13324. if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
  13325. tg3_flag_set(tp, PCI_HIGH_SPEED);
  13326. if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
  13327. tg3_flag_set(tp, PCI_32BIT);
  13328. /* Chip-specific fixup from Broadcom driver */
  13329. if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
  13330. (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
  13331. pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
  13332. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  13333. }
  13334. /* Default fast path register access methods */
  13335. tp->read32 = tg3_read32;
  13336. tp->write32 = tg3_write32;
  13337. tp->read32_mbox = tg3_read32;
  13338. tp->write32_mbox = tg3_write32;
  13339. tp->write32_tx_mbox = tg3_write32;
  13340. tp->write32_rx_mbox = tg3_write32;
  13341. /* Various workaround register access methods */
  13342. if (tg3_flag(tp, PCIX_TARGET_HWBUG))
  13343. tp->write32 = tg3_write_indirect_reg32;
  13344. else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
  13345. (tg3_flag(tp, PCI_EXPRESS) &&
  13346. tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
  13347. /*
  13348. * Back to back register writes can cause problems on these
  13349. * chips, the workaround is to read back all reg writes
  13350. * except those to mailbox regs.
  13351. *
  13352. * See tg3_write_indirect_reg32().
  13353. */
  13354. tp->write32 = tg3_write_flush_reg32;
  13355. }
  13356. if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
  13357. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  13358. if (tg3_flag(tp, MBOX_WRITE_REORDER))
  13359. tp->write32_rx_mbox = tg3_write_flush_reg32;
  13360. }
  13361. if (tg3_flag(tp, ICH_WORKAROUND)) {
  13362. tp->read32 = tg3_read_indirect_reg32;
  13363. tp->write32 = tg3_write_indirect_reg32;
  13364. tp->read32_mbox = tg3_read_indirect_mbox;
  13365. tp->write32_mbox = tg3_write_indirect_mbox;
  13366. tp->write32_tx_mbox = tg3_write_indirect_mbox;
  13367. tp->write32_rx_mbox = tg3_write_indirect_mbox;
  13368. iounmap(tp->regs);
  13369. tp->regs = NULL;
  13370. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  13371. pci_cmd &= ~PCI_COMMAND_MEMORY;
  13372. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  13373. }
  13374. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  13375. tp->read32_mbox = tg3_read32_mbox_5906;
  13376. tp->write32_mbox = tg3_write32_mbox_5906;
  13377. tp->write32_tx_mbox = tg3_write32_mbox_5906;
  13378. tp->write32_rx_mbox = tg3_write32_mbox_5906;
  13379. }
  13380. if (tp->write32 == tg3_write_indirect_reg32 ||
  13381. (tg3_flag(tp, PCIX_MODE) &&
  13382. (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  13383. tg3_asic_rev(tp) == ASIC_REV_5701)))
  13384. tg3_flag_set(tp, SRAM_USE_CONFIG);
  13385. /* The memory arbiter has to be enabled in order for SRAM accesses
  13386. * to succeed. Normally on powerup the tg3 chip firmware will make
  13387. * sure it is enabled, but other entities such as system netboot
  13388. * code might disable it.
  13389. */
  13390. val = tr32(MEMARB_MODE);
  13391. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  13392. tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
  13393. if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
  13394. tg3_flag(tp, 5780_CLASS)) {
  13395. if (tg3_flag(tp, PCIX_MODE)) {
  13396. pci_read_config_dword(tp->pdev,
  13397. tp->pcix_cap + PCI_X_STATUS,
  13398. &val);
  13399. tp->pci_fn = val & 0x7;
  13400. }
  13401. } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  13402. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  13403. tg3_asic_rev(tp) == ASIC_REV_5720) {
  13404. tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
  13405. if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
  13406. val = tr32(TG3_CPMU_STATUS);
  13407. if (tg3_asic_rev(tp) == ASIC_REV_5717)
  13408. tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
  13409. else
  13410. tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
  13411. TG3_CPMU_STATUS_FSHFT_5719;
  13412. }
  13413. if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
  13414. tp->write32_tx_mbox = tg3_write_flush_reg32;
  13415. tp->write32_rx_mbox = tg3_write_flush_reg32;
  13416. }
  13417. /* Get eeprom hw config before calling tg3_set_power_state().
  13418. * In particular, the TG3_FLAG_IS_NIC flag must be
  13419. * determined before calling tg3_set_power_state() so that
  13420. * we know whether or not to switch out of Vaux power.
  13421. * When the flag is set, it means that GPIO1 is used for eeprom
  13422. * write protect and also implies that it is a LOM where GPIOs
  13423. * are not used to switch power.
  13424. */
  13425. tg3_get_eeprom_hw_cfg(tp);
  13426. if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
  13427. tg3_flag_clear(tp, TSO_CAPABLE);
  13428. tg3_flag_clear(tp, TSO_BUG);
  13429. tp->fw_needed = NULL;
  13430. }
  13431. if (tg3_flag(tp, ENABLE_APE)) {
  13432. /* Allow reads and writes to the
  13433. * APE register and memory space.
  13434. */
  13435. pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  13436. PCISTATE_ALLOW_APE_SHMEM_WR |
  13437. PCISTATE_ALLOW_APE_PSPACE_WR;
  13438. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
  13439. pci_state_reg);
  13440. tg3_ape_lock_init(tp);
  13441. }
  13442. /* Set up tp->grc_local_ctrl before calling
  13443. * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
  13444. * will bring 5700's external PHY out of reset.
  13445. * It is also used as eeprom write protect on LOMs.
  13446. */
  13447. tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
  13448. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  13449. tg3_flag(tp, EEPROM_WRITE_PROT))
  13450. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  13451. GRC_LCLCTRL_GPIO_OUTPUT1);
  13452. /* Unused GPIO3 must be driven as output on 5752 because there
  13453. * are no pull-up resistors on unused GPIO pins.
  13454. */
  13455. else if (tg3_asic_rev(tp) == ASIC_REV_5752)
  13456. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  13457. if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  13458. tg3_asic_rev(tp) == ASIC_REV_57780 ||
  13459. tg3_flag(tp, 57765_CLASS))
  13460. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  13461. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  13462. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
  13463. /* Turn off the debug UART. */
  13464. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  13465. if (tg3_flag(tp, IS_NIC))
  13466. /* Keep VMain power. */
  13467. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  13468. GRC_LCLCTRL_GPIO_OUTPUT0;
  13469. }
  13470. if (tg3_asic_rev(tp) == ASIC_REV_5762)
  13471. tp->grc_local_ctrl |=
  13472. tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
  13473. /* Switch out of Vaux if it is a NIC */
  13474. tg3_pwrsrc_switch_to_vmain(tp);
  13475. /* Derive initial jumbo mode from MTU assigned in
  13476. * ether_setup() via the alloc_etherdev() call
  13477. */
  13478. if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
  13479. tg3_flag_set(tp, JUMBO_RING_ENABLE);
  13480. /* Determine WakeOnLan speed to use. */
  13481. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  13482. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  13483. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
  13484. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
  13485. tg3_flag_clear(tp, WOL_SPEED_100MB);
  13486. } else {
  13487. tg3_flag_set(tp, WOL_SPEED_100MB);
  13488. }
  13489. if (tg3_asic_rev(tp) == ASIC_REV_5906)
  13490. tp->phy_flags |= TG3_PHYFLG_IS_FET;
  13491. /* A few boards don't want Ethernet@WireSpeed phy feature */
  13492. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  13493. (tg3_asic_rev(tp) == ASIC_REV_5705 &&
  13494. (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
  13495. (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
  13496. (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
  13497. (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  13498. tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
  13499. if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
  13500. tg3_chip_rev(tp) == CHIPREV_5704_AX)
  13501. tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
  13502. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
  13503. tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
  13504. if (tg3_flag(tp, 5705_PLUS) &&
  13505. !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  13506. tg3_asic_rev(tp) != ASIC_REV_5785 &&
  13507. tg3_asic_rev(tp) != ASIC_REV_57780 &&
  13508. !tg3_flag(tp, 57765_PLUS)) {
  13509. if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  13510. tg3_asic_rev(tp) == ASIC_REV_5787 ||
  13511. tg3_asic_rev(tp) == ASIC_REV_5784 ||
  13512. tg3_asic_rev(tp) == ASIC_REV_5761) {
  13513. if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
  13514. tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
  13515. tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
  13516. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
  13517. tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
  13518. } else
  13519. tp->phy_flags |= TG3_PHYFLG_BER_BUG;
  13520. }
  13521. if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
  13522. tg3_chip_rev(tp) != CHIPREV_5784_AX) {
  13523. tp->phy_otp = tg3_read_otp_phycfg(tp);
  13524. if (tp->phy_otp == 0)
  13525. tp->phy_otp = TG3_OTP_DEFAULT;
  13526. }
  13527. if (tg3_flag(tp, CPMU_PRESENT))
  13528. tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
  13529. else
  13530. tp->mi_mode = MAC_MI_MODE_BASE;
  13531. tp->coalesce_mode = 0;
  13532. if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
  13533. tg3_chip_rev(tp) != CHIPREV_5700_BX)
  13534. tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
  13535. /* Set these bits to enable statistics workaround. */
  13536. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  13537. tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
  13538. tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
  13539. tp->coalesce_mode |= HOSTCC_MODE_ATTN;
  13540. tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
  13541. }
  13542. if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
  13543. tg3_asic_rev(tp) == ASIC_REV_57780)
  13544. tg3_flag_set(tp, USE_PHYLIB);
  13545. err = tg3_mdio_init(tp);
  13546. if (err)
  13547. return err;
  13548. /* Initialize data/descriptor byte/word swapping. */
  13549. val = tr32(GRC_MODE);
  13550. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  13551. tg3_asic_rev(tp) == ASIC_REV_5762)
  13552. val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
  13553. GRC_MODE_WORD_SWAP_B2HRX_DATA |
  13554. GRC_MODE_B2HRX_ENABLE |
  13555. GRC_MODE_HTX2B_ENABLE |
  13556. GRC_MODE_HOST_STACKUP);
  13557. else
  13558. val &= GRC_MODE_HOST_STACKUP;
  13559. tw32(GRC_MODE, val | tp->grc_mode);
  13560. tg3_switch_clocks(tp);
  13561. /* Clear this out for sanity. */
  13562. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  13563. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  13564. &pci_state_reg);
  13565. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
  13566. !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
  13567. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  13568. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
  13569. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
  13570. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
  13571. void __iomem *sram_base;
  13572. /* Write some dummy words into the SRAM status block
  13573. * area, see if it reads back correctly. If the return
  13574. * value is bad, force enable the PCIX workaround.
  13575. */
  13576. sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
  13577. writel(0x00000000, sram_base);
  13578. writel(0x00000000, sram_base + 4);
  13579. writel(0xffffffff, sram_base + 4);
  13580. if (readl(sram_base) != 0x00000000)
  13581. tg3_flag_set(tp, PCIX_TARGET_HWBUG);
  13582. }
  13583. }
  13584. udelay(50);
  13585. tg3_nvram_init(tp);
  13586. /* If the device has an NVRAM, no need to load patch firmware */
  13587. if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
  13588. !tg3_flag(tp, NO_NVRAM))
  13589. tp->fw_needed = NULL;
  13590. grc_misc_cfg = tr32(GRC_MISC_CFG);
  13591. grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
  13592. if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
  13593. (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
  13594. grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
  13595. tg3_flag_set(tp, IS_5788);
  13596. if (!tg3_flag(tp, IS_5788) &&
  13597. tg3_asic_rev(tp) != ASIC_REV_5700)
  13598. tg3_flag_set(tp, TAGGED_STATUS);
  13599. if (tg3_flag(tp, TAGGED_STATUS)) {
  13600. tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
  13601. HOSTCC_MODE_CLRTICK_TXBD);
  13602. tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
  13603. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  13604. tp->misc_host_ctrl);
  13605. }
  13606. /* Preserve the APE MAC_MODE bits */
  13607. if (tg3_flag(tp, ENABLE_APE))
  13608. tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  13609. else
  13610. tp->mac_mode = 0;
  13611. if (tg3_10_100_only_device(tp, ent))
  13612. tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
  13613. err = tg3_phy_probe(tp);
  13614. if (err) {
  13615. dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
  13616. /* ... but do not return immediately ... */
  13617. tg3_mdio_fini(tp);
  13618. }
  13619. tg3_read_vpd(tp);
  13620. tg3_read_fw_ver(tp);
  13621. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  13622. tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
  13623. } else {
  13624. if (tg3_asic_rev(tp) == ASIC_REV_5700)
  13625. tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
  13626. else
  13627. tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
  13628. }
  13629. /* 5700 {AX,BX} chips have a broken status block link
  13630. * change bit implementation, so we must use the
  13631. * status register in those cases.
  13632. */
  13633. if (tg3_asic_rev(tp) == ASIC_REV_5700)
  13634. tg3_flag_set(tp, USE_LINKCHG_REG);
  13635. else
  13636. tg3_flag_clear(tp, USE_LINKCHG_REG);
  13637. /* The led_ctrl is set during tg3_phy_probe, here we might
  13638. * have to force the link status polling mechanism based
  13639. * upon subsystem IDs.
  13640. */
  13641. if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  13642. tg3_asic_rev(tp) == ASIC_REV_5701 &&
  13643. !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  13644. tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
  13645. tg3_flag_set(tp, USE_LINKCHG_REG);
  13646. }
  13647. /* For all SERDES we poll the MAC status register. */
  13648. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  13649. tg3_flag_set(tp, POLL_SERDES);
  13650. else
  13651. tg3_flag_clear(tp, POLL_SERDES);
  13652. tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
  13653. tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
  13654. if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
  13655. tg3_flag(tp, PCIX_MODE)) {
  13656. tp->rx_offset = NET_SKB_PAD;
  13657. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  13658. tp->rx_copy_thresh = ~(u16)0;
  13659. #endif
  13660. }
  13661. tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
  13662. tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
  13663. tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
  13664. tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
  13665. /* Increment the rx prod index on the rx std ring by at most
  13666. * 8 for these chips to workaround hw errata.
  13667. */
  13668. if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
  13669. tg3_asic_rev(tp) == ASIC_REV_5752 ||
  13670. tg3_asic_rev(tp) == ASIC_REV_5755)
  13671. tp->rx_std_max_post = 8;
  13672. if (tg3_flag(tp, ASPM_WORKAROUND))
  13673. tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
  13674. PCIE_PWR_MGMT_L1_THRESH_MSK;
  13675. return err;
  13676. }
  13677. #ifdef CONFIG_SPARC
  13678. static int tg3_get_macaddr_sparc(struct tg3 *tp)
  13679. {
  13680. struct net_device *dev = tp->dev;
  13681. struct pci_dev *pdev = tp->pdev;
  13682. struct device_node *dp = pci_device_to_OF_node(pdev);
  13683. const unsigned char *addr;
  13684. int len;
  13685. addr = of_get_property(dp, "local-mac-address", &len);
  13686. if (addr && len == 6) {
  13687. memcpy(dev->dev_addr, addr, 6);
  13688. return 0;
  13689. }
  13690. return -ENODEV;
  13691. }
  13692. static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
  13693. {
  13694. struct net_device *dev = tp->dev;
  13695. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  13696. return 0;
  13697. }
  13698. #endif
  13699. static int tg3_get_device_address(struct tg3 *tp)
  13700. {
  13701. struct net_device *dev = tp->dev;
  13702. u32 hi, lo, mac_offset;
  13703. int addr_ok = 0;
  13704. int err;
  13705. #ifdef CONFIG_SPARC
  13706. if (!tg3_get_macaddr_sparc(tp))
  13707. return 0;
  13708. #endif
  13709. if (tg3_flag(tp, IS_SSB_CORE)) {
  13710. err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
  13711. if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
  13712. return 0;
  13713. }
  13714. mac_offset = 0x7c;
  13715. if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
  13716. tg3_flag(tp, 5780_CLASS)) {
  13717. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  13718. mac_offset = 0xcc;
  13719. if (tg3_nvram_lock(tp))
  13720. tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
  13721. else
  13722. tg3_nvram_unlock(tp);
  13723. } else if (tg3_flag(tp, 5717_PLUS)) {
  13724. if (tp->pci_fn & 1)
  13725. mac_offset = 0xcc;
  13726. if (tp->pci_fn > 1)
  13727. mac_offset += 0x18c;
  13728. } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
  13729. mac_offset = 0x10;
  13730. /* First try to get it from MAC address mailbox. */
  13731. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
  13732. if ((hi >> 16) == 0x484b) {
  13733. dev->dev_addr[0] = (hi >> 8) & 0xff;
  13734. dev->dev_addr[1] = (hi >> 0) & 0xff;
  13735. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
  13736. dev->dev_addr[2] = (lo >> 24) & 0xff;
  13737. dev->dev_addr[3] = (lo >> 16) & 0xff;
  13738. dev->dev_addr[4] = (lo >> 8) & 0xff;
  13739. dev->dev_addr[5] = (lo >> 0) & 0xff;
  13740. /* Some old bootcode may report a 0 MAC address in SRAM */
  13741. addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
  13742. }
  13743. if (!addr_ok) {
  13744. /* Next, try NVRAM. */
  13745. if (!tg3_flag(tp, NO_NVRAM) &&
  13746. !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
  13747. !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
  13748. memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
  13749. memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
  13750. }
  13751. /* Finally just fetch it out of the MAC control regs. */
  13752. else {
  13753. hi = tr32(MAC_ADDR_0_HIGH);
  13754. lo = tr32(MAC_ADDR_0_LOW);
  13755. dev->dev_addr[5] = lo & 0xff;
  13756. dev->dev_addr[4] = (lo >> 8) & 0xff;
  13757. dev->dev_addr[3] = (lo >> 16) & 0xff;
  13758. dev->dev_addr[2] = (lo >> 24) & 0xff;
  13759. dev->dev_addr[1] = hi & 0xff;
  13760. dev->dev_addr[0] = (hi >> 8) & 0xff;
  13761. }
  13762. }
  13763. if (!is_valid_ether_addr(&dev->dev_addr[0])) {
  13764. #ifdef CONFIG_SPARC
  13765. if (!tg3_get_default_macaddr_sparc(tp))
  13766. return 0;
  13767. #endif
  13768. return -EINVAL;
  13769. }
  13770. return 0;
  13771. }
  13772. #define BOUNDARY_SINGLE_CACHELINE 1
  13773. #define BOUNDARY_MULTI_CACHELINE 2
  13774. static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
  13775. {
  13776. int cacheline_size;
  13777. u8 byte;
  13778. int goal;
  13779. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
  13780. if (byte == 0)
  13781. cacheline_size = 1024;
  13782. else
  13783. cacheline_size = (int) byte * 4;
  13784. /* On 5703 and later chips, the boundary bits have no
  13785. * effect.
  13786. */
  13787. if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  13788. tg3_asic_rev(tp) != ASIC_REV_5701 &&
  13789. !tg3_flag(tp, PCI_EXPRESS))
  13790. goto out;
  13791. #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
  13792. goal = BOUNDARY_MULTI_CACHELINE;
  13793. #else
  13794. #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
  13795. goal = BOUNDARY_SINGLE_CACHELINE;
  13796. #else
  13797. goal = 0;
  13798. #endif
  13799. #endif
  13800. if (tg3_flag(tp, 57765_PLUS)) {
  13801. val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
  13802. goto out;
  13803. }
  13804. if (!goal)
  13805. goto out;
  13806. /* PCI controllers on most RISC systems tend to disconnect
  13807. * when a device tries to burst across a cache-line boundary.
  13808. * Therefore, letting tg3 do so just wastes PCI bandwidth.
  13809. *
  13810. * Unfortunately, for PCI-E there are only limited
  13811. * write-side controls for this, and thus for reads
  13812. * we will still get the disconnects. We'll also waste
  13813. * these PCI cycles for both read and write for chips
  13814. * other than 5700 and 5701 which do not implement the
  13815. * boundary bits.
  13816. */
  13817. if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
  13818. switch (cacheline_size) {
  13819. case 16:
  13820. case 32:
  13821. case 64:
  13822. case 128:
  13823. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13824. val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
  13825. DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
  13826. } else {
  13827. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  13828. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  13829. }
  13830. break;
  13831. case 256:
  13832. val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
  13833. DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
  13834. break;
  13835. default:
  13836. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  13837. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  13838. break;
  13839. }
  13840. } else if (tg3_flag(tp, PCI_EXPRESS)) {
  13841. switch (cacheline_size) {
  13842. case 16:
  13843. case 32:
  13844. case 64:
  13845. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13846. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  13847. val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
  13848. break;
  13849. }
  13850. /* fallthrough */
  13851. case 128:
  13852. default:
  13853. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  13854. val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
  13855. break;
  13856. }
  13857. } else {
  13858. switch (cacheline_size) {
  13859. case 16:
  13860. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13861. val |= (DMA_RWCTRL_READ_BNDRY_16 |
  13862. DMA_RWCTRL_WRITE_BNDRY_16);
  13863. break;
  13864. }
  13865. /* fallthrough */
  13866. case 32:
  13867. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13868. val |= (DMA_RWCTRL_READ_BNDRY_32 |
  13869. DMA_RWCTRL_WRITE_BNDRY_32);
  13870. break;
  13871. }
  13872. /* fallthrough */
  13873. case 64:
  13874. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13875. val |= (DMA_RWCTRL_READ_BNDRY_64 |
  13876. DMA_RWCTRL_WRITE_BNDRY_64);
  13877. break;
  13878. }
  13879. /* fallthrough */
  13880. case 128:
  13881. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13882. val |= (DMA_RWCTRL_READ_BNDRY_128 |
  13883. DMA_RWCTRL_WRITE_BNDRY_128);
  13884. break;
  13885. }
  13886. /* fallthrough */
  13887. case 256:
  13888. val |= (DMA_RWCTRL_READ_BNDRY_256 |
  13889. DMA_RWCTRL_WRITE_BNDRY_256);
  13890. break;
  13891. case 512:
  13892. val |= (DMA_RWCTRL_READ_BNDRY_512 |
  13893. DMA_RWCTRL_WRITE_BNDRY_512);
  13894. break;
  13895. case 1024:
  13896. default:
  13897. val |= (DMA_RWCTRL_READ_BNDRY_1024 |
  13898. DMA_RWCTRL_WRITE_BNDRY_1024);
  13899. break;
  13900. }
  13901. }
  13902. out:
  13903. return val;
  13904. }
  13905. static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
  13906. int size, bool to_device)
  13907. {
  13908. struct tg3_internal_buffer_desc test_desc;
  13909. u32 sram_dma_descs;
  13910. int i, ret;
  13911. sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
  13912. tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
  13913. tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
  13914. tw32(RDMAC_STATUS, 0);
  13915. tw32(WDMAC_STATUS, 0);
  13916. tw32(BUFMGR_MODE, 0);
  13917. tw32(FTQ_RESET, 0);
  13918. test_desc.addr_hi = ((u64) buf_dma) >> 32;
  13919. test_desc.addr_lo = buf_dma & 0xffffffff;
  13920. test_desc.nic_mbuf = 0x00002100;
  13921. test_desc.len = size;
  13922. /*
  13923. * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
  13924. * the *second* time the tg3 driver was getting loaded after an
  13925. * initial scan.
  13926. *
  13927. * Broadcom tells me:
  13928. * ...the DMA engine is connected to the GRC block and a DMA
  13929. * reset may affect the GRC block in some unpredictable way...
  13930. * The behavior of resets to individual blocks has not been tested.
  13931. *
  13932. * Broadcom noted the GRC reset will also reset all sub-components.
  13933. */
  13934. if (to_device) {
  13935. test_desc.cqid_sqid = (13 << 8) | 2;
  13936. tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
  13937. udelay(40);
  13938. } else {
  13939. test_desc.cqid_sqid = (16 << 8) | 7;
  13940. tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
  13941. udelay(40);
  13942. }
  13943. test_desc.flags = 0x00000005;
  13944. for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
  13945. u32 val;
  13946. val = *(((u32 *)&test_desc) + i);
  13947. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
  13948. sram_dma_descs + (i * sizeof(u32)));
  13949. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  13950. }
  13951. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  13952. if (to_device)
  13953. tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
  13954. else
  13955. tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
  13956. ret = -ENODEV;
  13957. for (i = 0; i < 40; i++) {
  13958. u32 val;
  13959. if (to_device)
  13960. val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
  13961. else
  13962. val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
  13963. if ((val & 0xffff) == sram_dma_descs) {
  13964. ret = 0;
  13965. break;
  13966. }
  13967. udelay(100);
  13968. }
  13969. return ret;
  13970. }
  13971. #define TEST_BUFFER_SIZE 0x2000
  13972. static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
  13973. { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
  13974. { },
  13975. };
  13976. static int tg3_test_dma(struct tg3 *tp)
  13977. {
  13978. dma_addr_t buf_dma;
  13979. u32 *buf, saved_dma_rwctrl;
  13980. int ret = 0;
  13981. buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
  13982. &buf_dma, GFP_KERNEL);
  13983. if (!buf) {
  13984. ret = -ENOMEM;
  13985. goto out_nofree;
  13986. }
  13987. tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  13988. (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
  13989. tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
  13990. if (tg3_flag(tp, 57765_PLUS))
  13991. goto out;
  13992. if (tg3_flag(tp, PCI_EXPRESS)) {
  13993. /* DMA read watermark not used on PCIE */
  13994. tp->dma_rwctrl |= 0x00180000;
  13995. } else if (!tg3_flag(tp, PCIX_MODE)) {
  13996. if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
  13997. tg3_asic_rev(tp) == ASIC_REV_5750)
  13998. tp->dma_rwctrl |= 0x003f0000;
  13999. else
  14000. tp->dma_rwctrl |= 0x003f000f;
  14001. } else {
  14002. if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
  14003. tg3_asic_rev(tp) == ASIC_REV_5704) {
  14004. u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
  14005. u32 read_water = 0x7;
  14006. /* If the 5704 is behind the EPB bridge, we can
  14007. * do the less restrictive ONE_DMA workaround for
  14008. * better performance.
  14009. */
  14010. if (tg3_flag(tp, 40BIT_DMA_BUG) &&
  14011. tg3_asic_rev(tp) == ASIC_REV_5704)
  14012. tp->dma_rwctrl |= 0x8000;
  14013. else if (ccval == 0x6 || ccval == 0x7)
  14014. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  14015. if (tg3_asic_rev(tp) == ASIC_REV_5703)
  14016. read_water = 4;
  14017. /* Set bit 23 to enable PCIX hw bug fix */
  14018. tp->dma_rwctrl |=
  14019. (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
  14020. (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  14021. (1 << 23);
  14022. } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
  14023. /* 5780 always in PCIX mode */
  14024. tp->dma_rwctrl |= 0x00144000;
  14025. } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  14026. /* 5714 always in PCIX mode */
  14027. tp->dma_rwctrl |= 0x00148000;
  14028. } else {
  14029. tp->dma_rwctrl |= 0x001b000f;
  14030. }
  14031. }
  14032. if (tg3_flag(tp, ONE_DMA_AT_ONCE))
  14033. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  14034. if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
  14035. tg3_asic_rev(tp) == ASIC_REV_5704)
  14036. tp->dma_rwctrl &= 0xfffffff0;
  14037. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  14038. tg3_asic_rev(tp) == ASIC_REV_5701) {
  14039. /* Remove this if it causes problems for some boards. */
  14040. tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  14041. /* On 5700/5701 chips, we need to set this bit.
  14042. * Otherwise the chip will issue cacheline transactions
  14043. * to streamable DMA memory with not all the byte
  14044. * enables turned on. This is an error on several
  14045. * RISC PCI controllers, in particular sparc64.
  14046. *
  14047. * On 5703/5704 chips, this bit has been reassigned
  14048. * a different meaning. In particular, it is used
  14049. * on those chips to enable a PCI-X workaround.
  14050. */
  14051. tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  14052. }
  14053. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  14054. #if 0
  14055. /* Unneeded, already done by tg3_get_invariants. */
  14056. tg3_switch_clocks(tp);
  14057. #endif
  14058. if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  14059. tg3_asic_rev(tp) != ASIC_REV_5701)
  14060. goto out;
  14061. /* It is best to perform DMA test with maximum write burst size
  14062. * to expose the 5700/5701 write DMA bug.
  14063. */
  14064. saved_dma_rwctrl = tp->dma_rwctrl;
  14065. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  14066. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  14067. while (1) {
  14068. u32 *p = buf, i;
  14069. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  14070. p[i] = i;
  14071. /* Send the buffer to the chip. */
  14072. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
  14073. if (ret) {
  14074. dev_err(&tp->pdev->dev,
  14075. "%s: Buffer write failed. err = %d\n",
  14076. __func__, ret);
  14077. break;
  14078. }
  14079. #if 0
  14080. /* validate data reached card RAM correctly. */
  14081. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  14082. u32 val;
  14083. tg3_read_mem(tp, 0x2100 + (i*4), &val);
  14084. if (le32_to_cpu(val) != p[i]) {
  14085. dev_err(&tp->pdev->dev,
  14086. "%s: Buffer corrupted on device! "
  14087. "(%d != %d)\n", __func__, val, i);
  14088. /* ret = -ENODEV here? */
  14089. }
  14090. p[i] = 0;
  14091. }
  14092. #endif
  14093. /* Now read it back. */
  14094. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
  14095. if (ret) {
  14096. dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
  14097. "err = %d\n", __func__, ret);
  14098. break;
  14099. }
  14100. /* Verify it. */
  14101. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  14102. if (p[i] == i)
  14103. continue;
  14104. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  14105. DMA_RWCTRL_WRITE_BNDRY_16) {
  14106. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  14107. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  14108. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  14109. break;
  14110. } else {
  14111. dev_err(&tp->pdev->dev,
  14112. "%s: Buffer corrupted on read back! "
  14113. "(%d != %d)\n", __func__, p[i], i);
  14114. ret = -ENODEV;
  14115. goto out;
  14116. }
  14117. }
  14118. if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
  14119. /* Success. */
  14120. ret = 0;
  14121. break;
  14122. }
  14123. }
  14124. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  14125. DMA_RWCTRL_WRITE_BNDRY_16) {
  14126. /* DMA test passed without adjusting DMA boundary,
  14127. * now look for chipsets that are known to expose the
  14128. * DMA bug without failing the test.
  14129. */
  14130. if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
  14131. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  14132. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  14133. } else {
  14134. /* Safe to use the calculated DMA boundary. */
  14135. tp->dma_rwctrl = saved_dma_rwctrl;
  14136. }
  14137. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  14138. }
  14139. out:
  14140. dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
  14141. out_nofree:
  14142. return ret;
  14143. }
  14144. static void tg3_init_bufmgr_config(struct tg3 *tp)
  14145. {
  14146. if (tg3_flag(tp, 57765_PLUS)) {
  14147. tp->bufmgr_config.mbuf_read_dma_low_water =
  14148. DEFAULT_MB_RDMA_LOW_WATER_5705;
  14149. tp->bufmgr_config.mbuf_mac_rx_low_water =
  14150. DEFAULT_MB_MACRX_LOW_WATER_57765;
  14151. tp->bufmgr_config.mbuf_high_water =
  14152. DEFAULT_MB_HIGH_WATER_57765;
  14153. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  14154. DEFAULT_MB_RDMA_LOW_WATER_5705;
  14155. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  14156. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
  14157. tp->bufmgr_config.mbuf_high_water_jumbo =
  14158. DEFAULT_MB_HIGH_WATER_JUMBO_57765;
  14159. } else if (tg3_flag(tp, 5705_PLUS)) {
  14160. tp->bufmgr_config.mbuf_read_dma_low_water =
  14161. DEFAULT_MB_RDMA_LOW_WATER_5705;
  14162. tp->bufmgr_config.mbuf_mac_rx_low_water =
  14163. DEFAULT_MB_MACRX_LOW_WATER_5705;
  14164. tp->bufmgr_config.mbuf_high_water =
  14165. DEFAULT_MB_HIGH_WATER_5705;
  14166. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  14167. tp->bufmgr_config.mbuf_mac_rx_low_water =
  14168. DEFAULT_MB_MACRX_LOW_WATER_5906;
  14169. tp->bufmgr_config.mbuf_high_water =
  14170. DEFAULT_MB_HIGH_WATER_5906;
  14171. }
  14172. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  14173. DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
  14174. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  14175. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
  14176. tp->bufmgr_config.mbuf_high_water_jumbo =
  14177. DEFAULT_MB_HIGH_WATER_JUMBO_5780;
  14178. } else {
  14179. tp->bufmgr_config.mbuf_read_dma_low_water =
  14180. DEFAULT_MB_RDMA_LOW_WATER;
  14181. tp->bufmgr_config.mbuf_mac_rx_low_water =
  14182. DEFAULT_MB_MACRX_LOW_WATER;
  14183. tp->bufmgr_config.mbuf_high_water =
  14184. DEFAULT_MB_HIGH_WATER;
  14185. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  14186. DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
  14187. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  14188. DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
  14189. tp->bufmgr_config.mbuf_high_water_jumbo =
  14190. DEFAULT_MB_HIGH_WATER_JUMBO;
  14191. }
  14192. tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
  14193. tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
  14194. }
  14195. static char *tg3_phy_string(struct tg3 *tp)
  14196. {
  14197. switch (tp->phy_id & TG3_PHY_ID_MASK) {
  14198. case TG3_PHY_ID_BCM5400: return "5400";
  14199. case TG3_PHY_ID_BCM5401: return "5401";
  14200. case TG3_PHY_ID_BCM5411: return "5411";
  14201. case TG3_PHY_ID_BCM5701: return "5701";
  14202. case TG3_PHY_ID_BCM5703: return "5703";
  14203. case TG3_PHY_ID_BCM5704: return "5704";
  14204. case TG3_PHY_ID_BCM5705: return "5705";
  14205. case TG3_PHY_ID_BCM5750: return "5750";
  14206. case TG3_PHY_ID_BCM5752: return "5752";
  14207. case TG3_PHY_ID_BCM5714: return "5714";
  14208. case TG3_PHY_ID_BCM5780: return "5780";
  14209. case TG3_PHY_ID_BCM5755: return "5755";
  14210. case TG3_PHY_ID_BCM5787: return "5787";
  14211. case TG3_PHY_ID_BCM5784: return "5784";
  14212. case TG3_PHY_ID_BCM5756: return "5722/5756";
  14213. case TG3_PHY_ID_BCM5906: return "5906";
  14214. case TG3_PHY_ID_BCM5761: return "5761";
  14215. case TG3_PHY_ID_BCM5718C: return "5718C";
  14216. case TG3_PHY_ID_BCM5718S: return "5718S";
  14217. case TG3_PHY_ID_BCM57765: return "57765";
  14218. case TG3_PHY_ID_BCM5719C: return "5719C";
  14219. case TG3_PHY_ID_BCM5720C: return "5720C";
  14220. case TG3_PHY_ID_BCM5762: return "5762C";
  14221. case TG3_PHY_ID_BCM8002: return "8002/serdes";
  14222. case 0: return "serdes";
  14223. default: return "unknown";
  14224. }
  14225. }
  14226. static char *tg3_bus_string(struct tg3 *tp, char *str)
  14227. {
  14228. if (tg3_flag(tp, PCI_EXPRESS)) {
  14229. strcpy(str, "PCI Express");
  14230. return str;
  14231. } else if (tg3_flag(tp, PCIX_MODE)) {
  14232. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
  14233. strcpy(str, "PCIX:");
  14234. if ((clock_ctrl == 7) ||
  14235. ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
  14236. GRC_MISC_CFG_BOARD_ID_5704CIOBE))
  14237. strcat(str, "133MHz");
  14238. else if (clock_ctrl == 0)
  14239. strcat(str, "33MHz");
  14240. else if (clock_ctrl == 2)
  14241. strcat(str, "50MHz");
  14242. else if (clock_ctrl == 4)
  14243. strcat(str, "66MHz");
  14244. else if (clock_ctrl == 6)
  14245. strcat(str, "100MHz");
  14246. } else {
  14247. strcpy(str, "PCI:");
  14248. if (tg3_flag(tp, PCI_HIGH_SPEED))
  14249. strcat(str, "66MHz");
  14250. else
  14251. strcat(str, "33MHz");
  14252. }
  14253. if (tg3_flag(tp, PCI_32BIT))
  14254. strcat(str, ":32-bit");
  14255. else
  14256. strcat(str, ":64-bit");
  14257. return str;
  14258. }
  14259. static void tg3_init_coal(struct tg3 *tp)
  14260. {
  14261. struct ethtool_coalesce *ec = &tp->coal;
  14262. memset(ec, 0, sizeof(*ec));
  14263. ec->cmd = ETHTOOL_GCOALESCE;
  14264. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
  14265. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
  14266. ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
  14267. ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
  14268. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
  14269. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
  14270. ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
  14271. ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
  14272. ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
  14273. if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
  14274. HOSTCC_MODE_CLRTICK_TXBD)) {
  14275. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
  14276. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
  14277. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
  14278. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
  14279. }
  14280. if (tg3_flag(tp, 5705_PLUS)) {
  14281. ec->rx_coalesce_usecs_irq = 0;
  14282. ec->tx_coalesce_usecs_irq = 0;
  14283. ec->stats_block_coalesce_usecs = 0;
  14284. }
  14285. }
  14286. static int tg3_init_one(struct pci_dev *pdev,
  14287. const struct pci_device_id *ent)
  14288. {
  14289. struct net_device *dev;
  14290. struct tg3 *tp;
  14291. int i, err;
  14292. u32 sndmbx, rcvmbx, intmbx;
  14293. char str[40];
  14294. u64 dma_mask, persist_dma_mask;
  14295. netdev_features_t features = 0;
  14296. printk_once(KERN_INFO "%s\n", version);
  14297. err = pci_enable_device(pdev);
  14298. if (err) {
  14299. dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
  14300. return err;
  14301. }
  14302. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  14303. if (err) {
  14304. dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
  14305. goto err_out_disable_pdev;
  14306. }
  14307. pci_set_master(pdev);
  14308. dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
  14309. if (!dev) {
  14310. err = -ENOMEM;
  14311. goto err_out_free_res;
  14312. }
  14313. SET_NETDEV_DEV(dev, &pdev->dev);
  14314. tp = netdev_priv(dev);
  14315. tp->pdev = pdev;
  14316. tp->dev = dev;
  14317. tp->pm_cap = pdev->pm_cap;
  14318. tp->rx_mode = TG3_DEF_RX_MODE;
  14319. tp->tx_mode = TG3_DEF_TX_MODE;
  14320. tp->irq_sync = 1;
  14321. if (tg3_debug > 0)
  14322. tp->msg_enable = tg3_debug;
  14323. else
  14324. tp->msg_enable = TG3_DEF_MSG_ENABLE;
  14325. if (pdev_is_ssb_gige_core(pdev)) {
  14326. tg3_flag_set(tp, IS_SSB_CORE);
  14327. if (ssb_gige_must_flush_posted_writes(pdev))
  14328. tg3_flag_set(tp, FLUSH_POSTED_WRITES);
  14329. if (ssb_gige_one_dma_at_once(pdev))
  14330. tg3_flag_set(tp, ONE_DMA_AT_ONCE);
  14331. if (ssb_gige_have_roboswitch(pdev))
  14332. tg3_flag_set(tp, ROBOSWITCH);
  14333. if (ssb_gige_is_rgmii(pdev))
  14334. tg3_flag_set(tp, RGMII_MODE);
  14335. }
  14336. /* The word/byte swap controls here control register access byte
  14337. * swapping. DMA data byte swapping is controlled in the GRC_MODE
  14338. * setting below.
  14339. */
  14340. tp->misc_host_ctrl =
  14341. MISC_HOST_CTRL_MASK_PCI_INT |
  14342. MISC_HOST_CTRL_WORD_SWAP |
  14343. MISC_HOST_CTRL_INDIR_ACCESS |
  14344. MISC_HOST_CTRL_PCISTATE_RW;
  14345. /* The NONFRM (non-frame) byte/word swap controls take effect
  14346. * on descriptor entries, anything which isn't packet data.
  14347. *
  14348. * The StrongARM chips on the board (one for tx, one for rx)
  14349. * are running in big-endian mode.
  14350. */
  14351. tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
  14352. GRC_MODE_WSWAP_NONFRM_DATA);
  14353. #ifdef __BIG_ENDIAN
  14354. tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
  14355. #endif
  14356. spin_lock_init(&tp->lock);
  14357. spin_lock_init(&tp->indirect_lock);
  14358. INIT_WORK(&tp->reset_task, tg3_reset_task);
  14359. tp->regs = pci_ioremap_bar(pdev, BAR_0);
  14360. if (!tp->regs) {
  14361. dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
  14362. err = -ENOMEM;
  14363. goto err_out_free_dev;
  14364. }
  14365. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  14366. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
  14367. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
  14368. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
  14369. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  14370. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
  14371. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
  14372. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
  14373. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
  14374. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
  14375. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
  14376. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727) {
  14377. tg3_flag_set(tp, ENABLE_APE);
  14378. tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
  14379. if (!tp->aperegs) {
  14380. dev_err(&pdev->dev,
  14381. "Cannot map APE registers, aborting\n");
  14382. err = -ENOMEM;
  14383. goto err_out_iounmap;
  14384. }
  14385. }
  14386. tp->rx_pending = TG3_DEF_RX_RING_PENDING;
  14387. tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
  14388. dev->ethtool_ops = &tg3_ethtool_ops;
  14389. dev->watchdog_timeo = TG3_TX_TIMEOUT;
  14390. dev->netdev_ops = &tg3_netdev_ops;
  14391. dev->irq = pdev->irq;
  14392. err = tg3_get_invariants(tp, ent);
  14393. if (err) {
  14394. dev_err(&pdev->dev,
  14395. "Problem fetching invariants of chip, aborting\n");
  14396. goto err_out_apeunmap;
  14397. }
  14398. /* The EPB bridge inside 5714, 5715, and 5780 and any
  14399. * device behind the EPB cannot support DMA addresses > 40-bit.
  14400. * On 64-bit systems with IOMMU, use 40-bit dma_mask.
  14401. * On 64-bit systems without IOMMU, use 64-bit dma_mask and
  14402. * do DMA address check in tg3_start_xmit().
  14403. */
  14404. if (tg3_flag(tp, IS_5788))
  14405. persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
  14406. else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
  14407. persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
  14408. #ifdef CONFIG_HIGHMEM
  14409. dma_mask = DMA_BIT_MASK(64);
  14410. #endif
  14411. } else
  14412. persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
  14413. /* Configure DMA attributes. */
  14414. if (dma_mask > DMA_BIT_MASK(32)) {
  14415. err = pci_set_dma_mask(pdev, dma_mask);
  14416. if (!err) {
  14417. features |= NETIF_F_HIGHDMA;
  14418. err = pci_set_consistent_dma_mask(pdev,
  14419. persist_dma_mask);
  14420. if (err < 0) {
  14421. dev_err(&pdev->dev, "Unable to obtain 64 bit "
  14422. "DMA for consistent allocations\n");
  14423. goto err_out_apeunmap;
  14424. }
  14425. }
  14426. }
  14427. if (err || dma_mask == DMA_BIT_MASK(32)) {
  14428. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  14429. if (err) {
  14430. dev_err(&pdev->dev,
  14431. "No usable DMA configuration, aborting\n");
  14432. goto err_out_apeunmap;
  14433. }
  14434. }
  14435. tg3_init_bufmgr_config(tp);
  14436. features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
  14437. /* 5700 B0 chips do not support checksumming correctly due
  14438. * to hardware bugs.
  14439. */
  14440. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
  14441. features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
  14442. if (tg3_flag(tp, 5755_PLUS))
  14443. features |= NETIF_F_IPV6_CSUM;
  14444. }
  14445. /* TSO is on by default on chips that support hardware TSO.
  14446. * Firmware TSO on older chips gives lower performance, so it
  14447. * is off by default, but can be enabled using ethtool.
  14448. */
  14449. if ((tg3_flag(tp, HW_TSO_1) ||
  14450. tg3_flag(tp, HW_TSO_2) ||
  14451. tg3_flag(tp, HW_TSO_3)) &&
  14452. (features & NETIF_F_IP_CSUM))
  14453. features |= NETIF_F_TSO;
  14454. if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
  14455. if (features & NETIF_F_IPV6_CSUM)
  14456. features |= NETIF_F_TSO6;
  14457. if (tg3_flag(tp, HW_TSO_3) ||
  14458. tg3_asic_rev(tp) == ASIC_REV_5761 ||
  14459. (tg3_asic_rev(tp) == ASIC_REV_5784 &&
  14460. tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
  14461. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  14462. tg3_asic_rev(tp) == ASIC_REV_57780)
  14463. features |= NETIF_F_TSO_ECN;
  14464. }
  14465. dev->features |= features;
  14466. dev->vlan_features |= features;
  14467. /*
  14468. * Add loopback capability only for a subset of devices that support
  14469. * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
  14470. * loopback for the remaining devices.
  14471. */
  14472. if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
  14473. !tg3_flag(tp, CPMU_PRESENT))
  14474. /* Add the loopback capability */
  14475. features |= NETIF_F_LOOPBACK;
  14476. dev->hw_features |= features;
  14477. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
  14478. !tg3_flag(tp, TSO_CAPABLE) &&
  14479. !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
  14480. tg3_flag_set(tp, MAX_RXPEND_64);
  14481. tp->rx_pending = 63;
  14482. }
  14483. err = tg3_get_device_address(tp);
  14484. if (err) {
  14485. dev_err(&pdev->dev,
  14486. "Could not obtain valid ethernet address, aborting\n");
  14487. goto err_out_apeunmap;
  14488. }
  14489. /*
  14490. * Reset chip in case UNDI or EFI driver did not shutdown
  14491. * DMA self test will enable WDMAC and we'll see (spurious)
  14492. * pending DMA on the PCI bus at that point.
  14493. */
  14494. if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
  14495. (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  14496. tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  14497. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  14498. }
  14499. err = tg3_test_dma(tp);
  14500. if (err) {
  14501. dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
  14502. goto err_out_apeunmap;
  14503. }
  14504. intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
  14505. rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
  14506. sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
  14507. for (i = 0; i < tp->irq_max; i++) {
  14508. struct tg3_napi *tnapi = &tp->napi[i];
  14509. tnapi->tp = tp;
  14510. tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
  14511. tnapi->int_mbox = intmbx;
  14512. if (i <= 4)
  14513. intmbx += 0x8;
  14514. else
  14515. intmbx += 0x4;
  14516. tnapi->consmbox = rcvmbx;
  14517. tnapi->prodmbox = sndmbx;
  14518. if (i)
  14519. tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
  14520. else
  14521. tnapi->coal_now = HOSTCC_MODE_NOW;
  14522. if (!tg3_flag(tp, SUPPORT_MSIX))
  14523. break;
  14524. /*
  14525. * If we support MSIX, we'll be using RSS. If we're using
  14526. * RSS, the first vector only handles link interrupts and the
  14527. * remaining vectors handle rx and tx interrupts. Reuse the
  14528. * mailbox values for the next iteration. The values we setup
  14529. * above are still useful for the single vectored mode.
  14530. */
  14531. if (!i)
  14532. continue;
  14533. rcvmbx += 0x8;
  14534. if (sndmbx & 0x4)
  14535. sndmbx -= 0x4;
  14536. else
  14537. sndmbx += 0xc;
  14538. }
  14539. tg3_init_coal(tp);
  14540. pci_set_drvdata(pdev, dev);
  14541. if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  14542. tg3_asic_rev(tp) == ASIC_REV_5720 ||
  14543. tg3_asic_rev(tp) == ASIC_REV_5762)
  14544. tg3_flag_set(tp, PTP_CAPABLE);
  14545. if (tg3_flag(tp, 5717_PLUS)) {
  14546. /* Resume a low-power mode */
  14547. tg3_frob_aux_power(tp, false);
  14548. }
  14549. tg3_timer_init(tp);
  14550. tg3_carrier_off(tp);
  14551. err = register_netdev(dev);
  14552. if (err) {
  14553. dev_err(&pdev->dev, "Cannot register net device, aborting\n");
  14554. goto err_out_apeunmap;
  14555. }
  14556. netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
  14557. tp->board_part_number,
  14558. tg3_chip_rev_id(tp),
  14559. tg3_bus_string(tp, str),
  14560. dev->dev_addr);
  14561. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  14562. struct phy_device *phydev;
  14563. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  14564. netdev_info(dev,
  14565. "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
  14566. phydev->drv->name, dev_name(&phydev->dev));
  14567. } else {
  14568. char *ethtype;
  14569. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  14570. ethtype = "10/100Base-TX";
  14571. else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  14572. ethtype = "1000Base-SX";
  14573. else
  14574. ethtype = "10/100/1000Base-T";
  14575. netdev_info(dev, "attached PHY is %s (%s Ethernet) "
  14576. "(WireSpeed[%d], EEE[%d])\n",
  14577. tg3_phy_string(tp), ethtype,
  14578. (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
  14579. (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
  14580. }
  14581. netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
  14582. (dev->features & NETIF_F_RXCSUM) != 0,
  14583. tg3_flag(tp, USE_LINKCHG_REG) != 0,
  14584. (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
  14585. tg3_flag(tp, ENABLE_ASF) != 0,
  14586. tg3_flag(tp, TSO_CAPABLE) != 0);
  14587. netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
  14588. tp->dma_rwctrl,
  14589. pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
  14590. ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
  14591. pci_save_state(pdev);
  14592. return 0;
  14593. err_out_apeunmap:
  14594. if (tp->aperegs) {
  14595. iounmap(tp->aperegs);
  14596. tp->aperegs = NULL;
  14597. }
  14598. err_out_iounmap:
  14599. if (tp->regs) {
  14600. iounmap(tp->regs);
  14601. tp->regs = NULL;
  14602. }
  14603. err_out_free_dev:
  14604. free_netdev(dev);
  14605. err_out_free_res:
  14606. pci_release_regions(pdev);
  14607. err_out_disable_pdev:
  14608. pci_disable_device(pdev);
  14609. pci_set_drvdata(pdev, NULL);
  14610. return err;
  14611. }
  14612. static void tg3_remove_one(struct pci_dev *pdev)
  14613. {
  14614. struct net_device *dev = pci_get_drvdata(pdev);
  14615. if (dev) {
  14616. struct tg3 *tp = netdev_priv(dev);
  14617. release_firmware(tp->fw);
  14618. tg3_reset_task_cancel(tp);
  14619. if (tg3_flag(tp, USE_PHYLIB)) {
  14620. tg3_phy_fini(tp);
  14621. tg3_mdio_fini(tp);
  14622. }
  14623. unregister_netdev(dev);
  14624. if (tp->aperegs) {
  14625. iounmap(tp->aperegs);
  14626. tp->aperegs = NULL;
  14627. }
  14628. if (tp->regs) {
  14629. iounmap(tp->regs);
  14630. tp->regs = NULL;
  14631. }
  14632. free_netdev(dev);
  14633. pci_release_regions(pdev);
  14634. pci_disable_device(pdev);
  14635. pci_set_drvdata(pdev, NULL);
  14636. }
  14637. }
  14638. #ifdef CONFIG_PM_SLEEP
  14639. static int tg3_suspend(struct device *device)
  14640. {
  14641. struct pci_dev *pdev = to_pci_dev(device);
  14642. struct net_device *dev = pci_get_drvdata(pdev);
  14643. struct tg3 *tp = netdev_priv(dev);
  14644. int err;
  14645. if (!netif_running(dev))
  14646. return 0;
  14647. tg3_reset_task_cancel(tp);
  14648. tg3_phy_stop(tp);
  14649. tg3_netif_stop(tp);
  14650. tg3_timer_stop(tp);
  14651. tg3_full_lock(tp, 1);
  14652. tg3_disable_ints(tp);
  14653. tg3_full_unlock(tp);
  14654. netif_device_detach(dev);
  14655. tg3_full_lock(tp, 0);
  14656. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  14657. tg3_flag_clear(tp, INIT_COMPLETE);
  14658. tg3_full_unlock(tp);
  14659. err = tg3_power_down_prepare(tp);
  14660. if (err) {
  14661. int err2;
  14662. tg3_full_lock(tp, 0);
  14663. tg3_flag_set(tp, INIT_COMPLETE);
  14664. err2 = tg3_restart_hw(tp, true);
  14665. if (err2)
  14666. goto out;
  14667. tg3_timer_start(tp);
  14668. netif_device_attach(dev);
  14669. tg3_netif_start(tp);
  14670. out:
  14671. tg3_full_unlock(tp);
  14672. if (!err2)
  14673. tg3_phy_start(tp);
  14674. }
  14675. return err;
  14676. }
  14677. static int tg3_resume(struct device *device)
  14678. {
  14679. struct pci_dev *pdev = to_pci_dev(device);
  14680. struct net_device *dev = pci_get_drvdata(pdev);
  14681. struct tg3 *tp = netdev_priv(dev);
  14682. int err;
  14683. if (!netif_running(dev))
  14684. return 0;
  14685. netif_device_attach(dev);
  14686. tg3_full_lock(tp, 0);
  14687. tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
  14688. tg3_flag_set(tp, INIT_COMPLETE);
  14689. err = tg3_restart_hw(tp,
  14690. !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
  14691. if (err)
  14692. goto out;
  14693. tg3_timer_start(tp);
  14694. tg3_netif_start(tp);
  14695. out:
  14696. tg3_full_unlock(tp);
  14697. if (!err)
  14698. tg3_phy_start(tp);
  14699. return err;
  14700. }
  14701. #endif /* CONFIG_PM_SLEEP */
  14702. static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
  14703. /**
  14704. * tg3_io_error_detected - called when PCI error is detected
  14705. * @pdev: Pointer to PCI device
  14706. * @state: The current pci connection state
  14707. *
  14708. * This function is called after a PCI bus error affecting
  14709. * this device has been detected.
  14710. */
  14711. static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
  14712. pci_channel_state_t state)
  14713. {
  14714. struct net_device *netdev = pci_get_drvdata(pdev);
  14715. struct tg3 *tp = netdev_priv(netdev);
  14716. pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
  14717. netdev_info(netdev, "PCI I/O error detected\n");
  14718. rtnl_lock();
  14719. if (!netif_running(netdev))
  14720. goto done;
  14721. tg3_phy_stop(tp);
  14722. tg3_netif_stop(tp);
  14723. tg3_timer_stop(tp);
  14724. /* Want to make sure that the reset task doesn't run */
  14725. tg3_reset_task_cancel(tp);
  14726. netif_device_detach(netdev);
  14727. /* Clean up software state, even if MMIO is blocked */
  14728. tg3_full_lock(tp, 0);
  14729. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  14730. tg3_full_unlock(tp);
  14731. done:
  14732. if (state == pci_channel_io_perm_failure) {
  14733. tg3_napi_enable(tp);
  14734. dev_close(netdev);
  14735. err = PCI_ERS_RESULT_DISCONNECT;
  14736. } else {
  14737. pci_disable_device(pdev);
  14738. }
  14739. rtnl_unlock();
  14740. return err;
  14741. }
  14742. /**
  14743. * tg3_io_slot_reset - called after the pci bus has been reset.
  14744. * @pdev: Pointer to PCI device
  14745. *
  14746. * Restart the card from scratch, as if from a cold-boot.
  14747. * At this point, the card has exprienced a hard reset,
  14748. * followed by fixups by BIOS, and has its config space
  14749. * set up identically to what it was at cold boot.
  14750. */
  14751. static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
  14752. {
  14753. struct net_device *netdev = pci_get_drvdata(pdev);
  14754. struct tg3 *tp = netdev_priv(netdev);
  14755. pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
  14756. int err;
  14757. rtnl_lock();
  14758. if (pci_enable_device(pdev)) {
  14759. netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
  14760. goto done;
  14761. }
  14762. pci_set_master(pdev);
  14763. pci_restore_state(pdev);
  14764. pci_save_state(pdev);
  14765. if (!netif_running(netdev)) {
  14766. rc = PCI_ERS_RESULT_RECOVERED;
  14767. goto done;
  14768. }
  14769. err = tg3_power_up(tp);
  14770. if (err)
  14771. goto done;
  14772. rc = PCI_ERS_RESULT_RECOVERED;
  14773. done:
  14774. if (rc != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) {
  14775. tg3_napi_enable(tp);
  14776. dev_close(netdev);
  14777. }
  14778. rtnl_unlock();
  14779. return rc;
  14780. }
  14781. /**
  14782. * tg3_io_resume - called when traffic can start flowing again.
  14783. * @pdev: Pointer to PCI device
  14784. *
  14785. * This callback is called when the error recovery driver tells
  14786. * us that its OK to resume normal operation.
  14787. */
  14788. static void tg3_io_resume(struct pci_dev *pdev)
  14789. {
  14790. struct net_device *netdev = pci_get_drvdata(pdev);
  14791. struct tg3 *tp = netdev_priv(netdev);
  14792. int err;
  14793. rtnl_lock();
  14794. if (!netif_running(netdev))
  14795. goto done;
  14796. tg3_full_lock(tp, 0);
  14797. tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
  14798. tg3_flag_set(tp, INIT_COMPLETE);
  14799. err = tg3_restart_hw(tp, true);
  14800. if (err) {
  14801. tg3_full_unlock(tp);
  14802. netdev_err(netdev, "Cannot restart hardware after reset.\n");
  14803. goto done;
  14804. }
  14805. netif_device_attach(netdev);
  14806. tg3_timer_start(tp);
  14807. tg3_netif_start(tp);
  14808. tg3_full_unlock(tp);
  14809. tg3_phy_start(tp);
  14810. done:
  14811. rtnl_unlock();
  14812. }
  14813. static const struct pci_error_handlers tg3_err_handler = {
  14814. .error_detected = tg3_io_error_detected,
  14815. .slot_reset = tg3_io_slot_reset,
  14816. .resume = tg3_io_resume
  14817. };
  14818. static struct pci_driver tg3_driver = {
  14819. .name = DRV_MODULE_NAME,
  14820. .id_table = tg3_pci_tbl,
  14821. .probe = tg3_init_one,
  14822. .remove = tg3_remove_one,
  14823. .err_handler = &tg3_err_handler,
  14824. .driver.pm = &tg3_pm_ops,
  14825. };
  14826. module_pci_driver(tg3_driver);