spear13xx.dtsi 7.4 KB

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  1. /*
  2. * DTS file for all SPEAr13xx SoCs
  3. *
  4. * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
  5. *
  6. * The code contained herein is licensed under the GNU General Public
  7. * License. You may obtain a copy of the GNU General Public License
  8. * Version 2 or later at the following locations:
  9. *
  10. * http://www.opensource.org/licenses/gpl-license.html
  11. * http://www.gnu.org/copyleft/gpl.html
  12. */
  13. /include/ "skeleton.dtsi"
  14. / {
  15. interrupt-parent = <&gic>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. cpu@0 {
  20. compatible = "arm,cortex-a9";
  21. reg = <0>;
  22. next-level-cache = <&L2>;
  23. };
  24. cpu@1 {
  25. compatible = "arm,cortex-a9";
  26. reg = <1>;
  27. next-level-cache = <&L2>;
  28. };
  29. };
  30. gic: interrupt-controller@ec801000 {
  31. compatible = "arm,cortex-a9-gic";
  32. interrupt-controller;
  33. #interrupt-cells = <3>;
  34. reg = < 0xec801000 0x1000 >,
  35. < 0xec800100 0x0100 >;
  36. };
  37. pmu {
  38. compatible = "arm,cortex-a9-pmu";
  39. interrupts = <0 6 0x04
  40. 0 7 0x04>;
  41. };
  42. L2: l2-cache {
  43. compatible = "arm,pl310-cache";
  44. reg = <0xed000000 0x1000>;
  45. cache-unified;
  46. cache-level = <2>;
  47. };
  48. memory {
  49. name = "memory";
  50. device_type = "memory";
  51. reg = <0 0x40000000>;
  52. };
  53. chosen {
  54. bootargs = "console=ttyAMA0,115200";
  55. };
  56. cpufreq {
  57. compatible = "st,cpufreq-spear";
  58. cpufreq_tbl = < 166000
  59. 200000
  60. 250000
  61. 300000
  62. 400000
  63. 500000
  64. 600000 >;
  65. status = "disabled";
  66. };
  67. ahb {
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. compatible = "simple-bus";
  71. ranges = <0x50000000 0x50000000 0x10000000
  72. 0xb0000000 0xb0000000 0x10000000
  73. 0xd0000000 0xd0000000 0x02000000
  74. 0xd8000000 0xd8000000 0x01000000
  75. 0xe0000000 0xe0000000 0x10000000>;
  76. sdhci@b3000000 {
  77. compatible = "st,sdhci-spear";
  78. reg = <0xb3000000 0x100>;
  79. interrupts = <0 28 0x4>;
  80. status = "disabled";
  81. };
  82. cf@b2800000 {
  83. compatible = "arasan,cf-spear1340";
  84. reg = <0xb2800000 0x1000>;
  85. interrupts = <0 29 0x4>;
  86. status = "disabled";
  87. };
  88. dma@ea800000 {
  89. compatible = "snps,dma-spear1340";
  90. reg = <0xea800000 0x1000>;
  91. interrupts = <0 19 0x4>;
  92. status = "disabled";
  93. nr_channels = <8>;
  94. chan_allocation_order = <1>;
  95. chan_priority = <1>;
  96. block_size = <0xfff>;
  97. nr_masters = <2>;
  98. data_width = <3 3 0 0>;
  99. slave_info {
  100. ssp0_tx {
  101. bus_id = "ssp0_tx";
  102. cfg_hi = <0x2000>; /* 0x4 << 11 */
  103. cfg_lo = <0>;
  104. src_master = <0>;
  105. dst_master = <0>;
  106. };
  107. ssp0_rx {
  108. bus_id = "ssp0_rx";
  109. cfg_hi = <0x280>; /* 0x5 << 7 */
  110. cfg_lo = <0>;
  111. src_master = <0>;
  112. dst_master = <0>;
  113. };
  114. cf {
  115. bus_id = "cf";
  116. cfg_hi = <0>;
  117. cfg_lo = <0>;
  118. src_master = <0>;
  119. dst_master = <0>;
  120. };
  121. };
  122. };
  123. dma@eb000000 {
  124. compatible = "snps,dma-spear1340";
  125. reg = <0xeb000000 0x1000>;
  126. interrupts = <0 59 0x4>;
  127. status = "disabled";
  128. nr_channels = <8>;
  129. chan_allocation_order = <1>;
  130. chan_priority = <1>;
  131. block_size = <0xfff>;
  132. nr_masters = <2>;
  133. data_width = <3 3 0 0>;
  134. };
  135. fsmc: flash@b0000000 {
  136. compatible = "st,spear600-fsmc-nand";
  137. #address-cells = <1>;
  138. #size-cells = <1>;
  139. reg = <0xb0000000 0x1000 /* FSMC Register*/
  140. 0xb0800000 0x0010 /* NAND Base DATA */
  141. 0xb0820000 0x0010 /* NAND Base ADDR */
  142. 0xb0810000 0x0010>; /* NAND Base CMD */
  143. reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
  144. interrupts = <0 20 0x4
  145. 0 21 0x4
  146. 0 22 0x4
  147. 0 23 0x4>;
  148. st,mode = <2>;
  149. status = "disabled";
  150. };
  151. gmac0: eth@e2000000 {
  152. compatible = "st,spear600-gmac";
  153. reg = <0xe2000000 0x8000>;
  154. interrupts = <0 33 0x4
  155. 0 34 0x4>;
  156. interrupt-names = "macirq", "eth_wake_irq";
  157. status = "disabled";
  158. };
  159. pcm {
  160. compatible = "st,pcm-audio";
  161. #address-cells = <0>;
  162. #size-cells = <0>;
  163. status = "disabled";
  164. };
  165. smi: flash@ea000000 {
  166. compatible = "st,spear600-smi";
  167. #address-cells = <1>;
  168. #size-cells = <1>;
  169. reg = <0xea000000 0x1000>;
  170. interrupts = <0 30 0x4>;
  171. status = "disabled";
  172. };
  173. ehci@e4800000 {
  174. compatible = "st,spear600-ehci", "usb-ehci";
  175. reg = <0xe4800000 0x1000>;
  176. interrupts = <0 64 0x4>;
  177. usbh0_id = <0>;
  178. status = "disabled";
  179. };
  180. ehci@e5800000 {
  181. compatible = "st,spear600-ehci", "usb-ehci";
  182. reg = <0xe5800000 0x1000>;
  183. interrupts = <0 66 0x4>;
  184. usbh1_id = <1>;
  185. status = "disabled";
  186. };
  187. ohci@e4000000 {
  188. compatible = "st,spear600-ohci", "usb-ohci";
  189. reg = <0xe4000000 0x1000>;
  190. interrupts = <0 65 0x4>;
  191. usbh0_id = <0>;
  192. status = "disabled";
  193. };
  194. ohci@e5000000 {
  195. compatible = "st,spear600-ohci", "usb-ohci";
  196. reg = <0xe5000000 0x1000>;
  197. interrupts = <0 67 0x4>;
  198. usbh1_id = <1>;
  199. status = "disabled";
  200. };
  201. apb {
  202. #address-cells = <1>;
  203. #size-cells = <1>;
  204. compatible = "simple-bus";
  205. ranges = <0x50000000 0x50000000 0x10000000
  206. 0xb0000000 0xb0000000 0x10000000
  207. 0xd0000000 0xd0000000 0x02000000
  208. 0xd8000000 0xd8000000 0x01000000
  209. 0xe0000000 0xe0000000 0x10000000>;
  210. gpio0: gpio@e0600000 {
  211. compatible = "arm,pl061", "arm,primecell";
  212. reg = <0xe0600000 0x1000>;
  213. interrupts = <0 24 0x4>;
  214. gpio-controller;
  215. #gpio-cells = <2>;
  216. interrupt-controller;
  217. #interrupt-cells = <2>;
  218. status = "disabled";
  219. };
  220. gpio1: gpio@e0680000 {
  221. compatible = "arm,pl061", "arm,primecell";
  222. reg = <0xe0680000 0x1000>;
  223. interrupts = <0 25 0x4>;
  224. gpio-controller;
  225. #gpio-cells = <2>;
  226. interrupt-controller;
  227. #interrupt-cells = <2>;
  228. status = "disabled";
  229. };
  230. kbd@e0300000 {
  231. compatible = "st,spear300-kbd";
  232. reg = <0xe0300000 0x1000>;
  233. interrupts = <0 52 0x4>;
  234. status = "disabled";
  235. };
  236. i2c0: i2c@e0280000 {
  237. #address-cells = <1>;
  238. #size-cells = <0>;
  239. compatible = "snps,designware-i2c";
  240. reg = <0xe0280000 0x1000>;
  241. interrupts = <0 41 0x4>;
  242. status = "disabled";
  243. };
  244. i2s@e0180000 {
  245. compatible = "st,designware-i2s";
  246. reg = <0xe0180000 0x1000>;
  247. interrupt-names = "play_irq", "record_irq";
  248. interrupts = <0 10 0x4
  249. 0 11 0x4 >;
  250. status = "disabled";
  251. };
  252. i2s@e0200000 {
  253. compatible = "st,designware-i2s";
  254. reg = <0xe0200000 0x1000>;
  255. interrupt-names = "play_irq", "record_irq";
  256. interrupts = <0 26 0x4
  257. 0 53 0x4>;
  258. status = "disabled";
  259. };
  260. spi0: spi@e0100000 {
  261. compatible = "arm,pl022", "arm,primecell";
  262. reg = <0xe0100000 0x1000>;
  263. #address-cells = <1>;
  264. #size-cells = <0>;
  265. interrupts = <0 31 0x4>;
  266. status = "disabled";
  267. };
  268. rtc@e0580000 {
  269. compatible = "st,spear600-rtc";
  270. reg = <0xe0580000 0x1000>;
  271. interrupts = <0 36 0x4>;
  272. status = "disabled";
  273. };
  274. serial@e0000000 {
  275. compatible = "arm,pl011", "arm,primecell";
  276. reg = <0xe0000000 0x1000>;
  277. interrupts = <0 35 0x4>;
  278. status = "disabled";
  279. };
  280. adc@e0080000 {
  281. compatible = "st,spear600-adc";
  282. reg = <0xe0080000 0x1000>;
  283. interrupts = <0 12 0x4>;
  284. status = "disabled";
  285. };
  286. timer@e0380000 {
  287. compatible = "st,spear-timer";
  288. reg = <0xe0380000 0x400>;
  289. interrupts = <0 37 0x4>;
  290. };
  291. timer@ec800600 {
  292. compatible = "arm,cortex-a9-twd-timer";
  293. reg = <0xec800600 0x20>;
  294. interrupts = <1 13 0x4>;
  295. status = "disabled";
  296. };
  297. wdt@ec800620 {
  298. compatible = "arm,cortex-a9-twd-wdt";
  299. reg = <0xec800620 0x20>;
  300. status = "disabled";
  301. };
  302. thermal@e07008c4 {
  303. compatible = "st,thermal-spear1340";
  304. reg = <0xe07008c4 0x4>;
  305. thermal_flags = <0x7000>;
  306. };
  307. };
  308. };
  309. };