fw_common.c 22 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2010 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include <linux/firmware.h>
  30. #include "../wifi.h"
  31. #include "../pci.h"
  32. #include "../base.h"
  33. #include "../rtl8192ce/reg.h"
  34. #include "../rtl8192ce/def.h"
  35. #include "fw_common.h"
  36. static void _rtl92c_enable_fw_download(struct ieee80211_hw *hw, bool enable)
  37. {
  38. struct rtl_priv *rtlpriv = rtl_priv(hw);
  39. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  40. if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU) {
  41. u32 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  42. if (enable)
  43. value32 |= MCUFWDL_EN;
  44. else
  45. value32 &= ~MCUFWDL_EN;
  46. rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
  47. } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE) {
  48. u8 tmp;
  49. if (enable) {
  50. tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  51. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1,
  52. tmp | 0x04);
  53. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  54. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
  55. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
  56. rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
  57. } else {
  58. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  59. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
  60. rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);
  61. }
  62. }
  63. }
  64. static void _rtl92c_fw_block_write(struct ieee80211_hw *hw,
  65. const u8 *buffer, u32 size)
  66. {
  67. struct rtl_priv *rtlpriv = rtl_priv(hw);
  68. u32 blockSize = sizeof(u32);
  69. u8 *bufferPtr = (u8 *) buffer;
  70. u32 *pu4BytePtr = (u32 *) buffer;
  71. u32 i, offset, blockCount, remainSize;
  72. blockCount = size / blockSize;
  73. remainSize = size % blockSize;
  74. for (i = 0; i < blockCount; i++) {
  75. offset = i * blockSize;
  76. rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
  77. *(pu4BytePtr + i));
  78. }
  79. if (remainSize) {
  80. offset = blockCount * blockSize;
  81. bufferPtr += offset;
  82. for (i = 0; i < remainSize; i++) {
  83. rtl_write_byte(rtlpriv, (FW_8192C_START_ADDRESS +
  84. offset + i), *(bufferPtr + i));
  85. }
  86. }
  87. }
  88. static void _rtl92c_fw_page_write(struct ieee80211_hw *hw,
  89. u32 page, const u8 *buffer, u32 size)
  90. {
  91. struct rtl_priv *rtlpriv = rtl_priv(hw);
  92. u8 value8;
  93. u8 u8page = (u8) (page & 0x07);
  94. value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
  95. rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
  96. _rtl92c_fw_block_write(hw, buffer, size);
  97. }
  98. static void _rtl92c_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
  99. {
  100. u32 fwlen = *pfwlen;
  101. u8 remain = (u8) (fwlen % 4);
  102. remain = (remain == 0) ? 0 : (4 - remain);
  103. while (remain > 0) {
  104. pfwbuf[fwlen] = 0;
  105. fwlen++;
  106. remain--;
  107. }
  108. *pfwlen = fwlen;
  109. }
  110. static void _rtl92c_write_fw(struct ieee80211_hw *hw,
  111. enum version_8192c version, u8 *buffer, u32 size)
  112. {
  113. struct rtl_priv *rtlpriv = rtl_priv(hw);
  114. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  115. u8 *bufferPtr = (u8 *) buffer;
  116. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, ("FW size is %d bytes,\n", size));
  117. if (IS_CHIP_VER_B(version)) {
  118. u32 pageNums, remainSize;
  119. u32 page, offset;
  120. if (IS_HARDWARE_TYPE_8192CE(rtlhal))
  121. _rtl92c_fill_dummy(bufferPtr, &size);
  122. pageNums = size / FW_8192C_PAGE_SIZE;
  123. remainSize = size % FW_8192C_PAGE_SIZE;
  124. if (pageNums > 4) {
  125. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  126. ("Page numbers should not greater then 4\n"));
  127. }
  128. for (page = 0; page < pageNums; page++) {
  129. offset = page * FW_8192C_PAGE_SIZE;
  130. _rtl92c_fw_page_write(hw, page, (bufferPtr + offset),
  131. FW_8192C_PAGE_SIZE);
  132. }
  133. if (remainSize) {
  134. offset = pageNums * FW_8192C_PAGE_SIZE;
  135. page = pageNums;
  136. _rtl92c_fw_page_write(hw, page, (bufferPtr + offset),
  137. remainSize);
  138. }
  139. } else {
  140. _rtl92c_fw_block_write(hw, buffer, size);
  141. }
  142. }
  143. static int _rtl92c_fw_free_to_go(struct ieee80211_hw *hw)
  144. {
  145. struct rtl_priv *rtlpriv = rtl_priv(hw);
  146. u32 counter = 0;
  147. u32 value32;
  148. do {
  149. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  150. } while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
  151. (!(value32 & FWDL_ChkSum_rpt)));
  152. if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
  153. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  154. ("chksum report faill ! REG_MCUFWDL:0x%08x .\n",
  155. value32));
  156. return -EIO;
  157. }
  158. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  159. ("Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32));
  160. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  161. value32 |= MCUFWDL_RDY;
  162. value32 &= ~WINTINI_RDY;
  163. rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
  164. counter = 0;
  165. do {
  166. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  167. if (value32 & WINTINI_RDY) {
  168. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  169. ("Polling FW ready success!!"
  170. " REG_MCUFWDL:0x%08x .\n",
  171. value32));
  172. return 0;
  173. }
  174. mdelay(FW_8192C_POLLING_DELAY);
  175. } while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
  176. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  177. ("Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n", value32));
  178. return -EIO;
  179. }
  180. int rtl92c_download_fw(struct ieee80211_hw *hw)
  181. {
  182. struct rtl_priv *rtlpriv = rtl_priv(hw);
  183. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  184. struct rtl92c_firmware_header *pfwheader;
  185. u8 *pfwdata;
  186. u32 fwsize;
  187. enum version_8192c version = rtlhal->version;
  188. const struct firmware *firmware;
  189. printk(KERN_INFO "rtl8192c: Loading firmware file %s\n",
  190. rtlpriv->cfg->fw_name);
  191. if (request_firmware(&firmware, rtlpriv->cfg->fw_name,
  192. rtlpriv->io.dev)) {
  193. printk(KERN_ERR "rtl8192c: Firmware loading failed\n");
  194. return 1;
  195. }
  196. if (firmware->size > 0x4000) {
  197. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  198. ("Firmware is too big!\n"));
  199. release_firmware(firmware);
  200. return 1;
  201. }
  202. memcpy(rtlhal->pfirmware, firmware->data, firmware->size);
  203. fwsize = firmware->size;
  204. release_firmware(firmware);
  205. pfwheader = (struct rtl92c_firmware_header *)rtlhal->pfirmware;
  206. pfwdata = (u8 *) rtlhal->pfirmware;
  207. if (IS_FW_HEADER_EXIST(pfwheader)) {
  208. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  209. ("Firmware Version(%d), Signature(%#x),Size(%d)\n",
  210. pfwheader->version, pfwheader->signature,
  211. (uint)sizeof(struct rtl92c_firmware_header)));
  212. pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header);
  213. fwsize = fwsize - sizeof(struct rtl92c_firmware_header);
  214. }
  215. _rtl92c_enable_fw_download(hw, true);
  216. _rtl92c_write_fw(hw, version, pfwdata, fwsize);
  217. _rtl92c_enable_fw_download(hw, false);
  218. if (_rtl92c_fw_free_to_go(hw)) {
  219. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  220. ("Firmware is not ready to run!\n"));
  221. } else {
  222. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  223. ("Firmware is ready to run!\n"));
  224. }
  225. return 0;
  226. }
  227. EXPORT_SYMBOL(rtl92c_download_fw);
  228. static bool _rtl92c_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
  229. {
  230. struct rtl_priv *rtlpriv = rtl_priv(hw);
  231. u8 val_hmetfr, val_mcutst_1;
  232. bool result = false;
  233. val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
  234. val_mcutst_1 = rtl_read_byte(rtlpriv, (REG_MCUTST_1 + boxnum));
  235. if (((val_hmetfr >> boxnum) & BIT(0)) == 0 && val_mcutst_1 == 0)
  236. result = true;
  237. return result;
  238. }
  239. static void _rtl92c_fill_h2c_command(struct ieee80211_hw *hw,
  240. u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
  241. {
  242. struct rtl_priv *rtlpriv = rtl_priv(hw);
  243. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  244. u8 boxnum;
  245. u16 box_reg, box_extreg;
  246. u8 u1b_tmp;
  247. bool isfw_read = false;
  248. bool bwrite_sucess = false;
  249. u8 wait_h2c_limmit = 100;
  250. u8 wait_writeh2c_limmit = 100;
  251. u8 boxcontent[4], boxextcontent[2];
  252. u32 h2c_waitcounter = 0;
  253. unsigned long flag;
  254. u8 idx;
  255. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("come in\n"));
  256. while (true) {
  257. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  258. if (rtlhal->h2c_setinprogress) {
  259. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  260. ("H2C set in progress! Wait to set.."
  261. "element_id(%d).\n", element_id));
  262. while (rtlhal->h2c_setinprogress) {
  263. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
  264. flag);
  265. h2c_waitcounter++;
  266. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  267. ("Wait 100 us (%d times)...\n",
  268. h2c_waitcounter));
  269. udelay(100);
  270. if (h2c_waitcounter > 1000)
  271. return;
  272. spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
  273. flag);
  274. }
  275. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  276. } else {
  277. rtlhal->h2c_setinprogress = true;
  278. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  279. break;
  280. }
  281. }
  282. while (!bwrite_sucess) {
  283. wait_writeh2c_limmit--;
  284. if (wait_writeh2c_limmit == 0) {
  285. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  286. ("Write H2C fail because no trigger "
  287. "for FW INT!\n"));
  288. break;
  289. }
  290. boxnum = rtlhal->last_hmeboxnum;
  291. switch (boxnum) {
  292. case 0:
  293. box_reg = REG_HMEBOX_0;
  294. box_extreg = REG_HMEBOX_EXT_0;
  295. break;
  296. case 1:
  297. box_reg = REG_HMEBOX_1;
  298. box_extreg = REG_HMEBOX_EXT_1;
  299. break;
  300. case 2:
  301. box_reg = REG_HMEBOX_2;
  302. box_extreg = REG_HMEBOX_EXT_2;
  303. break;
  304. case 3:
  305. box_reg = REG_HMEBOX_3;
  306. box_extreg = REG_HMEBOX_EXT_3;
  307. break;
  308. default:
  309. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  310. ("switch case not process\n"));
  311. break;
  312. }
  313. isfw_read = _rtl92c_check_fw_read_last_h2c(hw, boxnum);
  314. while (!isfw_read) {
  315. wait_h2c_limmit--;
  316. if (wait_h2c_limmit == 0) {
  317. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  318. ("Wating too long for FW read "
  319. "clear HMEBox(%d)!\n", boxnum));
  320. break;
  321. }
  322. udelay(10);
  323. isfw_read = _rtl92c_check_fw_read_last_h2c(hw, boxnum);
  324. u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF);
  325. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  326. ("Wating for FW read clear HMEBox(%d)!!! "
  327. "0x1BF = %2x\n", boxnum, u1b_tmp));
  328. }
  329. if (!isfw_read) {
  330. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  331. ("Write H2C register BOX[%d] fail!!!!! "
  332. "Fw do not read.\n", boxnum));
  333. break;
  334. }
  335. memset(boxcontent, 0, sizeof(boxcontent));
  336. memset(boxextcontent, 0, sizeof(boxextcontent));
  337. boxcontent[0] = element_id;
  338. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  339. ("Write element_id box_reg(%4x) = %2x\n",
  340. box_reg, element_id));
  341. switch (cmd_len) {
  342. case 1:
  343. boxcontent[0] &= ~(BIT(7));
  344. memcpy((u8 *) (boxcontent) + 1,
  345. p_cmdbuffer, 1);
  346. for (idx = 0; idx < 4; idx++) {
  347. rtl_write_byte(rtlpriv, box_reg + idx,
  348. boxcontent[idx]);
  349. }
  350. break;
  351. case 2:
  352. boxcontent[0] &= ~(BIT(7));
  353. memcpy((u8 *) (boxcontent) + 1,
  354. p_cmdbuffer, 2);
  355. for (idx = 0; idx < 4; idx++) {
  356. rtl_write_byte(rtlpriv, box_reg + idx,
  357. boxcontent[idx]);
  358. }
  359. break;
  360. case 3:
  361. boxcontent[0] &= ~(BIT(7));
  362. memcpy((u8 *) (boxcontent) + 1,
  363. p_cmdbuffer, 3);
  364. for (idx = 0; idx < 4; idx++) {
  365. rtl_write_byte(rtlpriv, box_reg + idx,
  366. boxcontent[idx]);
  367. }
  368. break;
  369. case 4:
  370. boxcontent[0] |= (BIT(7));
  371. memcpy((u8 *) (boxextcontent),
  372. p_cmdbuffer, 2);
  373. memcpy((u8 *) (boxcontent) + 1,
  374. p_cmdbuffer + 2, 2);
  375. for (idx = 0; idx < 2; idx++) {
  376. rtl_write_byte(rtlpriv, box_extreg + idx,
  377. boxextcontent[idx]);
  378. }
  379. for (idx = 0; idx < 4; idx++) {
  380. rtl_write_byte(rtlpriv, box_reg + idx,
  381. boxcontent[idx]);
  382. }
  383. break;
  384. case 5:
  385. boxcontent[0] |= (BIT(7));
  386. memcpy((u8 *) (boxextcontent),
  387. p_cmdbuffer, 2);
  388. memcpy((u8 *) (boxcontent) + 1,
  389. p_cmdbuffer + 2, 3);
  390. for (idx = 0; idx < 2; idx++) {
  391. rtl_write_byte(rtlpriv, box_extreg + idx,
  392. boxextcontent[idx]);
  393. }
  394. for (idx = 0; idx < 4; idx++) {
  395. rtl_write_byte(rtlpriv, box_reg + idx,
  396. boxcontent[idx]);
  397. }
  398. break;
  399. default:
  400. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  401. ("switch case not process\n"));
  402. break;
  403. }
  404. bwrite_sucess = true;
  405. rtlhal->last_hmeboxnum = boxnum + 1;
  406. if (rtlhal->last_hmeboxnum == 4)
  407. rtlhal->last_hmeboxnum = 0;
  408. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  409. ("pHalData->last_hmeboxnum = %d\n",
  410. rtlhal->last_hmeboxnum));
  411. }
  412. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  413. rtlhal->h2c_setinprogress = false;
  414. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  415. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("go out\n"));
  416. }
  417. void rtl92c_fill_h2c_cmd(struct ieee80211_hw *hw,
  418. u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
  419. {
  420. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  421. u32 tmp_cmdbuf[2];
  422. if (rtlhal->fw_ready == false) {
  423. RT_ASSERT(false, ("return H2C cmd because of Fw "
  424. "download fail!!!\n"));
  425. return;
  426. }
  427. memset(tmp_cmdbuf, 0, 8);
  428. memcpy(tmp_cmdbuf, p_cmdbuffer, cmd_len);
  429. _rtl92c_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
  430. return;
  431. }
  432. EXPORT_SYMBOL(rtl92c_fill_h2c_cmd);
  433. void rtl92c_firmware_selfreset(struct ieee80211_hw *hw)
  434. {
  435. u8 u1b_tmp;
  436. u8 delay = 100;
  437. struct rtl_priv *rtlpriv = rtl_priv(hw);
  438. rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20);
  439. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  440. while (u1b_tmp & BIT(2)) {
  441. delay--;
  442. if (delay == 0) {
  443. RT_ASSERT(false, ("8051 reset fail.\n"));
  444. break;
  445. }
  446. udelay(50);
  447. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  448. }
  449. }
  450. EXPORT_SYMBOL(rtl92c_firmware_selfreset);
  451. void rtl92c_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
  452. {
  453. struct rtl_priv *rtlpriv = rtl_priv(hw);
  454. u8 u1_h2c_set_pwrmode[3] = {0};
  455. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  456. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("FW LPS mode = %d\n", mode));
  457. SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode);
  458. SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode, 1);
  459. SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
  460. ppsc->reg_max_lps_awakeintvl);
  461. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  462. "rtl92c_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode\n",
  463. u1_h2c_set_pwrmode, 3);
  464. rtl92c_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
  465. }
  466. EXPORT_SYMBOL(rtl92c_set_fw_pwrmode_cmd);
  467. #define BEACON_PG 0 /*->1*/
  468. #define PSPOLL_PG 2
  469. #define NULL_PG 3
  470. #define PROBERSP_PG 4 /*->5*/
  471. #define TOTAL_RESERVED_PKT_LEN 768
  472. static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
  473. /* page 0 beacon */
  474. 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
  475. 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  476. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
  477. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  478. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  479. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  480. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  481. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  482. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  483. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  484. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  485. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  486. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  487. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  488. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  489. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  490. /* page 1 beacon */
  491. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  492. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  493. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  494. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  495. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  496. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  497. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  498. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  499. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  500. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  501. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  502. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  503. 0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
  504. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  505. 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  506. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  507. /* page 2 ps-poll */
  508. 0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
  509. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  510. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  511. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  512. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  513. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  514. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  515. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  516. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  517. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  518. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  519. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  520. 0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  521. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  522. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  523. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  524. /* page 3 null */
  525. 0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  526. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  527. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  528. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  529. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  530. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  531. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  532. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  533. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  534. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  535. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  536. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  537. 0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  538. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  539. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  540. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  541. /* page 4 probe_resp */
  542. 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  543. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  544. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  545. 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
  546. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  547. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  548. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  549. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  550. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  551. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  552. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  553. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  554. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  555. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  556. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  557. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  558. /* page 5 probe_resp */
  559. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  560. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  561. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  562. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  563. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  564. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  565. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  566. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  567. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  568. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  569. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  570. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  571. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  572. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  573. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  574. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  575. };
  576. void rtl92c_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
  577. {
  578. struct rtl_priv *rtlpriv = rtl_priv(hw);
  579. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  580. struct sk_buff *skb = NULL;
  581. u32 totalpacketlen;
  582. bool rtstatus;
  583. u8 u1RsvdPageLoc[3] = {0};
  584. bool b_dlok = false;
  585. u8 *beacon;
  586. u8 *p_pspoll;
  587. u8 *nullfunc;
  588. u8 *p_probersp;
  589. /*---------------------------------------------------------
  590. (1) beacon
  591. ---------------------------------------------------------*/
  592. beacon = &reserved_page_packet[BEACON_PG * 128];
  593. SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
  594. SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
  595. /*-------------------------------------------------------
  596. (2) ps-poll
  597. --------------------------------------------------------*/
  598. p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
  599. SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
  600. SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
  601. SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
  602. SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
  603. /*--------------------------------------------------------
  604. (3) null data
  605. ---------------------------------------------------------*/
  606. nullfunc = &reserved_page_packet[NULL_PG * 128];
  607. SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
  608. SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
  609. SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
  610. SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
  611. /*---------------------------------------------------------
  612. (4) probe response
  613. ----------------------------------------------------------*/
  614. p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
  615. SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
  616. SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
  617. SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
  618. SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
  619. totalpacketlen = TOTAL_RESERVED_PKT_LEN;
  620. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
  621. "rtl92c_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  622. &reserved_page_packet[0], totalpacketlen);
  623. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  624. "rtl92c_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  625. u1RsvdPageLoc, 3);
  626. skb = dev_alloc_skb(totalpacketlen);
  627. memcpy((u8 *) skb_put(skb, totalpacketlen),
  628. &reserved_page_packet, totalpacketlen);
  629. rtstatus = rtlpriv->cfg->ops->cmd_send_packet(hw, skb);
  630. if (rtstatus)
  631. b_dlok = true;
  632. if (b_dlok) {
  633. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  634. ("Set RSVD page location to Fw.\n"));
  635. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  636. "H2C_RSVDPAGE:\n",
  637. u1RsvdPageLoc, 3);
  638. rtl92c_fill_h2c_cmd(hw, H2C_RSVDPAGE,
  639. sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
  640. } else
  641. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  642. ("Set RSVD page location to Fw FAIL!!!!!!.\n"));
  643. }
  644. EXPORT_SYMBOL(rtl92c_set_fw_rsvdpagepkt);
  645. void rtl92c_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
  646. {
  647. u8 u1_joinbssrpt_parm[1] = {0};
  648. SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
  649. rtl92c_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
  650. }
  651. EXPORT_SYMBOL(rtl92c_set_fw_joinbss_report_cmd);