uhci-q.c 46 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760
  1. /*
  2. * Universal Host Controller Interface driver for USB.
  3. *
  4. * Maintainer: Alan Stern <stern@rowland.harvard.edu>
  5. *
  6. * (C) Copyright 1999 Linus Torvalds
  7. * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
  8. * (C) Copyright 1999 Randy Dunlap
  9. * (C) Copyright 1999 Georg Acher, acher@in.tum.de
  10. * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
  11. * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
  12. * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
  13. * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
  14. * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
  15. * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
  16. * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
  17. */
  18. /*
  19. * Technically, updating td->status here is a race, but it's not really a
  20. * problem. The worst that can happen is that we set the IOC bit again
  21. * generating a spurious interrupt. We could fix this by creating another
  22. * QH and leaving the IOC bit always set, but then we would have to play
  23. * games with the FSBR code to make sure we get the correct order in all
  24. * the cases. I don't think it's worth the effort
  25. */
  26. static void uhci_set_next_interrupt(struct uhci_hcd *uhci)
  27. {
  28. if (uhci->is_stopped)
  29. mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
  30. uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC);
  31. }
  32. static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
  33. {
  34. uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
  35. }
  36. /*
  37. * Full-Speed Bandwidth Reclamation (FSBR).
  38. * We turn on FSBR whenever a queue that wants it is advancing,
  39. * and leave it on for a short time thereafter.
  40. */
  41. static void uhci_fsbr_on(struct uhci_hcd *uhci)
  42. {
  43. struct uhci_qh *lqh;
  44. /* The terminating skeleton QH always points back to the first
  45. * FSBR QH. Make the last async QH point to the terminating
  46. * skeleton QH. */
  47. uhci->fsbr_is_on = 1;
  48. lqh = list_entry(uhci->skel_async_qh->node.prev,
  49. struct uhci_qh, node);
  50. lqh->link = LINK_TO_QH(uhci->skel_term_qh);
  51. }
  52. static void uhci_fsbr_off(struct uhci_hcd *uhci)
  53. {
  54. struct uhci_qh *lqh;
  55. /* Remove the link from the last async QH to the terminating
  56. * skeleton QH. */
  57. uhci->fsbr_is_on = 0;
  58. lqh = list_entry(uhci->skel_async_qh->node.prev,
  59. struct uhci_qh, node);
  60. lqh->link = UHCI_PTR_TERM;
  61. }
  62. static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  63. {
  64. struct urb_priv *urbp = urb->hcpriv;
  65. if (!(urb->transfer_flags & URB_NO_FSBR))
  66. urbp->fsbr = 1;
  67. }
  68. static void uhci_urbp_wants_fsbr(struct uhci_hcd *uhci, struct urb_priv *urbp)
  69. {
  70. if (urbp->fsbr) {
  71. uhci->fsbr_is_wanted = 1;
  72. if (!uhci->fsbr_is_on)
  73. uhci_fsbr_on(uhci);
  74. else if (uhci->fsbr_expiring) {
  75. uhci->fsbr_expiring = 0;
  76. del_timer(&uhci->fsbr_timer);
  77. }
  78. }
  79. }
  80. static void uhci_fsbr_timeout(unsigned long _uhci)
  81. {
  82. struct uhci_hcd *uhci = (struct uhci_hcd *) _uhci;
  83. unsigned long flags;
  84. spin_lock_irqsave(&uhci->lock, flags);
  85. if (uhci->fsbr_expiring) {
  86. uhci->fsbr_expiring = 0;
  87. uhci_fsbr_off(uhci);
  88. }
  89. spin_unlock_irqrestore(&uhci->lock, flags);
  90. }
  91. static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci)
  92. {
  93. dma_addr_t dma_handle;
  94. struct uhci_td *td;
  95. td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
  96. if (!td)
  97. return NULL;
  98. td->dma_handle = dma_handle;
  99. td->frame = -1;
  100. INIT_LIST_HEAD(&td->list);
  101. INIT_LIST_HEAD(&td->fl_list);
  102. return td;
  103. }
  104. static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
  105. {
  106. if (!list_empty(&td->list))
  107. dev_WARN(uhci_dev(uhci), "td %p still in list!\n", td);
  108. if (!list_empty(&td->fl_list))
  109. dev_WARN(uhci_dev(uhci), "td %p still in fl_list!\n", td);
  110. dma_pool_free(uhci->td_pool, td, td->dma_handle);
  111. }
  112. static inline void uhci_fill_td(struct uhci_td *td, u32 status,
  113. u32 token, u32 buffer)
  114. {
  115. td->status = cpu_to_le32(status);
  116. td->token = cpu_to_le32(token);
  117. td->buffer = cpu_to_le32(buffer);
  118. }
  119. static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp)
  120. {
  121. list_add_tail(&td->list, &urbp->td_list);
  122. }
  123. static void uhci_remove_td_from_urbp(struct uhci_td *td)
  124. {
  125. list_del_init(&td->list);
  126. }
  127. /*
  128. * We insert Isochronous URBs directly into the frame list at the beginning
  129. */
  130. static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci,
  131. struct uhci_td *td, unsigned framenum)
  132. {
  133. framenum &= (UHCI_NUMFRAMES - 1);
  134. td->frame = framenum;
  135. /* Is there a TD already mapped there? */
  136. if (uhci->frame_cpu[framenum]) {
  137. struct uhci_td *ftd, *ltd;
  138. ftd = uhci->frame_cpu[framenum];
  139. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  140. list_add_tail(&td->fl_list, &ftd->fl_list);
  141. td->link = ltd->link;
  142. wmb();
  143. ltd->link = LINK_TO_TD(td);
  144. } else {
  145. td->link = uhci->frame[framenum];
  146. wmb();
  147. uhci->frame[framenum] = LINK_TO_TD(td);
  148. uhci->frame_cpu[framenum] = td;
  149. }
  150. }
  151. static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci,
  152. struct uhci_td *td)
  153. {
  154. /* If it's not inserted, don't remove it */
  155. if (td->frame == -1) {
  156. WARN_ON(!list_empty(&td->fl_list));
  157. return;
  158. }
  159. if (uhci->frame_cpu[td->frame] == td) {
  160. if (list_empty(&td->fl_list)) {
  161. uhci->frame[td->frame] = td->link;
  162. uhci->frame_cpu[td->frame] = NULL;
  163. } else {
  164. struct uhci_td *ntd;
  165. ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list);
  166. uhci->frame[td->frame] = LINK_TO_TD(ntd);
  167. uhci->frame_cpu[td->frame] = ntd;
  168. }
  169. } else {
  170. struct uhci_td *ptd;
  171. ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
  172. ptd->link = td->link;
  173. }
  174. list_del_init(&td->fl_list);
  175. td->frame = -1;
  176. }
  177. static inline void uhci_remove_tds_from_frame(struct uhci_hcd *uhci,
  178. unsigned int framenum)
  179. {
  180. struct uhci_td *ftd, *ltd;
  181. framenum &= (UHCI_NUMFRAMES - 1);
  182. ftd = uhci->frame_cpu[framenum];
  183. if (ftd) {
  184. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  185. uhci->frame[framenum] = ltd->link;
  186. uhci->frame_cpu[framenum] = NULL;
  187. while (!list_empty(&ftd->fl_list))
  188. list_del_init(ftd->fl_list.prev);
  189. }
  190. }
  191. /*
  192. * Remove all the TDs for an Isochronous URB from the frame list
  193. */
  194. static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb)
  195. {
  196. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  197. struct uhci_td *td;
  198. list_for_each_entry(td, &urbp->td_list, list)
  199. uhci_remove_td_from_frame_list(uhci, td);
  200. }
  201. static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci,
  202. struct usb_device *udev, struct usb_host_endpoint *hep)
  203. {
  204. dma_addr_t dma_handle;
  205. struct uhci_qh *qh;
  206. qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
  207. if (!qh)
  208. return NULL;
  209. memset(qh, 0, sizeof(*qh));
  210. qh->dma_handle = dma_handle;
  211. qh->element = UHCI_PTR_TERM;
  212. qh->link = UHCI_PTR_TERM;
  213. INIT_LIST_HEAD(&qh->queue);
  214. INIT_LIST_HEAD(&qh->node);
  215. if (udev) { /* Normal QH */
  216. qh->type = hep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  217. if (qh->type != USB_ENDPOINT_XFER_ISOC) {
  218. qh->dummy_td = uhci_alloc_td(uhci);
  219. if (!qh->dummy_td) {
  220. dma_pool_free(uhci->qh_pool, qh, dma_handle);
  221. return NULL;
  222. }
  223. }
  224. qh->state = QH_STATE_IDLE;
  225. qh->hep = hep;
  226. qh->udev = udev;
  227. hep->hcpriv = qh;
  228. if (qh->type == USB_ENDPOINT_XFER_INT ||
  229. qh->type == USB_ENDPOINT_XFER_ISOC)
  230. qh->load = usb_calc_bus_time(udev->speed,
  231. usb_endpoint_dir_in(&hep->desc),
  232. qh->type == USB_ENDPOINT_XFER_ISOC,
  233. le16_to_cpu(hep->desc.wMaxPacketSize))
  234. / 1000 + 1;
  235. } else { /* Skeleton QH */
  236. qh->state = QH_STATE_ACTIVE;
  237. qh->type = -1;
  238. }
  239. return qh;
  240. }
  241. static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  242. {
  243. WARN_ON(qh->state != QH_STATE_IDLE && qh->udev);
  244. if (!list_empty(&qh->queue))
  245. dev_WARN(uhci_dev(uhci), "qh %p list not empty!\n", qh);
  246. list_del(&qh->node);
  247. if (qh->udev) {
  248. qh->hep->hcpriv = NULL;
  249. if (qh->dummy_td)
  250. uhci_free_td(uhci, qh->dummy_td);
  251. }
  252. dma_pool_free(uhci->qh_pool, qh, qh->dma_handle);
  253. }
  254. /*
  255. * When a queue is stopped and a dequeued URB is given back, adjust
  256. * the previous TD link (if the URB isn't first on the queue) or
  257. * save its toggle value (if it is first and is currently executing).
  258. *
  259. * Returns 0 if the URB should not yet be given back, 1 otherwise.
  260. */
  261. static int uhci_cleanup_queue(struct uhci_hcd *uhci, struct uhci_qh *qh,
  262. struct urb *urb)
  263. {
  264. struct urb_priv *urbp = urb->hcpriv;
  265. struct uhci_td *td;
  266. int ret = 1;
  267. /* Isochronous pipes don't use toggles and their TD link pointers
  268. * get adjusted during uhci_urb_dequeue(). But since their queues
  269. * cannot truly be stopped, we have to watch out for dequeues
  270. * occurring after the nominal unlink frame. */
  271. if (qh->type == USB_ENDPOINT_XFER_ISOC) {
  272. ret = (uhci->frame_number + uhci->is_stopped !=
  273. qh->unlink_frame);
  274. goto done;
  275. }
  276. /* If the URB isn't first on its queue, adjust the link pointer
  277. * of the last TD in the previous URB. The toggle doesn't need
  278. * to be saved since this URB can't be executing yet. */
  279. if (qh->queue.next != &urbp->node) {
  280. struct urb_priv *purbp;
  281. struct uhci_td *ptd;
  282. purbp = list_entry(urbp->node.prev, struct urb_priv, node);
  283. WARN_ON(list_empty(&purbp->td_list));
  284. ptd = list_entry(purbp->td_list.prev, struct uhci_td,
  285. list);
  286. td = list_entry(urbp->td_list.prev, struct uhci_td,
  287. list);
  288. ptd->link = td->link;
  289. goto done;
  290. }
  291. /* If the QH element pointer is UHCI_PTR_TERM then then currently
  292. * executing URB has already been unlinked, so this one isn't it. */
  293. if (qh_element(qh) == UHCI_PTR_TERM)
  294. goto done;
  295. qh->element = UHCI_PTR_TERM;
  296. /* Control pipes don't have to worry about toggles */
  297. if (qh->type == USB_ENDPOINT_XFER_CONTROL)
  298. goto done;
  299. /* Save the next toggle value */
  300. WARN_ON(list_empty(&urbp->td_list));
  301. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  302. qh->needs_fixup = 1;
  303. qh->initial_toggle = uhci_toggle(td_token(td));
  304. done:
  305. return ret;
  306. }
  307. /*
  308. * Fix up the data toggles for URBs in a queue, when one of them
  309. * terminates early (short transfer, error, or dequeued).
  310. */
  311. static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first)
  312. {
  313. struct urb_priv *urbp = NULL;
  314. struct uhci_td *td;
  315. unsigned int toggle = qh->initial_toggle;
  316. unsigned int pipe;
  317. /* Fixups for a short transfer start with the second URB in the
  318. * queue (the short URB is the first). */
  319. if (skip_first)
  320. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  321. /* When starting with the first URB, if the QH element pointer is
  322. * still valid then we know the URB's toggles are okay. */
  323. else if (qh_element(qh) != UHCI_PTR_TERM)
  324. toggle = 2;
  325. /* Fix up the toggle for the URBs in the queue. Normally this
  326. * loop won't run more than once: When an error or short transfer
  327. * occurs, the queue usually gets emptied. */
  328. urbp = list_prepare_entry(urbp, &qh->queue, node);
  329. list_for_each_entry_continue(urbp, &qh->queue, node) {
  330. /* If the first TD has the right toggle value, we don't
  331. * need to change any toggles in this URB */
  332. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  333. if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) {
  334. td = list_entry(urbp->td_list.prev, struct uhci_td,
  335. list);
  336. toggle = uhci_toggle(td_token(td)) ^ 1;
  337. /* Otherwise all the toggles in the URB have to be switched */
  338. } else {
  339. list_for_each_entry(td, &urbp->td_list, list) {
  340. td->token ^= __constant_cpu_to_le32(
  341. TD_TOKEN_TOGGLE);
  342. toggle ^= 1;
  343. }
  344. }
  345. }
  346. wmb();
  347. pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe;
  348. usb_settoggle(qh->udev, usb_pipeendpoint(pipe),
  349. usb_pipeout(pipe), toggle);
  350. qh->needs_fixup = 0;
  351. }
  352. /*
  353. * Link an Isochronous QH into its skeleton's list
  354. */
  355. static inline void link_iso(struct uhci_hcd *uhci, struct uhci_qh *qh)
  356. {
  357. list_add_tail(&qh->node, &uhci->skel_iso_qh->node);
  358. /* Isochronous QHs aren't linked by the hardware */
  359. }
  360. /*
  361. * Link a high-period interrupt QH into the schedule at the end of its
  362. * skeleton's list
  363. */
  364. static void link_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh)
  365. {
  366. struct uhci_qh *pqh;
  367. list_add_tail(&qh->node, &uhci->skelqh[qh->skel]->node);
  368. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  369. qh->link = pqh->link;
  370. wmb();
  371. pqh->link = LINK_TO_QH(qh);
  372. }
  373. /*
  374. * Link a period-1 interrupt or async QH into the schedule at the
  375. * correct spot in the async skeleton's list, and update the FSBR link
  376. */
  377. static void link_async(struct uhci_hcd *uhci, struct uhci_qh *qh)
  378. {
  379. struct uhci_qh *pqh;
  380. __le32 link_to_new_qh;
  381. /* Find the predecessor QH for our new one and insert it in the list.
  382. * The list of QHs is expected to be short, so linear search won't
  383. * take too long. */
  384. list_for_each_entry_reverse(pqh, &uhci->skel_async_qh->node, node) {
  385. if (pqh->skel <= qh->skel)
  386. break;
  387. }
  388. list_add(&qh->node, &pqh->node);
  389. /* Link it into the schedule */
  390. qh->link = pqh->link;
  391. wmb();
  392. link_to_new_qh = LINK_TO_QH(qh);
  393. pqh->link = link_to_new_qh;
  394. /* If this is now the first FSBR QH, link the terminating skeleton
  395. * QH to it. */
  396. if (pqh->skel < SKEL_FSBR && qh->skel >= SKEL_FSBR)
  397. uhci->skel_term_qh->link = link_to_new_qh;
  398. }
  399. /*
  400. * Put a QH on the schedule in both hardware and software
  401. */
  402. static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  403. {
  404. WARN_ON(list_empty(&qh->queue));
  405. /* Set the element pointer if it isn't set already.
  406. * This isn't needed for Isochronous queues, but it doesn't hurt. */
  407. if (qh_element(qh) == UHCI_PTR_TERM) {
  408. struct urb_priv *urbp = list_entry(qh->queue.next,
  409. struct urb_priv, node);
  410. struct uhci_td *td = list_entry(urbp->td_list.next,
  411. struct uhci_td, list);
  412. qh->element = LINK_TO_TD(td);
  413. }
  414. /* Treat the queue as if it has just advanced */
  415. qh->wait_expired = 0;
  416. qh->advance_jiffies = jiffies;
  417. if (qh->state == QH_STATE_ACTIVE)
  418. return;
  419. qh->state = QH_STATE_ACTIVE;
  420. /* Move the QH from its old list to the correct spot in the appropriate
  421. * skeleton's list */
  422. if (qh == uhci->next_qh)
  423. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  424. node);
  425. list_del(&qh->node);
  426. if (qh->skel == SKEL_ISO)
  427. link_iso(uhci, qh);
  428. else if (qh->skel < SKEL_ASYNC)
  429. link_interrupt(uhci, qh);
  430. else
  431. link_async(uhci, qh);
  432. }
  433. /*
  434. * Unlink a high-period interrupt QH from the schedule
  435. */
  436. static void unlink_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh)
  437. {
  438. struct uhci_qh *pqh;
  439. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  440. pqh->link = qh->link;
  441. mb();
  442. }
  443. /*
  444. * Unlink a period-1 interrupt or async QH from the schedule
  445. */
  446. static void unlink_async(struct uhci_hcd *uhci, struct uhci_qh *qh)
  447. {
  448. struct uhci_qh *pqh;
  449. __le32 link_to_next_qh = qh->link;
  450. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  451. pqh->link = link_to_next_qh;
  452. /* If this was the old first FSBR QH, link the terminating skeleton
  453. * QH to the next (new first FSBR) QH. */
  454. if (pqh->skel < SKEL_FSBR && qh->skel >= SKEL_FSBR)
  455. uhci->skel_term_qh->link = link_to_next_qh;
  456. mb();
  457. }
  458. /*
  459. * Take a QH off the hardware schedule
  460. */
  461. static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  462. {
  463. if (qh->state == QH_STATE_UNLINKING)
  464. return;
  465. WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev);
  466. qh->state = QH_STATE_UNLINKING;
  467. /* Unlink the QH from the schedule and record when we did it */
  468. if (qh->skel == SKEL_ISO)
  469. ;
  470. else if (qh->skel < SKEL_ASYNC)
  471. unlink_interrupt(uhci, qh);
  472. else
  473. unlink_async(uhci, qh);
  474. uhci_get_current_frame_number(uhci);
  475. qh->unlink_frame = uhci->frame_number;
  476. /* Force an interrupt so we know when the QH is fully unlinked */
  477. if (list_empty(&uhci->skel_unlink_qh->node))
  478. uhci_set_next_interrupt(uhci);
  479. /* Move the QH from its old list to the end of the unlinking list */
  480. if (qh == uhci->next_qh)
  481. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  482. node);
  483. list_move_tail(&qh->node, &uhci->skel_unlink_qh->node);
  484. }
  485. /*
  486. * When we and the controller are through with a QH, it becomes IDLE.
  487. * This happens when a QH has been off the schedule (on the unlinking
  488. * list) for more than one frame, or when an error occurs while adding
  489. * the first URB onto a new QH.
  490. */
  491. static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh)
  492. {
  493. WARN_ON(qh->state == QH_STATE_ACTIVE);
  494. if (qh == uhci->next_qh)
  495. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  496. node);
  497. list_move(&qh->node, &uhci->idle_qh_list);
  498. qh->state = QH_STATE_IDLE;
  499. /* Now that the QH is idle, its post_td isn't being used */
  500. if (qh->post_td) {
  501. uhci_free_td(uhci, qh->post_td);
  502. qh->post_td = NULL;
  503. }
  504. /* If anyone is waiting for a QH to become idle, wake them up */
  505. if (uhci->num_waiting)
  506. wake_up_all(&uhci->waitqh);
  507. }
  508. /*
  509. * Find the highest existing bandwidth load for a given phase and period.
  510. */
  511. static int uhci_highest_load(struct uhci_hcd *uhci, int phase, int period)
  512. {
  513. int highest_load = uhci->load[phase];
  514. for (phase += period; phase < MAX_PHASE; phase += period)
  515. highest_load = max_t(int, highest_load, uhci->load[phase]);
  516. return highest_load;
  517. }
  518. /*
  519. * Set qh->phase to the optimal phase for a periodic transfer and
  520. * check whether the bandwidth requirement is acceptable.
  521. */
  522. static int uhci_check_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  523. {
  524. int minimax_load;
  525. /* Find the optimal phase (unless it is already set) and get
  526. * its load value. */
  527. if (qh->phase >= 0)
  528. minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
  529. else {
  530. int phase, load;
  531. int max_phase = min_t(int, MAX_PHASE, qh->period);
  532. qh->phase = 0;
  533. minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
  534. for (phase = 1; phase < max_phase; ++phase) {
  535. load = uhci_highest_load(uhci, phase, qh->period);
  536. if (load < minimax_load) {
  537. minimax_load = load;
  538. qh->phase = phase;
  539. }
  540. }
  541. }
  542. /* Maximum allowable periodic bandwidth is 90%, or 900 us per frame */
  543. if (minimax_load + qh->load > 900) {
  544. dev_dbg(uhci_dev(uhci), "bandwidth allocation failed: "
  545. "period %d, phase %d, %d + %d us\n",
  546. qh->period, qh->phase, minimax_load, qh->load);
  547. return -ENOSPC;
  548. }
  549. return 0;
  550. }
  551. /*
  552. * Reserve a periodic QH's bandwidth in the schedule
  553. */
  554. static void uhci_reserve_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  555. {
  556. int i;
  557. int load = qh->load;
  558. char *p = "??";
  559. for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
  560. uhci->load[i] += load;
  561. uhci->total_load += load;
  562. }
  563. uhci_to_hcd(uhci)->self.bandwidth_allocated =
  564. uhci->total_load / MAX_PHASE;
  565. switch (qh->type) {
  566. case USB_ENDPOINT_XFER_INT:
  567. ++uhci_to_hcd(uhci)->self.bandwidth_int_reqs;
  568. p = "INT";
  569. break;
  570. case USB_ENDPOINT_XFER_ISOC:
  571. ++uhci_to_hcd(uhci)->self.bandwidth_isoc_reqs;
  572. p = "ISO";
  573. break;
  574. }
  575. qh->bandwidth_reserved = 1;
  576. dev_dbg(uhci_dev(uhci),
  577. "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
  578. "reserve", qh->udev->devnum,
  579. qh->hep->desc.bEndpointAddress, p,
  580. qh->period, qh->phase, load);
  581. }
  582. /*
  583. * Release a periodic QH's bandwidth reservation
  584. */
  585. static void uhci_release_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  586. {
  587. int i;
  588. int load = qh->load;
  589. char *p = "??";
  590. for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
  591. uhci->load[i] -= load;
  592. uhci->total_load -= load;
  593. }
  594. uhci_to_hcd(uhci)->self.bandwidth_allocated =
  595. uhci->total_load / MAX_PHASE;
  596. switch (qh->type) {
  597. case USB_ENDPOINT_XFER_INT:
  598. --uhci_to_hcd(uhci)->self.bandwidth_int_reqs;
  599. p = "INT";
  600. break;
  601. case USB_ENDPOINT_XFER_ISOC:
  602. --uhci_to_hcd(uhci)->self.bandwidth_isoc_reqs;
  603. p = "ISO";
  604. break;
  605. }
  606. qh->bandwidth_reserved = 0;
  607. dev_dbg(uhci_dev(uhci),
  608. "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
  609. "release", qh->udev->devnum,
  610. qh->hep->desc.bEndpointAddress, p,
  611. qh->period, qh->phase, load);
  612. }
  613. static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci,
  614. struct urb *urb)
  615. {
  616. struct urb_priv *urbp;
  617. urbp = kmem_cache_zalloc(uhci_up_cachep, GFP_ATOMIC);
  618. if (!urbp)
  619. return NULL;
  620. urbp->urb = urb;
  621. urb->hcpriv = urbp;
  622. INIT_LIST_HEAD(&urbp->node);
  623. INIT_LIST_HEAD(&urbp->td_list);
  624. return urbp;
  625. }
  626. static void uhci_free_urb_priv(struct uhci_hcd *uhci,
  627. struct urb_priv *urbp)
  628. {
  629. struct uhci_td *td, *tmp;
  630. if (!list_empty(&urbp->node))
  631. dev_WARN(uhci_dev(uhci), "urb %p still on QH's list!\n",
  632. urbp->urb);
  633. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  634. uhci_remove_td_from_urbp(td);
  635. uhci_free_td(uhci, td);
  636. }
  637. kmem_cache_free(uhci_up_cachep, urbp);
  638. }
  639. /*
  640. * Map status to standard result codes
  641. *
  642. * <status> is (td_status(td) & 0xF60000), a.k.a.
  643. * uhci_status_bits(td_status(td)).
  644. * Note: <status> does not include the TD_CTRL_NAK bit.
  645. * <dir_out> is True for output TDs and False for input TDs.
  646. */
  647. static int uhci_map_status(int status, int dir_out)
  648. {
  649. if (!status)
  650. return 0;
  651. if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */
  652. return -EPROTO;
  653. if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */
  654. if (dir_out)
  655. return -EPROTO;
  656. else
  657. return -EILSEQ;
  658. }
  659. if (status & TD_CTRL_BABBLE) /* Babble */
  660. return -EOVERFLOW;
  661. if (status & TD_CTRL_DBUFERR) /* Buffer error */
  662. return -ENOSR;
  663. if (status & TD_CTRL_STALLED) /* Stalled */
  664. return -EPIPE;
  665. return 0;
  666. }
  667. /*
  668. * Control transfers
  669. */
  670. static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb,
  671. struct uhci_qh *qh)
  672. {
  673. struct uhci_td *td;
  674. unsigned long destination, status;
  675. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  676. int len = urb->transfer_buffer_length;
  677. dma_addr_t data = urb->transfer_dma;
  678. __le32 *plink;
  679. struct urb_priv *urbp = urb->hcpriv;
  680. int skel;
  681. /* The "pipe" thing contains the destination in bits 8--18 */
  682. destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;
  683. /* 3 errors, dummy TD remains inactive */
  684. status = uhci_maxerr(3);
  685. if (urb->dev->speed == USB_SPEED_LOW)
  686. status |= TD_CTRL_LS;
  687. /*
  688. * Build the TD for the control request setup packet
  689. */
  690. td = qh->dummy_td;
  691. uhci_add_td_to_urbp(td, urbp);
  692. uhci_fill_td(td, status, destination | uhci_explen(8),
  693. urb->setup_dma);
  694. plink = &td->link;
  695. status |= TD_CTRL_ACTIVE;
  696. /*
  697. * If direction is "send", change the packet ID from SETUP (0x2D)
  698. * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
  699. * set Short Packet Detect (SPD) for all data packets.
  700. *
  701. * 0-length transfers always get treated as "send".
  702. */
  703. if (usb_pipeout(urb->pipe) || len == 0)
  704. destination ^= (USB_PID_SETUP ^ USB_PID_OUT);
  705. else {
  706. destination ^= (USB_PID_SETUP ^ USB_PID_IN);
  707. status |= TD_CTRL_SPD;
  708. }
  709. /*
  710. * Build the DATA TDs
  711. */
  712. while (len > 0) {
  713. int pktsze = maxsze;
  714. if (len <= pktsze) { /* The last data packet */
  715. pktsze = len;
  716. status &= ~TD_CTRL_SPD;
  717. }
  718. td = uhci_alloc_td(uhci);
  719. if (!td)
  720. goto nomem;
  721. *plink = LINK_TO_TD(td);
  722. /* Alternate Data0/1 (start with Data1) */
  723. destination ^= TD_TOKEN_TOGGLE;
  724. uhci_add_td_to_urbp(td, urbp);
  725. uhci_fill_td(td, status, destination | uhci_explen(pktsze),
  726. data);
  727. plink = &td->link;
  728. data += pktsze;
  729. len -= pktsze;
  730. }
  731. /*
  732. * Build the final TD for control status
  733. */
  734. td = uhci_alloc_td(uhci);
  735. if (!td)
  736. goto nomem;
  737. *plink = LINK_TO_TD(td);
  738. /* Change direction for the status transaction */
  739. destination ^= (USB_PID_IN ^ USB_PID_OUT);
  740. destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
  741. uhci_add_td_to_urbp(td, urbp);
  742. uhci_fill_td(td, status | TD_CTRL_IOC,
  743. destination | uhci_explen(0), 0);
  744. plink = &td->link;
  745. /*
  746. * Build the new dummy TD and activate the old one
  747. */
  748. td = uhci_alloc_td(uhci);
  749. if (!td)
  750. goto nomem;
  751. *plink = LINK_TO_TD(td);
  752. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  753. wmb();
  754. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  755. qh->dummy_td = td;
  756. /* Low-speed transfers get a different queue, and won't hog the bus.
  757. * Also, some devices enumerate better without FSBR; the easiest way
  758. * to do that is to put URBs on the low-speed queue while the device
  759. * isn't in the CONFIGURED state. */
  760. if (urb->dev->speed == USB_SPEED_LOW ||
  761. urb->dev->state != USB_STATE_CONFIGURED)
  762. skel = SKEL_LS_CONTROL;
  763. else {
  764. skel = SKEL_FS_CONTROL;
  765. uhci_add_fsbr(uhci, urb);
  766. }
  767. if (qh->state != QH_STATE_ACTIVE)
  768. qh->skel = skel;
  769. urb->actual_length = -8; /* Account for the SETUP packet */
  770. return 0;
  771. nomem:
  772. /* Remove the dummy TD from the td_list so it doesn't get freed */
  773. uhci_remove_td_from_urbp(qh->dummy_td);
  774. return -ENOMEM;
  775. }
  776. /*
  777. * Common submit for bulk and interrupt
  778. */
  779. static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb,
  780. struct uhci_qh *qh)
  781. {
  782. struct uhci_td *td;
  783. unsigned long destination, status;
  784. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  785. int len = urb->transfer_buffer_length;
  786. dma_addr_t data = urb->transfer_dma;
  787. __le32 *plink;
  788. struct urb_priv *urbp = urb->hcpriv;
  789. unsigned int toggle;
  790. if (len < 0)
  791. return -EINVAL;
  792. /* The "pipe" thing contains the destination in bits 8--18 */
  793. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  794. toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  795. usb_pipeout(urb->pipe));
  796. /* 3 errors, dummy TD remains inactive */
  797. status = uhci_maxerr(3);
  798. if (urb->dev->speed == USB_SPEED_LOW)
  799. status |= TD_CTRL_LS;
  800. if (usb_pipein(urb->pipe))
  801. status |= TD_CTRL_SPD;
  802. /*
  803. * Build the DATA TDs
  804. */
  805. plink = NULL;
  806. td = qh->dummy_td;
  807. do { /* Allow zero length packets */
  808. int pktsze = maxsze;
  809. if (len <= pktsze) { /* The last packet */
  810. pktsze = len;
  811. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  812. status &= ~TD_CTRL_SPD;
  813. }
  814. if (plink) {
  815. td = uhci_alloc_td(uhci);
  816. if (!td)
  817. goto nomem;
  818. *plink = LINK_TO_TD(td);
  819. }
  820. uhci_add_td_to_urbp(td, urbp);
  821. uhci_fill_td(td, status,
  822. destination | uhci_explen(pktsze) |
  823. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  824. data);
  825. plink = &td->link;
  826. status |= TD_CTRL_ACTIVE;
  827. data += pktsze;
  828. len -= maxsze;
  829. toggle ^= 1;
  830. } while (len > 0);
  831. /*
  832. * URB_ZERO_PACKET means adding a 0-length packet, if direction
  833. * is OUT and the transfer_length was an exact multiple of maxsze,
  834. * hence (len = transfer_length - N * maxsze) == 0
  835. * however, if transfer_length == 0, the zero packet was already
  836. * prepared above.
  837. */
  838. if ((urb->transfer_flags & URB_ZERO_PACKET) &&
  839. usb_pipeout(urb->pipe) && len == 0 &&
  840. urb->transfer_buffer_length > 0) {
  841. td = uhci_alloc_td(uhci);
  842. if (!td)
  843. goto nomem;
  844. *plink = LINK_TO_TD(td);
  845. uhci_add_td_to_urbp(td, urbp);
  846. uhci_fill_td(td, status,
  847. destination | uhci_explen(0) |
  848. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  849. data);
  850. plink = &td->link;
  851. toggle ^= 1;
  852. }
  853. /* Set the interrupt-on-completion flag on the last packet.
  854. * A more-or-less typical 4 KB URB (= size of one memory page)
  855. * will require about 3 ms to transfer; that's a little on the
  856. * fast side but not enough to justify delaying an interrupt
  857. * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
  858. * flag setting. */
  859. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  860. /*
  861. * Build the new dummy TD and activate the old one
  862. */
  863. td = uhci_alloc_td(uhci);
  864. if (!td)
  865. goto nomem;
  866. *plink = LINK_TO_TD(td);
  867. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  868. wmb();
  869. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  870. qh->dummy_td = td;
  871. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  872. usb_pipeout(urb->pipe), toggle);
  873. return 0;
  874. nomem:
  875. /* Remove the dummy TD from the td_list so it doesn't get freed */
  876. uhci_remove_td_from_urbp(qh->dummy_td);
  877. return -ENOMEM;
  878. }
  879. static int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb,
  880. struct uhci_qh *qh)
  881. {
  882. int ret;
  883. /* Can't have low-speed bulk transfers */
  884. if (urb->dev->speed == USB_SPEED_LOW)
  885. return -EINVAL;
  886. if (qh->state != QH_STATE_ACTIVE)
  887. qh->skel = SKEL_BULK;
  888. ret = uhci_submit_common(uhci, urb, qh);
  889. if (ret == 0)
  890. uhci_add_fsbr(uhci, urb);
  891. return ret;
  892. }
  893. static int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb,
  894. struct uhci_qh *qh)
  895. {
  896. int ret;
  897. /* USB 1.1 interrupt transfers only involve one packet per interval.
  898. * Drivers can submit URBs of any length, but longer ones will need
  899. * multiple intervals to complete.
  900. */
  901. if (!qh->bandwidth_reserved) {
  902. int exponent;
  903. /* Figure out which power-of-two queue to use */
  904. for (exponent = 7; exponent >= 0; --exponent) {
  905. if ((1 << exponent) <= urb->interval)
  906. break;
  907. }
  908. if (exponent < 0)
  909. return -EINVAL;
  910. qh->period = 1 << exponent;
  911. qh->skel = SKEL_INDEX(exponent);
  912. /* For now, interrupt phase is fixed by the layout
  913. * of the QH lists. */
  914. qh->phase = (qh->period / 2) & (MAX_PHASE - 1);
  915. ret = uhci_check_bandwidth(uhci, qh);
  916. if (ret)
  917. return ret;
  918. } else if (qh->period > urb->interval)
  919. return -EINVAL; /* Can't decrease the period */
  920. ret = uhci_submit_common(uhci, urb, qh);
  921. if (ret == 0) {
  922. urb->interval = qh->period;
  923. if (!qh->bandwidth_reserved)
  924. uhci_reserve_bandwidth(uhci, qh);
  925. }
  926. return ret;
  927. }
  928. /*
  929. * Fix up the data structures following a short transfer
  930. */
  931. static int uhci_fixup_short_transfer(struct uhci_hcd *uhci,
  932. struct uhci_qh *qh, struct urb_priv *urbp)
  933. {
  934. struct uhci_td *td;
  935. struct list_head *tmp;
  936. int ret;
  937. td = list_entry(urbp->td_list.prev, struct uhci_td, list);
  938. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  939. /* When a control transfer is short, we have to restart
  940. * the queue at the status stage transaction, which is
  941. * the last TD. */
  942. WARN_ON(list_empty(&urbp->td_list));
  943. qh->element = LINK_TO_TD(td);
  944. tmp = td->list.prev;
  945. ret = -EINPROGRESS;
  946. } else {
  947. /* When a bulk/interrupt transfer is short, we have to
  948. * fix up the toggles of the following URBs on the queue
  949. * before restarting the queue at the next URB. */
  950. qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1;
  951. uhci_fixup_toggles(qh, 1);
  952. if (list_empty(&urbp->td_list))
  953. td = qh->post_td;
  954. qh->element = td->link;
  955. tmp = urbp->td_list.prev;
  956. ret = 0;
  957. }
  958. /* Remove all the TDs we skipped over, from tmp back to the start */
  959. while (tmp != &urbp->td_list) {
  960. td = list_entry(tmp, struct uhci_td, list);
  961. tmp = tmp->prev;
  962. uhci_remove_td_from_urbp(td);
  963. uhci_free_td(uhci, td);
  964. }
  965. return ret;
  966. }
  967. /*
  968. * Common result for control, bulk, and interrupt
  969. */
  970. static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
  971. {
  972. struct urb_priv *urbp = urb->hcpriv;
  973. struct uhci_qh *qh = urbp->qh;
  974. struct uhci_td *td, *tmp;
  975. unsigned status;
  976. int ret = 0;
  977. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  978. unsigned int ctrlstat;
  979. int len;
  980. ctrlstat = td_status(td);
  981. status = uhci_status_bits(ctrlstat);
  982. if (status & TD_CTRL_ACTIVE)
  983. return -EINPROGRESS;
  984. len = uhci_actual_length(ctrlstat);
  985. urb->actual_length += len;
  986. if (status) {
  987. ret = uhci_map_status(status,
  988. uhci_packetout(td_token(td)));
  989. if ((debug == 1 && ret != -EPIPE) || debug > 1) {
  990. /* Some debugging code */
  991. dev_dbg(&urb->dev->dev,
  992. "%s: failed with status %x\n",
  993. __func__, status);
  994. if (debug > 1 && errbuf) {
  995. /* Print the chain for debugging */
  996. uhci_show_qh(uhci, urbp->qh, errbuf,
  997. ERRBUF_LEN, 0);
  998. lprintk(errbuf);
  999. }
  1000. }
  1001. /* Did we receive a short packet? */
  1002. } else if (len < uhci_expected_length(td_token(td))) {
  1003. /* For control transfers, go to the status TD if
  1004. * this isn't already the last data TD */
  1005. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  1006. if (td->list.next != urbp->td_list.prev)
  1007. ret = 1;
  1008. }
  1009. /* For bulk and interrupt, this may be an error */
  1010. else if (urb->transfer_flags & URB_SHORT_NOT_OK)
  1011. ret = -EREMOTEIO;
  1012. /* Fixup needed only if this isn't the URB's last TD */
  1013. else if (&td->list != urbp->td_list.prev)
  1014. ret = 1;
  1015. }
  1016. uhci_remove_td_from_urbp(td);
  1017. if (qh->post_td)
  1018. uhci_free_td(uhci, qh->post_td);
  1019. qh->post_td = td;
  1020. if (ret != 0)
  1021. goto err;
  1022. }
  1023. return ret;
  1024. err:
  1025. if (ret < 0) {
  1026. /* Note that the queue has stopped and save
  1027. * the next toggle value */
  1028. qh->element = UHCI_PTR_TERM;
  1029. qh->is_stopped = 1;
  1030. qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL);
  1031. qh->initial_toggle = uhci_toggle(td_token(td)) ^
  1032. (ret == -EREMOTEIO);
  1033. } else /* Short packet received */
  1034. ret = uhci_fixup_short_transfer(uhci, qh, urbp);
  1035. return ret;
  1036. }
  1037. /*
  1038. * Isochronous transfers
  1039. */
  1040. static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb,
  1041. struct uhci_qh *qh)
  1042. {
  1043. struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */
  1044. int i, frame;
  1045. unsigned long destination, status;
  1046. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  1047. /* Values must not be too big (could overflow below) */
  1048. if (urb->interval >= UHCI_NUMFRAMES ||
  1049. urb->number_of_packets >= UHCI_NUMFRAMES)
  1050. return -EFBIG;
  1051. /* Check the period and figure out the starting frame number */
  1052. if (!qh->bandwidth_reserved) {
  1053. qh->period = urb->interval;
  1054. if (urb->transfer_flags & URB_ISO_ASAP) {
  1055. qh->phase = -1; /* Find the best phase */
  1056. i = uhci_check_bandwidth(uhci, qh);
  1057. if (i)
  1058. return i;
  1059. /* Allow a little time to allocate the TDs */
  1060. uhci_get_current_frame_number(uhci);
  1061. frame = uhci->frame_number + 10;
  1062. /* Move forward to the first frame having the
  1063. * correct phase */
  1064. urb->start_frame = frame + ((qh->phase - frame) &
  1065. (qh->period - 1));
  1066. } else {
  1067. i = urb->start_frame - uhci->last_iso_frame;
  1068. if (i <= 0 || i >= UHCI_NUMFRAMES)
  1069. return -EINVAL;
  1070. qh->phase = urb->start_frame & (qh->period - 1);
  1071. i = uhci_check_bandwidth(uhci, qh);
  1072. if (i)
  1073. return i;
  1074. }
  1075. } else if (qh->period != urb->interval) {
  1076. return -EINVAL; /* Can't change the period */
  1077. } else {
  1078. /* Find the next unused frame */
  1079. if (list_empty(&qh->queue)) {
  1080. frame = qh->iso_frame;
  1081. } else {
  1082. struct urb *lurb;
  1083. lurb = list_entry(qh->queue.prev,
  1084. struct urb_priv, node)->urb;
  1085. frame = lurb->start_frame +
  1086. lurb->number_of_packets *
  1087. lurb->interval;
  1088. }
  1089. if (urb->transfer_flags & URB_ISO_ASAP) {
  1090. /* Skip some frames if necessary to insure
  1091. * the start frame is in the future.
  1092. */
  1093. uhci_get_current_frame_number(uhci);
  1094. if (uhci_frame_before_eq(frame, uhci->frame_number)) {
  1095. frame = uhci->frame_number + 1;
  1096. frame += ((qh->phase - frame) &
  1097. (qh->period - 1));
  1098. }
  1099. } /* Otherwise pick up where the last URB leaves off */
  1100. urb->start_frame = frame;
  1101. }
  1102. /* Make sure we won't have to go too far into the future */
  1103. if (uhci_frame_before_eq(uhci->last_iso_frame + UHCI_NUMFRAMES,
  1104. urb->start_frame + urb->number_of_packets *
  1105. urb->interval))
  1106. return -EFBIG;
  1107. status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
  1108. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  1109. for (i = 0; i < urb->number_of_packets; i++) {
  1110. td = uhci_alloc_td(uhci);
  1111. if (!td)
  1112. return -ENOMEM;
  1113. uhci_add_td_to_urbp(td, urbp);
  1114. uhci_fill_td(td, status, destination |
  1115. uhci_explen(urb->iso_frame_desc[i].length),
  1116. urb->transfer_dma +
  1117. urb->iso_frame_desc[i].offset);
  1118. }
  1119. /* Set the interrupt-on-completion flag on the last packet. */
  1120. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  1121. /* Add the TDs to the frame list */
  1122. frame = urb->start_frame;
  1123. list_for_each_entry(td, &urbp->td_list, list) {
  1124. uhci_insert_td_in_frame_list(uhci, td, frame);
  1125. frame += qh->period;
  1126. }
  1127. if (list_empty(&qh->queue)) {
  1128. qh->iso_packet_desc = &urb->iso_frame_desc[0];
  1129. qh->iso_frame = urb->start_frame;
  1130. }
  1131. qh->skel = SKEL_ISO;
  1132. if (!qh->bandwidth_reserved)
  1133. uhci_reserve_bandwidth(uhci, qh);
  1134. return 0;
  1135. }
  1136. static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
  1137. {
  1138. struct uhci_td *td, *tmp;
  1139. struct urb_priv *urbp = urb->hcpriv;
  1140. struct uhci_qh *qh = urbp->qh;
  1141. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  1142. unsigned int ctrlstat;
  1143. int status;
  1144. int actlength;
  1145. if (uhci_frame_before_eq(uhci->cur_iso_frame, qh->iso_frame))
  1146. return -EINPROGRESS;
  1147. uhci_remove_tds_from_frame(uhci, qh->iso_frame);
  1148. ctrlstat = td_status(td);
  1149. if (ctrlstat & TD_CTRL_ACTIVE) {
  1150. status = -EXDEV; /* TD was added too late? */
  1151. } else {
  1152. status = uhci_map_status(uhci_status_bits(ctrlstat),
  1153. usb_pipeout(urb->pipe));
  1154. actlength = uhci_actual_length(ctrlstat);
  1155. urb->actual_length += actlength;
  1156. qh->iso_packet_desc->actual_length = actlength;
  1157. qh->iso_packet_desc->status = status;
  1158. }
  1159. if (status)
  1160. urb->error_count++;
  1161. uhci_remove_td_from_urbp(td);
  1162. uhci_free_td(uhci, td);
  1163. qh->iso_frame += qh->period;
  1164. ++qh->iso_packet_desc;
  1165. }
  1166. return 0;
  1167. }
  1168. static int uhci_urb_enqueue(struct usb_hcd *hcd,
  1169. struct urb *urb, gfp_t mem_flags)
  1170. {
  1171. int ret;
  1172. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1173. unsigned long flags;
  1174. struct urb_priv *urbp;
  1175. struct uhci_qh *qh;
  1176. spin_lock_irqsave(&uhci->lock, flags);
  1177. ret = usb_hcd_link_urb_to_ep(hcd, urb);
  1178. if (ret)
  1179. goto done_not_linked;
  1180. ret = -ENOMEM;
  1181. urbp = uhci_alloc_urb_priv(uhci, urb);
  1182. if (!urbp)
  1183. goto done;
  1184. if (urb->ep->hcpriv)
  1185. qh = urb->ep->hcpriv;
  1186. else {
  1187. qh = uhci_alloc_qh(uhci, urb->dev, urb->ep);
  1188. if (!qh)
  1189. goto err_no_qh;
  1190. }
  1191. urbp->qh = qh;
  1192. switch (qh->type) {
  1193. case USB_ENDPOINT_XFER_CONTROL:
  1194. ret = uhci_submit_control(uhci, urb, qh);
  1195. break;
  1196. case USB_ENDPOINT_XFER_BULK:
  1197. ret = uhci_submit_bulk(uhci, urb, qh);
  1198. break;
  1199. case USB_ENDPOINT_XFER_INT:
  1200. ret = uhci_submit_interrupt(uhci, urb, qh);
  1201. break;
  1202. case USB_ENDPOINT_XFER_ISOC:
  1203. urb->error_count = 0;
  1204. ret = uhci_submit_isochronous(uhci, urb, qh);
  1205. break;
  1206. }
  1207. if (ret != 0)
  1208. goto err_submit_failed;
  1209. /* Add this URB to the QH */
  1210. urbp->qh = qh;
  1211. list_add_tail(&urbp->node, &qh->queue);
  1212. /* If the new URB is the first and only one on this QH then either
  1213. * the QH is new and idle or else it's unlinked and waiting to
  1214. * become idle, so we can activate it right away. But only if the
  1215. * queue isn't stopped. */
  1216. if (qh->queue.next == &urbp->node && !qh->is_stopped) {
  1217. uhci_activate_qh(uhci, qh);
  1218. uhci_urbp_wants_fsbr(uhci, urbp);
  1219. }
  1220. goto done;
  1221. err_submit_failed:
  1222. if (qh->state == QH_STATE_IDLE)
  1223. uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */
  1224. err_no_qh:
  1225. uhci_free_urb_priv(uhci, urbp);
  1226. done:
  1227. if (ret)
  1228. usb_hcd_unlink_urb_from_ep(hcd, urb);
  1229. done_not_linked:
  1230. spin_unlock_irqrestore(&uhci->lock, flags);
  1231. return ret;
  1232. }
  1233. static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  1234. {
  1235. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1236. unsigned long flags;
  1237. struct uhci_qh *qh;
  1238. int rc;
  1239. spin_lock_irqsave(&uhci->lock, flags);
  1240. rc = usb_hcd_check_unlink_urb(hcd, urb, status);
  1241. if (rc)
  1242. goto done;
  1243. qh = ((struct urb_priv *) urb->hcpriv)->qh;
  1244. /* Remove Isochronous TDs from the frame list ASAP */
  1245. if (qh->type == USB_ENDPOINT_XFER_ISOC) {
  1246. uhci_unlink_isochronous_tds(uhci, urb);
  1247. mb();
  1248. /* If the URB has already started, update the QH unlink time */
  1249. uhci_get_current_frame_number(uhci);
  1250. if (uhci_frame_before_eq(urb->start_frame, uhci->frame_number))
  1251. qh->unlink_frame = uhci->frame_number;
  1252. }
  1253. uhci_unlink_qh(uhci, qh);
  1254. done:
  1255. spin_unlock_irqrestore(&uhci->lock, flags);
  1256. return rc;
  1257. }
  1258. /*
  1259. * Finish unlinking an URB and give it back
  1260. */
  1261. static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh,
  1262. struct urb *urb, int status)
  1263. __releases(uhci->lock)
  1264. __acquires(uhci->lock)
  1265. {
  1266. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  1267. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  1268. /* urb->actual_length < 0 means the setup transaction didn't
  1269. * complete successfully. Either it failed or the URB was
  1270. * unlinked first. Regardless, don't confuse people with a
  1271. * negative length. */
  1272. urb->actual_length = max(urb->actual_length, 0);
  1273. }
  1274. /* When giving back the first URB in an Isochronous queue,
  1275. * reinitialize the QH's iso-related members for the next URB. */
  1276. else if (qh->type == USB_ENDPOINT_XFER_ISOC &&
  1277. urbp->node.prev == &qh->queue &&
  1278. urbp->node.next != &qh->queue) {
  1279. struct urb *nurb = list_entry(urbp->node.next,
  1280. struct urb_priv, node)->urb;
  1281. qh->iso_packet_desc = &nurb->iso_frame_desc[0];
  1282. qh->iso_frame = nurb->start_frame;
  1283. }
  1284. /* Take the URB off the QH's queue. If the queue is now empty,
  1285. * this is a perfect time for a toggle fixup. */
  1286. list_del_init(&urbp->node);
  1287. if (list_empty(&qh->queue) && qh->needs_fixup) {
  1288. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  1289. usb_pipeout(urb->pipe), qh->initial_toggle);
  1290. qh->needs_fixup = 0;
  1291. }
  1292. uhci_free_urb_priv(uhci, urbp);
  1293. usb_hcd_unlink_urb_from_ep(uhci_to_hcd(uhci), urb);
  1294. spin_unlock(&uhci->lock);
  1295. usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb, status);
  1296. spin_lock(&uhci->lock);
  1297. /* If the queue is now empty, we can unlink the QH and give up its
  1298. * reserved bandwidth. */
  1299. if (list_empty(&qh->queue)) {
  1300. uhci_unlink_qh(uhci, qh);
  1301. if (qh->bandwidth_reserved)
  1302. uhci_release_bandwidth(uhci, qh);
  1303. }
  1304. }
  1305. /*
  1306. * Scan the URBs in a QH's queue
  1307. */
  1308. #define QH_FINISHED_UNLINKING(qh) \
  1309. (qh->state == QH_STATE_UNLINKING && \
  1310. uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
  1311. static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1312. {
  1313. struct urb_priv *urbp;
  1314. struct urb *urb;
  1315. int status;
  1316. while (!list_empty(&qh->queue)) {
  1317. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1318. urb = urbp->urb;
  1319. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1320. status = uhci_result_isochronous(uhci, urb);
  1321. else
  1322. status = uhci_result_common(uhci, urb);
  1323. if (status == -EINPROGRESS)
  1324. break;
  1325. /* Dequeued but completed URBs can't be given back unless
  1326. * the QH is stopped or has finished unlinking. */
  1327. if (urb->unlinked) {
  1328. if (QH_FINISHED_UNLINKING(qh))
  1329. qh->is_stopped = 1;
  1330. else if (!qh->is_stopped)
  1331. return;
  1332. }
  1333. uhci_giveback_urb(uhci, qh, urb, status);
  1334. if (status < 0)
  1335. break;
  1336. }
  1337. /* If the QH is neither stopped nor finished unlinking (normal case),
  1338. * our work here is done. */
  1339. if (QH_FINISHED_UNLINKING(qh))
  1340. qh->is_stopped = 1;
  1341. else if (!qh->is_stopped)
  1342. return;
  1343. /* Otherwise give back each of the dequeued URBs */
  1344. restart:
  1345. list_for_each_entry(urbp, &qh->queue, node) {
  1346. urb = urbp->urb;
  1347. if (urb->unlinked) {
  1348. /* Fix up the TD links and save the toggles for
  1349. * non-Isochronous queues. For Isochronous queues,
  1350. * test for too-recent dequeues. */
  1351. if (!uhci_cleanup_queue(uhci, qh, urb)) {
  1352. qh->is_stopped = 0;
  1353. return;
  1354. }
  1355. uhci_giveback_urb(uhci, qh, urb, 0);
  1356. goto restart;
  1357. }
  1358. }
  1359. qh->is_stopped = 0;
  1360. /* There are no more dequeued URBs. If there are still URBs on the
  1361. * queue, the QH can now be re-activated. */
  1362. if (!list_empty(&qh->queue)) {
  1363. if (qh->needs_fixup)
  1364. uhci_fixup_toggles(qh, 0);
  1365. /* If the first URB on the queue wants FSBR but its time
  1366. * limit has expired, set the next TD to interrupt on
  1367. * completion before reactivating the QH. */
  1368. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1369. if (urbp->fsbr && qh->wait_expired) {
  1370. struct uhci_td *td = list_entry(urbp->td_list.next,
  1371. struct uhci_td, list);
  1372. td->status |= __cpu_to_le32(TD_CTRL_IOC);
  1373. }
  1374. uhci_activate_qh(uhci, qh);
  1375. }
  1376. /* The queue is empty. The QH can become idle if it is fully
  1377. * unlinked. */
  1378. else if (QH_FINISHED_UNLINKING(qh))
  1379. uhci_make_qh_idle(uhci, qh);
  1380. }
  1381. /*
  1382. * Check for queues that have made some forward progress.
  1383. * Returns 0 if the queue is not Isochronous, is ACTIVE, and
  1384. * has not advanced since last examined; 1 otherwise.
  1385. *
  1386. * Early Intel controllers have a bug which causes qh->element sometimes
  1387. * not to advance when a TD completes successfully. The queue remains
  1388. * stuck on the inactive completed TD. We detect such cases and advance
  1389. * the element pointer by hand.
  1390. */
  1391. static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1392. {
  1393. struct urb_priv *urbp = NULL;
  1394. struct uhci_td *td;
  1395. int ret = 1;
  1396. unsigned status;
  1397. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1398. goto done;
  1399. /* Treat an UNLINKING queue as though it hasn't advanced.
  1400. * This is okay because reactivation will treat it as though
  1401. * it has advanced, and if it is going to become IDLE then
  1402. * this doesn't matter anyway. Furthermore it's possible
  1403. * for an UNLINKING queue not to have any URBs at all, or
  1404. * for its first URB not to have any TDs (if it was dequeued
  1405. * just as it completed). So it's not easy in any case to
  1406. * test whether such queues have advanced. */
  1407. if (qh->state != QH_STATE_ACTIVE) {
  1408. urbp = NULL;
  1409. status = 0;
  1410. } else {
  1411. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1412. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  1413. status = td_status(td);
  1414. if (!(status & TD_CTRL_ACTIVE)) {
  1415. /* We're okay, the queue has advanced */
  1416. qh->wait_expired = 0;
  1417. qh->advance_jiffies = jiffies;
  1418. goto done;
  1419. }
  1420. ret = 0;
  1421. }
  1422. /* The queue hasn't advanced; check for timeout */
  1423. if (qh->wait_expired)
  1424. goto done;
  1425. if (time_after(jiffies, qh->advance_jiffies + QH_WAIT_TIMEOUT)) {
  1426. /* Detect the Intel bug and work around it */
  1427. if (qh->post_td && qh_element(qh) == LINK_TO_TD(qh->post_td)) {
  1428. qh->element = qh->post_td->link;
  1429. qh->advance_jiffies = jiffies;
  1430. ret = 1;
  1431. goto done;
  1432. }
  1433. qh->wait_expired = 1;
  1434. /* If the current URB wants FSBR, unlink it temporarily
  1435. * so that we can safely set the next TD to interrupt on
  1436. * completion. That way we'll know as soon as the queue
  1437. * starts moving again. */
  1438. if (urbp && urbp->fsbr && !(status & TD_CTRL_IOC))
  1439. uhci_unlink_qh(uhci, qh);
  1440. } else {
  1441. /* Unmoving but not-yet-expired queues keep FSBR alive */
  1442. if (urbp)
  1443. uhci_urbp_wants_fsbr(uhci, urbp);
  1444. }
  1445. done:
  1446. return ret;
  1447. }
  1448. /*
  1449. * Process events in the schedule, but only in one thread at a time
  1450. */
  1451. static void uhci_scan_schedule(struct uhci_hcd *uhci)
  1452. {
  1453. int i;
  1454. struct uhci_qh *qh;
  1455. /* Don't allow re-entrant calls */
  1456. if (uhci->scan_in_progress) {
  1457. uhci->need_rescan = 1;
  1458. return;
  1459. }
  1460. uhci->scan_in_progress = 1;
  1461. rescan:
  1462. uhci->need_rescan = 0;
  1463. uhci->fsbr_is_wanted = 0;
  1464. uhci_clear_next_interrupt(uhci);
  1465. uhci_get_current_frame_number(uhci);
  1466. uhci->cur_iso_frame = uhci->frame_number;
  1467. /* Go through all the QH queues and process the URBs in each one */
  1468. for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) {
  1469. uhci->next_qh = list_entry(uhci->skelqh[i]->node.next,
  1470. struct uhci_qh, node);
  1471. while ((qh = uhci->next_qh) != uhci->skelqh[i]) {
  1472. uhci->next_qh = list_entry(qh->node.next,
  1473. struct uhci_qh, node);
  1474. if (uhci_advance_check(uhci, qh)) {
  1475. uhci_scan_qh(uhci, qh);
  1476. if (qh->state == QH_STATE_ACTIVE) {
  1477. uhci_urbp_wants_fsbr(uhci,
  1478. list_entry(qh->queue.next, struct urb_priv, node));
  1479. }
  1480. }
  1481. }
  1482. }
  1483. uhci->last_iso_frame = uhci->cur_iso_frame;
  1484. if (uhci->need_rescan)
  1485. goto rescan;
  1486. uhci->scan_in_progress = 0;
  1487. if (uhci->fsbr_is_on && !uhci->fsbr_is_wanted &&
  1488. !uhci->fsbr_expiring) {
  1489. uhci->fsbr_expiring = 1;
  1490. mod_timer(&uhci->fsbr_timer, jiffies + FSBR_OFF_DELAY);
  1491. }
  1492. if (list_empty(&uhci->skel_unlink_qh->node))
  1493. uhci_clear_next_interrupt(uhci);
  1494. else
  1495. uhci_set_next_interrupt(uhci);
  1496. }