aic79xx_reg_print.c_shipped 62 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468
  1. /*
  2. * DO NOT EDIT - This file is automatically generated
  3. * from the following source files:
  4. *
  5. * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $
  6. * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $
  7. */
  8. #include "aic79xx_osm.h"
  9. static const ahd_reg_parse_entry_t MODE_PTR_parse_table[] = {
  10. { "SRC_MODE", 0x07, 0x07 },
  11. { "DST_MODE", 0x70, 0x70 }
  12. };
  13. int
  14. ahd_mode_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  15. {
  16. return (ahd_print_register(MODE_PTR_parse_table, 2, "MODE_PTR",
  17. 0x00, regvalue, cur_col, wrap));
  18. }
  19. static const ahd_reg_parse_entry_t INTSTAT_parse_table[] = {
  20. { "SPLTINT", 0x01, 0x01 },
  21. { "CMDCMPLT", 0x02, 0x02 },
  22. { "SEQINT", 0x04, 0x04 },
  23. { "SCSIINT", 0x08, 0x08 },
  24. { "PCIINT", 0x10, 0x10 },
  25. { "SWTMINT", 0x20, 0x20 },
  26. { "BRKADRINT", 0x40, 0x40 },
  27. { "HWERRINT", 0x80, 0x80 },
  28. { "INT_PEND", 0xff, 0xff }
  29. };
  30. int
  31. ahd_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  32. {
  33. return (ahd_print_register(INTSTAT_parse_table, 9, "INTSTAT",
  34. 0x01, regvalue, cur_col, wrap));
  35. }
  36. static const ahd_reg_parse_entry_t SEQINTCODE_parse_table[] = {
  37. { "NO_SEQINT", 0x00, 0xff },
  38. { "BAD_PHASE", 0x01, 0xff },
  39. { "SEND_REJECT", 0x02, 0xff },
  40. { "PROTO_VIOLATION", 0x03, 0xff },
  41. { "NO_MATCH", 0x04, 0xff },
  42. { "IGN_WIDE_RES", 0x05, 0xff },
  43. { "PDATA_REINIT", 0x06, 0xff },
  44. { "HOST_MSG_LOOP", 0x07, 0xff },
  45. { "BAD_STATUS", 0x08, 0xff },
  46. { "DATA_OVERRUN", 0x09, 0xff },
  47. { "MKMSG_FAILED", 0x0a, 0xff },
  48. { "MISSED_BUSFREE", 0x0b, 0xff },
  49. { "DUMP_CARD_STATE", 0x0c, 0xff },
  50. { "ILLEGAL_PHASE", 0x0d, 0xff },
  51. { "INVALID_SEQINT", 0x0e, 0xff },
  52. { "CFG4ISTAT_INTR", 0x0f, 0xff },
  53. { "STATUS_OVERRUN", 0x10, 0xff },
  54. { "CFG4OVERRUN", 0x11, 0xff },
  55. { "ENTERING_NONPACK", 0x12, 0xff },
  56. { "TASKMGMT_FUNC_COMPLETE",0x13, 0xff },
  57. { "TASKMGMT_CMD_CMPLT_OKAY",0x14, 0xff },
  58. { "TRACEPOINT0", 0x15, 0xff },
  59. { "TRACEPOINT1", 0x16, 0xff },
  60. { "TRACEPOINT2", 0x17, 0xff },
  61. { "TRACEPOINT3", 0x18, 0xff },
  62. { "SAW_HWERR", 0x19, 0xff },
  63. { "BAD_SCB_STATUS", 0x1a, 0xff }
  64. };
  65. int
  66. ahd_seqintcode_print(u_int regvalue, u_int *cur_col, u_int wrap)
  67. {
  68. return (ahd_print_register(SEQINTCODE_parse_table, 27, "SEQINTCODE",
  69. 0x02, regvalue, cur_col, wrap));
  70. }
  71. static const ahd_reg_parse_entry_t CLRINT_parse_table[] = {
  72. { "CLRSPLTINT", 0x01, 0x01 },
  73. { "CLRCMDINT", 0x02, 0x02 },
  74. { "CLRSEQINT", 0x04, 0x04 },
  75. { "CLRSCSIINT", 0x08, 0x08 },
  76. { "CLRPCIINT", 0x10, 0x10 },
  77. { "CLRSWTMINT", 0x20, 0x20 },
  78. { "CLRBRKADRINT", 0x40, 0x40 },
  79. { "CLRHWERRINT", 0x80, 0x80 }
  80. };
  81. int
  82. ahd_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap)
  83. {
  84. return (ahd_print_register(CLRINT_parse_table, 8, "CLRINT",
  85. 0x03, regvalue, cur_col, wrap));
  86. }
  87. static const ahd_reg_parse_entry_t ERROR_parse_table[] = {
  88. { "DSCTMOUT", 0x02, 0x02 },
  89. { "ILLOPCODE", 0x04, 0x04 },
  90. { "SQPARERR", 0x08, 0x08 },
  91. { "DPARERR", 0x10, 0x10 },
  92. { "MPARERR", 0x20, 0x20 },
  93. { "CIOACCESFAIL", 0x40, 0x40 },
  94. { "CIOPARERR", 0x80, 0x80 }
  95. };
  96. int
  97. ahd_error_print(u_int regvalue, u_int *cur_col, u_int wrap)
  98. {
  99. return (ahd_print_register(ERROR_parse_table, 7, "ERROR",
  100. 0x04, regvalue, cur_col, wrap));
  101. }
  102. static const ahd_reg_parse_entry_t HCNTRL_parse_table[] = {
  103. { "CHIPRST", 0x01, 0x01 },
  104. { "CHIPRSTACK", 0x01, 0x01 },
  105. { "INTEN", 0x02, 0x02 },
  106. { "PAUSE", 0x04, 0x04 },
  107. { "SWTIMER_START_B", 0x08, 0x08 },
  108. { "SWINT", 0x10, 0x10 },
  109. { "POWRDN", 0x40, 0x40 },
  110. { "SEQ_RESET", 0x80, 0x80 }
  111. };
  112. int
  113. ahd_hcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  114. {
  115. return (ahd_print_register(HCNTRL_parse_table, 8, "HCNTRL",
  116. 0x05, regvalue, cur_col, wrap));
  117. }
  118. int
  119. ahd_hnscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
  120. {
  121. return (ahd_print_register(NULL, 0, "HNSCB_QOFF",
  122. 0x06, regvalue, cur_col, wrap));
  123. }
  124. int
  125. ahd_hescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
  126. {
  127. return (ahd_print_register(NULL, 0, "HESCB_QOFF",
  128. 0x08, regvalue, cur_col, wrap));
  129. }
  130. static const ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
  131. { "ENINT_COALESCE", 0x40, 0x40 },
  132. { "HOST_TQINPOS", 0x80, 0x80 }
  133. };
  134. int
  135. ahd_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
  136. {
  137. return (ahd_print_register(HS_MAILBOX_parse_table, 2, "HS_MAILBOX",
  138. 0x0b, regvalue, cur_col, wrap));
  139. }
  140. static const ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = {
  141. { "SEQ_SPLTINT", 0x01, 0x01 },
  142. { "SEQ_PCIINT", 0x02, 0x02 },
  143. { "SEQ_SCSIINT", 0x04, 0x04 },
  144. { "SEQ_SEQINT", 0x08, 0x08 },
  145. { "SEQ_SWTMRTO", 0x10, 0x10 }
  146. };
  147. int
  148. ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  149. {
  150. return (ahd_print_register(SEQINTSTAT_parse_table, 5, "SEQINTSTAT",
  151. 0x0c, regvalue, cur_col, wrap));
  152. }
  153. static const ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = {
  154. { "CLRSEQ_SPLTINT", 0x01, 0x01 },
  155. { "CLRSEQ_PCIINT", 0x02, 0x02 },
  156. { "CLRSEQ_SCSIINT", 0x04, 0x04 },
  157. { "CLRSEQ_SEQINT", 0x08, 0x08 },
  158. { "CLRSEQ_SWTMRTO", 0x10, 0x10 }
  159. };
  160. int
  161. ahd_clrseqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  162. {
  163. return (ahd_print_register(CLRSEQINTSTAT_parse_table, 5, "CLRSEQINTSTAT",
  164. 0x0c, regvalue, cur_col, wrap));
  165. }
  166. int
  167. ahd_swtimer_print(u_int regvalue, u_int *cur_col, u_int wrap)
  168. {
  169. return (ahd_print_register(NULL, 0, "SWTIMER",
  170. 0x0e, regvalue, cur_col, wrap));
  171. }
  172. int
  173. ahd_snscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
  174. {
  175. return (ahd_print_register(NULL, 0, "SNSCB_QOFF",
  176. 0x10, regvalue, cur_col, wrap));
  177. }
  178. int
  179. ahd_sescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
  180. {
  181. return (ahd_print_register(NULL, 0, "SESCB_QOFF",
  182. 0x12, regvalue, cur_col, wrap));
  183. }
  184. int
  185. ahd_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
  186. {
  187. return (ahd_print_register(NULL, 0, "SDSCB_QOFF",
  188. 0x14, regvalue, cur_col, wrap));
  189. }
  190. static const ahd_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = {
  191. { "SCB_QSIZE_4", 0x00, 0x0f },
  192. { "SCB_QSIZE_8", 0x01, 0x0f },
  193. { "SCB_QSIZE_16", 0x02, 0x0f },
  194. { "SCB_QSIZE_32", 0x03, 0x0f },
  195. { "SCB_QSIZE_64", 0x04, 0x0f },
  196. { "SCB_QSIZE_128", 0x05, 0x0f },
  197. { "SCB_QSIZE_256", 0x06, 0x0f },
  198. { "SCB_QSIZE_512", 0x07, 0x0f },
  199. { "SCB_QSIZE_1024", 0x08, 0x0f },
  200. { "SCB_QSIZE_2048", 0x09, 0x0f },
  201. { "SCB_QSIZE_4096", 0x0a, 0x0f },
  202. { "SCB_QSIZE_8192", 0x0b, 0x0f },
  203. { "SCB_QSIZE_16384", 0x0c, 0x0f },
  204. { "SCB_QSIZE", 0x0f, 0x0f },
  205. { "HS_MAILBOX_ACT", 0x10, 0x10 },
  206. { "SDSCB_ROLLOVR", 0x20, 0x20 },
  207. { "NEW_SCB_AVAIL", 0x40, 0x40 },
  208. { "EMPTY_SCB_AVAIL", 0x80, 0x80 }
  209. };
  210. int
  211. ahd_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap)
  212. {
  213. return (ahd_print_register(QOFF_CTLSTA_parse_table, 18, "QOFF_CTLSTA",
  214. 0x16, regvalue, cur_col, wrap));
  215. }
  216. static const ahd_reg_parse_entry_t INTCTL_parse_table[] = {
  217. { "SPLTINTEN", 0x01, 0x01 },
  218. { "SEQINTEN", 0x02, 0x02 },
  219. { "SCSIINTEN", 0x04, 0x04 },
  220. { "PCIINTEN", 0x08, 0x08 },
  221. { "AUTOCLRCMDINT", 0x10, 0x10 },
  222. { "SWTIMER_START", 0x20, 0x20 },
  223. { "SWTMINTEN", 0x40, 0x40 },
  224. { "SWTMINTMASK", 0x80, 0x80 }
  225. };
  226. int
  227. ahd_intctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  228. {
  229. return (ahd_print_register(INTCTL_parse_table, 8, "INTCTL",
  230. 0x18, regvalue, cur_col, wrap));
  231. }
  232. static const ahd_reg_parse_entry_t DFCNTRL_parse_table[] = {
  233. { "DIRECTIONEN", 0x01, 0x01 },
  234. { "FIFOFLUSH", 0x02, 0x02 },
  235. { "FIFOFLUSHACK", 0x02, 0x02 },
  236. { "DIRECTION", 0x04, 0x04 },
  237. { "DIRECTIONACK", 0x04, 0x04 },
  238. { "HDMAEN", 0x08, 0x08 },
  239. { "HDMAENACK", 0x08, 0x08 },
  240. { "SCSIEN", 0x20, 0x20 },
  241. { "SCSIENACK", 0x20, 0x20 },
  242. { "SCSIENWRDIS", 0x40, 0x40 },
  243. { "PRELOADEN", 0x80, 0x80 }
  244. };
  245. int
  246. ahd_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  247. {
  248. return (ahd_print_register(DFCNTRL_parse_table, 11, "DFCNTRL",
  249. 0x19, regvalue, cur_col, wrap));
  250. }
  251. static const ahd_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
  252. { "CIOPARCKEN", 0x01, 0x01 },
  253. { "DISABLE_TWATE", 0x02, 0x02 },
  254. { "EXTREQLCK", 0x10, 0x10 },
  255. { "MPARCKEN", 0x20, 0x20 },
  256. { "DPARCKEN", 0x40, 0x40 },
  257. { "CACHETHEN", 0x80, 0x80 }
  258. };
  259. int
  260. ahd_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  261. {
  262. return (ahd_print_register(DSCOMMAND0_parse_table, 6, "DSCOMMAND0",
  263. 0x19, regvalue, cur_col, wrap));
  264. }
  265. static const ahd_reg_parse_entry_t DFSTATUS_parse_table[] = {
  266. { "FIFOEMP", 0x01, 0x01 },
  267. { "FIFOFULL", 0x02, 0x02 },
  268. { "DFTHRESH", 0x04, 0x04 },
  269. { "HDONE", 0x08, 0x08 },
  270. { "MREQPEND", 0x10, 0x10 },
  271. { "PKT_PRELOAD_AVAIL", 0x40, 0x40 },
  272. { "PRELOAD_AVAIL", 0x80, 0x80 }
  273. };
  274. int
  275. ahd_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
  276. {
  277. return (ahd_print_register(DFSTATUS_parse_table, 7, "DFSTATUS",
  278. 0x1a, regvalue, cur_col, wrap));
  279. }
  280. static const ahd_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
  281. { "LAST_SEG_DONE", 0x01, 0x01 },
  282. { "LAST_SEG", 0x02, 0x02 },
  283. { "ODD_SEG", 0x04, 0x04 },
  284. { "SG_ADDR_MASK", 0xf8, 0xf8 }
  285. };
  286. int
  287. ahd_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
  288. {
  289. return (ahd_print_register(SG_CACHE_SHADOW_parse_table, 4, "SG_CACHE_SHADOW",
  290. 0x1b, regvalue, cur_col, wrap));
  291. }
  292. static const ahd_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
  293. { "LAST_SEG", 0x02, 0x02 },
  294. { "ODD_SEG", 0x04, 0x04 },
  295. { "SG_ADDR_MASK", 0xf8, 0xf8 }
  296. };
  297. int
  298. ahd_sg_cache_pre_print(u_int regvalue, u_int *cur_col, u_int wrap)
  299. {
  300. return (ahd_print_register(SG_CACHE_PRE_parse_table, 3, "SG_CACHE_PRE",
  301. 0x1b, regvalue, cur_col, wrap));
  302. }
  303. int
  304. ahd_lqin_print(u_int regvalue, u_int *cur_col, u_int wrap)
  305. {
  306. return (ahd_print_register(NULL, 0, "LQIN",
  307. 0x20, regvalue, cur_col, wrap));
  308. }
  309. int
  310. ahd_lunptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  311. {
  312. return (ahd_print_register(NULL, 0, "LUNPTR",
  313. 0x22, regvalue, cur_col, wrap));
  314. }
  315. int
  316. ahd_cmdlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  317. {
  318. return (ahd_print_register(NULL, 0, "CMDLENPTR",
  319. 0x25, regvalue, cur_col, wrap));
  320. }
  321. int
  322. ahd_attrptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  323. {
  324. return (ahd_print_register(NULL, 0, "ATTRPTR",
  325. 0x26, regvalue, cur_col, wrap));
  326. }
  327. int
  328. ahd_flagptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  329. {
  330. return (ahd_print_register(NULL, 0, "FLAGPTR",
  331. 0x27, regvalue, cur_col, wrap));
  332. }
  333. int
  334. ahd_cmdptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  335. {
  336. return (ahd_print_register(NULL, 0, "CMDPTR",
  337. 0x28, regvalue, cur_col, wrap));
  338. }
  339. int
  340. ahd_qnextptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  341. {
  342. return (ahd_print_register(NULL, 0, "QNEXTPTR",
  343. 0x29, regvalue, cur_col, wrap));
  344. }
  345. int
  346. ahd_abrtbyteptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  347. {
  348. return (ahd_print_register(NULL, 0, "ABRTBYTEPTR",
  349. 0x2b, regvalue, cur_col, wrap));
  350. }
  351. int
  352. ahd_abrtbitptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  353. {
  354. return (ahd_print_register(NULL, 0, "ABRTBITPTR",
  355. 0x2c, regvalue, cur_col, wrap));
  356. }
  357. static const ahd_reg_parse_entry_t LUNLEN_parse_table[] = {
  358. { "ILUNLEN", 0x0f, 0x0f },
  359. { "TLUNLEN", 0xf0, 0xf0 }
  360. };
  361. int
  362. ahd_lunlen_print(u_int regvalue, u_int *cur_col, u_int wrap)
  363. {
  364. return (ahd_print_register(LUNLEN_parse_table, 2, "LUNLEN",
  365. 0x30, regvalue, cur_col, wrap));
  366. }
  367. int
  368. ahd_cdblimit_print(u_int regvalue, u_int *cur_col, u_int wrap)
  369. {
  370. return (ahd_print_register(NULL, 0, "CDBLIMIT",
  371. 0x31, regvalue, cur_col, wrap));
  372. }
  373. int
  374. ahd_maxcmd_print(u_int regvalue, u_int *cur_col, u_int wrap)
  375. {
  376. return (ahd_print_register(NULL, 0, "MAXCMD",
  377. 0x32, regvalue, cur_col, wrap));
  378. }
  379. int
  380. ahd_maxcmdcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  381. {
  382. return (ahd_print_register(NULL, 0, "MAXCMDCNT",
  383. 0x33, regvalue, cur_col, wrap));
  384. }
  385. static const ahd_reg_parse_entry_t LQCTL1_parse_table[] = {
  386. { "ABORTPENDING", 0x01, 0x01 },
  387. { "SINGLECMD", 0x02, 0x02 },
  388. { "PCI2PCI", 0x04, 0x04 }
  389. };
  390. int
  391. ahd_lqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  392. {
  393. return (ahd_print_register(LQCTL1_parse_table, 3, "LQCTL1",
  394. 0x38, regvalue, cur_col, wrap));
  395. }
  396. static const ahd_reg_parse_entry_t LQCTL2_parse_table[] = {
  397. { "LQOPAUSE", 0x01, 0x01 },
  398. { "LQOTOIDLE", 0x02, 0x02 },
  399. { "LQOCONTINUE", 0x04, 0x04 },
  400. { "LQORETRY", 0x08, 0x08 },
  401. { "LQIPAUSE", 0x10, 0x10 },
  402. { "LQITOIDLE", 0x20, 0x20 },
  403. { "LQICONTINUE", 0x40, 0x40 },
  404. { "LQIRETRY", 0x80, 0x80 }
  405. };
  406. int
  407. ahd_lqctl2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  408. {
  409. return (ahd_print_register(LQCTL2_parse_table, 8, "LQCTL2",
  410. 0x39, regvalue, cur_col, wrap));
  411. }
  412. static const ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = {
  413. { "SCSIRSTO", 0x01, 0x01 },
  414. { "FORCEBUSFREE", 0x10, 0x10 },
  415. { "ENARBO", 0x20, 0x20 },
  416. { "ENSELO", 0x40, 0x40 },
  417. { "TEMODEO", 0x80, 0x80 }
  418. };
  419. int
  420. ahd_scsiseq0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  421. {
  422. return (ahd_print_register(SCSISEQ0_parse_table, 5, "SCSISEQ0",
  423. 0x3a, regvalue, cur_col, wrap));
  424. }
  425. static const ahd_reg_parse_entry_t SCSISEQ1_parse_table[] = {
  426. { "ALTSTIM", 0x01, 0x01 },
  427. { "ENAUTOATNP", 0x02, 0x02 },
  428. { "MANUALP", 0x0c, 0x0c },
  429. { "ENRSELI", 0x10, 0x10 },
  430. { "ENSELI", 0x20, 0x20 },
  431. { "MANUALCTL", 0x40, 0x40 }
  432. };
  433. int
  434. ahd_scsiseq1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  435. {
  436. return (ahd_print_register(SCSISEQ1_parse_table, 6, "SCSISEQ1",
  437. 0x3b, regvalue, cur_col, wrap));
  438. }
  439. static const ahd_reg_parse_entry_t SXFRCTL0_parse_table[] = {
  440. { "SPIOEN", 0x08, 0x08 },
  441. { "BIOSCANCELEN", 0x10, 0x10 },
  442. { "DFPEXP", 0x40, 0x40 },
  443. { "DFON", 0x80, 0x80 }
  444. };
  445. int
  446. ahd_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  447. {
  448. return (ahd_print_register(SXFRCTL0_parse_table, 4, "SXFRCTL0",
  449. 0x3c, regvalue, cur_col, wrap));
  450. }
  451. static const ahd_reg_parse_entry_t SXFRCTL1_parse_table[] = {
  452. { "STPWEN", 0x01, 0x01 },
  453. { "ACTNEGEN", 0x02, 0x02 },
  454. { "ENSTIMER", 0x04, 0x04 },
  455. { "STIMESEL", 0x18, 0x18 },
  456. { "ENSPCHK", 0x20, 0x20 },
  457. { "ENSACHK", 0x40, 0x40 },
  458. { "BITBUCKET", 0x80, 0x80 }
  459. };
  460. int
  461. ahd_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  462. {
  463. return (ahd_print_register(SXFRCTL1_parse_table, 7, "SXFRCTL1",
  464. 0x3d, regvalue, cur_col, wrap));
  465. }
  466. static const ahd_reg_parse_entry_t DFFSTAT_parse_table[] = {
  467. { "CURRFIFO_0", 0x00, 0x03 },
  468. { "CURRFIFO_1", 0x01, 0x03 },
  469. { "CURRFIFO_NONE", 0x03, 0x03 },
  470. { "FIFO0FREE", 0x10, 0x10 },
  471. { "FIFO1FREE", 0x20, 0x20 },
  472. { "CURRFIFO", 0x03, 0x03 }
  473. };
  474. int
  475. ahd_dffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  476. {
  477. return (ahd_print_register(DFFSTAT_parse_table, 6, "DFFSTAT",
  478. 0x3f, regvalue, cur_col, wrap));
  479. }
  480. int
  481. ahd_multargid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  482. {
  483. return (ahd_print_register(NULL, 0, "MULTARGID",
  484. 0x40, regvalue, cur_col, wrap));
  485. }
  486. static const ahd_reg_parse_entry_t SCSISIGO_parse_table[] = {
  487. { "P_DATAOUT", 0x00, 0xe0 },
  488. { "P_DATAOUT_DT", 0x20, 0xe0 },
  489. { "P_DATAIN", 0x40, 0xe0 },
  490. { "P_DATAIN_DT", 0x60, 0xe0 },
  491. { "P_COMMAND", 0x80, 0xe0 },
  492. { "P_MESGOUT", 0xa0, 0xe0 },
  493. { "P_STATUS", 0xc0, 0xe0 },
  494. { "P_MESGIN", 0xe0, 0xe0 },
  495. { "ACKO", 0x01, 0x01 },
  496. { "REQO", 0x02, 0x02 },
  497. { "BSYO", 0x04, 0x04 },
  498. { "SELO", 0x08, 0x08 },
  499. { "ATNO", 0x10, 0x10 },
  500. { "MSGO", 0x20, 0x20 },
  501. { "IOO", 0x40, 0x40 },
  502. { "CDO", 0x80, 0x80 },
  503. { "PHASE_MASK", 0xe0, 0xe0 }
  504. };
  505. int
  506. ahd_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap)
  507. {
  508. return (ahd_print_register(SCSISIGO_parse_table, 17, "SCSISIGO",
  509. 0x40, regvalue, cur_col, wrap));
  510. }
  511. static const ahd_reg_parse_entry_t SCSISIGI_parse_table[] = {
  512. { "P_DATAOUT", 0x00, 0xe0 },
  513. { "P_DATAOUT_DT", 0x20, 0xe0 },
  514. { "P_DATAIN", 0x40, 0xe0 },
  515. { "P_DATAIN_DT", 0x60, 0xe0 },
  516. { "P_COMMAND", 0x80, 0xe0 },
  517. { "P_MESGOUT", 0xa0, 0xe0 },
  518. { "P_STATUS", 0xc0, 0xe0 },
  519. { "P_MESGIN", 0xe0, 0xe0 },
  520. { "ACKI", 0x01, 0x01 },
  521. { "REQI", 0x02, 0x02 },
  522. { "BSYI", 0x04, 0x04 },
  523. { "SELI", 0x08, 0x08 },
  524. { "ATNI", 0x10, 0x10 },
  525. { "MSGI", 0x20, 0x20 },
  526. { "IOI", 0x40, 0x40 },
  527. { "CDI", 0x80, 0x80 },
  528. { "PHASE_MASK", 0xe0, 0xe0 }
  529. };
  530. int
  531. ahd_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
  532. {
  533. return (ahd_print_register(SCSISIGI_parse_table, 17, "SCSISIGI",
  534. 0x41, regvalue, cur_col, wrap));
  535. }
  536. static const ahd_reg_parse_entry_t SCSIPHASE_parse_table[] = {
  537. { "DATA_OUT_PHASE", 0x01, 0x03 },
  538. { "DATA_IN_PHASE", 0x02, 0x03 },
  539. { "DATA_PHASE_MASK", 0x03, 0x03 },
  540. { "MSG_OUT_PHASE", 0x04, 0x04 },
  541. { "MSG_IN_PHASE", 0x08, 0x08 },
  542. { "COMMAND_PHASE", 0x10, 0x10 },
  543. { "STATUS_PHASE", 0x20, 0x20 }
  544. };
  545. int
  546. ahd_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
  547. {
  548. return (ahd_print_register(SCSIPHASE_parse_table, 7, "SCSIPHASE",
  549. 0x42, regvalue, cur_col, wrap));
  550. }
  551. int
  552. ahd_scsidat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  553. {
  554. return (ahd_print_register(NULL, 0, "SCSIDAT",
  555. 0x44, regvalue, cur_col, wrap));
  556. }
  557. int
  558. ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap)
  559. {
  560. return (ahd_print_register(NULL, 0, "SCSIBUS",
  561. 0x46, regvalue, cur_col, wrap));
  562. }
  563. static const ahd_reg_parse_entry_t TARGIDIN_parse_table[] = {
  564. { "TARGID", 0x0f, 0x0f },
  565. { "CLKOUT", 0x80, 0x80 }
  566. };
  567. int
  568. ahd_targidin_print(u_int regvalue, u_int *cur_col, u_int wrap)
  569. {
  570. return (ahd_print_register(TARGIDIN_parse_table, 2, "TARGIDIN",
  571. 0x48, regvalue, cur_col, wrap));
  572. }
  573. static const ahd_reg_parse_entry_t SELID_parse_table[] = {
  574. { "ONEBIT", 0x08, 0x08 },
  575. { "SELID_MASK", 0xf0, 0xf0 }
  576. };
  577. int
  578. ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  579. {
  580. return (ahd_print_register(SELID_parse_table, 2, "SELID",
  581. 0x49, regvalue, cur_col, wrap));
  582. }
  583. static const ahd_reg_parse_entry_t OPTIONMODE_parse_table[] = {
  584. { "AUTO_MSGOUT_DE", 0x02, 0x02 },
  585. { "ENDGFORMCHK", 0x04, 0x04 },
  586. { "BUSFREEREV", 0x10, 0x10 },
  587. { "BIASCANCTL", 0x20, 0x20 },
  588. { "AUTOACKEN", 0x40, 0x40 },
  589. { "BIOSCANCTL", 0x80, 0x80 },
  590. { "OPTIONMODE_DEFAULTS",0x02, 0x02 }
  591. };
  592. int
  593. ahd_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap)
  594. {
  595. return (ahd_print_register(OPTIONMODE_parse_table, 7, "OPTIONMODE",
  596. 0x4a, regvalue, cur_col, wrap));
  597. }
  598. static const ahd_reg_parse_entry_t SBLKCTL_parse_table[] = {
  599. { "SELWIDE", 0x02, 0x02 },
  600. { "ENAB20", 0x04, 0x04 },
  601. { "ENAB40", 0x08, 0x08 },
  602. { "DIAGLEDON", 0x40, 0x40 },
  603. { "DIAGLEDEN", 0x80, 0x80 }
  604. };
  605. int
  606. ahd_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  607. {
  608. return (ahd_print_register(SBLKCTL_parse_table, 5, "SBLKCTL",
  609. 0x4a, regvalue, cur_col, wrap));
  610. }
  611. static const ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
  612. { "ARBDO", 0x01, 0x01 },
  613. { "SPIORDY", 0x02, 0x02 },
  614. { "OVERRUN", 0x04, 0x04 },
  615. { "IOERR", 0x08, 0x08 },
  616. { "SELINGO", 0x10, 0x10 },
  617. { "SELDI", 0x20, 0x20 },
  618. { "SELDO", 0x40, 0x40 },
  619. { "TARGET", 0x80, 0x80 }
  620. };
  621. int
  622. ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  623. {
  624. return (ahd_print_register(SSTAT0_parse_table, 8, "SSTAT0",
  625. 0x4b, regvalue, cur_col, wrap));
  626. }
  627. static const ahd_reg_parse_entry_t SIMODE0_parse_table[] = {
  628. { "ENARBDO", 0x01, 0x01 },
  629. { "ENSPIORDY", 0x02, 0x02 },
  630. { "ENOVERRUN", 0x04, 0x04 },
  631. { "ENIOERR", 0x08, 0x08 },
  632. { "ENSELINGO", 0x10, 0x10 },
  633. { "ENSELDI", 0x20, 0x20 },
  634. { "ENSELDO", 0x40, 0x40 }
  635. };
  636. int
  637. ahd_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  638. {
  639. return (ahd_print_register(SIMODE0_parse_table, 7, "SIMODE0",
  640. 0x4b, regvalue, cur_col, wrap));
  641. }
  642. static const ahd_reg_parse_entry_t CLRSINT0_parse_table[] = {
  643. { "CLRARBDO", 0x01, 0x01 },
  644. { "CLRSPIORDY", 0x02, 0x02 },
  645. { "CLROVERRUN", 0x04, 0x04 },
  646. { "CLRIOERR", 0x08, 0x08 },
  647. { "CLRSELINGO", 0x10, 0x10 },
  648. { "CLRSELDI", 0x20, 0x20 },
  649. { "CLRSELDO", 0x40, 0x40 }
  650. };
  651. int
  652. ahd_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  653. {
  654. return (ahd_print_register(CLRSINT0_parse_table, 7, "CLRSINT0",
  655. 0x4b, regvalue, cur_col, wrap));
  656. }
  657. static const ahd_reg_parse_entry_t SSTAT1_parse_table[] = {
  658. { "REQINIT", 0x01, 0x01 },
  659. { "STRB2FAST", 0x02, 0x02 },
  660. { "SCSIPERR", 0x04, 0x04 },
  661. { "BUSFREE", 0x08, 0x08 },
  662. { "PHASEMIS", 0x10, 0x10 },
  663. { "SCSIRSTI", 0x20, 0x20 },
  664. { "ATNTARG", 0x40, 0x40 },
  665. { "SELTO", 0x80, 0x80 }
  666. };
  667. int
  668. ahd_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  669. {
  670. return (ahd_print_register(SSTAT1_parse_table, 8, "SSTAT1",
  671. 0x4c, regvalue, cur_col, wrap));
  672. }
  673. static const ahd_reg_parse_entry_t CLRSINT1_parse_table[] = {
  674. { "CLRREQINIT", 0x01, 0x01 },
  675. { "CLRSTRB2FAST", 0x02, 0x02 },
  676. { "CLRSCSIPERR", 0x04, 0x04 },
  677. { "CLRBUSFREE", 0x08, 0x08 },
  678. { "CLRSCSIRSTI", 0x20, 0x20 },
  679. { "CLRATNO", 0x40, 0x40 },
  680. { "CLRSELTIMEO", 0x80, 0x80 }
  681. };
  682. int
  683. ahd_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  684. {
  685. return (ahd_print_register(CLRSINT1_parse_table, 7, "CLRSINT1",
  686. 0x4c, regvalue, cur_col, wrap));
  687. }
  688. static const ahd_reg_parse_entry_t SSTAT2_parse_table[] = {
  689. { "BUSFREE_LQO", 0x40, 0xc0 },
  690. { "BUSFREE_DFF0", 0x80, 0xc0 },
  691. { "BUSFREE_DFF1", 0xc0, 0xc0 },
  692. { "DMADONE", 0x01, 0x01 },
  693. { "SDONE", 0x02, 0x02 },
  694. { "WIDE_RES", 0x04, 0x04 },
  695. { "BSYX", 0x08, 0x08 },
  696. { "EXP_ACTIVE", 0x10, 0x10 },
  697. { "NONPACKREQ", 0x20, 0x20 },
  698. { "BUSFREETIME", 0xc0, 0xc0 }
  699. };
  700. int
  701. ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  702. {
  703. return (ahd_print_register(SSTAT2_parse_table, 10, "SSTAT2",
  704. 0x4d, regvalue, cur_col, wrap));
  705. }
  706. static const ahd_reg_parse_entry_t CLRSINT2_parse_table[] = {
  707. { "CLRDMADONE", 0x01, 0x01 },
  708. { "CLRSDONE", 0x02, 0x02 },
  709. { "CLRWIDE_RES", 0x04, 0x04 },
  710. { "CLRNONPACKREQ", 0x20, 0x20 }
  711. };
  712. int
  713. ahd_clrsint2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  714. {
  715. return (ahd_print_register(CLRSINT2_parse_table, 4, "CLRSINT2",
  716. 0x4d, regvalue, cur_col, wrap));
  717. }
  718. static const ahd_reg_parse_entry_t PERRDIAG_parse_table[] = {
  719. { "DTERR", 0x01, 0x01 },
  720. { "DGFORMERR", 0x02, 0x02 },
  721. { "CRCERR", 0x04, 0x04 },
  722. { "AIPERR", 0x08, 0x08 },
  723. { "PARITYERR", 0x10, 0x10 },
  724. { "PREVPHASE", 0x20, 0x20 },
  725. { "HIPERR", 0x40, 0x40 },
  726. { "HIZERO", 0x80, 0x80 }
  727. };
  728. int
  729. ahd_perrdiag_print(u_int regvalue, u_int *cur_col, u_int wrap)
  730. {
  731. return (ahd_print_register(PERRDIAG_parse_table, 8, "PERRDIAG",
  732. 0x4e, regvalue, cur_col, wrap));
  733. }
  734. int
  735. ahd_lqistate_print(u_int regvalue, u_int *cur_col, u_int wrap)
  736. {
  737. return (ahd_print_register(NULL, 0, "LQISTATE",
  738. 0x4e, regvalue, cur_col, wrap));
  739. }
  740. int
  741. ahd_soffcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  742. {
  743. return (ahd_print_register(NULL, 0, "SOFFCNT",
  744. 0x4f, regvalue, cur_col, wrap));
  745. }
  746. int
  747. ahd_lqostate_print(u_int regvalue, u_int *cur_col, u_int wrap)
  748. {
  749. return (ahd_print_register(NULL, 0, "LQOSTATE",
  750. 0x4f, regvalue, cur_col, wrap));
  751. }
  752. static const ahd_reg_parse_entry_t LQISTAT0_parse_table[] = {
  753. { "LQIATNCMD", 0x01, 0x01 },
  754. { "LQIATNLQ", 0x02, 0x02 },
  755. { "LQIBADLQT", 0x04, 0x04 },
  756. { "LQICRCT2", 0x08, 0x08 },
  757. { "LQICRCT1", 0x10, 0x10 },
  758. { "LQIATNQAS", 0x20, 0x20 }
  759. };
  760. int
  761. ahd_lqistat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  762. {
  763. return (ahd_print_register(LQISTAT0_parse_table, 6, "LQISTAT0",
  764. 0x50, regvalue, cur_col, wrap));
  765. }
  766. static const ahd_reg_parse_entry_t LQIMODE0_parse_table[] = {
  767. { "ENLQIATNCMD", 0x01, 0x01 },
  768. { "ENLQIATNLQ", 0x02, 0x02 },
  769. { "ENLQIBADLQT", 0x04, 0x04 },
  770. { "ENLQICRCT2", 0x08, 0x08 },
  771. { "ENLQICRCT1", 0x10, 0x10 },
  772. { "ENLQIATNQASK", 0x20, 0x20 }
  773. };
  774. int
  775. ahd_lqimode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  776. {
  777. return (ahd_print_register(LQIMODE0_parse_table, 6, "LQIMODE0",
  778. 0x50, regvalue, cur_col, wrap));
  779. }
  780. static const ahd_reg_parse_entry_t CLRLQIINT0_parse_table[] = {
  781. { "CLRLQIATNCMD", 0x01, 0x01 },
  782. { "CLRLQIATNLQ", 0x02, 0x02 },
  783. { "CLRLQIBADLQT", 0x04, 0x04 },
  784. { "CLRLQICRCT2", 0x08, 0x08 },
  785. { "CLRLQICRCT1", 0x10, 0x10 },
  786. { "CLRLQIATNQAS", 0x20, 0x20 }
  787. };
  788. int
  789. ahd_clrlqiint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  790. {
  791. return (ahd_print_register(CLRLQIINT0_parse_table, 6, "CLRLQIINT0",
  792. 0x50, regvalue, cur_col, wrap));
  793. }
  794. static const ahd_reg_parse_entry_t LQIMODE1_parse_table[] = {
  795. { "ENLQIOVERI_NLQ", 0x01, 0x01 },
  796. { "ENLQIOVERI_LQ", 0x02, 0x02 },
  797. { "ENLQIBADLQI", 0x04, 0x04 },
  798. { "ENLQICRCI_NLQ", 0x08, 0x08 },
  799. { "ENLQICRCI_LQ", 0x10, 0x10 },
  800. { "ENLIQABORT", 0x20, 0x20 },
  801. { "ENLQIPHASE_NLQ", 0x40, 0x40 },
  802. { "ENLQIPHASE_LQ", 0x80, 0x80 }
  803. };
  804. int
  805. ahd_lqimode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  806. {
  807. return (ahd_print_register(LQIMODE1_parse_table, 8, "LQIMODE1",
  808. 0x51, regvalue, cur_col, wrap));
  809. }
  810. static const ahd_reg_parse_entry_t LQISTAT1_parse_table[] = {
  811. { "LQIOVERI_NLQ", 0x01, 0x01 },
  812. { "LQIOVERI_LQ", 0x02, 0x02 },
  813. { "LQIBADLQI", 0x04, 0x04 },
  814. { "LQICRCI_NLQ", 0x08, 0x08 },
  815. { "LQICRCI_LQ", 0x10, 0x10 },
  816. { "LQIABORT", 0x20, 0x20 },
  817. { "LQIPHASE_NLQ", 0x40, 0x40 },
  818. { "LQIPHASE_LQ", 0x80, 0x80 }
  819. };
  820. int
  821. ahd_lqistat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  822. {
  823. return (ahd_print_register(LQISTAT1_parse_table, 8, "LQISTAT1",
  824. 0x51, regvalue, cur_col, wrap));
  825. }
  826. static const ahd_reg_parse_entry_t CLRLQIINT1_parse_table[] = {
  827. { "CLRLQIOVERI_NLQ", 0x01, 0x01 },
  828. { "CLRLQIOVERI_LQ", 0x02, 0x02 },
  829. { "CLRLQIBADLQI", 0x04, 0x04 },
  830. { "CLRLQICRCI_NLQ", 0x08, 0x08 },
  831. { "CLRLQICRCI_LQ", 0x10, 0x10 },
  832. { "CLRLIQABORT", 0x20, 0x20 },
  833. { "CLRLQIPHASE_NLQ", 0x40, 0x40 },
  834. { "CLRLQIPHASE_LQ", 0x80, 0x80 }
  835. };
  836. int
  837. ahd_clrlqiint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  838. {
  839. return (ahd_print_register(CLRLQIINT1_parse_table, 8, "CLRLQIINT1",
  840. 0x51, regvalue, cur_col, wrap));
  841. }
  842. static const ahd_reg_parse_entry_t LQISTAT2_parse_table[] = {
  843. { "LQIGSAVAIL", 0x01, 0x01 },
  844. { "LQISTOPCMD", 0x02, 0x02 },
  845. { "LQISTOPLQ", 0x04, 0x04 },
  846. { "LQISTOPPKT", 0x08, 0x08 },
  847. { "LQIWAITFIFO", 0x10, 0x10 },
  848. { "LQIWORKONLQ", 0x20, 0x20 },
  849. { "LQIPHASE_OUTPKT", 0x40, 0x40 },
  850. { "PACKETIZED", 0x80, 0x80 }
  851. };
  852. int
  853. ahd_lqistat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  854. {
  855. return (ahd_print_register(LQISTAT2_parse_table, 8, "LQISTAT2",
  856. 0x52, regvalue, cur_col, wrap));
  857. }
  858. static const ahd_reg_parse_entry_t SSTAT3_parse_table[] = {
  859. { "OSRAMPERR", 0x01, 0x01 },
  860. { "NTRAMPERR", 0x02, 0x02 }
  861. };
  862. int
  863. ahd_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
  864. {
  865. return (ahd_print_register(SSTAT3_parse_table, 2, "SSTAT3",
  866. 0x53, regvalue, cur_col, wrap));
  867. }
  868. static const ahd_reg_parse_entry_t SIMODE3_parse_table[] = {
  869. { "ENOSRAMPERR", 0x01, 0x01 },
  870. { "ENNTRAMPERR", 0x02, 0x02 }
  871. };
  872. int
  873. ahd_simode3_print(u_int regvalue, u_int *cur_col, u_int wrap)
  874. {
  875. return (ahd_print_register(SIMODE3_parse_table, 2, "SIMODE3",
  876. 0x53, regvalue, cur_col, wrap));
  877. }
  878. static const ahd_reg_parse_entry_t CLRSINT3_parse_table[] = {
  879. { "CLROSRAMPERR", 0x01, 0x01 },
  880. { "CLRNTRAMPERR", 0x02, 0x02 }
  881. };
  882. int
  883. ahd_clrsint3_print(u_int regvalue, u_int *cur_col, u_int wrap)
  884. {
  885. return (ahd_print_register(CLRSINT3_parse_table, 2, "CLRSINT3",
  886. 0x53, regvalue, cur_col, wrap));
  887. }
  888. static const ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = {
  889. { "LQOTCRC", 0x01, 0x01 },
  890. { "LQOATNPKT", 0x02, 0x02 },
  891. { "LQOATNLQ", 0x04, 0x04 },
  892. { "LQOSTOPT2", 0x08, 0x08 },
  893. { "LQOTARGSCBPERR", 0x10, 0x10 }
  894. };
  895. int
  896. ahd_lqostat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  897. {
  898. return (ahd_print_register(LQOSTAT0_parse_table, 5, "LQOSTAT0",
  899. 0x54, regvalue, cur_col, wrap));
  900. }
  901. static const ahd_reg_parse_entry_t CLRLQOINT0_parse_table[] = {
  902. { "CLRLQOTCRC", 0x01, 0x01 },
  903. { "CLRLQOATNPKT", 0x02, 0x02 },
  904. { "CLRLQOATNLQ", 0x04, 0x04 },
  905. { "CLRLQOSTOPT2", 0x08, 0x08 },
  906. { "CLRLQOTARGSCBPERR", 0x10, 0x10 }
  907. };
  908. int
  909. ahd_clrlqoint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  910. {
  911. return (ahd_print_register(CLRLQOINT0_parse_table, 5, "CLRLQOINT0",
  912. 0x54, regvalue, cur_col, wrap));
  913. }
  914. static const ahd_reg_parse_entry_t LQOMODE0_parse_table[] = {
  915. { "ENLQOTCRC", 0x01, 0x01 },
  916. { "ENLQOATNPKT", 0x02, 0x02 },
  917. { "ENLQOATNLQ", 0x04, 0x04 },
  918. { "ENLQOSTOPT2", 0x08, 0x08 },
  919. { "ENLQOTARGSCBPERR", 0x10, 0x10 }
  920. };
  921. int
  922. ahd_lqomode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  923. {
  924. return (ahd_print_register(LQOMODE0_parse_table, 5, "LQOMODE0",
  925. 0x54, regvalue, cur_col, wrap));
  926. }
  927. static const ahd_reg_parse_entry_t LQOMODE1_parse_table[] = {
  928. { "ENLQOPHACHGINPKT", 0x01, 0x01 },
  929. { "ENLQOBUSFREE", 0x02, 0x02 },
  930. { "ENLQOBADQAS", 0x04, 0x04 },
  931. { "ENLQOSTOPI2", 0x08, 0x08 },
  932. { "ENLQOINITSCBPERR", 0x10, 0x10 }
  933. };
  934. int
  935. ahd_lqomode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  936. {
  937. return (ahd_print_register(LQOMODE1_parse_table, 5, "LQOMODE1",
  938. 0x55, regvalue, cur_col, wrap));
  939. }
  940. static const ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = {
  941. { "LQOPHACHGINPKT", 0x01, 0x01 },
  942. { "LQOBUSFREE", 0x02, 0x02 },
  943. { "LQOBADQAS", 0x04, 0x04 },
  944. { "LQOSTOPI2", 0x08, 0x08 },
  945. { "LQOINITSCBPERR", 0x10, 0x10 }
  946. };
  947. int
  948. ahd_lqostat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  949. {
  950. return (ahd_print_register(LQOSTAT1_parse_table, 5, "LQOSTAT1",
  951. 0x55, regvalue, cur_col, wrap));
  952. }
  953. static const ahd_reg_parse_entry_t CLRLQOINT1_parse_table[] = {
  954. { "CLRLQOPHACHGINPKT", 0x01, 0x01 },
  955. { "CLRLQOBUSFREE", 0x02, 0x02 },
  956. { "CLRLQOBADQAS", 0x04, 0x04 },
  957. { "CLRLQOSTOPI2", 0x08, 0x08 },
  958. { "CLRLQOINITSCBPERR", 0x10, 0x10 }
  959. };
  960. int
  961. ahd_clrlqoint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  962. {
  963. return (ahd_print_register(CLRLQOINT1_parse_table, 5, "CLRLQOINT1",
  964. 0x55, regvalue, cur_col, wrap));
  965. }
  966. static const ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = {
  967. { "LQOSTOP0", 0x01, 0x01 },
  968. { "LQOPHACHGOUTPKT", 0x02, 0x02 },
  969. { "LQOWAITFIFO", 0x10, 0x10 },
  970. { "LQOPKT", 0xe0, 0xe0 }
  971. };
  972. int
  973. ahd_lqostat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  974. {
  975. return (ahd_print_register(LQOSTAT2_parse_table, 4, "LQOSTAT2",
  976. 0x56, regvalue, cur_col, wrap));
  977. }
  978. int
  979. ahd_os_space_cnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  980. {
  981. return (ahd_print_register(NULL, 0, "OS_SPACE_CNT",
  982. 0x56, regvalue, cur_col, wrap));
  983. }
  984. static const ahd_reg_parse_entry_t SIMODE1_parse_table[] = {
  985. { "ENREQINIT", 0x01, 0x01 },
  986. { "ENSTRB2FAST", 0x02, 0x02 },
  987. { "ENSCSIPERR", 0x04, 0x04 },
  988. { "ENBUSFREE", 0x08, 0x08 },
  989. { "ENPHASEMIS", 0x10, 0x10 },
  990. { "ENSCSIRST", 0x20, 0x20 },
  991. { "ENATNTARG", 0x40, 0x40 },
  992. { "ENSELTIMO", 0x80, 0x80 }
  993. };
  994. int
  995. ahd_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  996. {
  997. return (ahd_print_register(SIMODE1_parse_table, 8, "SIMODE1",
  998. 0x57, regvalue, cur_col, wrap));
  999. }
  1000. int
  1001. ahd_gsfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1002. {
  1003. return (ahd_print_register(NULL, 0, "GSFIFO",
  1004. 0x58, regvalue, cur_col, wrap));
  1005. }
  1006. static const ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = {
  1007. { "RSTCHN", 0x01, 0x01 },
  1008. { "CLRCHN", 0x02, 0x02 },
  1009. { "CLRSHCNT", 0x04, 0x04 },
  1010. { "DFFBITBUCKET", 0x08, 0x08 }
  1011. };
  1012. int
  1013. ahd_dffsxfrctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1014. {
  1015. return (ahd_print_register(DFFSXFRCTL_parse_table, 4, "DFFSXFRCTL",
  1016. 0x5a, regvalue, cur_col, wrap));
  1017. }
  1018. static const ahd_reg_parse_entry_t LQOSCSCTL_parse_table[] = {
  1019. { "LQONOCHKOVER", 0x01, 0x01 },
  1020. { "LQONOHOLDLACK", 0x02, 0x02 },
  1021. { "LQOBUSETDLY", 0x40, 0x40 },
  1022. { "LQOH2A_VERSION", 0x80, 0x80 }
  1023. };
  1024. int
  1025. ahd_lqoscsctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1026. {
  1027. return (ahd_print_register(LQOSCSCTL_parse_table, 4, "LQOSCSCTL",
  1028. 0x5a, regvalue, cur_col, wrap));
  1029. }
  1030. int
  1031. ahd_nextscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1032. {
  1033. return (ahd_print_register(NULL, 0, "NEXTSCB",
  1034. 0x5a, regvalue, cur_col, wrap));
  1035. }
  1036. static const ahd_reg_parse_entry_t CLRSEQINTSRC_parse_table[] = {
  1037. { "CLRCFG4TCMD", 0x01, 0x01 },
  1038. { "CLRCFG4ICMD", 0x02, 0x02 },
  1039. { "CLRCFG4TSTAT", 0x04, 0x04 },
  1040. { "CLRCFG4ISTAT", 0x08, 0x08 },
  1041. { "CLRCFG4DATA", 0x10, 0x10 },
  1042. { "CLRSAVEPTRS", 0x20, 0x20 },
  1043. { "CLRCTXTDONE", 0x40, 0x40 }
  1044. };
  1045. int
  1046. ahd_clrseqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1047. {
  1048. return (ahd_print_register(CLRSEQINTSRC_parse_table, 7, "CLRSEQINTSRC",
  1049. 0x5b, regvalue, cur_col, wrap));
  1050. }
  1051. static const ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = {
  1052. { "CFG4TCMD", 0x01, 0x01 },
  1053. { "CFG4ICMD", 0x02, 0x02 },
  1054. { "CFG4TSTAT", 0x04, 0x04 },
  1055. { "CFG4ISTAT", 0x08, 0x08 },
  1056. { "CFG4DATA", 0x10, 0x10 },
  1057. { "SAVEPTRS", 0x20, 0x20 },
  1058. { "CTXTDONE", 0x40, 0x40 }
  1059. };
  1060. int
  1061. ahd_seqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1062. {
  1063. return (ahd_print_register(SEQINTSRC_parse_table, 7, "SEQINTSRC",
  1064. 0x5b, regvalue, cur_col, wrap));
  1065. }
  1066. static const ahd_reg_parse_entry_t SEQIMODE_parse_table[] = {
  1067. { "ENCFG4TCMD", 0x01, 0x01 },
  1068. { "ENCFG4ICMD", 0x02, 0x02 },
  1069. { "ENCFG4TSTAT", 0x04, 0x04 },
  1070. { "ENCFG4ISTAT", 0x08, 0x08 },
  1071. { "ENCFG4DATA", 0x10, 0x10 },
  1072. { "ENSAVEPTRS", 0x20, 0x20 },
  1073. { "ENCTXTDONE", 0x40, 0x40 }
  1074. };
  1075. int
  1076. ahd_seqimode_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1077. {
  1078. return (ahd_print_register(SEQIMODE_parse_table, 7, "SEQIMODE",
  1079. 0x5c, regvalue, cur_col, wrap));
  1080. }
  1081. int
  1082. ahd_currscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1083. {
  1084. return (ahd_print_register(NULL, 0, "CURRSCB",
  1085. 0x5c, regvalue, cur_col, wrap));
  1086. }
  1087. static const ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = {
  1088. { "FIFOFREE", 0x01, 0x01 },
  1089. { "DATAINFIFO", 0x02, 0x02 },
  1090. { "DLZERO", 0x04, 0x04 },
  1091. { "SHVALID", 0x08, 0x08 },
  1092. { "LASTSDONE", 0x10, 0x10 },
  1093. { "SHCNTMINUS1", 0x20, 0x20 },
  1094. { "SHCNTNEGATIVE", 0x40, 0x40 }
  1095. };
  1096. int
  1097. ahd_mdffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1098. {
  1099. return (ahd_print_register(MDFFSTAT_parse_table, 7, "MDFFSTAT",
  1100. 0x5d, regvalue, cur_col, wrap));
  1101. }
  1102. int
  1103. ahd_lastscb_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1104. {
  1105. return (ahd_print_register(NULL, 0, "LASTSCB",
  1106. 0x5e, regvalue, cur_col, wrap));
  1107. }
  1108. int
  1109. ahd_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1110. {
  1111. return (ahd_print_register(NULL, 0, "SHADDR",
  1112. 0x60, regvalue, cur_col, wrap));
  1113. }
  1114. int
  1115. ahd_negoaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1116. {
  1117. return (ahd_print_register(NULL, 0, "NEGOADDR",
  1118. 0x60, regvalue, cur_col, wrap));
  1119. }
  1120. int
  1121. ahd_negperiod_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1122. {
  1123. return (ahd_print_register(NULL, 0, "NEGPERIOD",
  1124. 0x61, regvalue, cur_col, wrap));
  1125. }
  1126. int
  1127. ahd_negoffset_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1128. {
  1129. return (ahd_print_register(NULL, 0, "NEGOFFSET",
  1130. 0x62, regvalue, cur_col, wrap));
  1131. }
  1132. static const ahd_reg_parse_entry_t NEGPPROPTS_parse_table[] = {
  1133. { "PPROPT_IUT", 0x01, 0x01 },
  1134. { "PPROPT_DT", 0x02, 0x02 },
  1135. { "PPROPT_QAS", 0x04, 0x04 },
  1136. { "PPROPT_PACE", 0x08, 0x08 }
  1137. };
  1138. int
  1139. ahd_negppropts_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1140. {
  1141. return (ahd_print_register(NEGPPROPTS_parse_table, 4, "NEGPPROPTS",
  1142. 0x63, regvalue, cur_col, wrap));
  1143. }
  1144. static const ahd_reg_parse_entry_t NEGCONOPTS_parse_table[] = {
  1145. { "WIDEXFER", 0x01, 0x01 },
  1146. { "ENAUTOATNO", 0x02, 0x02 },
  1147. { "ENAUTOATNI", 0x04, 0x04 },
  1148. { "ENSLOWCRC", 0x08, 0x08 },
  1149. { "RTI_OVRDTRN", 0x10, 0x10 },
  1150. { "RTI_WRTDIS", 0x20, 0x20 },
  1151. { "ENSNAPSHOT", 0x40, 0x40 }
  1152. };
  1153. int
  1154. ahd_negconopts_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1155. {
  1156. return (ahd_print_register(NEGCONOPTS_parse_table, 7, "NEGCONOPTS",
  1157. 0x64, regvalue, cur_col, wrap));
  1158. }
  1159. int
  1160. ahd_annexcol_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1161. {
  1162. return (ahd_print_register(NULL, 0, "ANNEXCOL",
  1163. 0x65, regvalue, cur_col, wrap));
  1164. }
  1165. int
  1166. ahd_annexdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1167. {
  1168. return (ahd_print_register(NULL, 0, "ANNEXDAT",
  1169. 0x66, regvalue, cur_col, wrap));
  1170. }
  1171. static const ahd_reg_parse_entry_t SCSCHKN_parse_table[] = {
  1172. { "LSTSGCLRDIS", 0x01, 0x01 },
  1173. { "SHVALIDSTDIS", 0x02, 0x02 },
  1174. { "DFFACTCLR", 0x04, 0x04 },
  1175. { "SDONEMSKDIS", 0x08, 0x08 },
  1176. { "WIDERESEN", 0x10, 0x10 },
  1177. { "CURRFIFODEF", 0x20, 0x20 },
  1178. { "STSELSKIDDIS", 0x40, 0x40 },
  1179. { "BIDICHKDIS", 0x80, 0x80 }
  1180. };
  1181. int
  1182. ahd_scschkn_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1183. {
  1184. return (ahd_print_register(SCSCHKN_parse_table, 8, "SCSCHKN",
  1185. 0x66, regvalue, cur_col, wrap));
  1186. }
  1187. int
  1188. ahd_iownid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1189. {
  1190. return (ahd_print_register(NULL, 0, "IOWNID",
  1191. 0x67, regvalue, cur_col, wrap));
  1192. }
  1193. int
  1194. ahd_shcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1195. {
  1196. return (ahd_print_register(NULL, 0, "SHCNT",
  1197. 0x68, regvalue, cur_col, wrap));
  1198. }
  1199. int
  1200. ahd_townid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1201. {
  1202. return (ahd_print_register(NULL, 0, "TOWNID",
  1203. 0x69, regvalue, cur_col, wrap));
  1204. }
  1205. int
  1206. ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1207. {
  1208. return (ahd_print_register(NULL, 0, "SELOID",
  1209. 0x6b, regvalue, cur_col, wrap));
  1210. }
  1211. int
  1212. ahd_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1213. {
  1214. return (ahd_print_register(NULL, 0, "HADDR",
  1215. 0x70, regvalue, cur_col, wrap));
  1216. }
  1217. int
  1218. ahd_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1219. {
  1220. return (ahd_print_register(NULL, 0, "HCNT",
  1221. 0x78, regvalue, cur_col, wrap));
  1222. }
  1223. int
  1224. ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1225. {
  1226. return (ahd_print_register(NULL, 0, "SGHADDR",
  1227. 0x7c, regvalue, cur_col, wrap));
  1228. }
  1229. int
  1230. ahd_scbhaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1231. {
  1232. return (ahd_print_register(NULL, 0, "SCBHADDR",
  1233. 0x7c, regvalue, cur_col, wrap));
  1234. }
  1235. int
  1236. ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1237. {
  1238. return (ahd_print_register(NULL, 0, "SGHCNT",
  1239. 0x84, regvalue, cur_col, wrap));
  1240. }
  1241. int
  1242. ahd_scbhcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1243. {
  1244. return (ahd_print_register(NULL, 0, "SCBHCNT",
  1245. 0x84, regvalue, cur_col, wrap));
  1246. }
  1247. static const ahd_reg_parse_entry_t DFF_THRSH_parse_table[] = {
  1248. { "WR_DFTHRSH_MIN", 0x00, 0x70 },
  1249. { "RD_DFTHRSH_MIN", 0x00, 0x07 },
  1250. { "RD_DFTHRSH_25", 0x01, 0x07 },
  1251. { "RD_DFTHRSH_50", 0x02, 0x07 },
  1252. { "RD_DFTHRSH_63", 0x03, 0x07 },
  1253. { "RD_DFTHRSH_75", 0x04, 0x07 },
  1254. { "RD_DFTHRSH_85", 0x05, 0x07 },
  1255. { "RD_DFTHRSH_90", 0x06, 0x07 },
  1256. { "RD_DFTHRSH_MAX", 0x07, 0x07 },
  1257. { "WR_DFTHRSH_25", 0x10, 0x70 },
  1258. { "WR_DFTHRSH_50", 0x20, 0x70 },
  1259. { "WR_DFTHRSH_63", 0x30, 0x70 },
  1260. { "WR_DFTHRSH_75", 0x40, 0x70 },
  1261. { "WR_DFTHRSH_85", 0x50, 0x70 },
  1262. { "WR_DFTHRSH_90", 0x60, 0x70 },
  1263. { "WR_DFTHRSH_MAX", 0x70, 0x70 },
  1264. { "RD_DFTHRSH", 0x07, 0x07 },
  1265. { "WR_DFTHRSH", 0x70, 0x70 }
  1266. };
  1267. int
  1268. ahd_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1269. {
  1270. return (ahd_print_register(DFF_THRSH_parse_table, 18, "DFF_THRSH",
  1271. 0x88, regvalue, cur_col, wrap));
  1272. }
  1273. static const ahd_reg_parse_entry_t PCIXCTL_parse_table[] = {
  1274. { "CMPABCDIS", 0x01, 0x01 },
  1275. { "TSCSERREN", 0x02, 0x02 },
  1276. { "SRSPDPEEN", 0x04, 0x04 },
  1277. { "SPLTSTADIS", 0x08, 0x08 },
  1278. { "SPLTSMADIS", 0x10, 0x10 },
  1279. { "UNEXPSCIEN", 0x20, 0x20 },
  1280. { "SERRPULSE", 0x80, 0x80 }
  1281. };
  1282. int
  1283. ahd_pcixctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1284. {
  1285. return (ahd_print_register(PCIXCTL_parse_table, 7, "PCIXCTL",
  1286. 0x93, regvalue, cur_col, wrap));
  1287. }
  1288. static const ahd_reg_parse_entry_t DCHSPLTSTAT0_parse_table[] = {
  1289. { "RXSPLTRSP", 0x01, 0x01 },
  1290. { "RXSCEMSG", 0x02, 0x02 },
  1291. { "RXOVRUN", 0x04, 0x04 },
  1292. { "CNTNOTCMPLT", 0x08, 0x08 },
  1293. { "SCDATBUCKET", 0x10, 0x10 },
  1294. { "SCADERR", 0x20, 0x20 },
  1295. { "SCBCERR", 0x40, 0x40 },
  1296. { "STAETERM", 0x80, 0x80 }
  1297. };
  1298. int
  1299. ahd_dchspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1300. {
  1301. return (ahd_print_register(DCHSPLTSTAT0_parse_table, 8, "DCHSPLTSTAT0",
  1302. 0x96, regvalue, cur_col, wrap));
  1303. }
  1304. static const ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = {
  1305. { "RXDATABUCKET", 0x01, 0x01 }
  1306. };
  1307. int
  1308. ahd_dchspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1309. {
  1310. return (ahd_print_register(DCHSPLTSTAT1_parse_table, 1, "DCHSPLTSTAT1",
  1311. 0x97, regvalue, cur_col, wrap));
  1312. }
  1313. static const ahd_reg_parse_entry_t SGSPLTSTAT0_parse_table[] = {
  1314. { "RXSPLTRSP", 0x01, 0x01 },
  1315. { "RXSCEMSG", 0x02, 0x02 },
  1316. { "RXOVRUN", 0x04, 0x04 },
  1317. { "CNTNOTCMPLT", 0x08, 0x08 },
  1318. { "SCDATBUCKET", 0x10, 0x10 },
  1319. { "SCADERR", 0x20, 0x20 },
  1320. { "SCBCERR", 0x40, 0x40 },
  1321. { "STAETERM", 0x80, 0x80 }
  1322. };
  1323. int
  1324. ahd_sgspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1325. {
  1326. return (ahd_print_register(SGSPLTSTAT0_parse_table, 8, "SGSPLTSTAT0",
  1327. 0x9e, regvalue, cur_col, wrap));
  1328. }
  1329. static const ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = {
  1330. { "RXDATABUCKET", 0x01, 0x01 }
  1331. };
  1332. int
  1333. ahd_sgspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1334. {
  1335. return (ahd_print_register(SGSPLTSTAT1_parse_table, 1, "SGSPLTSTAT1",
  1336. 0x9f, regvalue, cur_col, wrap));
  1337. }
  1338. static const ahd_reg_parse_entry_t DF0PCISTAT_parse_table[] = {
  1339. { "DPR", 0x01, 0x01 },
  1340. { "TWATERR", 0x02, 0x02 },
  1341. { "RDPERR", 0x04, 0x04 },
  1342. { "SCAAPERR", 0x08, 0x08 },
  1343. { "RTA", 0x10, 0x10 },
  1344. { "RMA", 0x20, 0x20 },
  1345. { "SSE", 0x40, 0x40 },
  1346. { "DPE", 0x80, 0x80 }
  1347. };
  1348. int
  1349. ahd_df0pcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1350. {
  1351. return (ahd_print_register(DF0PCISTAT_parse_table, 8, "DF0PCISTAT",
  1352. 0xa0, regvalue, cur_col, wrap));
  1353. }
  1354. int
  1355. ahd_reg0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1356. {
  1357. return (ahd_print_register(NULL, 0, "REG0",
  1358. 0xa0, regvalue, cur_col, wrap));
  1359. }
  1360. int
  1361. ahd_reg_isr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1362. {
  1363. return (ahd_print_register(NULL, 0, "REG_ISR",
  1364. 0xa4, regvalue, cur_col, wrap));
  1365. }
  1366. static const ahd_reg_parse_entry_t SG_STATE_parse_table[] = {
  1367. { "SEGS_AVAIL", 0x01, 0x01 },
  1368. { "LOADING_NEEDED", 0x02, 0x02 },
  1369. { "FETCH_INPROG", 0x04, 0x04 }
  1370. };
  1371. int
  1372. ahd_sg_state_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1373. {
  1374. return (ahd_print_register(SG_STATE_parse_table, 3, "SG_STATE",
  1375. 0xa6, regvalue, cur_col, wrap));
  1376. }
  1377. static const ahd_reg_parse_entry_t TARGPCISTAT_parse_table[] = {
  1378. { "TWATERR", 0x02, 0x02 },
  1379. { "STA", 0x08, 0x08 },
  1380. { "SSE", 0x40, 0x40 },
  1381. { "DPE", 0x80, 0x80 }
  1382. };
  1383. int
  1384. ahd_targpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1385. {
  1386. return (ahd_print_register(TARGPCISTAT_parse_table, 4, "TARGPCISTAT",
  1387. 0xa7, regvalue, cur_col, wrap));
  1388. }
  1389. int
  1390. ahd_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1391. {
  1392. return (ahd_print_register(NULL, 0, "SCBPTR",
  1393. 0xa8, regvalue, cur_col, wrap));
  1394. }
  1395. static const ahd_reg_parse_entry_t SCBAUTOPTR_parse_table[] = {
  1396. { "SCBPTR_OFF", 0x07, 0x07 },
  1397. { "SCBPTR_ADDR", 0x38, 0x38 },
  1398. { "AUSCBPTR_EN", 0x80, 0x80 }
  1399. };
  1400. int
  1401. ahd_scbautoptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1402. {
  1403. return (ahd_print_register(SCBAUTOPTR_parse_table, 3, "SCBAUTOPTR",
  1404. 0xab, regvalue, cur_col, wrap));
  1405. }
  1406. int
  1407. ahd_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1408. {
  1409. return (ahd_print_register(NULL, 0, "CCSGADDR",
  1410. 0xac, regvalue, cur_col, wrap));
  1411. }
  1412. int
  1413. ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1414. {
  1415. return (ahd_print_register(NULL, 0, "CCSCBADDR",
  1416. 0xac, regvalue, cur_col, wrap));
  1417. }
  1418. static const ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = {
  1419. { "CCSCBRESET", 0x01, 0x01 },
  1420. { "CCSCBDIR", 0x04, 0x04 },
  1421. { "CCSCBEN", 0x08, 0x08 },
  1422. { "CCARREN", 0x10, 0x10 },
  1423. { "ARRDONE", 0x40, 0x40 },
  1424. { "CCSCBDONE", 0x80, 0x80 }
  1425. };
  1426. int
  1427. ahd_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1428. {
  1429. return (ahd_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL",
  1430. 0xad, regvalue, cur_col, wrap));
  1431. }
  1432. static const ahd_reg_parse_entry_t CCSGCTL_parse_table[] = {
  1433. { "CCSGRESET", 0x01, 0x01 },
  1434. { "SG_FETCH_REQ", 0x02, 0x02 },
  1435. { "CCSGENACK", 0x08, 0x08 },
  1436. { "SG_CACHE_AVAIL", 0x10, 0x10 },
  1437. { "CCSGDONE", 0x80, 0x80 },
  1438. { "CCSGEN", 0x0c, 0x0c }
  1439. };
  1440. int
  1441. ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1442. {
  1443. return (ahd_print_register(CCSGCTL_parse_table, 6, "CCSGCTL",
  1444. 0xad, regvalue, cur_col, wrap));
  1445. }
  1446. int
  1447. ahd_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1448. {
  1449. return (ahd_print_register(NULL, 0, "CCSGRAM",
  1450. 0xb0, regvalue, cur_col, wrap));
  1451. }
  1452. int
  1453. ahd_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1454. {
  1455. return (ahd_print_register(NULL, 0, "CCSCBRAM",
  1456. 0xb0, regvalue, cur_col, wrap));
  1457. }
  1458. int
  1459. ahd_brddat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1460. {
  1461. return (ahd_print_register(NULL, 0, "BRDDAT",
  1462. 0xb8, regvalue, cur_col, wrap));
  1463. }
  1464. static const ahd_reg_parse_entry_t BRDCTL_parse_table[] = {
  1465. { "BRDSTB", 0x01, 0x01 },
  1466. { "BRDRW", 0x02, 0x02 },
  1467. { "BRDEN", 0x04, 0x04 },
  1468. { "BRDADDR", 0x38, 0x38 },
  1469. { "FLXARBREQ", 0x40, 0x40 },
  1470. { "FLXARBACK", 0x80, 0x80 }
  1471. };
  1472. int
  1473. ahd_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1474. {
  1475. return (ahd_print_register(BRDCTL_parse_table, 6, "BRDCTL",
  1476. 0xb9, regvalue, cur_col, wrap));
  1477. }
  1478. int
  1479. ahd_seeadr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1480. {
  1481. return (ahd_print_register(NULL, 0, "SEEADR",
  1482. 0xba, regvalue, cur_col, wrap));
  1483. }
  1484. int
  1485. ahd_seedat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1486. {
  1487. return (ahd_print_register(NULL, 0, "SEEDAT",
  1488. 0xbc, regvalue, cur_col, wrap));
  1489. }
  1490. static const ahd_reg_parse_entry_t SEECTL_parse_table[] = {
  1491. { "SEEOP_ERAL", 0x40, 0x70 },
  1492. { "SEEOP_WRITE", 0x50, 0x70 },
  1493. { "SEEOP_READ", 0x60, 0x70 },
  1494. { "SEEOP_ERASE", 0x70, 0x70 },
  1495. { "SEESTART", 0x01, 0x01 },
  1496. { "SEERST", 0x02, 0x02 },
  1497. { "SEEOPCODE", 0x70, 0x70 },
  1498. { "SEEOP_EWEN", 0x40, 0x40 },
  1499. { "SEEOP_WALL", 0x40, 0x40 },
  1500. { "SEEOP_EWDS", 0x40, 0x40 }
  1501. };
  1502. int
  1503. ahd_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1504. {
  1505. return (ahd_print_register(SEECTL_parse_table, 10, "SEECTL",
  1506. 0xbe, regvalue, cur_col, wrap));
  1507. }
  1508. static const ahd_reg_parse_entry_t SEESTAT_parse_table[] = {
  1509. { "SEESTART", 0x01, 0x01 },
  1510. { "SEEBUSY", 0x02, 0x02 },
  1511. { "SEEARBACK", 0x04, 0x04 },
  1512. { "LDALTID_L", 0x08, 0x08 },
  1513. { "SEEOPCODE", 0x70, 0x70 },
  1514. { "INIT_DONE", 0x80, 0x80 }
  1515. };
  1516. int
  1517. ahd_seestat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1518. {
  1519. return (ahd_print_register(SEESTAT_parse_table, 6, "SEESTAT",
  1520. 0xbe, regvalue, cur_col, wrap));
  1521. }
  1522. static const ahd_reg_parse_entry_t DSPDATACTL_parse_table[] = {
  1523. { "XMITOFFSTDIS", 0x02, 0x02 },
  1524. { "RCVROFFSTDIS", 0x04, 0x04 },
  1525. { "DESQDIS", 0x10, 0x10 },
  1526. { "BYPASSENAB", 0x80, 0x80 }
  1527. };
  1528. int
  1529. ahd_dspdatactl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1530. {
  1531. return (ahd_print_register(DSPDATACTL_parse_table, 4, "DSPDATACTL",
  1532. 0xc1, regvalue, cur_col, wrap));
  1533. }
  1534. int
  1535. ahd_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1536. {
  1537. return (ahd_print_register(NULL, 0, "DFDAT",
  1538. 0xc4, regvalue, cur_col, wrap));
  1539. }
  1540. static const ahd_reg_parse_entry_t DSPSELECT_parse_table[] = {
  1541. { "DSPSEL", 0x1f, 0x1f },
  1542. { "AUTOINCEN", 0x80, 0x80 }
  1543. };
  1544. int
  1545. ahd_dspselect_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1546. {
  1547. return (ahd_print_register(DSPSELECT_parse_table, 2, "DSPSELECT",
  1548. 0xc4, regvalue, cur_col, wrap));
  1549. }
  1550. static const ahd_reg_parse_entry_t WRTBIASCTL_parse_table[] = {
  1551. { "XMITMANVAL", 0x3f, 0x3f },
  1552. { "AUTOXBCDIS", 0x80, 0x80 }
  1553. };
  1554. int
  1555. ahd_wrtbiasctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1556. {
  1557. return (ahd_print_register(WRTBIASCTL_parse_table, 2, "WRTBIASCTL",
  1558. 0xc5, regvalue, cur_col, wrap));
  1559. }
  1560. static const ahd_reg_parse_entry_t SEQCTL0_parse_table[] = {
  1561. { "LOADRAM", 0x01, 0x01 },
  1562. { "SEQRESET", 0x02, 0x02 },
  1563. { "STEP", 0x04, 0x04 },
  1564. { "BRKADRINTEN", 0x08, 0x08 },
  1565. { "FASTMODE", 0x10, 0x10 },
  1566. { "FAILDIS", 0x20, 0x20 },
  1567. { "PAUSEDIS", 0x40, 0x40 },
  1568. { "PERRORDIS", 0x80, 0x80 }
  1569. };
  1570. int
  1571. ahd_seqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1572. {
  1573. return (ahd_print_register(SEQCTL0_parse_table, 8, "SEQCTL0",
  1574. 0xd6, regvalue, cur_col, wrap));
  1575. }
  1576. static const ahd_reg_parse_entry_t FLAGS_parse_table[] = {
  1577. { "CARRY", 0x01, 0x01 },
  1578. { "ZERO", 0x02, 0x02 }
  1579. };
  1580. int
  1581. ahd_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1582. {
  1583. return (ahd_print_register(FLAGS_parse_table, 2, "FLAGS",
  1584. 0xd8, regvalue, cur_col, wrap));
  1585. }
  1586. static const ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = {
  1587. { "IRET", 0x01, 0x01 },
  1588. { "INTMASK1", 0x02, 0x02 },
  1589. { "INTMASK2", 0x04, 0x04 },
  1590. { "SCS_SEQ_INT1M0", 0x08, 0x08 },
  1591. { "SCS_SEQ_INT1M1", 0x10, 0x10 },
  1592. { "INT1_CONTEXT", 0x20, 0x20 },
  1593. { "INTVEC1DSL", 0x80, 0x80 }
  1594. };
  1595. int
  1596. ahd_seqintctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1597. {
  1598. return (ahd_print_register(SEQINTCTL_parse_table, 7, "SEQINTCTL",
  1599. 0xd9, regvalue, cur_col, wrap));
  1600. }
  1601. int
  1602. ahd_seqram_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1603. {
  1604. return (ahd_print_register(NULL, 0, "SEQRAM",
  1605. 0xda, regvalue, cur_col, wrap));
  1606. }
  1607. int
  1608. ahd_prgmcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1609. {
  1610. return (ahd_print_register(NULL, 0, "PRGMCNT",
  1611. 0xde, regvalue, cur_col, wrap));
  1612. }
  1613. int
  1614. ahd_accum_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1615. {
  1616. return (ahd_print_register(NULL, 0, "ACCUM",
  1617. 0xe0, regvalue, cur_col, wrap));
  1618. }
  1619. int
  1620. ahd_sindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1621. {
  1622. return (ahd_print_register(NULL, 0, "SINDEX",
  1623. 0xe2, regvalue, cur_col, wrap));
  1624. }
  1625. int
  1626. ahd_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1627. {
  1628. return (ahd_print_register(NULL, 0, "DINDEX",
  1629. 0xe4, regvalue, cur_col, wrap));
  1630. }
  1631. int
  1632. ahd_allones_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1633. {
  1634. return (ahd_print_register(NULL, 0, "ALLONES",
  1635. 0xe8, regvalue, cur_col, wrap));
  1636. }
  1637. int
  1638. ahd_allzeros_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1639. {
  1640. return (ahd_print_register(NULL, 0, "ALLZEROS",
  1641. 0xea, regvalue, cur_col, wrap));
  1642. }
  1643. int
  1644. ahd_none_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1645. {
  1646. return (ahd_print_register(NULL, 0, "NONE",
  1647. 0xea, regvalue, cur_col, wrap));
  1648. }
  1649. int
  1650. ahd_sindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1651. {
  1652. return (ahd_print_register(NULL, 0, "SINDIR",
  1653. 0xec, regvalue, cur_col, wrap));
  1654. }
  1655. int
  1656. ahd_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1657. {
  1658. return (ahd_print_register(NULL, 0, "DINDIR",
  1659. 0xed, regvalue, cur_col, wrap));
  1660. }
  1661. int
  1662. ahd_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1663. {
  1664. return (ahd_print_register(NULL, 0, "STACK",
  1665. 0xf2, regvalue, cur_col, wrap));
  1666. }
  1667. int
  1668. ahd_intvec1_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1669. {
  1670. return (ahd_print_register(NULL, 0, "INTVEC1_ADDR",
  1671. 0xf4, regvalue, cur_col, wrap));
  1672. }
  1673. int
  1674. ahd_curaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1675. {
  1676. return (ahd_print_register(NULL, 0, "CURADDR",
  1677. 0xf4, regvalue, cur_col, wrap));
  1678. }
  1679. int
  1680. ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1681. {
  1682. return (ahd_print_register(NULL, 0, "INTVEC2_ADDR",
  1683. 0xf6, regvalue, cur_col, wrap));
  1684. }
  1685. int
  1686. ahd_longjmp_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1687. {
  1688. return (ahd_print_register(NULL, 0, "LONGJMP_ADDR",
  1689. 0xf8, regvalue, cur_col, wrap));
  1690. }
  1691. int
  1692. ahd_accum_save_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1693. {
  1694. return (ahd_print_register(NULL, 0, "ACCUM_SAVE",
  1695. 0xfa, regvalue, cur_col, wrap));
  1696. }
  1697. int
  1698. ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1699. {
  1700. return (ahd_print_register(NULL, 0, "SRAM_BASE",
  1701. 0x100, regvalue, cur_col, wrap));
  1702. }
  1703. int
  1704. ahd_waiting_scb_tails_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1705. {
  1706. return (ahd_print_register(NULL, 0, "WAITING_SCB_TAILS",
  1707. 0x100, regvalue, cur_col, wrap));
  1708. }
  1709. int
  1710. ahd_waiting_tid_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1711. {
  1712. return (ahd_print_register(NULL, 0, "WAITING_TID_HEAD",
  1713. 0x120, regvalue, cur_col, wrap));
  1714. }
  1715. int
  1716. ahd_waiting_tid_tail_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1717. {
  1718. return (ahd_print_register(NULL, 0, "WAITING_TID_TAIL",
  1719. 0x122, regvalue, cur_col, wrap));
  1720. }
  1721. int
  1722. ahd_next_queued_scb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1723. {
  1724. return (ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR",
  1725. 0x124, regvalue, cur_col, wrap));
  1726. }
  1727. int
  1728. ahd_complete_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1729. {
  1730. return (ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD",
  1731. 0x128, regvalue, cur_col, wrap));
  1732. }
  1733. int
  1734. ahd_complete_scb_dmainprog_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1735. {
  1736. return (ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD",
  1737. 0x12a, regvalue, cur_col, wrap));
  1738. }
  1739. int
  1740. ahd_complete_dma_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1741. {
  1742. return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD",
  1743. 0x12c, regvalue, cur_col, wrap));
  1744. }
  1745. int
  1746. ahd_complete_dma_scb_tail_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1747. {
  1748. return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL",
  1749. 0x12e, regvalue, cur_col, wrap));
  1750. }
  1751. int
  1752. ahd_complete_on_qfreeze_head_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1753. {
  1754. return (ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD",
  1755. 0x130, regvalue, cur_col, wrap));
  1756. }
  1757. int
  1758. ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1759. {
  1760. return (ahd_print_register(NULL, 0, "QFREEZE_COUNT",
  1761. 0x132, regvalue, cur_col, wrap));
  1762. }
  1763. int
  1764. ahd_kernel_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1765. {
  1766. return (ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT",
  1767. 0x134, regvalue, cur_col, wrap));
  1768. }
  1769. int
  1770. ahd_saved_mode_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1771. {
  1772. return (ahd_print_register(NULL, 0, "SAVED_MODE",
  1773. 0x136, regvalue, cur_col, wrap));
  1774. }
  1775. int
  1776. ahd_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1777. {
  1778. return (ahd_print_register(NULL, 0, "MSG_OUT",
  1779. 0x137, regvalue, cur_col, wrap));
  1780. }
  1781. static const ahd_reg_parse_entry_t DMAPARAMS_parse_table[] = {
  1782. { "FIFORESET", 0x01, 0x01 },
  1783. { "FIFOFLUSH", 0x02, 0x02 },
  1784. { "DIRECTION", 0x04, 0x04 },
  1785. { "HDMAEN", 0x08, 0x08 },
  1786. { "HDMAENACK", 0x08, 0x08 },
  1787. { "SDMAEN", 0x10, 0x10 },
  1788. { "SDMAENACK", 0x10, 0x10 },
  1789. { "SCSIEN", 0x20, 0x20 },
  1790. { "WIDEODD", 0x40, 0x40 },
  1791. { "PRELOADEN", 0x80, 0x80 }
  1792. };
  1793. int
  1794. ahd_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1795. {
  1796. return (ahd_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS",
  1797. 0x138, regvalue, cur_col, wrap));
  1798. }
  1799. static const ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
  1800. { "NO_DISCONNECT", 0x01, 0x01 },
  1801. { "SPHASE_PENDING", 0x02, 0x02 },
  1802. { "DPHASE_PENDING", 0x04, 0x04 },
  1803. { "CMDPHASE_PENDING", 0x08, 0x08 },
  1804. { "TARG_CMD_PENDING", 0x10, 0x10 },
  1805. { "DPHASE", 0x20, 0x20 },
  1806. { "NO_CDB_SENT", 0x40, 0x40 },
  1807. { "TARGET_CMD_IS_TAGGED",0x40, 0x40 },
  1808. { "NOT_IDENTIFIED", 0x80, 0x80 }
  1809. };
  1810. int
  1811. ahd_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1812. {
  1813. return (ahd_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS",
  1814. 0x139, regvalue, cur_col, wrap));
  1815. }
  1816. int
  1817. ahd_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1818. {
  1819. return (ahd_print_register(NULL, 0, "SAVED_SCSIID",
  1820. 0x13a, regvalue, cur_col, wrap));
  1821. }
  1822. int
  1823. ahd_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1824. {
  1825. return (ahd_print_register(NULL, 0, "SAVED_LUN",
  1826. 0x13b, regvalue, cur_col, wrap));
  1827. }
  1828. static const ahd_reg_parse_entry_t LASTPHASE_parse_table[] = {
  1829. { "P_DATAOUT", 0x00, 0xe0 },
  1830. { "P_DATAOUT_DT", 0x20, 0xe0 },
  1831. { "P_DATAIN", 0x40, 0xe0 },
  1832. { "P_DATAIN_DT", 0x60, 0xe0 },
  1833. { "P_COMMAND", 0x80, 0xe0 },
  1834. { "P_MESGOUT", 0xa0, 0xe0 },
  1835. { "P_STATUS", 0xc0, 0xe0 },
  1836. { "P_MESGIN", 0xe0, 0xe0 },
  1837. { "P_BUSFREE", 0x01, 0x01 },
  1838. { "MSGI", 0x20, 0x20 },
  1839. { "IOI", 0x40, 0x40 },
  1840. { "CDI", 0x80, 0x80 },
  1841. { "PHASE_MASK", 0xe0, 0xe0 }
  1842. };
  1843. int
  1844. ahd_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1845. {
  1846. return (ahd_print_register(LASTPHASE_parse_table, 13, "LASTPHASE",
  1847. 0x13c, regvalue, cur_col, wrap));
  1848. }
  1849. int
  1850. ahd_qoutfifo_entry_valid_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1851. {
  1852. return (ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG",
  1853. 0x13d, regvalue, cur_col, wrap));
  1854. }
  1855. int
  1856. ahd_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1857. {
  1858. return (ahd_print_register(NULL, 0, "KERNEL_TQINPOS",
  1859. 0x13e, regvalue, cur_col, wrap));
  1860. }
  1861. int
  1862. ahd_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1863. {
  1864. return (ahd_print_register(NULL, 0, "TQINPOS",
  1865. 0x13f, regvalue, cur_col, wrap));
  1866. }
  1867. int
  1868. ahd_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1869. {
  1870. return (ahd_print_register(NULL, 0, "SHARED_DATA_ADDR",
  1871. 0x140, regvalue, cur_col, wrap));
  1872. }
  1873. int
  1874. ahd_qoutfifo_next_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1875. {
  1876. return (ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR",
  1877. 0x144, regvalue, cur_col, wrap));
  1878. }
  1879. static const ahd_reg_parse_entry_t ARG_1_parse_table[] = {
  1880. { "CONT_MSG_LOOP_TARG", 0x02, 0x02 },
  1881. { "CONT_MSG_LOOP_READ", 0x03, 0x03 },
  1882. { "CONT_MSG_LOOP_WRITE",0x04, 0x04 },
  1883. { "EXIT_MSG_LOOP", 0x08, 0x08 },
  1884. { "MSGOUT_PHASEMIS", 0x10, 0x10 },
  1885. { "SEND_REJ", 0x20, 0x20 },
  1886. { "SEND_SENSE", 0x40, 0x40 },
  1887. { "SEND_MSG", 0x80, 0x80 }
  1888. };
  1889. int
  1890. ahd_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1891. {
  1892. return (ahd_print_register(ARG_1_parse_table, 8, "ARG_1",
  1893. 0x148, regvalue, cur_col, wrap));
  1894. }
  1895. int
  1896. ahd_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1897. {
  1898. return (ahd_print_register(NULL, 0, "ARG_2",
  1899. 0x149, regvalue, cur_col, wrap));
  1900. }
  1901. int
  1902. ahd_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1903. {
  1904. return (ahd_print_register(NULL, 0, "LAST_MSG",
  1905. 0x14a, regvalue, cur_col, wrap));
  1906. }
  1907. static const ahd_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
  1908. { "ALTSTIM", 0x01, 0x01 },
  1909. { "ENAUTOATNP", 0x02, 0x02 },
  1910. { "MANUALP", 0x0c, 0x0c },
  1911. { "ENRSELI", 0x10, 0x10 },
  1912. { "ENSELI", 0x20, 0x20 },
  1913. { "MANUALCTL", 0x40, 0x40 }
  1914. };
  1915. int
  1916. ahd_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1917. {
  1918. return (ahd_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE",
  1919. 0x14b, regvalue, cur_col, wrap));
  1920. }
  1921. int
  1922. ahd_initiator_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1923. {
  1924. return (ahd_print_register(NULL, 0, "INITIATOR_TAG",
  1925. 0x14c, regvalue, cur_col, wrap));
  1926. }
  1927. static const ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
  1928. { "PENDING_MK_MESSAGE", 0x01, 0x01 },
  1929. { "TARGET_MSG_PENDING", 0x02, 0x02 },
  1930. { "SELECTOUT_QFROZEN", 0x04, 0x04 }
  1931. };
  1932. int
  1933. ahd_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1934. {
  1935. return (ahd_print_register(SEQ_FLAGS2_parse_table, 3, "SEQ_FLAGS2",
  1936. 0x14d, regvalue, cur_col, wrap));
  1937. }
  1938. int
  1939. ahd_allocfifo_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1940. {
  1941. return (ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR",
  1942. 0x14e, regvalue, cur_col, wrap));
  1943. }
  1944. int
  1945. ahd_int_coalescing_timer_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1946. {
  1947. return (ahd_print_register(NULL, 0, "INT_COALESCING_TIMER",
  1948. 0x150, regvalue, cur_col, wrap));
  1949. }
  1950. int
  1951. ahd_int_coalescing_maxcmds_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1952. {
  1953. return (ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS",
  1954. 0x152, regvalue, cur_col, wrap));
  1955. }
  1956. int
  1957. ahd_int_coalescing_mincmds_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1958. {
  1959. return (ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS",
  1960. 0x153, regvalue, cur_col, wrap));
  1961. }
  1962. int
  1963. ahd_cmds_pending_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1964. {
  1965. return (ahd_print_register(NULL, 0, "CMDS_PENDING",
  1966. 0x154, regvalue, cur_col, wrap));
  1967. }
  1968. int
  1969. ahd_int_coalescing_cmdcount_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1970. {
  1971. return (ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT",
  1972. 0x156, regvalue, cur_col, wrap));
  1973. }
  1974. int
  1975. ahd_local_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1976. {
  1977. return (ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX",
  1978. 0x157, regvalue, cur_col, wrap));
  1979. }
  1980. int
  1981. ahd_cmdsize_table_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1982. {
  1983. return (ahd_print_register(NULL, 0, "CMDSIZE_TABLE",
  1984. 0x158, regvalue, cur_col, wrap));
  1985. }
  1986. int
  1987. ahd_mk_message_scb_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1988. {
  1989. return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCB",
  1990. 0x160, regvalue, cur_col, wrap));
  1991. }
  1992. int
  1993. ahd_mk_message_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  1994. {
  1995. return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID",
  1996. 0x162, regvalue, cur_col, wrap));
  1997. }
  1998. int
  1999. ahd_scb_residual_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2000. {
  2001. return (ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT",
  2002. 0x180, regvalue, cur_col, wrap));
  2003. }
  2004. int
  2005. ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2006. {
  2007. return (ahd_print_register(NULL, 0, "SCB_BASE",
  2008. 0x180, regvalue, cur_col, wrap));
  2009. }
  2010. static const ahd_reg_parse_entry_t SCB_RESIDUAL_SGPTR_parse_table[] = {
  2011. { "SG_LIST_NULL", 0x01, 0x01 },
  2012. { "SG_OVERRUN_RESID", 0x02, 0x02 },
  2013. { "SG_ADDR_MASK", 0xf8, 0xf8 }
  2014. };
  2015. int
  2016. ahd_scb_residual_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2017. {
  2018. return (ahd_print_register(SCB_RESIDUAL_SGPTR_parse_table, 3, "SCB_RESIDUAL_SGPTR",
  2019. 0x184, regvalue, cur_col, wrap));
  2020. }
  2021. int
  2022. ahd_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2023. {
  2024. return (ahd_print_register(NULL, 0, "SCB_SCSI_STATUS",
  2025. 0x188, regvalue, cur_col, wrap));
  2026. }
  2027. int
  2028. ahd_scb_sense_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2029. {
  2030. return (ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR",
  2031. 0x18c, regvalue, cur_col, wrap));
  2032. }
  2033. int
  2034. ahd_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2035. {
  2036. return (ahd_print_register(NULL, 0, "SCB_TAG",
  2037. 0x190, regvalue, cur_col, wrap));
  2038. }
  2039. static const ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
  2040. { "SCB_TAG_TYPE", 0x03, 0x03 },
  2041. { "DISCONNECTED", 0x04, 0x04 },
  2042. { "STATUS_RCVD", 0x08, 0x08 },
  2043. { "MK_MESSAGE", 0x10, 0x10 },
  2044. { "TAG_ENB", 0x20, 0x20 },
  2045. { "DISCENB", 0x40, 0x40 },
  2046. { "TARGET_SCB", 0x80, 0x80 }
  2047. };
  2048. int
  2049. ahd_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2050. {
  2051. return (ahd_print_register(SCB_CONTROL_parse_table, 7, "SCB_CONTROL",
  2052. 0x192, regvalue, cur_col, wrap));
  2053. }
  2054. static const ahd_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
  2055. { "OID", 0x0f, 0x0f },
  2056. { "TID", 0xf0, 0xf0 }
  2057. };
  2058. int
  2059. ahd_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2060. {
  2061. return (ahd_print_register(SCB_SCSIID_parse_table, 2, "SCB_SCSIID",
  2062. 0x193, regvalue, cur_col, wrap));
  2063. }
  2064. static const ahd_reg_parse_entry_t SCB_LUN_parse_table[] = {
  2065. { "LID", 0xff, 0xff }
  2066. };
  2067. int
  2068. ahd_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2069. {
  2070. return (ahd_print_register(SCB_LUN_parse_table, 1, "SCB_LUN",
  2071. 0x194, regvalue, cur_col, wrap));
  2072. }
  2073. static const ahd_reg_parse_entry_t SCB_TASK_ATTRIBUTE_parse_table[] = {
  2074. { "SCB_XFERLEN_ODD", 0x01, 0x01 }
  2075. };
  2076. int
  2077. ahd_scb_task_attribute_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2078. {
  2079. return (ahd_print_register(SCB_TASK_ATTRIBUTE_parse_table, 1, "SCB_TASK_ATTRIBUTE",
  2080. 0x195, regvalue, cur_col, wrap));
  2081. }
  2082. static const ahd_reg_parse_entry_t SCB_CDB_LEN_parse_table[] = {
  2083. { "SCB_CDB_LEN_PTR", 0x80, 0x80 }
  2084. };
  2085. int
  2086. ahd_scb_cdb_len_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2087. {
  2088. return (ahd_print_register(SCB_CDB_LEN_parse_table, 1, "SCB_CDB_LEN",
  2089. 0x196, regvalue, cur_col, wrap));
  2090. }
  2091. int
  2092. ahd_scb_task_management_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2093. {
  2094. return (ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT",
  2095. 0x197, regvalue, cur_col, wrap));
  2096. }
  2097. int
  2098. ahd_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2099. {
  2100. return (ahd_print_register(NULL, 0, "SCB_DATAPTR",
  2101. 0x198, regvalue, cur_col, wrap));
  2102. }
  2103. static const ahd_reg_parse_entry_t SCB_DATACNT_parse_table[] = {
  2104. { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f },
  2105. { "SG_LAST_SEG", 0x80, 0x80 }
  2106. };
  2107. int
  2108. ahd_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2109. {
  2110. return (ahd_print_register(SCB_DATACNT_parse_table, 2, "SCB_DATACNT",
  2111. 0x1a0, regvalue, cur_col, wrap));
  2112. }
  2113. static const ahd_reg_parse_entry_t SCB_SGPTR_parse_table[] = {
  2114. { "SG_LIST_NULL", 0x01, 0x01 },
  2115. { "SG_FULL_RESID", 0x02, 0x02 },
  2116. { "SG_STATUS_VALID", 0x04, 0x04 }
  2117. };
  2118. int
  2119. ahd_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2120. {
  2121. return (ahd_print_register(SCB_SGPTR_parse_table, 3, "SCB_SGPTR",
  2122. 0x1a4, regvalue, cur_col, wrap));
  2123. }
  2124. int
  2125. ahd_scb_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2126. {
  2127. return (ahd_print_register(NULL, 0, "SCB_BUSADDR",
  2128. 0x1a8, regvalue, cur_col, wrap));
  2129. }
  2130. int
  2131. ahd_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2132. {
  2133. return (ahd_print_register(NULL, 0, "SCB_NEXT",
  2134. 0x1ac, regvalue, cur_col, wrap));
  2135. }
  2136. int
  2137. ahd_scb_next2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2138. {
  2139. return (ahd_print_register(NULL, 0, "SCB_NEXT2",
  2140. 0x1ae, regvalue, cur_col, wrap));
  2141. }
  2142. int
  2143. ahd_scb_disconnected_lists_print(u_int regvalue, u_int *cur_col, u_int wrap)
  2144. {
  2145. return (ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS",
  2146. 0x1b8, regvalue, cur_col, wrap));
  2147. }