mpc8349emitx.dts 7.2 KB

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  1. /*
  2. * MPC8349E-mITX Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMITX";
  14. compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. PowerPC,8349@0 {
  29. device_type = "cpu";
  30. reg = <0x0>;
  31. d-cache-line-size = <32>;
  32. i-cache-line-size = <32>;
  33. d-cache-size = <32768>;
  34. i-cache-size = <32768>;
  35. timebase-frequency = <0>; // from bootloader
  36. bus-frequency = <0>; // from bootloader
  37. clock-frequency = <0>; // from bootloader
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x10000000>;
  43. };
  44. soc8349@e0000000 {
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. device_type = "soc";
  48. compatible = "simple-bus";
  49. ranges = <0x0 0xe0000000 0x00100000>;
  50. reg = <0xe0000000 0x00000200>;
  51. bus-frequency = <0>; // from bootloader
  52. wdt@200 {
  53. device_type = "watchdog";
  54. compatible = "mpc83xx_wdt";
  55. reg = <0x200 0x100>;
  56. };
  57. i2c@3000 {
  58. #address-cells = <1>;
  59. #size-cells = <0>;
  60. cell-index = <0>;
  61. compatible = "fsl-i2c";
  62. reg = <0x3000 0x100>;
  63. interrupts = <14 0x8>;
  64. interrupt-parent = <&ipic>;
  65. dfsrr;
  66. };
  67. i2c@3100 {
  68. #address-cells = <1>;
  69. #size-cells = <0>;
  70. cell-index = <1>;
  71. compatible = "fsl-i2c";
  72. reg = <0x3100 0x100>;
  73. interrupts = <15 0x8>;
  74. interrupt-parent = <&ipic>;
  75. dfsrr;
  76. };
  77. spi@7000 {
  78. cell-index = <0>;
  79. compatible = "fsl,spi";
  80. reg = <0x7000 0x1000>;
  81. interrupts = <16 0x8>;
  82. interrupt-parent = <&ipic>;
  83. mode = "cpu";
  84. };
  85. dma@82a8 {
  86. #address-cells = <1>;
  87. #size-cells = <1>;
  88. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  89. reg = <0x82a8 4>;
  90. ranges = <0 0x8100 0x1a8>;
  91. interrupt-parent = <&ipic>;
  92. interrupts = <71 8>;
  93. cell-index = <0>;
  94. dma-channel@0 {
  95. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  96. reg = <0 0x80>;
  97. cell-index = <0>;
  98. interrupt-parent = <&ipic>;
  99. interrupts = <71 8>;
  100. };
  101. dma-channel@80 {
  102. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  103. reg = <0x80 0x80>;
  104. cell-index = <1>;
  105. interrupt-parent = <&ipic>;
  106. interrupts = <71 8>;
  107. };
  108. dma-channel@100 {
  109. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  110. reg = <0x100 0x80>;
  111. cell-index = <2>;
  112. interrupt-parent = <&ipic>;
  113. interrupts = <71 8>;
  114. };
  115. dma-channel@180 {
  116. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  117. reg = <0x180 0x28>;
  118. cell-index = <3>;
  119. interrupt-parent = <&ipic>;
  120. interrupts = <71 8>;
  121. };
  122. };
  123. usb@22000 {
  124. compatible = "fsl-usb2-mph";
  125. reg = <0x22000 0x1000>;
  126. #address-cells = <1>;
  127. #size-cells = <0>;
  128. interrupt-parent = <&ipic>;
  129. interrupts = <39 0x8>;
  130. phy_type = "ulpi";
  131. port1;
  132. };
  133. usb@23000 {
  134. compatible = "fsl-usb2-dr";
  135. reg = <0x23000 0x1000>;
  136. #address-cells = <1>;
  137. #size-cells = <0>;
  138. interrupt-parent = <&ipic>;
  139. interrupts = <38 0x8>;
  140. dr_mode = "peripheral";
  141. phy_type = "ulpi";
  142. };
  143. mdio@24520 {
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. compatible = "fsl,gianfar-mdio";
  147. reg = <0x24520 0x20>;
  148. /* Vitesse 8201 */
  149. phy1c: ethernet-phy@1c {
  150. interrupt-parent = <&ipic>;
  151. interrupts = <18 0x8>;
  152. reg = <0x1c>;
  153. device_type = "ethernet-phy";
  154. };
  155. };
  156. enet0: ethernet@24000 {
  157. cell-index = <0>;
  158. device_type = "network";
  159. model = "TSEC";
  160. compatible = "gianfar";
  161. reg = <0x24000 0x1000>;
  162. local-mac-address = [ 00 00 00 00 00 00 ];
  163. interrupts = <32 0x8 33 0x8 34 0x8>;
  164. interrupt-parent = <&ipic>;
  165. phy-handle = <&phy1c>;
  166. linux,network-index = <0>;
  167. };
  168. enet1: ethernet@25000 {
  169. cell-index = <1>;
  170. device_type = "network";
  171. model = "TSEC";
  172. compatible = "gianfar";
  173. reg = <0x25000 0x1000>;
  174. local-mac-address = [ 00 00 00 00 00 00 ];
  175. interrupts = <35 0x8 36 0x8 37 0x8>;
  176. interrupt-parent = <&ipic>;
  177. /* Vitesse 7385 isn't on the MDIO bus */
  178. fixed-link = <1 1 1000 0 0>;
  179. linux,network-index = <1>;
  180. };
  181. serial0: serial@4500 {
  182. cell-index = <0>;
  183. device_type = "serial";
  184. compatible = "ns16550";
  185. reg = <0x4500 0x100>;
  186. clock-frequency = <0>; // from bootloader
  187. interrupts = <9 0x8>;
  188. interrupt-parent = <&ipic>;
  189. };
  190. serial1: serial@4600 {
  191. cell-index = <1>;
  192. device_type = "serial";
  193. compatible = "ns16550";
  194. reg = <0x4600 0x100>;
  195. clock-frequency = <0>; // from bootloader
  196. interrupts = <10 0x8>;
  197. interrupt-parent = <&ipic>;
  198. };
  199. crypto@30000 {
  200. compatible = "fsl,sec2.0";
  201. reg = <0x30000 0x10000>;
  202. interrupts = <11 0x8>;
  203. interrupt-parent = <&ipic>;
  204. fsl,num-channels = <4>;
  205. fsl,channel-fifo-len = <24>;
  206. fsl,exec-units-mask = <0x7e>;
  207. fsl,descriptor-types-mask = <0x01010ebf>;
  208. };
  209. ipic: pic@700 {
  210. interrupt-controller;
  211. #address-cells = <0>;
  212. #interrupt-cells = <2>;
  213. reg = <0x700 0x100>;
  214. device_type = "ipic";
  215. };
  216. };
  217. pci0: pci@e0008500 {
  218. cell-index = <1>;
  219. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  220. interrupt-map = <
  221. /* IDSEL 0x10 - SATA */
  222. 0x8000 0x0 0x0 0x1 &ipic 22 0x8 /* SATA_INTA */
  223. >;
  224. interrupt-parent = <&ipic>;
  225. interrupts = <66 0x8>;
  226. bus-range = <0x0 0x0>;
  227. ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  228. 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  229. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
  230. clock-frequency = <66666666>;
  231. #interrupt-cells = <1>;
  232. #size-cells = <2>;
  233. #address-cells = <3>;
  234. reg = <0xe0008500 0x100 /* internal registers */
  235. 0xe0008300 0x8>; /* config space access registers */
  236. compatible = "fsl,mpc8349-pci";
  237. device_type = "pci";
  238. };
  239. pci1: pci@e0008600 {
  240. cell-index = <2>;
  241. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  242. interrupt-map = <
  243. /* IDSEL 0x0E - MiniPCI Slot */
  244. 0x7000 0x0 0x0 0x1 &ipic 21 0x8 /* PCI_INTA */
  245. /* IDSEL 0x0F - PCI Slot */
  246. 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
  247. 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
  248. >;
  249. interrupt-parent = <&ipic>;
  250. interrupts = <67 0x8>;
  251. bus-range = <0x0 0x0>;
  252. ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  253. 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  254. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
  255. clock-frequency = <66666666>;
  256. #interrupt-cells = <1>;
  257. #size-cells = <2>;
  258. #address-cells = <3>;
  259. reg = <0xe0008600 0x100 /* internal registers */
  260. 0xe0008380 0x8>; /* config space access registers */
  261. compatible = "fsl,mpc8349-pci";
  262. device_type = "pci";
  263. };
  264. localbus@e0005000 {
  265. #address-cells = <2>;
  266. #size-cells = <1>;
  267. compatible = "fsl,mpc8349e-localbus",
  268. "fsl,pq2pro-localbus";
  269. reg = <0xe0005000 0xd8>;
  270. ranges = <0x3 0x0 0xf0000000 0x210>;
  271. pata@3,0 {
  272. compatible = "fsl,mpc8349emitx-pata", "ata-generic";
  273. reg = <0x3 0x0 0x10 0x3 0x20c 0x4>;
  274. reg-shift = <1>;
  275. pio-mode = <6>;
  276. interrupts = <23 0x8>;
  277. interrupt-parent = <&ipic>;
  278. };
  279. };
  280. };