mce.c 33 KB

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  1. /*
  2. * Machine check handler.
  3. *
  4. * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
  5. * Rest from unknown author(s).
  6. * 2004 Andi Kleen. Rewrote most of it.
  7. * Copyright 2008 Intel Corporation
  8. * Author: Andi Kleen
  9. */
  10. #include <linux/thread_info.h>
  11. #include <linux/capability.h>
  12. #include <linux/miscdevice.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/ratelimit.h>
  15. #include <linux/kallsyms.h>
  16. #include <linux/rcupdate.h>
  17. #include <linux/kobject.h>
  18. #include <linux/uaccess.h>
  19. #include <linux/kdebug.h>
  20. #include <linux/kernel.h>
  21. #include <linux/percpu.h>
  22. #include <linux/string.h>
  23. #include <linux/sysdev.h>
  24. #include <linux/ctype.h>
  25. #include <linux/sched.h>
  26. #include <linux/sysfs.h>
  27. #include <linux/types.h>
  28. #include <linux/init.h>
  29. #include <linux/kmod.h>
  30. #include <linux/poll.h>
  31. #include <linux/cpu.h>
  32. #include <linux/smp.h>
  33. #include <linux/fs.h>
  34. #include <asm/processor.h>
  35. #include <asm/hw_irq.h>
  36. #include <asm/apic.h>
  37. #include <asm/idle.h>
  38. #include <asm/ipi.h>
  39. #include <asm/mce.h>
  40. #include <asm/msr.h>
  41. #include "mce-internal.h"
  42. #include "mce.h"
  43. /* Handle unconfigured int18 (should never happen) */
  44. static void unexpected_machine_check(struct pt_regs *regs, long error_code)
  45. {
  46. printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
  47. smp_processor_id());
  48. }
  49. /* Call the installed machine check handler for this CPU setup. */
  50. void (*machine_check_vector)(struct pt_regs *, long error_code) =
  51. unexpected_machine_check;
  52. int mce_disabled;
  53. #ifdef CONFIG_X86_NEW_MCE
  54. #define MISC_MCELOG_MINOR 227
  55. atomic_t mce_entry;
  56. DEFINE_PER_CPU(unsigned, mce_exception_count);
  57. /*
  58. * Tolerant levels:
  59. * 0: always panic on uncorrected errors, log corrected errors
  60. * 1: panic or SIGBUS on uncorrected errors, log corrected errors
  61. * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
  62. * 3: never panic or SIGBUS, log all errors (for testing only)
  63. */
  64. static int tolerant = 1;
  65. static int banks;
  66. static u64 *bank;
  67. static unsigned long notify_user;
  68. static int rip_msr;
  69. static int mce_bootlog = -1;
  70. static char trigger[128];
  71. static char *trigger_argv[2] = { trigger, NULL };
  72. static unsigned long dont_init_banks;
  73. static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
  74. /* MCA banks polled by the period polling timer for corrected events */
  75. DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
  76. [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
  77. };
  78. static inline int skip_bank_init(int i)
  79. {
  80. return i < BITS_PER_LONG && test_bit(i, &dont_init_banks);
  81. }
  82. /* Do initial initialization of a struct mce */
  83. void mce_setup(struct mce *m)
  84. {
  85. memset(m, 0, sizeof(struct mce));
  86. m->cpu = m->extcpu = smp_processor_id();
  87. rdtscll(m->tsc);
  88. /* We hope get_seconds stays lockless */
  89. m->time = get_seconds();
  90. m->cpuvendor = boot_cpu_data.x86_vendor;
  91. m->cpuid = cpuid_eax(1);
  92. #ifdef CONFIG_SMP
  93. m->socketid = cpu_data(m->extcpu).phys_proc_id;
  94. #endif
  95. m->apicid = cpu_data(m->extcpu).initial_apicid;
  96. rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
  97. }
  98. DEFINE_PER_CPU(struct mce, injectm);
  99. EXPORT_PER_CPU_SYMBOL_GPL(injectm);
  100. /*
  101. * Lockless MCE logging infrastructure.
  102. * This avoids deadlocks on printk locks without having to break locks. Also
  103. * separate MCEs from kernel messages to avoid bogus bug reports.
  104. */
  105. static struct mce_log mcelog = {
  106. .signature = MCE_LOG_SIGNATURE,
  107. .len = MCE_LOG_LEN,
  108. .recordlen = sizeof(struct mce),
  109. };
  110. void mce_log(struct mce *mce)
  111. {
  112. unsigned next, entry;
  113. mce->finished = 0;
  114. wmb();
  115. for (;;) {
  116. entry = rcu_dereference(mcelog.next);
  117. for (;;) {
  118. /*
  119. * When the buffer fills up discard new entries.
  120. * Assume that the earlier errors are the more
  121. * interesting ones:
  122. */
  123. if (entry >= MCE_LOG_LEN) {
  124. set_bit(MCE_OVERFLOW,
  125. (unsigned long *)&mcelog.flags);
  126. return;
  127. }
  128. /* Old left over entry. Skip: */
  129. if (mcelog.entry[entry].finished) {
  130. entry++;
  131. continue;
  132. }
  133. break;
  134. }
  135. smp_rmb();
  136. next = entry + 1;
  137. if (cmpxchg(&mcelog.next, entry, next) == entry)
  138. break;
  139. }
  140. memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
  141. wmb();
  142. mcelog.entry[entry].finished = 1;
  143. wmb();
  144. mce->finished = 1;
  145. set_bit(0, &notify_user);
  146. }
  147. static void print_mce(struct mce *m)
  148. {
  149. printk(KERN_EMERG "\n"
  150. KERN_EMERG "HARDWARE ERROR\n"
  151. KERN_EMERG
  152. "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
  153. m->extcpu, m->mcgstatus, m->bank, m->status);
  154. if (m->ip) {
  155. printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
  156. !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
  157. m->cs, m->ip);
  158. if (m->cs == __KERNEL_CS)
  159. print_symbol("{%s}", m->ip);
  160. printk("\n");
  161. }
  162. printk(KERN_EMERG "TSC %llx ", m->tsc);
  163. if (m->addr)
  164. printk("ADDR %llx ", m->addr);
  165. if (m->misc)
  166. printk("MISC %llx ", m->misc);
  167. printk("\n");
  168. printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
  169. m->cpuvendor, m->cpuid, m->time, m->socketid,
  170. m->apicid);
  171. printk(KERN_EMERG "This is not a software problem!\n");
  172. printk(KERN_EMERG "Run through mcelog --ascii to decode "
  173. "and contact your hardware vendor\n");
  174. }
  175. #define PANIC_TIMEOUT 5 /* 5 seconds */
  176. static atomic_t mce_paniced;
  177. /* Panic in progress. Enable interrupts and wait for final IPI */
  178. static void wait_for_panic(void)
  179. {
  180. long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
  181. preempt_disable();
  182. local_irq_enable();
  183. while (timeout-- > 0)
  184. udelay(1);
  185. panic("Panicing machine check CPU died");
  186. }
  187. static void mce_panic(char *msg, struct mce *final, char *exp)
  188. {
  189. int i;
  190. /*
  191. * Make sure only one CPU runs in machine check panic
  192. */
  193. if (atomic_add_return(1, &mce_paniced) > 1)
  194. wait_for_panic();
  195. barrier();
  196. bust_spinlocks(1);
  197. console_verbose();
  198. /* First print corrected ones that are still unlogged */
  199. for (i = 0; i < MCE_LOG_LEN; i++) {
  200. struct mce *m = &mcelog.entry[i];
  201. if ((m->status & MCI_STATUS_VAL) &&
  202. !(m->status & MCI_STATUS_UC))
  203. print_mce(m);
  204. }
  205. /* Now print uncorrected but with the final one last */
  206. for (i = 0; i < MCE_LOG_LEN; i++) {
  207. struct mce *m = &mcelog.entry[i];
  208. if (!(m->status & MCI_STATUS_VAL))
  209. continue;
  210. if (!final || memcmp(m, final, sizeof(struct mce)))
  211. print_mce(m);
  212. }
  213. if (final)
  214. print_mce(final);
  215. if (exp)
  216. printk(KERN_EMERG "Machine check: %s\n", exp);
  217. panic(msg);
  218. }
  219. /* Support code for software error injection */
  220. static int msr_to_offset(u32 msr)
  221. {
  222. unsigned bank = __get_cpu_var(injectm.bank);
  223. if (msr == rip_msr)
  224. return offsetof(struct mce, ip);
  225. if (msr == MSR_IA32_MC0_STATUS + bank*4)
  226. return offsetof(struct mce, status);
  227. if (msr == MSR_IA32_MC0_ADDR + bank*4)
  228. return offsetof(struct mce, addr);
  229. if (msr == MSR_IA32_MC0_MISC + bank*4)
  230. return offsetof(struct mce, misc);
  231. if (msr == MSR_IA32_MCG_STATUS)
  232. return offsetof(struct mce, mcgstatus);
  233. return -1;
  234. }
  235. /* MSR access wrappers used for error injection */
  236. static u64 mce_rdmsrl(u32 msr)
  237. {
  238. u64 v;
  239. if (__get_cpu_var(injectm).finished) {
  240. int offset = msr_to_offset(msr);
  241. if (offset < 0)
  242. return 0;
  243. return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
  244. }
  245. rdmsrl(msr, v);
  246. return v;
  247. }
  248. static void mce_wrmsrl(u32 msr, u64 v)
  249. {
  250. if (__get_cpu_var(injectm).finished) {
  251. int offset = msr_to_offset(msr);
  252. if (offset >= 0)
  253. *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
  254. return;
  255. }
  256. wrmsrl(msr, v);
  257. }
  258. int mce_available(struct cpuinfo_x86 *c)
  259. {
  260. if (mce_disabled)
  261. return 0;
  262. return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
  263. }
  264. static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
  265. {
  266. if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) {
  267. m->ip = regs->ip;
  268. m->cs = regs->cs;
  269. } else {
  270. m->ip = 0;
  271. m->cs = 0;
  272. }
  273. if (rip_msr) {
  274. /* Assume the RIP in the MSR is exact. Is this true? */
  275. m->mcgstatus |= MCG_STATUS_EIPV;
  276. m->ip = mce_rdmsrl(rip_msr);
  277. m->cs = 0;
  278. }
  279. }
  280. #ifdef CONFIG_X86_LOCAL_APIC
  281. /*
  282. * Called after interrupts have been reenabled again
  283. * when a MCE happened during an interrupts off region
  284. * in the kernel.
  285. */
  286. asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
  287. {
  288. ack_APIC_irq();
  289. exit_idle();
  290. irq_enter();
  291. mce_notify_user();
  292. irq_exit();
  293. }
  294. #endif
  295. static void mce_report_event(struct pt_regs *regs)
  296. {
  297. if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
  298. mce_notify_user();
  299. return;
  300. }
  301. #ifdef CONFIG_X86_LOCAL_APIC
  302. /*
  303. * Without APIC do not notify. The event will be picked
  304. * up eventually.
  305. */
  306. if (!cpu_has_apic)
  307. return;
  308. /*
  309. * When interrupts are disabled we cannot use
  310. * kernel services safely. Trigger an self interrupt
  311. * through the APIC to instead do the notification
  312. * after interrupts are reenabled again.
  313. */
  314. apic->send_IPI_self(MCE_SELF_VECTOR);
  315. /*
  316. * Wait for idle afterwards again so that we don't leave the
  317. * APIC in a non idle state because the normal APIC writes
  318. * cannot exclude us.
  319. */
  320. apic_wait_icr_idle();
  321. #endif
  322. }
  323. DEFINE_PER_CPU(unsigned, mce_poll_count);
  324. /*
  325. * Poll for corrected events or events that happened before reset.
  326. * Those are just logged through /dev/mcelog.
  327. *
  328. * This is executed in standard interrupt context.
  329. */
  330. void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
  331. {
  332. struct mce m;
  333. int i;
  334. __get_cpu_var(mce_poll_count)++;
  335. mce_setup(&m);
  336. m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
  337. for (i = 0; i < banks; i++) {
  338. if (!bank[i] || !test_bit(i, *b))
  339. continue;
  340. m.misc = 0;
  341. m.addr = 0;
  342. m.bank = i;
  343. m.tsc = 0;
  344. barrier();
  345. m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
  346. if (!(m.status & MCI_STATUS_VAL))
  347. continue;
  348. /*
  349. * Uncorrected events are handled by the exception handler
  350. * when it is enabled. But when the exception is disabled log
  351. * everything.
  352. *
  353. * TBD do the same check for MCI_STATUS_EN here?
  354. */
  355. if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC))
  356. continue;
  357. if (m.status & MCI_STATUS_MISCV)
  358. m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
  359. if (m.status & MCI_STATUS_ADDRV)
  360. m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
  361. if (!(flags & MCP_TIMESTAMP))
  362. m.tsc = 0;
  363. /*
  364. * Don't get the IP here because it's unlikely to
  365. * have anything to do with the actual error location.
  366. */
  367. if (!(flags & MCP_DONTLOG)) {
  368. mce_log(&m);
  369. add_taint(TAINT_MACHINE_CHECK);
  370. }
  371. /*
  372. * Clear state for this bank.
  373. */
  374. mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
  375. }
  376. /*
  377. * Don't clear MCG_STATUS here because it's only defined for
  378. * exceptions.
  379. */
  380. sync_core();
  381. }
  382. EXPORT_SYMBOL_GPL(machine_check_poll);
  383. /*
  384. * Do a quick check if any of the events requires a panic.
  385. * This decides if we keep the events around or clear them.
  386. */
  387. static int mce_no_way_out(struct mce *m, char **msg)
  388. {
  389. int i;
  390. for (i = 0; i < banks; i++) {
  391. m->status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
  392. if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
  393. return 1;
  394. }
  395. return 0;
  396. }
  397. /*
  398. * The actual machine check handler. This only handles real
  399. * exceptions when something got corrupted coming in through int 18.
  400. *
  401. * This is executed in NMI context not subject to normal locking rules. This
  402. * implies that most kernel services cannot be safely used. Don't even
  403. * think about putting a printk in there!
  404. */
  405. void do_machine_check(struct pt_regs *regs, long error_code)
  406. {
  407. struct mce m, panicm;
  408. int panicm_found = 0;
  409. int i;
  410. /*
  411. * If no_way_out gets set, there is no safe way to recover from this
  412. * MCE. If tolerant is cranked up, we'll try anyway.
  413. */
  414. int no_way_out = 0;
  415. /*
  416. * If kill_it gets set, there might be a way to recover from this
  417. * error.
  418. */
  419. int kill_it = 0;
  420. DECLARE_BITMAP(toclear, MAX_NR_BANKS);
  421. char *msg = "Unknown";
  422. atomic_inc(&mce_entry);
  423. __get_cpu_var(mce_exception_count)++;
  424. if (notify_die(DIE_NMI, "machine check", regs, error_code,
  425. 18, SIGKILL) == NOTIFY_STOP)
  426. goto out;
  427. if (!banks)
  428. goto out;
  429. mce_setup(&m);
  430. m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
  431. no_way_out = mce_no_way_out(&m, &msg);
  432. barrier();
  433. for (i = 0; i < banks; i++) {
  434. __clear_bit(i, toclear);
  435. if (!bank[i])
  436. continue;
  437. m.misc = 0;
  438. m.addr = 0;
  439. m.bank = i;
  440. m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
  441. if ((m.status & MCI_STATUS_VAL) == 0)
  442. continue;
  443. /*
  444. * Non uncorrected errors are handled by machine_check_poll
  445. * Leave them alone, unless this panics.
  446. */
  447. if ((m.status & MCI_STATUS_UC) == 0 && !no_way_out)
  448. continue;
  449. /*
  450. * Set taint even when machine check was not enabled.
  451. */
  452. add_taint(TAINT_MACHINE_CHECK);
  453. __set_bit(i, toclear);
  454. if (m.status & MCI_STATUS_EN) {
  455. /*
  456. * If this error was uncorrectable and there was
  457. * an overflow, we're in trouble. If no overflow,
  458. * we might get away with just killing a task.
  459. */
  460. if (m.status & MCI_STATUS_UC)
  461. kill_it = 1;
  462. } else {
  463. /*
  464. * Machine check event was not enabled. Clear, but
  465. * ignore.
  466. */
  467. continue;
  468. }
  469. if (m.status & MCI_STATUS_MISCV)
  470. m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
  471. if (m.status & MCI_STATUS_ADDRV)
  472. m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
  473. mce_get_rip(&m, regs);
  474. mce_log(&m);
  475. /*
  476. * Did this bank cause the exception?
  477. *
  478. * Assume that the bank with uncorrectable errors did it,
  479. * and that there is only a single one:
  480. */
  481. if ((m.status & MCI_STATUS_UC) &&
  482. (m.status & MCI_STATUS_EN)) {
  483. panicm = m;
  484. panicm_found = 1;
  485. }
  486. }
  487. /*
  488. * If we didn't find an uncorrectable error, pick
  489. * the last one (shouldn't happen, just being safe).
  490. */
  491. if (!panicm_found)
  492. panicm = m;
  493. /*
  494. * If we have decided that we just CAN'T continue, and the user
  495. * has not set tolerant to an insane level, give up and die.
  496. */
  497. if (no_way_out && tolerant < 3)
  498. mce_panic("Machine check", &panicm, msg);
  499. /*
  500. * If the error seems to be unrecoverable, something should be
  501. * done. Try to kill as little as possible. If we can kill just
  502. * one task, do that. If the user has set the tolerance very
  503. * high, don't try to do anything at all.
  504. */
  505. if (kill_it && tolerant < 3) {
  506. int user_space = 0;
  507. /*
  508. * If the EIPV bit is set, it means the saved IP is the
  509. * instruction which caused the MCE.
  510. */
  511. if (m.mcgstatus & MCG_STATUS_EIPV)
  512. user_space = panicm.ip && (panicm.cs & 3);
  513. /*
  514. * If we know that the error was in user space, send a
  515. * SIGBUS. Otherwise, panic if tolerance is low.
  516. *
  517. * force_sig() takes an awful lot of locks and has a slight
  518. * risk of deadlocking.
  519. */
  520. if (user_space) {
  521. force_sig(SIGBUS, current);
  522. } else if (panic_on_oops || tolerant < 2) {
  523. mce_panic("Uncorrected machine check", &panicm, msg);
  524. }
  525. }
  526. /* notify userspace ASAP */
  527. set_thread_flag(TIF_MCE_NOTIFY);
  528. mce_report_event(regs);
  529. /* the last thing we do is clear state */
  530. for (i = 0; i < banks; i++) {
  531. if (test_bit(i, toclear))
  532. mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
  533. }
  534. mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
  535. out:
  536. atomic_dec(&mce_entry);
  537. sync_core();
  538. }
  539. EXPORT_SYMBOL_GPL(do_machine_check);
  540. #ifdef CONFIG_X86_MCE_INTEL
  541. /***
  542. * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
  543. * @cpu: The CPU on which the event occurred.
  544. * @status: Event status information
  545. *
  546. * This function should be called by the thermal interrupt after the
  547. * event has been processed and the decision was made to log the event
  548. * further.
  549. *
  550. * The status parameter will be saved to the 'status' field of 'struct mce'
  551. * and historically has been the register value of the
  552. * MSR_IA32_THERMAL_STATUS (Intel) msr.
  553. */
  554. void mce_log_therm_throt_event(__u64 status)
  555. {
  556. struct mce m;
  557. mce_setup(&m);
  558. m.bank = MCE_THERMAL_BANK;
  559. m.status = status;
  560. mce_log(&m);
  561. }
  562. #endif /* CONFIG_X86_MCE_INTEL */
  563. /*
  564. * Periodic polling timer for "silent" machine check errors. If the
  565. * poller finds an MCE, poll 2x faster. When the poller finds no more
  566. * errors, poll 2x slower (up to check_interval seconds).
  567. */
  568. static int check_interval = 5 * 60; /* 5 minutes */
  569. static DEFINE_PER_CPU(int, next_interval); /* in jiffies */
  570. static DEFINE_PER_CPU(struct timer_list, mce_timer);
  571. static void mcheck_timer(unsigned long data)
  572. {
  573. struct timer_list *t = &per_cpu(mce_timer, data);
  574. int *n;
  575. WARN_ON(smp_processor_id() != data);
  576. if (mce_available(&current_cpu_data)) {
  577. machine_check_poll(MCP_TIMESTAMP,
  578. &__get_cpu_var(mce_poll_banks));
  579. }
  580. /*
  581. * Alert userspace if needed. If we logged an MCE, reduce the
  582. * polling interval, otherwise increase the polling interval.
  583. */
  584. n = &__get_cpu_var(next_interval);
  585. if (mce_notify_user())
  586. *n = max(*n/2, HZ/100);
  587. else
  588. *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
  589. t->expires = jiffies + *n;
  590. add_timer(t);
  591. }
  592. static void mce_do_trigger(struct work_struct *work)
  593. {
  594. call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT);
  595. }
  596. static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
  597. /*
  598. * Notify the user(s) about new machine check events.
  599. * Can be called from interrupt context, but not from machine check/NMI
  600. * context.
  601. */
  602. int mce_notify_user(void)
  603. {
  604. /* Not more than two messages every minute */
  605. static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
  606. clear_thread_flag(TIF_MCE_NOTIFY);
  607. if (test_and_clear_bit(0, &notify_user)) {
  608. wake_up_interruptible(&mce_wait);
  609. /*
  610. * There is no risk of missing notifications because
  611. * work_pending is always cleared before the function is
  612. * executed.
  613. */
  614. if (trigger[0] && !work_pending(&mce_trigger_work))
  615. schedule_work(&mce_trigger_work);
  616. if (__ratelimit(&ratelimit))
  617. printk(KERN_INFO "Machine check events logged\n");
  618. return 1;
  619. }
  620. return 0;
  621. }
  622. EXPORT_SYMBOL_GPL(mce_notify_user);
  623. /*
  624. * Initialize Machine Checks for a CPU.
  625. */
  626. static int mce_cap_init(void)
  627. {
  628. unsigned b;
  629. u64 cap;
  630. rdmsrl(MSR_IA32_MCG_CAP, cap);
  631. b = cap & MCG_BANKCNT_MASK;
  632. printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
  633. if (b > MAX_NR_BANKS) {
  634. printk(KERN_WARNING
  635. "MCE: Using only %u machine check banks out of %u\n",
  636. MAX_NR_BANKS, b);
  637. b = MAX_NR_BANKS;
  638. }
  639. /* Don't support asymmetric configurations today */
  640. WARN_ON(banks != 0 && b != banks);
  641. banks = b;
  642. if (!bank) {
  643. bank = kmalloc(banks * sizeof(u64), GFP_KERNEL);
  644. if (!bank)
  645. return -ENOMEM;
  646. memset(bank, 0xff, banks * sizeof(u64));
  647. }
  648. /* Use accurate RIP reporting if available. */
  649. if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
  650. rip_msr = MSR_IA32_MCG_EIP;
  651. return 0;
  652. }
  653. static void mce_init(void)
  654. {
  655. mce_banks_t all_banks;
  656. u64 cap;
  657. int i;
  658. /*
  659. * Log the machine checks left over from the previous reset.
  660. */
  661. bitmap_fill(all_banks, MAX_NR_BANKS);
  662. machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
  663. set_in_cr4(X86_CR4_MCE);
  664. rdmsrl(MSR_IA32_MCG_CAP, cap);
  665. if (cap & MCG_CTL_P)
  666. wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
  667. for (i = 0; i < banks; i++) {
  668. if (skip_bank_init(i))
  669. continue;
  670. wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
  671. wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
  672. }
  673. }
  674. /* Add per CPU specific workarounds here */
  675. static void mce_cpu_quirks(struct cpuinfo_x86 *c)
  676. {
  677. /* This should be disabled by the BIOS, but isn't always */
  678. if (c->x86_vendor == X86_VENDOR_AMD) {
  679. if (c->x86 == 15 && banks > 4) {
  680. /*
  681. * disable GART TBL walk error reporting, which
  682. * trips off incorrectly with the IOMMU & 3ware
  683. * & Cerberus:
  684. */
  685. clear_bit(10, (unsigned long *)&bank[4]);
  686. }
  687. if (c->x86 <= 17 && mce_bootlog < 0) {
  688. /*
  689. * Lots of broken BIOS around that don't clear them
  690. * by default and leave crap in there. Don't log:
  691. */
  692. mce_bootlog = 0;
  693. }
  694. /*
  695. * Various K7s with broken bank 0 around. Always disable
  696. * by default.
  697. */
  698. if (c->x86 == 6)
  699. bank[0] = 0;
  700. }
  701. if (c->x86_vendor == X86_VENDOR_INTEL) {
  702. /*
  703. * SDM documents that on family 6 bank 0 should not be written
  704. * because it aliases to another special BIOS controlled
  705. * register.
  706. * But it's not aliased anymore on model 0x1a+
  707. * Don't ignore bank 0 completely because there could be a
  708. * valid event later, merely don't write CTL0.
  709. */
  710. if (c->x86 == 6 && c->x86_model < 0x1A)
  711. __set_bit(0, &dont_init_banks);
  712. }
  713. }
  714. static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
  715. {
  716. if (c->x86 != 5)
  717. return;
  718. switch (c->x86_vendor) {
  719. case X86_VENDOR_INTEL:
  720. if (mce_p5_enabled())
  721. intel_p5_mcheck_init(c);
  722. break;
  723. case X86_VENDOR_CENTAUR:
  724. winchip_mcheck_init(c);
  725. break;
  726. }
  727. }
  728. static void mce_cpu_features(struct cpuinfo_x86 *c)
  729. {
  730. switch (c->x86_vendor) {
  731. case X86_VENDOR_INTEL:
  732. mce_intel_feature_init(c);
  733. break;
  734. case X86_VENDOR_AMD:
  735. mce_amd_feature_init(c);
  736. break;
  737. default:
  738. break;
  739. }
  740. }
  741. static void mce_init_timer(void)
  742. {
  743. struct timer_list *t = &__get_cpu_var(mce_timer);
  744. int *n = &__get_cpu_var(next_interval);
  745. *n = check_interval * HZ;
  746. if (!*n)
  747. return;
  748. setup_timer(t, mcheck_timer, smp_processor_id());
  749. t->expires = round_jiffies(jiffies + *n);
  750. add_timer(t);
  751. }
  752. /*
  753. * Called for each booted CPU to set up machine checks.
  754. * Must be called with preempt off:
  755. */
  756. void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
  757. {
  758. if (mce_disabled)
  759. return;
  760. mce_ancient_init(c);
  761. if (!mce_available(c))
  762. return;
  763. if (mce_cap_init() < 0) {
  764. mce_disabled = 1;
  765. return;
  766. }
  767. mce_cpu_quirks(c);
  768. machine_check_vector = do_machine_check;
  769. mce_init();
  770. mce_cpu_features(c);
  771. mce_init_timer();
  772. }
  773. /*
  774. * Character device to read and clear the MCE log.
  775. */
  776. static DEFINE_SPINLOCK(mce_state_lock);
  777. static int open_count; /* #times opened */
  778. static int open_exclu; /* already open exclusive? */
  779. static int mce_open(struct inode *inode, struct file *file)
  780. {
  781. spin_lock(&mce_state_lock);
  782. if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
  783. spin_unlock(&mce_state_lock);
  784. return -EBUSY;
  785. }
  786. if (file->f_flags & O_EXCL)
  787. open_exclu = 1;
  788. open_count++;
  789. spin_unlock(&mce_state_lock);
  790. return nonseekable_open(inode, file);
  791. }
  792. static int mce_release(struct inode *inode, struct file *file)
  793. {
  794. spin_lock(&mce_state_lock);
  795. open_count--;
  796. open_exclu = 0;
  797. spin_unlock(&mce_state_lock);
  798. return 0;
  799. }
  800. static void collect_tscs(void *data)
  801. {
  802. unsigned long *cpu_tsc = (unsigned long *)data;
  803. rdtscll(cpu_tsc[smp_processor_id()]);
  804. }
  805. static DEFINE_MUTEX(mce_read_mutex);
  806. static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
  807. loff_t *off)
  808. {
  809. char __user *buf = ubuf;
  810. unsigned long *cpu_tsc;
  811. unsigned prev, next;
  812. int i, err;
  813. cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
  814. if (!cpu_tsc)
  815. return -ENOMEM;
  816. mutex_lock(&mce_read_mutex);
  817. next = rcu_dereference(mcelog.next);
  818. /* Only supports full reads right now */
  819. if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
  820. mutex_unlock(&mce_read_mutex);
  821. kfree(cpu_tsc);
  822. return -EINVAL;
  823. }
  824. err = 0;
  825. prev = 0;
  826. do {
  827. for (i = prev; i < next; i++) {
  828. unsigned long start = jiffies;
  829. while (!mcelog.entry[i].finished) {
  830. if (time_after_eq(jiffies, start + 2)) {
  831. memset(mcelog.entry + i, 0,
  832. sizeof(struct mce));
  833. goto timeout;
  834. }
  835. cpu_relax();
  836. }
  837. smp_rmb();
  838. err |= copy_to_user(buf, mcelog.entry + i,
  839. sizeof(struct mce));
  840. buf += sizeof(struct mce);
  841. timeout:
  842. ;
  843. }
  844. memset(mcelog.entry + prev, 0,
  845. (next - prev) * sizeof(struct mce));
  846. prev = next;
  847. next = cmpxchg(&mcelog.next, prev, 0);
  848. } while (next != prev);
  849. synchronize_sched();
  850. /*
  851. * Collect entries that were still getting written before the
  852. * synchronize.
  853. */
  854. on_each_cpu(collect_tscs, cpu_tsc, 1);
  855. for (i = next; i < MCE_LOG_LEN; i++) {
  856. if (mcelog.entry[i].finished &&
  857. mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
  858. err |= copy_to_user(buf, mcelog.entry+i,
  859. sizeof(struct mce));
  860. smp_rmb();
  861. buf += sizeof(struct mce);
  862. memset(&mcelog.entry[i], 0, sizeof(struct mce));
  863. }
  864. }
  865. mutex_unlock(&mce_read_mutex);
  866. kfree(cpu_tsc);
  867. return err ? -EFAULT : buf - ubuf;
  868. }
  869. static unsigned int mce_poll(struct file *file, poll_table *wait)
  870. {
  871. poll_wait(file, &mce_wait, wait);
  872. if (rcu_dereference(mcelog.next))
  873. return POLLIN | POLLRDNORM;
  874. return 0;
  875. }
  876. static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
  877. {
  878. int __user *p = (int __user *)arg;
  879. if (!capable(CAP_SYS_ADMIN))
  880. return -EPERM;
  881. switch (cmd) {
  882. case MCE_GET_RECORD_LEN:
  883. return put_user(sizeof(struct mce), p);
  884. case MCE_GET_LOG_LEN:
  885. return put_user(MCE_LOG_LEN, p);
  886. case MCE_GETCLEAR_FLAGS: {
  887. unsigned flags;
  888. do {
  889. flags = mcelog.flags;
  890. } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
  891. return put_user(flags, p);
  892. }
  893. default:
  894. return -ENOTTY;
  895. }
  896. }
  897. /* Modified in mce-inject.c, so not static or const */
  898. struct file_operations mce_chrdev_ops = {
  899. .open = mce_open,
  900. .release = mce_release,
  901. .read = mce_read,
  902. .poll = mce_poll,
  903. .unlocked_ioctl = mce_ioctl,
  904. };
  905. EXPORT_SYMBOL_GPL(mce_chrdev_ops);
  906. static struct miscdevice mce_log_device = {
  907. MISC_MCELOG_MINOR,
  908. "mcelog",
  909. &mce_chrdev_ops,
  910. };
  911. /*
  912. * mce=off disables machine check
  913. * mce=TOLERANCELEVEL (number, see above)
  914. * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
  915. * mce=nobootlog Don't log MCEs from before booting.
  916. */
  917. static int __init mcheck_enable(char *str)
  918. {
  919. if (*str == 0)
  920. enable_p5_mce();
  921. if (*str == '=')
  922. str++;
  923. if (!strcmp(str, "off"))
  924. mce_disabled = 1;
  925. else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
  926. mce_bootlog = (str[0] == 'b');
  927. else if (isdigit(str[0]))
  928. get_option(&str, &tolerant);
  929. else {
  930. printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
  931. str);
  932. return 0;
  933. }
  934. return 1;
  935. }
  936. __setup("mce", mcheck_enable);
  937. /*
  938. * Sysfs support
  939. */
  940. /*
  941. * Disable machine checks on suspend and shutdown. We can't really handle
  942. * them later.
  943. */
  944. static int mce_disable(void)
  945. {
  946. int i;
  947. for (i = 0; i < banks; i++) {
  948. if (!skip_bank_init(i))
  949. wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
  950. }
  951. return 0;
  952. }
  953. static int mce_suspend(struct sys_device *dev, pm_message_t state)
  954. {
  955. return mce_disable();
  956. }
  957. static int mce_shutdown(struct sys_device *dev)
  958. {
  959. return mce_disable();
  960. }
  961. /*
  962. * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
  963. * Only one CPU is active at this time, the others get re-added later using
  964. * CPU hotplug:
  965. */
  966. static int mce_resume(struct sys_device *dev)
  967. {
  968. mce_init();
  969. mce_cpu_features(&current_cpu_data);
  970. return 0;
  971. }
  972. static void mce_cpu_restart(void *data)
  973. {
  974. del_timer_sync(&__get_cpu_var(mce_timer));
  975. if (mce_available(&current_cpu_data))
  976. mce_init();
  977. mce_init_timer();
  978. }
  979. /* Reinit MCEs after user configuration changes */
  980. static void mce_restart(void)
  981. {
  982. on_each_cpu(mce_cpu_restart, NULL, 1);
  983. }
  984. static struct sysdev_class mce_sysclass = {
  985. .suspend = mce_suspend,
  986. .shutdown = mce_shutdown,
  987. .resume = mce_resume,
  988. .name = "machinecheck",
  989. };
  990. DEFINE_PER_CPU(struct sys_device, mce_dev);
  991. __cpuinitdata
  992. void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
  993. static struct sysdev_attribute *bank_attrs;
  994. static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
  995. char *buf)
  996. {
  997. u64 b = bank[attr - bank_attrs];
  998. return sprintf(buf, "%llx\n", b);
  999. }
  1000. static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
  1001. const char *buf, size_t size)
  1002. {
  1003. u64 new;
  1004. if (strict_strtoull(buf, 0, &new) < 0)
  1005. return -EINVAL;
  1006. bank[attr - bank_attrs] = new;
  1007. mce_restart();
  1008. return size;
  1009. }
  1010. static ssize_t
  1011. show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
  1012. {
  1013. strcpy(buf, trigger);
  1014. strcat(buf, "\n");
  1015. return strlen(trigger) + 1;
  1016. }
  1017. static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
  1018. const char *buf, size_t siz)
  1019. {
  1020. char *p;
  1021. int len;
  1022. strncpy(trigger, buf, sizeof(trigger));
  1023. trigger[sizeof(trigger)-1] = 0;
  1024. len = strlen(trigger);
  1025. p = strchr(trigger, '\n');
  1026. if (*p)
  1027. *p = 0;
  1028. return len;
  1029. }
  1030. static ssize_t store_int_with_restart(struct sys_device *s,
  1031. struct sysdev_attribute *attr,
  1032. const char *buf, size_t size)
  1033. {
  1034. ssize_t ret = sysdev_store_int(s, attr, buf, size);
  1035. mce_restart();
  1036. return ret;
  1037. }
  1038. static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
  1039. static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
  1040. static struct sysdev_ext_attribute attr_check_interval = {
  1041. _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
  1042. store_int_with_restart),
  1043. &check_interval
  1044. };
  1045. static struct sysdev_attribute *mce_attrs[] = {
  1046. &attr_tolerant.attr, &attr_check_interval.attr, &attr_trigger,
  1047. NULL
  1048. };
  1049. static cpumask_var_t mce_dev_initialized;
  1050. /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
  1051. static __cpuinit int mce_create_device(unsigned int cpu)
  1052. {
  1053. int err;
  1054. int i;
  1055. if (!mce_available(&boot_cpu_data))
  1056. return -EIO;
  1057. memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
  1058. per_cpu(mce_dev, cpu).id = cpu;
  1059. per_cpu(mce_dev, cpu).cls = &mce_sysclass;
  1060. err = sysdev_register(&per_cpu(mce_dev, cpu));
  1061. if (err)
  1062. return err;
  1063. for (i = 0; mce_attrs[i]; i++) {
  1064. err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
  1065. if (err)
  1066. goto error;
  1067. }
  1068. for (i = 0; i < banks; i++) {
  1069. err = sysdev_create_file(&per_cpu(mce_dev, cpu),
  1070. &bank_attrs[i]);
  1071. if (err)
  1072. goto error2;
  1073. }
  1074. cpumask_set_cpu(cpu, mce_dev_initialized);
  1075. return 0;
  1076. error2:
  1077. while (--i >= 0)
  1078. sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
  1079. error:
  1080. while (--i >= 0)
  1081. sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
  1082. sysdev_unregister(&per_cpu(mce_dev, cpu));
  1083. return err;
  1084. }
  1085. static __cpuinit void mce_remove_device(unsigned int cpu)
  1086. {
  1087. int i;
  1088. if (!cpumask_test_cpu(cpu, mce_dev_initialized))
  1089. return;
  1090. for (i = 0; mce_attrs[i]; i++)
  1091. sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
  1092. for (i = 0; i < banks; i++)
  1093. sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
  1094. sysdev_unregister(&per_cpu(mce_dev, cpu));
  1095. cpumask_clear_cpu(cpu, mce_dev_initialized);
  1096. }
  1097. /* Make sure there are no machine checks on offlined CPUs. */
  1098. static void mce_disable_cpu(void *h)
  1099. {
  1100. unsigned long action = *(unsigned long *)h;
  1101. int i;
  1102. if (!mce_available(&current_cpu_data))
  1103. return;
  1104. if (!(action & CPU_TASKS_FROZEN))
  1105. cmci_clear();
  1106. for (i = 0; i < banks; i++) {
  1107. if (!skip_bank_init(i))
  1108. wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
  1109. }
  1110. }
  1111. static void mce_reenable_cpu(void *h)
  1112. {
  1113. unsigned long action = *(unsigned long *)h;
  1114. int i;
  1115. if (!mce_available(&current_cpu_data))
  1116. return;
  1117. if (!(action & CPU_TASKS_FROZEN))
  1118. cmci_reenable();
  1119. for (i = 0; i < banks; i++) {
  1120. if (!skip_bank_init(i))
  1121. wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]);
  1122. }
  1123. }
  1124. /* Get notified when a cpu comes on/off. Be hotplug friendly. */
  1125. static int __cpuinit
  1126. mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
  1127. {
  1128. unsigned int cpu = (unsigned long)hcpu;
  1129. struct timer_list *t = &per_cpu(mce_timer, cpu);
  1130. switch (action) {
  1131. case CPU_ONLINE:
  1132. case CPU_ONLINE_FROZEN:
  1133. mce_create_device(cpu);
  1134. if (threshold_cpu_callback)
  1135. threshold_cpu_callback(action, cpu);
  1136. break;
  1137. case CPU_DEAD:
  1138. case CPU_DEAD_FROZEN:
  1139. if (threshold_cpu_callback)
  1140. threshold_cpu_callback(action, cpu);
  1141. mce_remove_device(cpu);
  1142. break;
  1143. case CPU_DOWN_PREPARE:
  1144. case CPU_DOWN_PREPARE_FROZEN:
  1145. del_timer_sync(t);
  1146. smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
  1147. break;
  1148. case CPU_DOWN_FAILED:
  1149. case CPU_DOWN_FAILED_FROZEN:
  1150. t->expires = round_jiffies(jiffies +
  1151. __get_cpu_var(next_interval));
  1152. add_timer_on(t, cpu);
  1153. smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
  1154. break;
  1155. case CPU_POST_DEAD:
  1156. /* intentionally ignoring frozen here */
  1157. cmci_rediscover(cpu);
  1158. break;
  1159. }
  1160. return NOTIFY_OK;
  1161. }
  1162. static struct notifier_block mce_cpu_notifier __cpuinitdata = {
  1163. .notifier_call = mce_cpu_callback,
  1164. };
  1165. static __init int mce_init_banks(void)
  1166. {
  1167. int i;
  1168. bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks,
  1169. GFP_KERNEL);
  1170. if (!bank_attrs)
  1171. return -ENOMEM;
  1172. for (i = 0; i < banks; i++) {
  1173. struct sysdev_attribute *a = &bank_attrs[i];
  1174. a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i);
  1175. if (!a->attr.name)
  1176. goto nomem;
  1177. a->attr.mode = 0644;
  1178. a->show = show_bank;
  1179. a->store = set_bank;
  1180. }
  1181. return 0;
  1182. nomem:
  1183. while (--i >= 0)
  1184. kfree(bank_attrs[i].attr.name);
  1185. kfree(bank_attrs);
  1186. bank_attrs = NULL;
  1187. return -ENOMEM;
  1188. }
  1189. static __init int mce_init_device(void)
  1190. {
  1191. int err;
  1192. int i = 0;
  1193. if (!mce_available(&boot_cpu_data))
  1194. return -EIO;
  1195. alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
  1196. err = mce_init_banks();
  1197. if (err)
  1198. return err;
  1199. err = sysdev_class_register(&mce_sysclass);
  1200. if (err)
  1201. return err;
  1202. for_each_online_cpu(i) {
  1203. err = mce_create_device(i);
  1204. if (err)
  1205. return err;
  1206. }
  1207. register_hotcpu_notifier(&mce_cpu_notifier);
  1208. misc_register(&mce_log_device);
  1209. return err;
  1210. }
  1211. device_initcall(mce_init_device);
  1212. #else /* CONFIG_X86_OLD_MCE: */
  1213. int nr_mce_banks;
  1214. EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */
  1215. /* This has to be run for each processor */
  1216. void mcheck_init(struct cpuinfo_x86 *c)
  1217. {
  1218. if (mce_disabled == 1)
  1219. return;
  1220. switch (c->x86_vendor) {
  1221. case X86_VENDOR_AMD:
  1222. amd_mcheck_init(c);
  1223. break;
  1224. case X86_VENDOR_INTEL:
  1225. if (c->x86 == 5)
  1226. intel_p5_mcheck_init(c);
  1227. if (c->x86 == 6)
  1228. intel_p6_mcheck_init(c);
  1229. if (c->x86 == 15)
  1230. intel_p4_mcheck_init(c);
  1231. break;
  1232. case X86_VENDOR_CENTAUR:
  1233. if (c->x86 == 5)
  1234. winchip_mcheck_init(c);
  1235. break;
  1236. default:
  1237. break;
  1238. }
  1239. printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks);
  1240. }
  1241. static int __init mcheck_enable(char *str)
  1242. {
  1243. mce_disabled = -1;
  1244. return 1;
  1245. }
  1246. __setup("mce", mcheck_enable);
  1247. #endif /* CONFIG_X86_OLD_MCE */
  1248. /*
  1249. * Old style boot options parsing. Only for compatibility.
  1250. */
  1251. static int __init mcheck_disable(char *str)
  1252. {
  1253. mce_disabled = 1;
  1254. return 1;
  1255. }
  1256. __setup("nomce", mcheck_disable);