xmit.c 63 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include "ath9k.h"
  18. #include "ar9003_mac.h"
  19. #define BITS_PER_BYTE 8
  20. #define OFDM_PLCP_BITS 22
  21. #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
  22. #define L_STF 8
  23. #define L_LTF 8
  24. #define L_SIG 4
  25. #define HT_SIG 8
  26. #define HT_STF 4
  27. #define HT_LTF(_ns) (4 * (_ns))
  28. #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
  29. #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
  30. #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
  31. #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
  32. static u16 bits_per_symbol[][2] = {
  33. /* 20MHz 40MHz */
  34. { 26, 54 }, /* 0: BPSK */
  35. { 52, 108 }, /* 1: QPSK 1/2 */
  36. { 78, 162 }, /* 2: QPSK 3/4 */
  37. { 104, 216 }, /* 3: 16-QAM 1/2 */
  38. { 156, 324 }, /* 4: 16-QAM 3/4 */
  39. { 208, 432 }, /* 5: 64-QAM 2/3 */
  40. { 234, 486 }, /* 6: 64-QAM 3/4 */
  41. { 260, 540 }, /* 7: 64-QAM 5/6 */
  42. };
  43. #define IS_HT_RATE(_rate) ((_rate) & 0x80)
  44. static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
  45. struct ath_atx_tid *tid, struct sk_buff *skb);
  46. static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  47. int tx_flags, struct ath_txq *txq);
  48. static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
  49. struct ath_txq *txq, struct list_head *bf_q,
  50. struct ath_tx_status *ts, int txok);
  51. static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
  52. struct list_head *head, bool internal);
  53. static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
  54. struct ath_tx_status *ts, int nframes, int nbad,
  55. int txok);
  56. static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
  57. int seqno);
  58. static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
  59. struct ath_txq *txq,
  60. struct ath_atx_tid *tid,
  61. struct sk_buff *skb);
  62. enum {
  63. MCS_HT20,
  64. MCS_HT20_SGI,
  65. MCS_HT40,
  66. MCS_HT40_SGI,
  67. };
  68. static int ath_max_4ms_framelen[4][32] = {
  69. [MCS_HT20] = {
  70. 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
  71. 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
  72. 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
  73. 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
  74. },
  75. [MCS_HT20_SGI] = {
  76. 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
  77. 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
  78. 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
  79. 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
  80. },
  81. [MCS_HT40] = {
  82. 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
  83. 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
  84. 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
  85. 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
  86. },
  87. [MCS_HT40_SGI] = {
  88. 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
  89. 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
  90. 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
  91. 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
  92. }
  93. };
  94. /*********************/
  95. /* Aggregation logic */
  96. /*********************/
  97. static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
  98. {
  99. struct ath_atx_ac *ac = tid->ac;
  100. if (tid->paused)
  101. return;
  102. if (tid->sched)
  103. return;
  104. tid->sched = true;
  105. list_add_tail(&tid->list, &ac->tid_q);
  106. if (ac->sched)
  107. return;
  108. ac->sched = true;
  109. list_add_tail(&ac->list, &txq->axq_acq);
  110. }
  111. static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
  112. {
  113. struct ath_txq *txq = tid->ac->txq;
  114. WARN_ON(!tid->paused);
  115. spin_lock_bh(&txq->axq_lock);
  116. tid->paused = false;
  117. if (skb_queue_empty(&tid->buf_q))
  118. goto unlock;
  119. ath_tx_queue_tid(txq, tid);
  120. ath_txq_schedule(sc, txq);
  121. unlock:
  122. spin_unlock_bh(&txq->axq_lock);
  123. }
  124. static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
  125. {
  126. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  127. BUILD_BUG_ON(sizeof(struct ath_frame_info) >
  128. sizeof(tx_info->rate_driver_data));
  129. return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
  130. }
  131. static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
  132. {
  133. ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
  134. seqno << IEEE80211_SEQ_SEQ_SHIFT);
  135. }
  136. static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
  137. {
  138. struct ath_txq *txq = tid->ac->txq;
  139. struct sk_buff *skb;
  140. struct ath_buf *bf;
  141. struct list_head bf_head;
  142. struct ath_tx_status ts;
  143. struct ath_frame_info *fi;
  144. bool sendbar = false;
  145. INIT_LIST_HEAD(&bf_head);
  146. memset(&ts, 0, sizeof(ts));
  147. while ((skb = __skb_dequeue(&tid->buf_q))) {
  148. fi = get_frame_info(skb);
  149. bf = fi->bf;
  150. if (bf && fi->retries) {
  151. list_add_tail(&bf->list, &bf_head);
  152. ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
  153. ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
  154. sendbar = true;
  155. } else {
  156. ath_tx_send_normal(sc, txq, NULL, skb);
  157. }
  158. }
  159. if (tid->baw_head == tid->baw_tail) {
  160. tid->state &= ~AGGR_ADDBA_COMPLETE;
  161. tid->state &= ~AGGR_CLEANUP;
  162. }
  163. if (sendbar)
  164. ath_send_bar(tid, tid->seq_start);
  165. }
  166. static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
  167. int seqno)
  168. {
  169. int index, cindex;
  170. index = ATH_BA_INDEX(tid->seq_start, seqno);
  171. cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
  172. __clear_bit(cindex, tid->tx_buf);
  173. while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
  174. INCR(tid->seq_start, IEEE80211_SEQ_MAX);
  175. INCR(tid->baw_head, ATH_TID_MAX_BUFS);
  176. if (tid->bar_index >= 0)
  177. tid->bar_index--;
  178. }
  179. }
  180. static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
  181. u16 seqno)
  182. {
  183. int index, cindex;
  184. index = ATH_BA_INDEX(tid->seq_start, seqno);
  185. cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
  186. __set_bit(cindex, tid->tx_buf);
  187. if (index >= ((tid->baw_tail - tid->baw_head) &
  188. (ATH_TID_MAX_BUFS - 1))) {
  189. tid->baw_tail = cindex;
  190. INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
  191. }
  192. }
  193. /*
  194. * TODO: For frame(s) that are in the retry state, we will reuse the
  195. * sequence number(s) without setting the retry bit. The
  196. * alternative is to give up on these and BAR the receiver's window
  197. * forward.
  198. */
  199. static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
  200. struct ath_atx_tid *tid)
  201. {
  202. struct sk_buff *skb;
  203. struct ath_buf *bf;
  204. struct list_head bf_head;
  205. struct ath_tx_status ts;
  206. struct ath_frame_info *fi;
  207. memset(&ts, 0, sizeof(ts));
  208. INIT_LIST_HEAD(&bf_head);
  209. while ((skb = __skb_dequeue(&tid->buf_q))) {
  210. fi = get_frame_info(skb);
  211. bf = fi->bf;
  212. if (!bf) {
  213. ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
  214. continue;
  215. }
  216. list_add_tail(&bf->list, &bf_head);
  217. if (fi->retries)
  218. ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
  219. ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
  220. }
  221. tid->seq_next = tid->seq_start;
  222. tid->baw_tail = tid->baw_head;
  223. tid->bar_index = -1;
  224. }
  225. static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
  226. struct sk_buff *skb, int count)
  227. {
  228. struct ath_frame_info *fi = get_frame_info(skb);
  229. struct ath_buf *bf = fi->bf;
  230. struct ieee80211_hdr *hdr;
  231. int prev = fi->retries;
  232. TX_STAT_INC(txq->axq_qnum, a_retries);
  233. fi->retries += count;
  234. if (prev > 0)
  235. return;
  236. hdr = (struct ieee80211_hdr *)skb->data;
  237. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
  238. dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
  239. sizeof(*hdr), DMA_TO_DEVICE);
  240. }
  241. static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
  242. {
  243. struct ath_buf *bf = NULL;
  244. spin_lock_bh(&sc->tx.txbuflock);
  245. if (unlikely(list_empty(&sc->tx.txbuf))) {
  246. spin_unlock_bh(&sc->tx.txbuflock);
  247. return NULL;
  248. }
  249. bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
  250. list_del(&bf->list);
  251. spin_unlock_bh(&sc->tx.txbuflock);
  252. return bf;
  253. }
  254. static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
  255. {
  256. spin_lock_bh(&sc->tx.txbuflock);
  257. list_add_tail(&bf->list, &sc->tx.txbuf);
  258. spin_unlock_bh(&sc->tx.txbuflock);
  259. }
  260. static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
  261. {
  262. struct ath_buf *tbf;
  263. tbf = ath_tx_get_buffer(sc);
  264. if (WARN_ON(!tbf))
  265. return NULL;
  266. ATH_TXBUF_RESET(tbf);
  267. tbf->bf_mpdu = bf->bf_mpdu;
  268. tbf->bf_buf_addr = bf->bf_buf_addr;
  269. memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
  270. tbf->bf_state = bf->bf_state;
  271. return tbf;
  272. }
  273. static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
  274. struct ath_tx_status *ts, int txok,
  275. int *nframes, int *nbad)
  276. {
  277. struct ath_frame_info *fi;
  278. u16 seq_st = 0;
  279. u32 ba[WME_BA_BMP_SIZE >> 5];
  280. int ba_index;
  281. int isaggr = 0;
  282. *nbad = 0;
  283. *nframes = 0;
  284. isaggr = bf_isaggr(bf);
  285. if (isaggr) {
  286. seq_st = ts->ts_seqnum;
  287. memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
  288. }
  289. while (bf) {
  290. fi = get_frame_info(bf->bf_mpdu);
  291. ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
  292. (*nframes)++;
  293. if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
  294. (*nbad)++;
  295. bf = bf->bf_next;
  296. }
  297. }
  298. static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
  299. struct ath_buf *bf, struct list_head *bf_q,
  300. struct ath_tx_status *ts, int txok, bool retry)
  301. {
  302. struct ath_node *an = NULL;
  303. struct sk_buff *skb;
  304. struct ieee80211_sta *sta;
  305. struct ieee80211_hw *hw = sc->hw;
  306. struct ieee80211_hdr *hdr;
  307. struct ieee80211_tx_info *tx_info;
  308. struct ath_atx_tid *tid = NULL;
  309. struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
  310. struct list_head bf_head;
  311. struct sk_buff_head bf_pending;
  312. u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
  313. u32 ba[WME_BA_BMP_SIZE >> 5];
  314. int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
  315. bool rc_update = true;
  316. struct ieee80211_tx_rate rates[4];
  317. struct ath_frame_info *fi;
  318. int nframes;
  319. u8 tidno;
  320. bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
  321. int i, retries;
  322. int bar_index = -1;
  323. skb = bf->bf_mpdu;
  324. hdr = (struct ieee80211_hdr *)skb->data;
  325. tx_info = IEEE80211_SKB_CB(skb);
  326. memcpy(rates, tx_info->control.rates, sizeof(rates));
  327. retries = ts->ts_longretry + 1;
  328. for (i = 0; i < ts->ts_rateindex; i++)
  329. retries += rates[i].count;
  330. rcu_read_lock();
  331. sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
  332. if (!sta) {
  333. rcu_read_unlock();
  334. INIT_LIST_HEAD(&bf_head);
  335. while (bf) {
  336. bf_next = bf->bf_next;
  337. if (!bf->bf_stale || bf_next != NULL)
  338. list_move_tail(&bf->list, &bf_head);
  339. ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
  340. bf = bf_next;
  341. }
  342. return;
  343. }
  344. an = (struct ath_node *)sta->drv_priv;
  345. tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
  346. tid = ATH_AN_2_TID(an, tidno);
  347. seq_first = tid->seq_start;
  348. /*
  349. * The hardware occasionally sends a tx status for the wrong TID.
  350. * In this case, the BA status cannot be considered valid and all
  351. * subframes need to be retransmitted
  352. */
  353. if (tidno != ts->tid)
  354. txok = false;
  355. isaggr = bf_isaggr(bf);
  356. memset(ba, 0, WME_BA_BMP_SIZE >> 3);
  357. if (isaggr && txok) {
  358. if (ts->ts_flags & ATH9K_TX_BA) {
  359. seq_st = ts->ts_seqnum;
  360. memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
  361. } else {
  362. /*
  363. * AR5416 can become deaf/mute when BA
  364. * issue happens. Chip needs to be reset.
  365. * But AP code may have sychronization issues
  366. * when perform internal reset in this routine.
  367. * Only enable reset in STA mode for now.
  368. */
  369. if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
  370. needreset = 1;
  371. }
  372. }
  373. __skb_queue_head_init(&bf_pending);
  374. ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
  375. while (bf) {
  376. u16 seqno = bf->bf_state.seqno;
  377. txfail = txpending = sendbar = 0;
  378. bf_next = bf->bf_next;
  379. skb = bf->bf_mpdu;
  380. tx_info = IEEE80211_SKB_CB(skb);
  381. fi = get_frame_info(skb);
  382. if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
  383. /* transmit completion, subframe is
  384. * acked by block ack */
  385. acked_cnt++;
  386. } else if (!isaggr && txok) {
  387. /* transmit completion */
  388. acked_cnt++;
  389. } else if ((tid->state & AGGR_CLEANUP) || !retry) {
  390. /*
  391. * cleanup in progress, just fail
  392. * the un-acked sub-frames
  393. */
  394. txfail = 1;
  395. } else if (flush) {
  396. txpending = 1;
  397. } else if (fi->retries < ATH_MAX_SW_RETRIES) {
  398. if (txok || !an->sleeping)
  399. ath_tx_set_retry(sc, txq, bf->bf_mpdu,
  400. retries);
  401. txpending = 1;
  402. } else {
  403. txfail = 1;
  404. txfail_cnt++;
  405. bar_index = max_t(int, bar_index,
  406. ATH_BA_INDEX(seq_first, seqno));
  407. }
  408. /*
  409. * Make sure the last desc is reclaimed if it
  410. * not a holding desc.
  411. */
  412. INIT_LIST_HEAD(&bf_head);
  413. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
  414. bf_next != NULL || !bf_last->bf_stale)
  415. list_move_tail(&bf->list, &bf_head);
  416. if (!txpending || (tid->state & AGGR_CLEANUP)) {
  417. /*
  418. * complete the acked-ones/xretried ones; update
  419. * block-ack window
  420. */
  421. ath_tx_update_baw(sc, tid, seqno);
  422. if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
  423. memcpy(tx_info->control.rates, rates, sizeof(rates));
  424. ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
  425. rc_update = false;
  426. }
  427. ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
  428. !txfail);
  429. } else {
  430. /* retry the un-acked ones */
  431. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  432. bf->bf_next == NULL && bf_last->bf_stale) {
  433. struct ath_buf *tbf;
  434. tbf = ath_clone_txbuf(sc, bf_last);
  435. /*
  436. * Update tx baw and complete the
  437. * frame with failed status if we
  438. * run out of tx buf.
  439. */
  440. if (!tbf) {
  441. ath_tx_update_baw(sc, tid, seqno);
  442. ath_tx_complete_buf(sc, bf, txq,
  443. &bf_head, ts, 0);
  444. bar_index = max_t(int, bar_index,
  445. ATH_BA_INDEX(seq_first, seqno));
  446. break;
  447. }
  448. fi->bf = tbf;
  449. }
  450. /*
  451. * Put this buffer to the temporary pending
  452. * queue to retain ordering
  453. */
  454. __skb_queue_tail(&bf_pending, skb);
  455. }
  456. bf = bf_next;
  457. }
  458. if (bar_index >= 0) {
  459. u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
  460. ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
  461. if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
  462. tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
  463. }
  464. /* prepend un-acked frames to the beginning of the pending frame queue */
  465. if (!skb_queue_empty(&bf_pending)) {
  466. if (an->sleeping)
  467. ieee80211_sta_set_buffered(sta, tid->tidno, true);
  468. skb_queue_splice(&bf_pending, &tid->buf_q);
  469. if (!an->sleeping) {
  470. ath_tx_queue_tid(txq, tid);
  471. if (ts->ts_status & ATH9K_TXERR_FILT)
  472. tid->ac->clear_ps_filter = true;
  473. }
  474. }
  475. if (tid->state & AGGR_CLEANUP)
  476. ath_tx_flush_tid(sc, tid);
  477. rcu_read_unlock();
  478. if (needreset) {
  479. RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
  480. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  481. }
  482. }
  483. static bool ath_lookup_legacy(struct ath_buf *bf)
  484. {
  485. struct sk_buff *skb;
  486. struct ieee80211_tx_info *tx_info;
  487. struct ieee80211_tx_rate *rates;
  488. int i;
  489. skb = bf->bf_mpdu;
  490. tx_info = IEEE80211_SKB_CB(skb);
  491. rates = tx_info->control.rates;
  492. for (i = 0; i < 4; i++) {
  493. if (!rates[i].count || rates[i].idx < 0)
  494. break;
  495. if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
  496. return true;
  497. }
  498. return false;
  499. }
  500. static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
  501. struct ath_atx_tid *tid)
  502. {
  503. struct sk_buff *skb;
  504. struct ieee80211_tx_info *tx_info;
  505. struct ieee80211_tx_rate *rates;
  506. struct ath_mci_profile *mci = &sc->btcoex.mci;
  507. u32 max_4ms_framelen, frmlen;
  508. u16 aggr_limit, legacy = 0;
  509. int i;
  510. skb = bf->bf_mpdu;
  511. tx_info = IEEE80211_SKB_CB(skb);
  512. rates = tx_info->control.rates;
  513. /*
  514. * Find the lowest frame length among the rate series that will have a
  515. * 4ms transmit duration.
  516. * TODO - TXOP limit needs to be considered.
  517. */
  518. max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
  519. for (i = 0; i < 4; i++) {
  520. int modeidx;
  521. if (!rates[i].count)
  522. continue;
  523. if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
  524. legacy = 1;
  525. break;
  526. }
  527. if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
  528. modeidx = MCS_HT40;
  529. else
  530. modeidx = MCS_HT20;
  531. if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
  532. modeidx++;
  533. frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
  534. max_4ms_framelen = min(max_4ms_framelen, frmlen);
  535. }
  536. /*
  537. * limit aggregate size by the minimum rate if rate selected is
  538. * not a probe rate, if rate selected is a probe rate then
  539. * avoid aggregation of this packet.
  540. */
  541. if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
  542. return 0;
  543. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && mci->aggr_limit)
  544. aggr_limit = (max_4ms_framelen * mci->aggr_limit) >> 4;
  545. else if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
  546. aggr_limit = min((max_4ms_framelen * 3) / 8,
  547. (u32)ATH_AMPDU_LIMIT_MAX);
  548. else
  549. aggr_limit = min(max_4ms_framelen,
  550. (u32)ATH_AMPDU_LIMIT_MAX);
  551. /*
  552. * h/w can accept aggregates up to 16 bit lengths (65535).
  553. * The IE, however can hold up to 65536, which shows up here
  554. * as zero. Ignore 65536 since we are constrained by hw.
  555. */
  556. if (tid->an->maxampdu)
  557. aggr_limit = min(aggr_limit, tid->an->maxampdu);
  558. return aggr_limit;
  559. }
  560. /*
  561. * Returns the number of delimiters to be added to
  562. * meet the minimum required mpdudensity.
  563. */
  564. static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
  565. struct ath_buf *bf, u16 frmlen,
  566. bool first_subfrm)
  567. {
  568. #define FIRST_DESC_NDELIMS 60
  569. struct sk_buff *skb = bf->bf_mpdu;
  570. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  571. u32 nsymbits, nsymbols;
  572. u16 minlen;
  573. u8 flags, rix;
  574. int width, streams, half_gi, ndelim, mindelim;
  575. struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
  576. /* Select standard number of delimiters based on frame length alone */
  577. ndelim = ATH_AGGR_GET_NDELIM(frmlen);
  578. /*
  579. * If encryption enabled, hardware requires some more padding between
  580. * subframes.
  581. * TODO - this could be improved to be dependent on the rate.
  582. * The hardware can keep up at lower rates, but not higher rates
  583. */
  584. if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
  585. !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
  586. ndelim += ATH_AGGR_ENCRYPTDELIM;
  587. /*
  588. * Add delimiter when using RTS/CTS with aggregation
  589. * and non enterprise AR9003 card
  590. */
  591. if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
  592. (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
  593. ndelim = max(ndelim, FIRST_DESC_NDELIMS);
  594. /*
  595. * Convert desired mpdu density from microeconds to bytes based
  596. * on highest rate in rate series (i.e. first rate) to determine
  597. * required minimum length for subframe. Take into account
  598. * whether high rate is 20 or 40Mhz and half or full GI.
  599. *
  600. * If there is no mpdu density restriction, no further calculation
  601. * is needed.
  602. */
  603. if (tid->an->mpdudensity == 0)
  604. return ndelim;
  605. rix = tx_info->control.rates[0].idx;
  606. flags = tx_info->control.rates[0].flags;
  607. width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
  608. half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
  609. if (half_gi)
  610. nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
  611. else
  612. nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
  613. if (nsymbols == 0)
  614. nsymbols = 1;
  615. streams = HT_RC_2_STREAMS(rix);
  616. nsymbits = bits_per_symbol[rix % 8][width] * streams;
  617. minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
  618. if (frmlen < minlen) {
  619. mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
  620. ndelim = max(mindelim, ndelim);
  621. }
  622. return ndelim;
  623. }
  624. static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
  625. struct ath_txq *txq,
  626. struct ath_atx_tid *tid,
  627. struct list_head *bf_q,
  628. int *aggr_len)
  629. {
  630. #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
  631. struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
  632. int rl = 0, nframes = 0, ndelim, prev_al = 0;
  633. u16 aggr_limit = 0, al = 0, bpad = 0,
  634. al_delta, h_baw = tid->baw_size / 2;
  635. enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
  636. struct ieee80211_tx_info *tx_info;
  637. struct ath_frame_info *fi;
  638. struct sk_buff *skb;
  639. u16 seqno;
  640. do {
  641. skb = skb_peek(&tid->buf_q);
  642. fi = get_frame_info(skb);
  643. bf = fi->bf;
  644. if (!fi->bf)
  645. bf = ath_tx_setup_buffer(sc, txq, tid, skb);
  646. if (!bf)
  647. continue;
  648. bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
  649. seqno = bf->bf_state.seqno;
  650. /* do not step over block-ack window */
  651. if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
  652. status = ATH_AGGR_BAW_CLOSED;
  653. break;
  654. }
  655. if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
  656. struct ath_tx_status ts = {};
  657. struct list_head bf_head;
  658. INIT_LIST_HEAD(&bf_head);
  659. list_add(&bf->list, &bf_head);
  660. __skb_unlink(skb, &tid->buf_q);
  661. ath_tx_update_baw(sc, tid, seqno);
  662. ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
  663. continue;
  664. }
  665. if (!bf_first)
  666. bf_first = bf;
  667. if (!rl) {
  668. aggr_limit = ath_lookup_rate(sc, bf, tid);
  669. rl = 1;
  670. }
  671. /* do not exceed aggregation limit */
  672. al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
  673. if (nframes &&
  674. ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
  675. ath_lookup_legacy(bf))) {
  676. status = ATH_AGGR_LIMITED;
  677. break;
  678. }
  679. tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
  680. if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
  681. break;
  682. /* do not exceed subframe limit */
  683. if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
  684. status = ATH_AGGR_LIMITED;
  685. break;
  686. }
  687. /* add padding for previous frame to aggregation length */
  688. al += bpad + al_delta;
  689. /*
  690. * Get the delimiters needed to meet the MPDU
  691. * density for this node.
  692. */
  693. ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
  694. !nframes);
  695. bpad = PADBYTES(al_delta) + (ndelim << 2);
  696. nframes++;
  697. bf->bf_next = NULL;
  698. /* link buffers of this frame to the aggregate */
  699. if (!fi->retries)
  700. ath_tx_addto_baw(sc, tid, seqno);
  701. bf->bf_state.ndelim = ndelim;
  702. __skb_unlink(skb, &tid->buf_q);
  703. list_add_tail(&bf->list, bf_q);
  704. if (bf_prev)
  705. bf_prev->bf_next = bf;
  706. bf_prev = bf;
  707. } while (!skb_queue_empty(&tid->buf_q));
  708. *aggr_len = al;
  709. return status;
  710. #undef PADBYTES
  711. }
  712. /*
  713. * rix - rate index
  714. * pktlen - total bytes (delims + data + fcs + pads + pad delims)
  715. * width - 0 for 20 MHz, 1 for 40 MHz
  716. * half_gi - to use 4us v/s 3.6 us for symbol time
  717. */
  718. static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
  719. int width, int half_gi, bool shortPreamble)
  720. {
  721. u32 nbits, nsymbits, duration, nsymbols;
  722. int streams;
  723. /* find number of symbols: PLCP + data */
  724. streams = HT_RC_2_STREAMS(rix);
  725. nbits = (pktlen << 3) + OFDM_PLCP_BITS;
  726. nsymbits = bits_per_symbol[rix % 8][width] * streams;
  727. nsymbols = (nbits + nsymbits - 1) / nsymbits;
  728. if (!half_gi)
  729. duration = SYMBOL_TIME(nsymbols);
  730. else
  731. duration = SYMBOL_TIME_HALFGI(nsymbols);
  732. /* addup duration for legacy/ht training and signal fields */
  733. duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
  734. return duration;
  735. }
  736. static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
  737. struct ath_tx_info *info, int len)
  738. {
  739. struct ath_hw *ah = sc->sc_ah;
  740. struct sk_buff *skb;
  741. struct ieee80211_tx_info *tx_info;
  742. struct ieee80211_tx_rate *rates;
  743. const struct ieee80211_rate *rate;
  744. struct ieee80211_hdr *hdr;
  745. int i;
  746. u8 rix = 0;
  747. skb = bf->bf_mpdu;
  748. tx_info = IEEE80211_SKB_CB(skb);
  749. rates = tx_info->control.rates;
  750. hdr = (struct ieee80211_hdr *)skb->data;
  751. /* set dur_update_en for l-sig computation except for PS-Poll frames */
  752. info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
  753. /*
  754. * We check if Short Preamble is needed for the CTS rate by
  755. * checking the BSS's global flag.
  756. * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
  757. */
  758. rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
  759. info->rtscts_rate = rate->hw_value;
  760. if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
  761. info->rtscts_rate |= rate->hw_value_short;
  762. for (i = 0; i < 4; i++) {
  763. bool is_40, is_sgi, is_sp;
  764. int phy;
  765. if (!rates[i].count || (rates[i].idx < 0))
  766. continue;
  767. rix = rates[i].idx;
  768. info->rates[i].Tries = rates[i].count;
  769. if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  770. info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
  771. info->flags |= ATH9K_TXDESC_RTSENA;
  772. } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  773. info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
  774. info->flags |= ATH9K_TXDESC_CTSENA;
  775. }
  776. if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
  777. info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
  778. if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
  779. info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
  780. is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
  781. is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
  782. is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
  783. if (rates[i].flags & IEEE80211_TX_RC_MCS) {
  784. /* MCS rates */
  785. info->rates[i].Rate = rix | 0x80;
  786. info->rates[i].ChSel = ath_txchainmask_reduction(sc,
  787. ah->txchainmask, info->rates[i].Rate);
  788. info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
  789. is_40, is_sgi, is_sp);
  790. if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
  791. info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
  792. continue;
  793. }
  794. /* legacy rates */
  795. if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
  796. !(rate->flags & IEEE80211_RATE_ERP_G))
  797. phy = WLAN_RC_PHY_CCK;
  798. else
  799. phy = WLAN_RC_PHY_OFDM;
  800. rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
  801. info->rates[i].Rate = rate->hw_value;
  802. if (rate->hw_value_short) {
  803. if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
  804. info->rates[i].Rate |= rate->hw_value_short;
  805. } else {
  806. is_sp = false;
  807. }
  808. if (bf->bf_state.bfs_paprd)
  809. info->rates[i].ChSel = ah->txchainmask;
  810. else
  811. info->rates[i].ChSel = ath_txchainmask_reduction(sc,
  812. ah->txchainmask, info->rates[i].Rate);
  813. info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
  814. phy, rate->bitrate * 100, len, rix, is_sp);
  815. }
  816. /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
  817. if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
  818. info->flags &= ~ATH9K_TXDESC_RTSENA;
  819. /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
  820. if (info->flags & ATH9K_TXDESC_RTSENA)
  821. info->flags &= ~ATH9K_TXDESC_CTSENA;
  822. }
  823. static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
  824. {
  825. struct ieee80211_hdr *hdr;
  826. enum ath9k_pkt_type htype;
  827. __le16 fc;
  828. hdr = (struct ieee80211_hdr *)skb->data;
  829. fc = hdr->frame_control;
  830. if (ieee80211_is_beacon(fc))
  831. htype = ATH9K_PKT_TYPE_BEACON;
  832. else if (ieee80211_is_probe_resp(fc))
  833. htype = ATH9K_PKT_TYPE_PROBE_RESP;
  834. else if (ieee80211_is_atim(fc))
  835. htype = ATH9K_PKT_TYPE_ATIM;
  836. else if (ieee80211_is_pspoll(fc))
  837. htype = ATH9K_PKT_TYPE_PSPOLL;
  838. else
  839. htype = ATH9K_PKT_TYPE_NORMAL;
  840. return htype;
  841. }
  842. static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
  843. struct ath_txq *txq, int len)
  844. {
  845. struct ath_hw *ah = sc->sc_ah;
  846. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
  847. struct ath_buf *bf_first = bf;
  848. struct ath_tx_info info;
  849. bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
  850. memset(&info, 0, sizeof(info));
  851. info.is_first = true;
  852. info.is_last = true;
  853. info.txpower = MAX_RATE_POWER;
  854. info.qcu = txq->axq_qnum;
  855. info.flags = ATH9K_TXDESC_INTREQ;
  856. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
  857. info.flags |= ATH9K_TXDESC_NOACK;
  858. if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
  859. info.flags |= ATH9K_TXDESC_LDPC;
  860. ath_buf_set_rate(sc, bf, &info, len);
  861. if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
  862. info.flags |= ATH9K_TXDESC_CLRDMASK;
  863. if (bf->bf_state.bfs_paprd)
  864. info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
  865. while (bf) {
  866. struct sk_buff *skb = bf->bf_mpdu;
  867. struct ath_frame_info *fi = get_frame_info(skb);
  868. info.type = get_hw_packet_type(skb);
  869. if (bf->bf_next)
  870. info.link = bf->bf_next->bf_daddr;
  871. else
  872. info.link = 0;
  873. info.buf_addr[0] = bf->bf_buf_addr;
  874. info.buf_len[0] = skb->len;
  875. info.pkt_len = fi->framelen;
  876. info.keyix = fi->keyix;
  877. info.keytype = fi->keytype;
  878. if (aggr) {
  879. if (bf == bf_first)
  880. info.aggr = AGGR_BUF_FIRST;
  881. else if (!bf->bf_next)
  882. info.aggr = AGGR_BUF_LAST;
  883. else
  884. info.aggr = AGGR_BUF_MIDDLE;
  885. info.ndelim = bf->bf_state.ndelim;
  886. info.aggr_len = len;
  887. }
  888. ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
  889. bf = bf->bf_next;
  890. }
  891. }
  892. static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
  893. struct ath_atx_tid *tid)
  894. {
  895. struct ath_buf *bf;
  896. enum ATH_AGGR_STATUS status;
  897. struct ieee80211_tx_info *tx_info;
  898. struct list_head bf_q;
  899. int aggr_len;
  900. do {
  901. if (skb_queue_empty(&tid->buf_q))
  902. return;
  903. INIT_LIST_HEAD(&bf_q);
  904. status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
  905. /*
  906. * no frames picked up to be aggregated;
  907. * block-ack window is not open.
  908. */
  909. if (list_empty(&bf_q))
  910. break;
  911. bf = list_first_entry(&bf_q, struct ath_buf, list);
  912. bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
  913. tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
  914. if (tid->ac->clear_ps_filter) {
  915. tid->ac->clear_ps_filter = false;
  916. tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
  917. } else {
  918. tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
  919. }
  920. /* if only one frame, send as non-aggregate */
  921. if (bf == bf->bf_lastbf) {
  922. aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
  923. bf->bf_state.bf_type = BUF_AMPDU;
  924. } else {
  925. TX_STAT_INC(txq->axq_qnum, a_aggr);
  926. }
  927. ath_tx_fill_desc(sc, bf, txq, aggr_len);
  928. ath_tx_txqaddbuf(sc, txq, &bf_q, false);
  929. } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
  930. status != ATH_AGGR_BAW_CLOSED);
  931. }
  932. int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
  933. u16 tid, u16 *ssn)
  934. {
  935. struct ath_atx_tid *txtid;
  936. struct ath_node *an;
  937. an = (struct ath_node *)sta->drv_priv;
  938. txtid = ATH_AN_2_TID(an, tid);
  939. if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
  940. return -EAGAIN;
  941. txtid->state |= AGGR_ADDBA_PROGRESS;
  942. txtid->paused = true;
  943. *ssn = txtid->seq_start = txtid->seq_next;
  944. txtid->bar_index = -1;
  945. memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
  946. txtid->baw_head = txtid->baw_tail = 0;
  947. return 0;
  948. }
  949. void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
  950. {
  951. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  952. struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
  953. struct ath_txq *txq = txtid->ac->txq;
  954. if (txtid->state & AGGR_CLEANUP)
  955. return;
  956. if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
  957. txtid->state &= ~AGGR_ADDBA_PROGRESS;
  958. return;
  959. }
  960. spin_lock_bh(&txq->axq_lock);
  961. txtid->paused = true;
  962. /*
  963. * If frames are still being transmitted for this TID, they will be
  964. * cleaned up during tx completion. To prevent race conditions, this
  965. * TID can only be reused after all in-progress subframes have been
  966. * completed.
  967. */
  968. if (txtid->baw_head != txtid->baw_tail)
  969. txtid->state |= AGGR_CLEANUP;
  970. else
  971. txtid->state &= ~AGGR_ADDBA_COMPLETE;
  972. ath_tx_flush_tid(sc, txtid);
  973. spin_unlock_bh(&txq->axq_lock);
  974. }
  975. void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
  976. struct ath_node *an)
  977. {
  978. struct ath_atx_tid *tid;
  979. struct ath_atx_ac *ac;
  980. struct ath_txq *txq;
  981. bool buffered;
  982. int tidno;
  983. for (tidno = 0, tid = &an->tid[tidno];
  984. tidno < WME_NUM_TID; tidno++, tid++) {
  985. if (!tid->sched)
  986. continue;
  987. ac = tid->ac;
  988. txq = ac->txq;
  989. spin_lock_bh(&txq->axq_lock);
  990. buffered = !skb_queue_empty(&tid->buf_q);
  991. tid->sched = false;
  992. list_del(&tid->list);
  993. if (ac->sched) {
  994. ac->sched = false;
  995. list_del(&ac->list);
  996. }
  997. spin_unlock_bh(&txq->axq_lock);
  998. ieee80211_sta_set_buffered(sta, tidno, buffered);
  999. }
  1000. }
  1001. void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
  1002. {
  1003. struct ath_atx_tid *tid;
  1004. struct ath_atx_ac *ac;
  1005. struct ath_txq *txq;
  1006. int tidno;
  1007. for (tidno = 0, tid = &an->tid[tidno];
  1008. tidno < WME_NUM_TID; tidno++, tid++) {
  1009. ac = tid->ac;
  1010. txq = ac->txq;
  1011. spin_lock_bh(&txq->axq_lock);
  1012. ac->clear_ps_filter = true;
  1013. if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
  1014. ath_tx_queue_tid(txq, tid);
  1015. ath_txq_schedule(sc, txq);
  1016. }
  1017. spin_unlock_bh(&txq->axq_lock);
  1018. }
  1019. }
  1020. void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
  1021. {
  1022. struct ath_atx_tid *txtid;
  1023. struct ath_node *an;
  1024. an = (struct ath_node *)sta->drv_priv;
  1025. if (sc->sc_flags & SC_OP_TXAGGR) {
  1026. txtid = ATH_AN_2_TID(an, tid);
  1027. txtid->baw_size =
  1028. IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
  1029. txtid->state |= AGGR_ADDBA_COMPLETE;
  1030. txtid->state &= ~AGGR_ADDBA_PROGRESS;
  1031. ath_tx_resume_tid(sc, txtid);
  1032. }
  1033. }
  1034. /********************/
  1035. /* Queue Management */
  1036. /********************/
  1037. static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
  1038. struct ath_txq *txq)
  1039. {
  1040. struct ath_atx_ac *ac, *ac_tmp;
  1041. struct ath_atx_tid *tid, *tid_tmp;
  1042. list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
  1043. list_del(&ac->list);
  1044. ac->sched = false;
  1045. list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
  1046. list_del(&tid->list);
  1047. tid->sched = false;
  1048. ath_tid_drain(sc, txq, tid);
  1049. }
  1050. }
  1051. }
  1052. struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
  1053. {
  1054. struct ath_hw *ah = sc->sc_ah;
  1055. struct ath9k_tx_queue_info qi;
  1056. static const int subtype_txq_to_hwq[] = {
  1057. [WME_AC_BE] = ATH_TXQ_AC_BE,
  1058. [WME_AC_BK] = ATH_TXQ_AC_BK,
  1059. [WME_AC_VI] = ATH_TXQ_AC_VI,
  1060. [WME_AC_VO] = ATH_TXQ_AC_VO,
  1061. };
  1062. int axq_qnum, i;
  1063. memset(&qi, 0, sizeof(qi));
  1064. qi.tqi_subtype = subtype_txq_to_hwq[subtype];
  1065. qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
  1066. qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
  1067. qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
  1068. qi.tqi_physCompBuf = 0;
  1069. /*
  1070. * Enable interrupts only for EOL and DESC conditions.
  1071. * We mark tx descriptors to receive a DESC interrupt
  1072. * when a tx queue gets deep; otherwise waiting for the
  1073. * EOL to reap descriptors. Note that this is done to
  1074. * reduce interrupt load and this only defers reaping
  1075. * descriptors, never transmitting frames. Aside from
  1076. * reducing interrupts this also permits more concurrency.
  1077. * The only potential downside is if the tx queue backs
  1078. * up in which case the top half of the kernel may backup
  1079. * due to a lack of tx descriptors.
  1080. *
  1081. * The UAPSD queue is an exception, since we take a desc-
  1082. * based intr on the EOSP frames.
  1083. */
  1084. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  1085. qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
  1086. TXQ_FLAG_TXERRINT_ENABLE;
  1087. } else {
  1088. if (qtype == ATH9K_TX_QUEUE_UAPSD)
  1089. qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
  1090. else
  1091. qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
  1092. TXQ_FLAG_TXDESCINT_ENABLE;
  1093. }
  1094. axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
  1095. if (axq_qnum == -1) {
  1096. /*
  1097. * NB: don't print a message, this happens
  1098. * normally on parts with too few tx queues
  1099. */
  1100. return NULL;
  1101. }
  1102. if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
  1103. struct ath_txq *txq = &sc->tx.txq[axq_qnum];
  1104. txq->axq_qnum = axq_qnum;
  1105. txq->mac80211_qnum = -1;
  1106. txq->axq_link = NULL;
  1107. INIT_LIST_HEAD(&txq->axq_q);
  1108. INIT_LIST_HEAD(&txq->axq_acq);
  1109. spin_lock_init(&txq->axq_lock);
  1110. txq->axq_depth = 0;
  1111. txq->axq_ampdu_depth = 0;
  1112. txq->axq_tx_inprogress = false;
  1113. sc->tx.txqsetup |= 1<<axq_qnum;
  1114. txq->txq_headidx = txq->txq_tailidx = 0;
  1115. for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
  1116. INIT_LIST_HEAD(&txq->txq_fifo[i]);
  1117. }
  1118. return &sc->tx.txq[axq_qnum];
  1119. }
  1120. int ath_txq_update(struct ath_softc *sc, int qnum,
  1121. struct ath9k_tx_queue_info *qinfo)
  1122. {
  1123. struct ath_hw *ah = sc->sc_ah;
  1124. int error = 0;
  1125. struct ath9k_tx_queue_info qi;
  1126. if (qnum == sc->beacon.beaconq) {
  1127. /*
  1128. * XXX: for beacon queue, we just save the parameter.
  1129. * It will be picked up by ath_beaconq_config when
  1130. * it's necessary.
  1131. */
  1132. sc->beacon.beacon_qi = *qinfo;
  1133. return 0;
  1134. }
  1135. BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
  1136. ath9k_hw_get_txq_props(ah, qnum, &qi);
  1137. qi.tqi_aifs = qinfo->tqi_aifs;
  1138. qi.tqi_cwmin = qinfo->tqi_cwmin;
  1139. qi.tqi_cwmax = qinfo->tqi_cwmax;
  1140. qi.tqi_burstTime = qinfo->tqi_burstTime;
  1141. qi.tqi_readyTime = qinfo->tqi_readyTime;
  1142. if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
  1143. ath_err(ath9k_hw_common(sc->sc_ah),
  1144. "Unable to update hardware queue %u!\n", qnum);
  1145. error = -EIO;
  1146. } else {
  1147. ath9k_hw_resettxqueue(ah, qnum);
  1148. }
  1149. return error;
  1150. }
  1151. int ath_cabq_update(struct ath_softc *sc)
  1152. {
  1153. struct ath9k_tx_queue_info qi;
  1154. struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
  1155. int qnum = sc->beacon.cabq->axq_qnum;
  1156. ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
  1157. /*
  1158. * Ensure the readytime % is within the bounds.
  1159. */
  1160. if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
  1161. sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
  1162. else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
  1163. sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
  1164. qi.tqi_readyTime = (cur_conf->beacon_interval *
  1165. sc->config.cabqReadytime) / 100;
  1166. ath_txq_update(sc, qnum, &qi);
  1167. return 0;
  1168. }
  1169. static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
  1170. {
  1171. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
  1172. return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
  1173. }
  1174. static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
  1175. struct list_head *list, bool retry_tx)
  1176. {
  1177. struct ath_buf *bf, *lastbf;
  1178. struct list_head bf_head;
  1179. struct ath_tx_status ts;
  1180. memset(&ts, 0, sizeof(ts));
  1181. ts.ts_status = ATH9K_TX_FLUSH;
  1182. INIT_LIST_HEAD(&bf_head);
  1183. while (!list_empty(list)) {
  1184. bf = list_first_entry(list, struct ath_buf, list);
  1185. if (bf->bf_stale) {
  1186. list_del(&bf->list);
  1187. ath_tx_return_buffer(sc, bf);
  1188. continue;
  1189. }
  1190. lastbf = bf->bf_lastbf;
  1191. list_cut_position(&bf_head, list, &lastbf->list);
  1192. txq->axq_depth--;
  1193. if (bf_is_ampdu_not_probing(bf))
  1194. txq->axq_ampdu_depth--;
  1195. if (bf_isampdu(bf))
  1196. ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
  1197. retry_tx);
  1198. else
  1199. ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
  1200. }
  1201. }
  1202. /*
  1203. * Drain a given TX queue (could be Beacon or Data)
  1204. *
  1205. * This assumes output has been stopped and
  1206. * we do not need to block ath_tx_tasklet.
  1207. */
  1208. void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
  1209. {
  1210. spin_lock_bh(&txq->axq_lock);
  1211. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  1212. int idx = txq->txq_tailidx;
  1213. while (!list_empty(&txq->txq_fifo[idx])) {
  1214. ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
  1215. retry_tx);
  1216. INCR(idx, ATH_TXFIFO_DEPTH);
  1217. }
  1218. txq->txq_tailidx = idx;
  1219. }
  1220. txq->axq_link = NULL;
  1221. txq->axq_tx_inprogress = false;
  1222. ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
  1223. /* flush any pending frames if aggregation is enabled */
  1224. if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
  1225. ath_txq_drain_pending_buffers(sc, txq);
  1226. spin_unlock_bh(&txq->axq_lock);
  1227. }
  1228. bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
  1229. {
  1230. struct ath_hw *ah = sc->sc_ah;
  1231. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1232. struct ath_txq *txq;
  1233. int i;
  1234. u32 npend = 0;
  1235. if (sc->sc_flags & SC_OP_INVALID)
  1236. return true;
  1237. ath9k_hw_abort_tx_dma(ah);
  1238. /* Check if any queue remains active */
  1239. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1240. if (!ATH_TXQ_SETUP(sc, i))
  1241. continue;
  1242. if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
  1243. npend |= BIT(i);
  1244. }
  1245. if (npend)
  1246. ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
  1247. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1248. if (!ATH_TXQ_SETUP(sc, i))
  1249. continue;
  1250. /*
  1251. * The caller will resume queues with ieee80211_wake_queues.
  1252. * Mark the queue as not stopped to prevent ath_tx_complete
  1253. * from waking the queue too early.
  1254. */
  1255. txq = &sc->tx.txq[i];
  1256. txq->stopped = false;
  1257. ath_draintxq(sc, txq, retry_tx);
  1258. }
  1259. return !npend;
  1260. }
  1261. void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
  1262. {
  1263. ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
  1264. sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
  1265. }
  1266. /* For each axq_acq entry, for each tid, try to schedule packets
  1267. * for transmit until ampdu_depth has reached min Q depth.
  1268. */
  1269. void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
  1270. {
  1271. struct ath_atx_ac *ac, *ac_tmp, *last_ac;
  1272. struct ath_atx_tid *tid, *last_tid;
  1273. if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
  1274. txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
  1275. return;
  1276. ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
  1277. last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
  1278. list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
  1279. last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
  1280. list_del(&ac->list);
  1281. ac->sched = false;
  1282. while (!list_empty(&ac->tid_q)) {
  1283. tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
  1284. list);
  1285. list_del(&tid->list);
  1286. tid->sched = false;
  1287. if (tid->paused)
  1288. continue;
  1289. ath_tx_sched_aggr(sc, txq, tid);
  1290. /*
  1291. * add tid to round-robin queue if more frames
  1292. * are pending for the tid
  1293. */
  1294. if (!skb_queue_empty(&tid->buf_q))
  1295. ath_tx_queue_tid(txq, tid);
  1296. if (tid == last_tid ||
  1297. txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
  1298. break;
  1299. }
  1300. if (!list_empty(&ac->tid_q) && !ac->sched) {
  1301. ac->sched = true;
  1302. list_add_tail(&ac->list, &txq->axq_acq);
  1303. }
  1304. if (ac == last_ac ||
  1305. txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
  1306. return;
  1307. }
  1308. }
  1309. /***********/
  1310. /* TX, DMA */
  1311. /***********/
  1312. /*
  1313. * Insert a chain of ath_buf (descriptors) on a txq and
  1314. * assume the descriptors are already chained together by caller.
  1315. */
  1316. static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
  1317. struct list_head *head, bool internal)
  1318. {
  1319. struct ath_hw *ah = sc->sc_ah;
  1320. struct ath_common *common = ath9k_hw_common(ah);
  1321. struct ath_buf *bf, *bf_last;
  1322. bool puttxbuf = false;
  1323. bool edma;
  1324. /*
  1325. * Insert the frame on the outbound list and
  1326. * pass it on to the hardware.
  1327. */
  1328. if (list_empty(head))
  1329. return;
  1330. edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1331. bf = list_first_entry(head, struct ath_buf, list);
  1332. bf_last = list_entry(head->prev, struct ath_buf, list);
  1333. ath_dbg(common, ATH_DBG_QUEUE,
  1334. "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
  1335. if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
  1336. list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
  1337. INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
  1338. puttxbuf = true;
  1339. } else {
  1340. list_splice_tail_init(head, &txq->axq_q);
  1341. if (txq->axq_link) {
  1342. ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
  1343. ath_dbg(common, ATH_DBG_XMIT,
  1344. "link[%u] (%p)=%llx (%p)\n",
  1345. txq->axq_qnum, txq->axq_link,
  1346. ito64(bf->bf_daddr), bf->bf_desc);
  1347. } else if (!edma)
  1348. puttxbuf = true;
  1349. txq->axq_link = bf_last->bf_desc;
  1350. }
  1351. if (puttxbuf) {
  1352. TX_STAT_INC(txq->axq_qnum, puttxbuf);
  1353. ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
  1354. ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
  1355. txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
  1356. }
  1357. if (!edma) {
  1358. TX_STAT_INC(txq->axq_qnum, txstart);
  1359. ath9k_hw_txstart(ah, txq->axq_qnum);
  1360. }
  1361. if (!internal) {
  1362. txq->axq_depth++;
  1363. if (bf_is_ampdu_not_probing(bf))
  1364. txq->axq_ampdu_depth++;
  1365. }
  1366. }
  1367. static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
  1368. struct sk_buff *skb, struct ath_tx_control *txctl)
  1369. {
  1370. struct ath_frame_info *fi = get_frame_info(skb);
  1371. struct list_head bf_head;
  1372. struct ath_buf *bf;
  1373. /*
  1374. * Do not queue to h/w when any of the following conditions is true:
  1375. * - there are pending frames in software queue
  1376. * - the TID is currently paused for ADDBA/BAR request
  1377. * - seqno is not within block-ack window
  1378. * - h/w queue depth exceeds low water mark
  1379. */
  1380. if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
  1381. !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
  1382. txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
  1383. /*
  1384. * Add this frame to software queue for scheduling later
  1385. * for aggregation.
  1386. */
  1387. TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
  1388. __skb_queue_tail(&tid->buf_q, skb);
  1389. if (!txctl->an || !txctl->an->sleeping)
  1390. ath_tx_queue_tid(txctl->txq, tid);
  1391. return;
  1392. }
  1393. bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
  1394. if (!bf)
  1395. return;
  1396. bf->bf_state.bf_type = BUF_AMPDU;
  1397. INIT_LIST_HEAD(&bf_head);
  1398. list_add(&bf->list, &bf_head);
  1399. /* Add sub-frame to BAW */
  1400. ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
  1401. /* Queue to h/w without aggregation */
  1402. TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
  1403. bf->bf_lastbf = bf;
  1404. ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
  1405. ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
  1406. }
  1407. static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
  1408. struct ath_atx_tid *tid, struct sk_buff *skb)
  1409. {
  1410. struct ath_frame_info *fi = get_frame_info(skb);
  1411. struct list_head bf_head;
  1412. struct ath_buf *bf;
  1413. bf = fi->bf;
  1414. if (!bf)
  1415. bf = ath_tx_setup_buffer(sc, txq, tid, skb);
  1416. if (!bf)
  1417. return;
  1418. INIT_LIST_HEAD(&bf_head);
  1419. list_add_tail(&bf->list, &bf_head);
  1420. bf->bf_state.bf_type = 0;
  1421. bf->bf_lastbf = bf;
  1422. ath_tx_fill_desc(sc, bf, txq, fi->framelen);
  1423. ath_tx_txqaddbuf(sc, txq, &bf_head, false);
  1424. TX_STAT_INC(txq->axq_qnum, queued);
  1425. }
  1426. static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
  1427. int framelen)
  1428. {
  1429. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1430. struct ieee80211_sta *sta = tx_info->control.sta;
  1431. struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
  1432. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1433. struct ath_frame_info *fi = get_frame_info(skb);
  1434. struct ath_node *an = NULL;
  1435. enum ath9k_key_type keytype;
  1436. keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
  1437. if (sta)
  1438. an = (struct ath_node *) sta->drv_priv;
  1439. memset(fi, 0, sizeof(*fi));
  1440. if (hw_key)
  1441. fi->keyix = hw_key->hw_key_idx;
  1442. else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
  1443. fi->keyix = an->ps_key;
  1444. else
  1445. fi->keyix = ATH9K_TXKEYIX_INVALID;
  1446. fi->keytype = keytype;
  1447. fi->framelen = framelen;
  1448. }
  1449. u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
  1450. {
  1451. struct ath_hw *ah = sc->sc_ah;
  1452. struct ath9k_channel *curchan = ah->curchan;
  1453. if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
  1454. (curchan->channelFlags & CHANNEL_5GHZ) &&
  1455. (chainmask == 0x7) && (rate < 0x90))
  1456. return 0x3;
  1457. else
  1458. return chainmask;
  1459. }
  1460. /*
  1461. * Assign a descriptor (and sequence number if necessary,
  1462. * and map buffer for DMA. Frees skb on error
  1463. */
  1464. static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
  1465. struct ath_txq *txq,
  1466. struct ath_atx_tid *tid,
  1467. struct sk_buff *skb)
  1468. {
  1469. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1470. struct ath_frame_info *fi = get_frame_info(skb);
  1471. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1472. struct ath_buf *bf;
  1473. u16 seqno;
  1474. bf = ath_tx_get_buffer(sc);
  1475. if (!bf) {
  1476. ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
  1477. goto error;
  1478. }
  1479. ATH_TXBUF_RESET(bf);
  1480. if (tid) {
  1481. seqno = tid->seq_next;
  1482. hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
  1483. INCR(tid->seq_next, IEEE80211_SEQ_MAX);
  1484. bf->bf_state.seqno = seqno;
  1485. }
  1486. bf->bf_mpdu = skb;
  1487. bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
  1488. skb->len, DMA_TO_DEVICE);
  1489. if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
  1490. bf->bf_mpdu = NULL;
  1491. bf->bf_buf_addr = 0;
  1492. ath_err(ath9k_hw_common(sc->sc_ah),
  1493. "dma_mapping_error() on TX\n");
  1494. ath_tx_return_buffer(sc, bf);
  1495. goto error;
  1496. }
  1497. fi->bf = bf;
  1498. return bf;
  1499. error:
  1500. dev_kfree_skb_any(skb);
  1501. return NULL;
  1502. }
  1503. /* FIXME: tx power */
  1504. static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
  1505. struct ath_tx_control *txctl)
  1506. {
  1507. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1508. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1509. struct ath_atx_tid *tid = NULL;
  1510. struct ath_buf *bf;
  1511. u8 tidno;
  1512. if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
  1513. ieee80211_is_data_qos(hdr->frame_control)) {
  1514. tidno = ieee80211_get_qos_ctl(hdr)[0] &
  1515. IEEE80211_QOS_CTL_TID_MASK;
  1516. tid = ATH_AN_2_TID(txctl->an, tidno);
  1517. WARN_ON(tid->ac->txq != txctl->txq);
  1518. }
  1519. if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
  1520. /*
  1521. * Try aggregation if it's a unicast data frame
  1522. * and the destination is HT capable.
  1523. */
  1524. ath_tx_send_ampdu(sc, tid, skb, txctl);
  1525. } else {
  1526. bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
  1527. if (!bf)
  1528. return;
  1529. bf->bf_state.bfs_paprd = txctl->paprd;
  1530. if (txctl->paprd)
  1531. bf->bf_state.bfs_paprd_timestamp = jiffies;
  1532. ath_tx_send_normal(sc, txctl->txq, tid, skb);
  1533. }
  1534. }
  1535. /* Upon failure caller should free skb */
  1536. int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
  1537. struct ath_tx_control *txctl)
  1538. {
  1539. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  1540. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1541. struct ieee80211_sta *sta = info->control.sta;
  1542. struct ieee80211_vif *vif = info->control.vif;
  1543. struct ath_softc *sc = hw->priv;
  1544. struct ath_txq *txq = txctl->txq;
  1545. int padpos, padsize;
  1546. int frmlen = skb->len + FCS_LEN;
  1547. int q;
  1548. /* NOTE: sta can be NULL according to net/mac80211.h */
  1549. if (sta)
  1550. txctl->an = (struct ath_node *)sta->drv_priv;
  1551. if (info->control.hw_key)
  1552. frmlen += info->control.hw_key->icv_len;
  1553. /*
  1554. * As a temporary workaround, assign seq# here; this will likely need
  1555. * to be cleaned up to work better with Beacon transmission and virtual
  1556. * BSSes.
  1557. */
  1558. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1559. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1560. sc->tx.seq_no += 0x10;
  1561. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1562. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1563. }
  1564. /* Add the padding after the header if this is not already done */
  1565. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1566. padsize = padpos & 3;
  1567. if (padsize && skb->len > padpos) {
  1568. if (skb_headroom(skb) < padsize)
  1569. return -ENOMEM;
  1570. skb_push(skb, padsize);
  1571. memmove(skb->data, skb->data + padsize, padpos);
  1572. hdr = (struct ieee80211_hdr *) skb->data;
  1573. }
  1574. if ((vif && vif->type != NL80211_IFTYPE_AP &&
  1575. vif->type != NL80211_IFTYPE_AP_VLAN) ||
  1576. !ieee80211_is_data(hdr->frame_control))
  1577. info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
  1578. setup_frame_info(hw, skb, frmlen);
  1579. /*
  1580. * At this point, the vif, hw_key and sta pointers in the tx control
  1581. * info are no longer valid (overwritten by the ath_frame_info data.
  1582. */
  1583. q = skb_get_queue_mapping(skb);
  1584. spin_lock_bh(&txq->axq_lock);
  1585. if (txq == sc->tx.txq_map[q] &&
  1586. ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
  1587. ieee80211_stop_queue(sc->hw, q);
  1588. txq->stopped = 1;
  1589. }
  1590. ath_tx_start_dma(sc, skb, txctl);
  1591. spin_unlock_bh(&txq->axq_lock);
  1592. return 0;
  1593. }
  1594. /*****************/
  1595. /* TX Completion */
  1596. /*****************/
  1597. static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  1598. int tx_flags, struct ath_txq *txq)
  1599. {
  1600. struct ieee80211_hw *hw = sc->hw;
  1601. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1602. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1603. struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
  1604. int q, padpos, padsize;
  1605. ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
  1606. if (!(tx_flags & ATH_TX_ERROR))
  1607. /* Frame was ACKed */
  1608. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  1609. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1610. padsize = padpos & 3;
  1611. if (padsize && skb->len>padpos+padsize) {
  1612. /*
  1613. * Remove MAC header padding before giving the frame back to
  1614. * mac80211.
  1615. */
  1616. memmove(skb->data + padsize, skb->data, padpos);
  1617. skb_pull(skb, padsize);
  1618. }
  1619. if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
  1620. sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
  1621. ath_dbg(common, ATH_DBG_PS,
  1622. "Going back to sleep after having received TX status (0x%lx)\n",
  1623. sc->ps_flags & (PS_WAIT_FOR_BEACON |
  1624. PS_WAIT_FOR_CAB |
  1625. PS_WAIT_FOR_PSPOLL_DATA |
  1626. PS_WAIT_FOR_TX_ACK));
  1627. }
  1628. q = skb_get_queue_mapping(skb);
  1629. if (txq == sc->tx.txq_map[q]) {
  1630. if (WARN_ON(--txq->pending_frames < 0))
  1631. txq->pending_frames = 0;
  1632. if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
  1633. ieee80211_wake_queue(sc->hw, q);
  1634. txq->stopped = 0;
  1635. }
  1636. }
  1637. ieee80211_tx_status(hw, skb);
  1638. }
  1639. static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
  1640. struct ath_txq *txq, struct list_head *bf_q,
  1641. struct ath_tx_status *ts, int txok)
  1642. {
  1643. struct sk_buff *skb = bf->bf_mpdu;
  1644. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1645. unsigned long flags;
  1646. int tx_flags = 0;
  1647. if (!txok)
  1648. tx_flags |= ATH_TX_ERROR;
  1649. if (ts->ts_status & ATH9K_TXERR_FILT)
  1650. tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
  1651. dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
  1652. bf->bf_buf_addr = 0;
  1653. if (bf->bf_state.bfs_paprd) {
  1654. if (time_after(jiffies,
  1655. bf->bf_state.bfs_paprd_timestamp +
  1656. msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
  1657. dev_kfree_skb_any(skb);
  1658. else
  1659. complete(&sc->paprd_complete);
  1660. } else {
  1661. ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
  1662. ath_tx_complete(sc, skb, tx_flags, txq);
  1663. }
  1664. /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
  1665. * accidentally reference it later.
  1666. */
  1667. bf->bf_mpdu = NULL;
  1668. /*
  1669. * Return the list of ath_buf of this mpdu to free queue
  1670. */
  1671. spin_lock_irqsave(&sc->tx.txbuflock, flags);
  1672. list_splice_tail_init(bf_q, &sc->tx.txbuf);
  1673. spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
  1674. }
  1675. static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
  1676. struct ath_tx_status *ts, int nframes, int nbad,
  1677. int txok)
  1678. {
  1679. struct sk_buff *skb = bf->bf_mpdu;
  1680. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1681. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1682. struct ieee80211_hw *hw = sc->hw;
  1683. struct ath_hw *ah = sc->sc_ah;
  1684. u8 i, tx_rateindex;
  1685. if (txok)
  1686. tx_info->status.ack_signal = ts->ts_rssi;
  1687. tx_rateindex = ts->ts_rateindex;
  1688. WARN_ON(tx_rateindex >= hw->max_rates);
  1689. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
  1690. tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
  1691. BUG_ON(nbad > nframes);
  1692. }
  1693. tx_info->status.ampdu_len = nframes;
  1694. tx_info->status.ampdu_ack_len = nframes - nbad;
  1695. if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
  1696. (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
  1697. /*
  1698. * If an underrun error is seen assume it as an excessive
  1699. * retry only if max frame trigger level has been reached
  1700. * (2 KB for single stream, and 4 KB for dual stream).
  1701. * Adjust the long retry as if the frame was tried
  1702. * hw->max_rate_tries times to affect how rate control updates
  1703. * PER for the failed rate.
  1704. * In case of congestion on the bus penalizing this type of
  1705. * underruns should help hardware actually transmit new frames
  1706. * successfully by eventually preferring slower rates.
  1707. * This itself should also alleviate congestion on the bus.
  1708. */
  1709. if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
  1710. ATH9K_TX_DELIM_UNDERRUN)) &&
  1711. ieee80211_is_data(hdr->frame_control) &&
  1712. ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
  1713. tx_info->status.rates[tx_rateindex].count =
  1714. hw->max_rate_tries;
  1715. }
  1716. for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
  1717. tx_info->status.rates[i].count = 0;
  1718. tx_info->status.rates[i].idx = -1;
  1719. }
  1720. tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
  1721. }
  1722. static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
  1723. struct ath_tx_status *ts, struct ath_buf *bf,
  1724. struct list_head *bf_head)
  1725. {
  1726. int txok;
  1727. txq->axq_depth--;
  1728. txok = !(ts->ts_status & ATH9K_TXERR_MASK);
  1729. txq->axq_tx_inprogress = false;
  1730. if (bf_is_ampdu_not_probing(bf))
  1731. txq->axq_ampdu_depth--;
  1732. if (!bf_isampdu(bf)) {
  1733. ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
  1734. ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
  1735. } else
  1736. ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
  1737. if (sc->sc_flags & SC_OP_TXAGGR)
  1738. ath_txq_schedule(sc, txq);
  1739. }
  1740. static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
  1741. {
  1742. struct ath_hw *ah = sc->sc_ah;
  1743. struct ath_common *common = ath9k_hw_common(ah);
  1744. struct ath_buf *bf, *lastbf, *bf_held = NULL;
  1745. struct list_head bf_head;
  1746. struct ath_desc *ds;
  1747. struct ath_tx_status ts;
  1748. int status;
  1749. ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
  1750. txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
  1751. txq->axq_link);
  1752. spin_lock_bh(&txq->axq_lock);
  1753. for (;;) {
  1754. if (work_pending(&sc->hw_reset_work))
  1755. break;
  1756. if (list_empty(&txq->axq_q)) {
  1757. txq->axq_link = NULL;
  1758. if (sc->sc_flags & SC_OP_TXAGGR)
  1759. ath_txq_schedule(sc, txq);
  1760. break;
  1761. }
  1762. bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
  1763. /*
  1764. * There is a race condition that a BH gets scheduled
  1765. * after sw writes TxE and before hw re-load the last
  1766. * descriptor to get the newly chained one.
  1767. * Software must keep the last DONE descriptor as a
  1768. * holding descriptor - software does so by marking
  1769. * it with the STALE flag.
  1770. */
  1771. bf_held = NULL;
  1772. if (bf->bf_stale) {
  1773. bf_held = bf;
  1774. if (list_is_last(&bf_held->list, &txq->axq_q))
  1775. break;
  1776. bf = list_entry(bf_held->list.next, struct ath_buf,
  1777. list);
  1778. }
  1779. lastbf = bf->bf_lastbf;
  1780. ds = lastbf->bf_desc;
  1781. memset(&ts, 0, sizeof(ts));
  1782. status = ath9k_hw_txprocdesc(ah, ds, &ts);
  1783. if (status == -EINPROGRESS)
  1784. break;
  1785. TX_STAT_INC(txq->axq_qnum, txprocdesc);
  1786. /*
  1787. * Remove ath_buf's of the same transmit unit from txq,
  1788. * however leave the last descriptor back as the holding
  1789. * descriptor for hw.
  1790. */
  1791. lastbf->bf_stale = true;
  1792. INIT_LIST_HEAD(&bf_head);
  1793. if (!list_is_singular(&lastbf->list))
  1794. list_cut_position(&bf_head,
  1795. &txq->axq_q, lastbf->list.prev);
  1796. if (bf_held) {
  1797. list_del(&bf_held->list);
  1798. ath_tx_return_buffer(sc, bf_held);
  1799. }
  1800. ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
  1801. }
  1802. spin_unlock_bh(&txq->axq_lock);
  1803. }
  1804. static void ath_tx_complete_poll_work(struct work_struct *work)
  1805. {
  1806. struct ath_softc *sc = container_of(work, struct ath_softc,
  1807. tx_complete_work.work);
  1808. struct ath_txq *txq;
  1809. int i;
  1810. bool needreset = false;
  1811. #ifdef CONFIG_ATH9K_DEBUGFS
  1812. sc->tx_complete_poll_work_seen++;
  1813. #endif
  1814. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
  1815. if (ATH_TXQ_SETUP(sc, i)) {
  1816. txq = &sc->tx.txq[i];
  1817. spin_lock_bh(&txq->axq_lock);
  1818. if (txq->axq_depth) {
  1819. if (txq->axq_tx_inprogress) {
  1820. needreset = true;
  1821. spin_unlock_bh(&txq->axq_lock);
  1822. break;
  1823. } else {
  1824. txq->axq_tx_inprogress = true;
  1825. }
  1826. }
  1827. spin_unlock_bh(&txq->axq_lock);
  1828. }
  1829. if (needreset) {
  1830. ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
  1831. "tx hung, resetting the chip\n");
  1832. RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
  1833. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  1834. }
  1835. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
  1836. msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
  1837. }
  1838. void ath_tx_tasklet(struct ath_softc *sc)
  1839. {
  1840. int i;
  1841. u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
  1842. ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
  1843. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1844. if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
  1845. ath_tx_processq(sc, &sc->tx.txq[i]);
  1846. }
  1847. }
  1848. void ath_tx_edma_tasklet(struct ath_softc *sc)
  1849. {
  1850. struct ath_tx_status ts;
  1851. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1852. struct ath_hw *ah = sc->sc_ah;
  1853. struct ath_txq *txq;
  1854. struct ath_buf *bf, *lastbf;
  1855. struct list_head bf_head;
  1856. int status;
  1857. for (;;) {
  1858. if (work_pending(&sc->hw_reset_work))
  1859. break;
  1860. status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
  1861. if (status == -EINPROGRESS)
  1862. break;
  1863. if (status == -EIO) {
  1864. ath_dbg(common, ATH_DBG_XMIT,
  1865. "Error processing tx status\n");
  1866. break;
  1867. }
  1868. /* Skip beacon completions */
  1869. if (ts.qid == sc->beacon.beaconq)
  1870. continue;
  1871. txq = &sc->tx.txq[ts.qid];
  1872. spin_lock_bh(&txq->axq_lock);
  1873. if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
  1874. spin_unlock_bh(&txq->axq_lock);
  1875. return;
  1876. }
  1877. bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
  1878. struct ath_buf, list);
  1879. lastbf = bf->bf_lastbf;
  1880. INIT_LIST_HEAD(&bf_head);
  1881. list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
  1882. &lastbf->list);
  1883. if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
  1884. INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
  1885. if (!list_empty(&txq->axq_q)) {
  1886. struct list_head bf_q;
  1887. INIT_LIST_HEAD(&bf_q);
  1888. txq->axq_link = NULL;
  1889. list_splice_tail_init(&txq->axq_q, &bf_q);
  1890. ath_tx_txqaddbuf(sc, txq, &bf_q, true);
  1891. }
  1892. }
  1893. ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
  1894. spin_unlock_bh(&txq->axq_lock);
  1895. }
  1896. }
  1897. /*****************/
  1898. /* Init, Cleanup */
  1899. /*****************/
  1900. static int ath_txstatus_setup(struct ath_softc *sc, int size)
  1901. {
  1902. struct ath_descdma *dd = &sc->txsdma;
  1903. u8 txs_len = sc->sc_ah->caps.txs_len;
  1904. dd->dd_desc_len = size * txs_len;
  1905. dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
  1906. &dd->dd_desc_paddr, GFP_KERNEL);
  1907. if (!dd->dd_desc)
  1908. return -ENOMEM;
  1909. return 0;
  1910. }
  1911. static int ath_tx_edma_init(struct ath_softc *sc)
  1912. {
  1913. int err;
  1914. err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
  1915. if (!err)
  1916. ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
  1917. sc->txsdma.dd_desc_paddr,
  1918. ATH_TXSTATUS_RING_SIZE);
  1919. return err;
  1920. }
  1921. static void ath_tx_edma_cleanup(struct ath_softc *sc)
  1922. {
  1923. struct ath_descdma *dd = &sc->txsdma;
  1924. dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
  1925. dd->dd_desc_paddr);
  1926. }
  1927. int ath_tx_init(struct ath_softc *sc, int nbufs)
  1928. {
  1929. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1930. int error = 0;
  1931. spin_lock_init(&sc->tx.txbuflock);
  1932. error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
  1933. "tx", nbufs, 1, 1);
  1934. if (error != 0) {
  1935. ath_err(common,
  1936. "Failed to allocate tx descriptors: %d\n", error);
  1937. goto err;
  1938. }
  1939. error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
  1940. "beacon", ATH_BCBUF, 1, 1);
  1941. if (error != 0) {
  1942. ath_err(common,
  1943. "Failed to allocate beacon descriptors: %d\n", error);
  1944. goto err;
  1945. }
  1946. INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
  1947. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  1948. error = ath_tx_edma_init(sc);
  1949. if (error)
  1950. goto err;
  1951. }
  1952. err:
  1953. if (error != 0)
  1954. ath_tx_cleanup(sc);
  1955. return error;
  1956. }
  1957. void ath_tx_cleanup(struct ath_softc *sc)
  1958. {
  1959. if (sc->beacon.bdma.dd_desc_len != 0)
  1960. ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
  1961. if (sc->tx.txdma.dd_desc_len != 0)
  1962. ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
  1963. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  1964. ath_tx_edma_cleanup(sc);
  1965. }
  1966. void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
  1967. {
  1968. struct ath_atx_tid *tid;
  1969. struct ath_atx_ac *ac;
  1970. int tidno, acno;
  1971. for (tidno = 0, tid = &an->tid[tidno];
  1972. tidno < WME_NUM_TID;
  1973. tidno++, tid++) {
  1974. tid->an = an;
  1975. tid->tidno = tidno;
  1976. tid->seq_start = tid->seq_next = 0;
  1977. tid->baw_size = WME_MAX_BA;
  1978. tid->baw_head = tid->baw_tail = 0;
  1979. tid->sched = false;
  1980. tid->paused = false;
  1981. tid->state &= ~AGGR_CLEANUP;
  1982. __skb_queue_head_init(&tid->buf_q);
  1983. acno = TID_TO_WME_AC(tidno);
  1984. tid->ac = &an->ac[acno];
  1985. tid->state &= ~AGGR_ADDBA_COMPLETE;
  1986. tid->state &= ~AGGR_ADDBA_PROGRESS;
  1987. }
  1988. for (acno = 0, ac = &an->ac[acno];
  1989. acno < WME_NUM_AC; acno++, ac++) {
  1990. ac->sched = false;
  1991. ac->txq = sc->tx.txq_map[acno];
  1992. INIT_LIST_HEAD(&ac->tid_q);
  1993. }
  1994. }
  1995. void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
  1996. {
  1997. struct ath_atx_ac *ac;
  1998. struct ath_atx_tid *tid;
  1999. struct ath_txq *txq;
  2000. int tidno;
  2001. for (tidno = 0, tid = &an->tid[tidno];
  2002. tidno < WME_NUM_TID; tidno++, tid++) {
  2003. ac = tid->ac;
  2004. txq = ac->txq;
  2005. spin_lock_bh(&txq->axq_lock);
  2006. if (tid->sched) {
  2007. list_del(&tid->list);
  2008. tid->sched = false;
  2009. }
  2010. if (ac->sched) {
  2011. list_del(&ac->list);
  2012. tid->ac->sched = false;
  2013. }
  2014. ath_tid_drain(sc, txq, tid);
  2015. tid->state &= ~AGGR_ADDBA_COMPLETE;
  2016. tid->state &= ~AGGR_CLEANUP;
  2017. spin_unlock_bh(&txq->axq_lock);
  2018. }
  2019. }