neponset.c 11 KB

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  1. /*
  2. * linux/arch/arm/mach-sa1100/neponset.c
  3. */
  4. #include <linux/err.h>
  5. #include <linux/init.h>
  6. #include <linux/ioport.h>
  7. #include <linux/irq.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pm.h>
  12. #include <linux/serial_core.h>
  13. #include <linux/slab.h>
  14. #include <asm/mach-types.h>
  15. #include <asm/mach/map.h>
  16. #include <asm/mach/serial_sa1100.h>
  17. #include <asm/hardware/sa1111.h>
  18. #include <asm/sizes.h>
  19. #include <mach/hardware.h>
  20. #include <mach/assabet.h>
  21. #include <mach/neponset.h>
  22. #define NEP_IRQ_SMC91X 0
  23. #define NEP_IRQ_USAR 1
  24. #define NEP_IRQ_SA1111 2
  25. #define NEP_IRQ_NR 3
  26. #define WHOAMI 0x00
  27. #define LEDS 0x10
  28. #define SWPK 0x20
  29. #define IRR 0x24
  30. #define KP_Y_IN 0x80
  31. #define KP_X_OUT 0x90
  32. #define NCR_0 0xa0
  33. #define MDM_CTL_0 0xb0
  34. #define MDM_CTL_1 0xb4
  35. #define AUD_CTL 0xc0
  36. #define IRR_ETHERNET (1 << 0)
  37. #define IRR_USAR (1 << 1)
  38. #define IRR_SA1111 (1 << 2)
  39. #define MDM_CTL0_RTS1 (1 << 0)
  40. #define MDM_CTL0_DTR1 (1 << 1)
  41. #define MDM_CTL0_RTS2 (1 << 2)
  42. #define MDM_CTL0_DTR2 (1 << 3)
  43. #define MDM_CTL1_CTS1 (1 << 0)
  44. #define MDM_CTL1_DSR1 (1 << 1)
  45. #define MDM_CTL1_DCD1 (1 << 2)
  46. #define MDM_CTL1_CTS2 (1 << 3)
  47. #define MDM_CTL1_DSR2 (1 << 4)
  48. #define MDM_CTL1_DCD2 (1 << 5)
  49. #define AUD_SEL_1341 (1 << 0)
  50. #define AUD_MUTE_1341 (1 << 1)
  51. extern void sa1110_mb_disable(void);
  52. struct neponset_drvdata {
  53. void __iomem *base;
  54. struct platform_device *sa1111;
  55. struct platform_device *smc91x;
  56. unsigned irq_base;
  57. #ifdef CONFIG_PM_SLEEP
  58. u32 ncr0;
  59. u32 mdm_ctl_0;
  60. #endif
  61. };
  62. static void __iomem *nep_base;
  63. void neponset_ncr_frob(unsigned int mask, unsigned int val)
  64. {
  65. void __iomem *base = nep_base;
  66. if (base) {
  67. unsigned long flags;
  68. unsigned v;
  69. local_irq_save(flags);
  70. v = readb_relaxed(base + NCR_0);
  71. writeb_relaxed((v & ~mask) | val, base + NCR_0);
  72. local_irq_restore(flags);
  73. } else {
  74. WARN(1, "nep_base unset\n");
  75. }
  76. }
  77. static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
  78. {
  79. void __iomem *base = nep_base;
  80. u_int mdm_ctl0;
  81. if (!base)
  82. return;
  83. mdm_ctl0 = readb_relaxed(base + MDM_CTL_0);
  84. if (port->mapbase == _Ser1UTCR0) {
  85. if (mctrl & TIOCM_RTS)
  86. mdm_ctl0 &= ~MDM_CTL0_RTS2;
  87. else
  88. mdm_ctl0 |= MDM_CTL0_RTS2;
  89. if (mctrl & TIOCM_DTR)
  90. mdm_ctl0 &= ~MDM_CTL0_DTR2;
  91. else
  92. mdm_ctl0 |= MDM_CTL0_DTR2;
  93. } else if (port->mapbase == _Ser3UTCR0) {
  94. if (mctrl & TIOCM_RTS)
  95. mdm_ctl0 &= ~MDM_CTL0_RTS1;
  96. else
  97. mdm_ctl0 |= MDM_CTL0_RTS1;
  98. if (mctrl & TIOCM_DTR)
  99. mdm_ctl0 &= ~MDM_CTL0_DTR1;
  100. else
  101. mdm_ctl0 |= MDM_CTL0_DTR1;
  102. }
  103. writeb_relaxed(mdm_ctl0, base + MDM_CTL_0);
  104. }
  105. static u_int neponset_get_mctrl(struct uart_port *port)
  106. {
  107. void __iomem *base = nep_base;
  108. u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
  109. u_int mdm_ctl1;
  110. if (!base)
  111. return ret;
  112. mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
  113. if (port->mapbase == _Ser1UTCR0) {
  114. if (mdm_ctl1 & MDM_CTL1_DCD2)
  115. ret &= ~TIOCM_CD;
  116. if (mdm_ctl1 & MDM_CTL1_CTS2)
  117. ret &= ~TIOCM_CTS;
  118. if (mdm_ctl1 & MDM_CTL1_DSR2)
  119. ret &= ~TIOCM_DSR;
  120. } else if (port->mapbase == _Ser3UTCR0) {
  121. if (mdm_ctl1 & MDM_CTL1_DCD1)
  122. ret &= ~TIOCM_CD;
  123. if (mdm_ctl1 & MDM_CTL1_CTS1)
  124. ret &= ~TIOCM_CTS;
  125. if (mdm_ctl1 & MDM_CTL1_DSR1)
  126. ret &= ~TIOCM_DSR;
  127. }
  128. return ret;
  129. }
  130. static struct sa1100_port_fns neponset_port_fns __devinitdata = {
  131. .set_mctrl = neponset_set_mctrl,
  132. .get_mctrl = neponset_get_mctrl,
  133. };
  134. /*
  135. * Install handler for Neponset IRQ. Note that we have to loop here
  136. * since the ETHERNET and USAR IRQs are level based, and we need to
  137. * ensure that the IRQ signal is deasserted before returning. This
  138. * is rather unfortunate.
  139. */
  140. static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
  141. {
  142. struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
  143. unsigned int irr;
  144. while (1) {
  145. /*
  146. * Acknowledge the parent IRQ.
  147. */
  148. desc->irq_data.chip->irq_ack(&desc->irq_data);
  149. /*
  150. * Read the interrupt reason register. Let's have all
  151. * active IRQ bits high. Note: there is a typo in the
  152. * Neponset user's guide for the SA1111 IRR level.
  153. */
  154. irr = readb_relaxed(d->base + IRR);
  155. irr ^= IRR_ETHERNET | IRR_USAR;
  156. if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
  157. break;
  158. /*
  159. * Since there is no individual mask, we have to
  160. * mask the parent IRQ. This is safe, since we'll
  161. * recheck the register for any pending IRQs.
  162. */
  163. if (irr & (IRR_ETHERNET | IRR_USAR)) {
  164. desc->irq_data.chip->irq_mask(&desc->irq_data);
  165. /*
  166. * Ack the interrupt now to prevent re-entering
  167. * this neponset handler. Again, this is safe
  168. * since we'll check the IRR register prior to
  169. * leaving.
  170. */
  171. desc->irq_data.chip->irq_ack(&desc->irq_data);
  172. if (irr & IRR_ETHERNET)
  173. generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
  174. if (irr & IRR_USAR)
  175. generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
  176. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  177. }
  178. if (irr & IRR_SA1111)
  179. generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
  180. }
  181. }
  182. /* Yes, we really do not have any kind of masking or unmasking */
  183. static void nochip_noop(struct irq_data *irq)
  184. {
  185. }
  186. static struct irq_chip nochip = {
  187. .name = "neponset",
  188. .irq_ack = nochip_noop,
  189. .irq_mask = nochip_noop,
  190. .irq_unmask = nochip_noop,
  191. };
  192. static struct sa1111_platform_data sa1111_info = {
  193. .irq_base = IRQ_BOARD_END,
  194. };
  195. static int __devinit neponset_probe(struct platform_device *dev)
  196. {
  197. struct neponset_drvdata *d;
  198. struct resource *nep_res, *sa1111_res, *smc91x_res;
  199. struct resource sa1111_resources[] = {
  200. DEFINE_RES_MEM(0x40000000, SZ_8K),
  201. { .flags = IORESOURCE_IRQ },
  202. };
  203. struct platform_device_info sa1111_devinfo = {
  204. .parent = &dev->dev,
  205. .name = "sa1111",
  206. .id = 0,
  207. .res = sa1111_resources,
  208. .num_res = ARRAY_SIZE(sa1111_resources),
  209. .data = &sa1111_info,
  210. .size_data = sizeof(sa1111_info),
  211. .dma_mask = 0xffffffffUL,
  212. };
  213. struct resource smc91x_resources[] = {
  214. DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
  215. 0x02000000, "smc91x-regs"),
  216. DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
  217. 0x02000000, "smc91x-attrib"),
  218. { .flags = IORESOURCE_IRQ },
  219. };
  220. struct platform_device_info smc91x_devinfo = {
  221. .parent = &dev->dev,
  222. .name = "smc91x",
  223. .id = 0,
  224. .res = smc91x_resources,
  225. .num_res = ARRAY_SIZE(smc91x_resources),
  226. };
  227. int ret, irq;
  228. if (nep_base)
  229. return -EBUSY;
  230. irq = ret = platform_get_irq(dev, 0);
  231. if (ret < 0)
  232. goto err_alloc;
  233. nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  234. smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
  235. sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
  236. if (!nep_res || !smc91x_res || !sa1111_res) {
  237. ret = -ENXIO;
  238. goto err_alloc;
  239. }
  240. d = kzalloc(sizeof(*d), GFP_KERNEL);
  241. if (!d) {
  242. ret = -ENOMEM;
  243. goto err_alloc;
  244. }
  245. d->base = ioremap(nep_res->start, SZ_4K);
  246. if (!d->base) {
  247. ret = -ENOMEM;
  248. goto err_ioremap;
  249. }
  250. if (readb_relaxed(d->base + WHOAMI) != 0x11) {
  251. dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
  252. readb_relaxed(d->base + WHOAMI));
  253. ret = -ENODEV;
  254. goto err_id;
  255. }
  256. ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
  257. if (ret <= 0) {
  258. dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
  259. NEP_IRQ_NR, ret);
  260. if (ret == 0)
  261. ret = -ENOMEM;
  262. goto err_irq_alloc;
  263. }
  264. d->irq_base = ret;
  265. irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
  266. handle_simple_irq);
  267. set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE);
  268. irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
  269. handle_simple_irq);
  270. set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE);
  271. irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
  272. irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
  273. irq_set_handler_data(irq, d);
  274. irq_set_chained_handler(irq, neponset_irq_handler);
  275. /*
  276. * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
  277. * something on the Neponset activates this IRQ on sleep (eth?)
  278. */
  279. #if 0
  280. enable_irq_wake(irq);
  281. #endif
  282. dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
  283. d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
  284. nep_base = d->base;
  285. sa1100_register_uart_fns(&neponset_port_fns);
  286. /* Ensure that the memory bus request/grant signals are setup */
  287. sa1110_mb_disable();
  288. /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
  289. writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
  290. sa1111_resources[0].parent = sa1111_res;
  291. sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
  292. sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
  293. d->sa1111 = platform_device_register_full(&sa1111_devinfo);
  294. smc91x_resources[0].parent = smc91x_res;
  295. smc91x_resources[1].parent = smc91x_res;
  296. smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
  297. smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
  298. d->smc91x = platform_device_register_full(&smc91x_devinfo);
  299. platform_set_drvdata(dev, d);
  300. return 0;
  301. err_irq_alloc:
  302. err_id:
  303. iounmap(d->base);
  304. err_ioremap:
  305. kfree(d);
  306. err_alloc:
  307. return ret;
  308. }
  309. static int __devexit neponset_remove(struct platform_device *dev)
  310. {
  311. struct neponset_drvdata *d = platform_get_drvdata(dev);
  312. int irq = platform_get_irq(dev, 0);
  313. if (!IS_ERR(d->sa1111))
  314. platform_device_unregister(d->sa1111);
  315. if (!IS_ERR(d->smc91x))
  316. platform_device_unregister(d->smc91x);
  317. irq_set_chained_handler(irq, NULL);
  318. irq_free_descs(d->irq_base, NEP_IRQ_NR);
  319. nep_base = NULL;
  320. iounmap(d->base);
  321. kfree(d);
  322. return 0;
  323. }
  324. #ifdef CONFIG_PM_SLEEP
  325. static int neponset_suspend(struct device *dev)
  326. {
  327. struct neponset_drvdata *d = dev_get_drvdata(dev);
  328. d->ncr0 = readb_relaxed(d->base + NCR_0);
  329. d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0);
  330. return 0;
  331. }
  332. static int neponset_resume(struct device *dev)
  333. {
  334. struct neponset_drvdata *d = dev_get_drvdata(dev);
  335. writeb_relaxed(d->ncr0, d->base + NCR_0);
  336. writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0);
  337. return 0;
  338. }
  339. static const struct dev_pm_ops neponset_pm_ops = {
  340. .suspend_noirq = neponset_suspend,
  341. .resume_noirq = neponset_resume,
  342. .freeze_noirq = neponset_suspend,
  343. .restore_noirq = neponset_resume,
  344. };
  345. #define PM_OPS &neponset_pm_ops
  346. #else
  347. #define PM_OPS NULL
  348. #endif
  349. static struct platform_driver neponset_device_driver = {
  350. .probe = neponset_probe,
  351. .remove = __devexit_p(neponset_remove),
  352. .driver = {
  353. .name = "neponset",
  354. .owner = THIS_MODULE,
  355. .pm = PM_OPS,
  356. },
  357. };
  358. static int __init neponset_init(void)
  359. {
  360. return platform_driver_register(&neponset_device_driver);
  361. }
  362. subsys_initcall(neponset_init);
  363. static struct map_desc neponset_io_desc[] __initdata = {
  364. { /* System Registers */
  365. .virtual = 0xf3000000,
  366. .pfn = __phys_to_pfn(0x10000000),
  367. .length = SZ_1M,
  368. .type = MT_DEVICE
  369. }, { /* SA-1111 */
  370. .virtual = 0xf4000000,
  371. .pfn = __phys_to_pfn(0x40000000),
  372. .length = SZ_1M,
  373. .type = MT_DEVICE
  374. }
  375. };
  376. void __init neponset_map_io(void)
  377. {
  378. iotable_init(neponset_io_desc, ARRAY_SIZE(neponset_io_desc));
  379. }