mci.c 21 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include <linux/slab.h>
  18. #include "ath9k.h"
  19. #include "mci.h"
  20. static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };
  21. static struct ath_mci_profile_info*
  22. ath_mci_find_profile(struct ath_mci_profile *mci,
  23. struct ath_mci_profile_info *info)
  24. {
  25. struct ath_mci_profile_info *entry;
  26. if (list_empty(&mci->info))
  27. return NULL;
  28. list_for_each_entry(entry, &mci->info, list) {
  29. if (entry->conn_handle == info->conn_handle)
  30. return entry;
  31. }
  32. return NULL;
  33. }
  34. static bool ath_mci_add_profile(struct ath_common *common,
  35. struct ath_mci_profile *mci,
  36. struct ath_mci_profile_info *info)
  37. {
  38. struct ath_mci_profile_info *entry;
  39. u8 voice_priority[] = { 110, 110, 110, 112, 110, 110, 114, 116, 118 };
  40. if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
  41. (info->type == MCI_GPM_COEX_PROFILE_VOICE))
  42. return false;
  43. if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
  44. (info->type != MCI_GPM_COEX_PROFILE_VOICE))
  45. return false;
  46. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  47. if (!entry)
  48. return false;
  49. memcpy(entry, info, 10);
  50. INC_PROF(mci, info);
  51. list_add_tail(&entry->list, &mci->info);
  52. if (info->type == MCI_GPM_COEX_PROFILE_VOICE) {
  53. if (info->voice_type < sizeof(voice_priority))
  54. mci->voice_priority = voice_priority[info->voice_type];
  55. else
  56. mci->voice_priority = 110;
  57. }
  58. return true;
  59. }
  60. static void ath_mci_del_profile(struct ath_common *common,
  61. struct ath_mci_profile *mci,
  62. struct ath_mci_profile_info *entry)
  63. {
  64. if (!entry)
  65. return;
  66. DEC_PROF(mci, entry);
  67. list_del(&entry->list);
  68. kfree(entry);
  69. }
  70. void ath_mci_flush_profile(struct ath_mci_profile *mci)
  71. {
  72. struct ath_mci_profile_info *info, *tinfo;
  73. mci->aggr_limit = 0;
  74. mci->num_mgmt = 0;
  75. if (list_empty(&mci->info))
  76. return;
  77. list_for_each_entry_safe(info, tinfo, &mci->info, list) {
  78. list_del(&info->list);
  79. DEC_PROF(mci, info);
  80. kfree(info);
  81. }
  82. }
  83. static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
  84. {
  85. struct ath_mci_profile *mci = &btcoex->mci;
  86. u32 wlan_airtime = btcoex->btcoex_period *
  87. (100 - btcoex->duty_cycle) / 100;
  88. /*
  89. * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
  90. * When wlan_airtime is less than 4ms, aggregation limit has to be
  91. * adjusted half of wlan_airtime to ensure that the aggregation can fit
  92. * without collision with BT traffic.
  93. */
  94. if ((wlan_airtime <= 4) &&
  95. (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
  96. mci->aggr_limit = 2 * wlan_airtime;
  97. }
  98. static void ath_mci_update_scheme(struct ath_softc *sc)
  99. {
  100. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  101. struct ath_btcoex *btcoex = &sc->btcoex;
  102. struct ath_mci_profile *mci = &btcoex->mci;
  103. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  104. struct ath_mci_profile_info *info;
  105. u32 num_profile = NUM_PROF(mci);
  106. if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
  107. goto skip_tuning;
  108. mci->aggr_limit = 0;
  109. btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];
  110. btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
  111. if (NUM_PROF(mci))
  112. btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
  113. else
  114. btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
  115. ATH_BTCOEX_STOMP_LOW;
  116. if (num_profile == 1) {
  117. info = list_first_entry(&mci->info,
  118. struct ath_mci_profile_info,
  119. list);
  120. if (mci->num_sco) {
  121. if (info->T == 12)
  122. mci->aggr_limit = 8;
  123. else if (info->T == 6) {
  124. mci->aggr_limit = 6;
  125. btcoex->duty_cycle = 30;
  126. } else
  127. mci->aggr_limit = 6;
  128. ath_dbg(common, MCI,
  129. "Single SCO, aggregation limit %d 1/4 ms\n",
  130. mci->aggr_limit);
  131. } else if (mci->num_pan || mci->num_other_acl) {
  132. /*
  133. * For single PAN/FTP profile, allocate 35% for BT
  134. * to improve WLAN throughput.
  135. */
  136. btcoex->duty_cycle = AR_SREV_9565(sc->sc_ah) ? 40 : 35;
  137. btcoex->btcoex_period = 53;
  138. ath_dbg(common, MCI,
  139. "Single PAN/FTP bt period %d ms dutycycle %d\n",
  140. btcoex->duty_cycle, btcoex->btcoex_period);
  141. } else if (mci->num_hid) {
  142. btcoex->duty_cycle = 30;
  143. mci->aggr_limit = 6;
  144. ath_dbg(common, MCI,
  145. "Multiple attempt/timeout single HID "
  146. "aggregation limit 1.5 ms dutycycle 30%%\n");
  147. }
  148. } else if (num_profile == 2) {
  149. if (mci->num_hid == 2)
  150. btcoex->duty_cycle = 30;
  151. mci->aggr_limit = 6;
  152. ath_dbg(common, MCI,
  153. "Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
  154. btcoex->duty_cycle);
  155. } else if (num_profile >= 3) {
  156. mci->aggr_limit = 4;
  157. ath_dbg(common, MCI,
  158. "Three or more profiles aggregation limit 1 ms\n");
  159. }
  160. skip_tuning:
  161. if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
  162. if (IS_CHAN_HT(sc->sc_ah->curchan))
  163. ath_mci_adjust_aggr_limit(btcoex);
  164. else
  165. btcoex->btcoex_period >>= 1;
  166. }
  167. ath9k_btcoex_timer_pause(sc);
  168. ath9k_hw_btcoex_disable(sc->sc_ah);
  169. if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
  170. return;
  171. btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
  172. if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
  173. btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
  174. btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 *
  175. (100 - btcoex->duty_cycle) / 100;
  176. ath9k_hw_btcoex_enable(sc->sc_ah);
  177. ath9k_btcoex_timer_resume(sc);
  178. }
  179. static void ath_mci_wait_btcal_done(struct ath_softc *sc)
  180. {
  181. struct ath_hw *ah = sc->sc_ah;
  182. /* Stop tx & rx */
  183. ieee80211_stop_queues(sc->hw);
  184. ath_stoprecv(sc);
  185. ath_drain_all_txq(sc, false);
  186. /* Wait for cal done */
  187. ar9003_mci_start_reset(ah, ah->curchan);
  188. /* Resume tx & rx */
  189. ath_startrecv(sc);
  190. ieee80211_wake_queues(sc->hw);
  191. }
  192. static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  193. {
  194. struct ath_hw *ah = sc->sc_ah;
  195. struct ath_common *common = ath9k_hw_common(ah);
  196. struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
  197. u32 payload[4] = {0, 0, 0, 0};
  198. switch (opcode) {
  199. case MCI_GPM_BT_CAL_REQ:
  200. if (mci_hw->bt_state == MCI_BT_AWAKE) {
  201. mci_hw->bt_state = MCI_BT_CAL_START;
  202. ath_mci_wait_btcal_done(sc);
  203. }
  204. ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
  205. break;
  206. case MCI_GPM_BT_CAL_GRANT:
  207. MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
  208. ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
  209. 16, false, true);
  210. break;
  211. default:
  212. ath_dbg(common, MCI, "Unknown GPM CAL message\n");
  213. break;
  214. }
  215. }
  216. static void ath9k_mci_work(struct work_struct *work)
  217. {
  218. struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);
  219. ath_mci_update_scheme(sc);
  220. }
  221. static void ath_mci_update_stomp_txprio(u8 cur_txprio, u8 *stomp_prio)
  222. {
  223. if (cur_txprio < stomp_prio[ATH_BTCOEX_STOMP_NONE])
  224. stomp_prio[ATH_BTCOEX_STOMP_NONE] = cur_txprio;
  225. if (cur_txprio > stomp_prio[ATH_BTCOEX_STOMP_ALL])
  226. stomp_prio[ATH_BTCOEX_STOMP_ALL] = cur_txprio;
  227. if ((cur_txprio > ATH_MCI_HI_PRIO) &&
  228. (cur_txprio < stomp_prio[ATH_BTCOEX_STOMP_LOW]))
  229. stomp_prio[ATH_BTCOEX_STOMP_LOW] = cur_txprio;
  230. }
  231. static void ath_mci_set_concur_txprio(struct ath_softc *sc)
  232. {
  233. struct ath_btcoex *btcoex = &sc->btcoex;
  234. struct ath_mci_profile *mci = &btcoex->mci;
  235. u8 stomp_txprio[] = { 0, 0, 0, 0 }; /* all, low, none, low_ftp */
  236. if (mci->num_mgmt) {
  237. stomp_txprio[ATH_BTCOEX_STOMP_ALL] = ATH_MCI_INQUIRY_PRIO;
  238. if (!mci->num_pan && !mci->num_other_acl)
  239. stomp_txprio[ATH_BTCOEX_STOMP_NONE] =
  240. ATH_MCI_INQUIRY_PRIO;
  241. } else {
  242. u8 prof_prio[] = { 50, 90, 94, 52 };/* RFCOMM, A2DP, HID, PAN */
  243. stomp_txprio[ATH_BTCOEX_STOMP_LOW] =
  244. stomp_txprio[ATH_BTCOEX_STOMP_NONE] = 0xff;
  245. if (mci->num_sco)
  246. ath_mci_update_stomp_txprio(mci->voice_priority,
  247. stomp_txprio);
  248. if (mci->num_other_acl)
  249. ath_mci_update_stomp_txprio(prof_prio[0], stomp_txprio);
  250. if (mci->num_a2dp)
  251. ath_mci_update_stomp_txprio(prof_prio[1], stomp_txprio);
  252. if (mci->num_hid)
  253. ath_mci_update_stomp_txprio(prof_prio[2], stomp_txprio);
  254. if (mci->num_pan)
  255. ath_mci_update_stomp_txprio(prof_prio[3], stomp_txprio);
  256. if (stomp_txprio[ATH_BTCOEX_STOMP_NONE] == 0xff)
  257. stomp_txprio[ATH_BTCOEX_STOMP_NONE] = 0;
  258. if (stomp_txprio[ATH_BTCOEX_STOMP_LOW] == 0xff)
  259. stomp_txprio[ATH_BTCOEX_STOMP_LOW] = 0;
  260. }
  261. ath9k_hw_btcoex_set_concur_txprio(sc->sc_ah, stomp_txprio);
  262. }
  263. static u8 ath_mci_process_profile(struct ath_softc *sc,
  264. struct ath_mci_profile_info *info)
  265. {
  266. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  267. struct ath_btcoex *btcoex = &sc->btcoex;
  268. struct ath_mci_profile *mci = &btcoex->mci;
  269. struct ath_mci_profile_info *entry = NULL;
  270. entry = ath_mci_find_profile(mci, info);
  271. if (entry) {
  272. /*
  273. * Two MCI interrupts are generated while connecting to
  274. * headset and A2DP profile, but only one MCI interrupt
  275. * is generated with last added profile type while disconnecting
  276. * both profiles.
  277. * So while adding second profile type decrement
  278. * the first one.
  279. */
  280. if (entry->type != info->type) {
  281. DEC_PROF(mci, entry);
  282. INC_PROF(mci, info);
  283. }
  284. memcpy(entry, info, 10);
  285. }
  286. if (info->start) {
  287. if (!entry && !ath_mci_add_profile(common, mci, info))
  288. return 0;
  289. } else
  290. ath_mci_del_profile(common, mci, entry);
  291. ath_mci_set_concur_txprio(sc);
  292. return 1;
  293. }
  294. static u8 ath_mci_process_status(struct ath_softc *sc,
  295. struct ath_mci_profile_status *status)
  296. {
  297. struct ath_btcoex *btcoex = &sc->btcoex;
  298. struct ath_mci_profile *mci = &btcoex->mci;
  299. struct ath_mci_profile_info info;
  300. int i = 0, old_num_mgmt = mci->num_mgmt;
  301. /* Link status type are not handled */
  302. if (status->is_link)
  303. return 0;
  304. info.conn_handle = status->conn_handle;
  305. if (ath_mci_find_profile(mci, &info))
  306. return 0;
  307. if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
  308. return 0;
  309. if (status->is_critical)
  310. __set_bit(status->conn_handle, mci->status);
  311. else
  312. __clear_bit(status->conn_handle, mci->status);
  313. mci->num_mgmt = 0;
  314. do {
  315. if (test_bit(i, mci->status))
  316. mci->num_mgmt++;
  317. } while (++i < ATH_MCI_MAX_PROFILE);
  318. ath_mci_set_concur_txprio(sc);
  319. if (old_num_mgmt != mci->num_mgmt)
  320. return 1;
  321. return 0;
  322. }
  323. static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  324. {
  325. struct ath_hw *ah = sc->sc_ah;
  326. struct ath_mci_profile_info profile_info;
  327. struct ath_mci_profile_status profile_status;
  328. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  329. u8 major, minor, update_scheme = 0;
  330. u32 seq_num;
  331. if (ar9003_mci_state(ah, MCI_STATE_NEED_FLUSH_BT_INFO) &&
  332. ar9003_mci_state(ah, MCI_STATE_ENABLE)) {
  333. ath_dbg(common, MCI, "(MCI) Need to flush BT profiles\n");
  334. ath_mci_flush_profile(&sc->btcoex.mci);
  335. ar9003_mci_state(ah, MCI_STATE_SEND_STATUS_QUERY);
  336. }
  337. switch (opcode) {
  338. case MCI_GPM_COEX_VERSION_QUERY:
  339. ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
  340. break;
  341. case MCI_GPM_COEX_VERSION_RESPONSE:
  342. major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
  343. minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
  344. ar9003_mci_set_bt_version(ah, major, minor);
  345. break;
  346. case MCI_GPM_COEX_STATUS_QUERY:
  347. ar9003_mci_send_wlan_channels(ah);
  348. break;
  349. case MCI_GPM_COEX_BT_PROFILE_INFO:
  350. memcpy(&profile_info,
  351. (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
  352. if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
  353. (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
  354. ath_dbg(common, MCI,
  355. "Illegal profile type = %d, state = %d\n",
  356. profile_info.type,
  357. profile_info.start);
  358. break;
  359. }
  360. update_scheme += ath_mci_process_profile(sc, &profile_info);
  361. break;
  362. case MCI_GPM_COEX_BT_STATUS_UPDATE:
  363. profile_status.is_link = *(rx_payload +
  364. MCI_GPM_COEX_B_STATUS_TYPE);
  365. profile_status.conn_handle = *(rx_payload +
  366. MCI_GPM_COEX_B_STATUS_LINKID);
  367. profile_status.is_critical = *(rx_payload +
  368. MCI_GPM_COEX_B_STATUS_STATE);
  369. seq_num = *((u32 *)(rx_payload + 12));
  370. ath_dbg(common, MCI,
  371. "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%u\n",
  372. profile_status.is_link, profile_status.conn_handle,
  373. profile_status.is_critical, seq_num);
  374. update_scheme += ath_mci_process_status(sc, &profile_status);
  375. break;
  376. default:
  377. ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
  378. break;
  379. }
  380. if (update_scheme)
  381. ieee80211_queue_work(sc->hw, &sc->mci_work);
  382. }
  383. int ath_mci_setup(struct ath_softc *sc)
  384. {
  385. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  386. struct ath_mci_coex *mci = &sc->mci_coex;
  387. struct ath_mci_buf *buf = &mci->sched_buf;
  388. int ret;
  389. buf->bf_addr = dma_alloc_coherent(sc->dev,
  390. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  391. &buf->bf_paddr, GFP_KERNEL);
  392. if (buf->bf_addr == NULL) {
  393. ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
  394. return -ENOMEM;
  395. }
  396. memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
  397. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
  398. mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
  399. mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
  400. mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
  401. mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
  402. ret = ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
  403. mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
  404. mci->sched_buf.bf_paddr);
  405. if (ret) {
  406. ath_err(common, "Failed to initialize MCI\n");
  407. return ret;
  408. }
  409. INIT_WORK(&sc->mci_work, ath9k_mci_work);
  410. ath_dbg(common, MCI, "MCI Initialized\n");
  411. return 0;
  412. }
  413. void ath_mci_cleanup(struct ath_softc *sc)
  414. {
  415. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  416. struct ath_hw *ah = sc->sc_ah;
  417. struct ath_mci_coex *mci = &sc->mci_coex;
  418. struct ath_mci_buf *buf = &mci->sched_buf;
  419. if (buf->bf_addr)
  420. dma_free_coherent(sc->dev,
  421. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  422. buf->bf_addr, buf->bf_paddr);
  423. ar9003_mci_cleanup(ah);
  424. ath_dbg(common, MCI, "MCI De-Initialized\n");
  425. }
  426. void ath_mci_intr(struct ath_softc *sc)
  427. {
  428. struct ath_mci_coex *mci = &sc->mci_coex;
  429. struct ath_hw *ah = sc->sc_ah;
  430. struct ath_common *common = ath9k_hw_common(ah);
  431. struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
  432. u32 mci_int, mci_int_rxmsg;
  433. u32 offset, subtype, opcode;
  434. u32 *pgpm;
  435. u32 more_data = MCI_GPM_MORE;
  436. bool skip_gpm = false;
  437. ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
  438. if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) {
  439. ar9003_mci_get_next_gpm_offset(ah, true, NULL);
  440. return;
  441. }
  442. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
  443. u32 payload[4] = { 0xffffffff, 0xffffffff,
  444. 0xffffffff, 0xffffff00};
  445. /*
  446. * The following REMOTE_RESET and SYS_WAKING used to sent
  447. * only when BT wake up. Now they are always sent, as a
  448. * recovery method to reset BT MCI's RX alignment.
  449. */
  450. ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
  451. payload, 16, true, false);
  452. ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
  453. NULL, 0, true, false);
  454. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
  455. ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE);
  456. /*
  457. * always do this for recovery and 2G/5G toggling and LNA_TRANS
  458. */
  459. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
  460. }
  461. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
  462. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
  463. if ((mci_hw->bt_state == MCI_BT_SLEEP) &&
  464. (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
  465. MCI_BT_SLEEP))
  466. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
  467. }
  468. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
  469. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
  470. if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
  471. (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
  472. MCI_BT_AWAKE))
  473. mci_hw->bt_state = MCI_BT_SLEEP;
  474. }
  475. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  476. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  477. ar9003_mci_state(ah, MCI_STATE_RECOVER_RX);
  478. skip_gpm = true;
  479. }
  480. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
  481. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
  482. offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET);
  483. }
  484. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
  485. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
  486. while (more_data == MCI_GPM_MORE) {
  487. pgpm = mci->gpm_buf.bf_addr;
  488. offset = ar9003_mci_get_next_gpm_offset(ah, false,
  489. &more_data);
  490. if (offset == MCI_GPM_INVALID)
  491. break;
  492. pgpm += (offset >> 2);
  493. /*
  494. * The first dword is timer.
  495. * The real data starts from 2nd dword.
  496. */
  497. subtype = MCI_GPM_TYPE(pgpm);
  498. opcode = MCI_GPM_OPCODE(pgpm);
  499. if (skip_gpm)
  500. goto recycle;
  501. if (MCI_GPM_IS_CAL_TYPE(subtype)) {
  502. ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
  503. } else {
  504. switch (subtype) {
  505. case MCI_GPM_COEX_AGENT:
  506. ath_mci_msg(sc, opcode, (u8 *)pgpm);
  507. break;
  508. default:
  509. break;
  510. }
  511. }
  512. recycle:
  513. MCI_GPM_RECYCLE(pgpm);
  514. }
  515. }
  516. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
  517. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
  518. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
  519. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
  520. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
  521. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
  522. int value_dbm = MS(mci_hw->cont_status,
  523. AR_MCI_CONT_RSSI_POWER);
  524. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
  525. ath_dbg(common, MCI,
  526. "MCI CONT_INFO: (%s) pri = %d pwr = %d dBm\n",
  527. MS(mci_hw->cont_status, AR_MCI_CONT_TXRX) ?
  528. "tx" : "rx",
  529. MS(mci_hw->cont_status, AR_MCI_CONT_PRIORITY),
  530. value_dbm);
  531. }
  532. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
  533. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
  534. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
  535. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
  536. }
  537. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  538. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  539. mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
  540. AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
  541. ath_mci_msg(sc, MCI_GPM_COEX_NOOP, NULL);
  542. }
  543. }
  544. void ath_mci_enable(struct ath_softc *sc)
  545. {
  546. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  547. if (!common->btcoex_enabled)
  548. return;
  549. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
  550. sc->sc_ah->imask |= ATH9K_INT_MCI;
  551. }
  552. void ath9k_mci_update_wlan_channels(struct ath_softc *sc, bool allow_all)
  553. {
  554. struct ath_hw *ah = sc->sc_ah;
  555. struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
  556. struct ath9k_channel *chan = ah->curchan;
  557. u32 channelmap[] = {0x00000000, 0xffff0000, 0xffffffff, 0x7fffffff};
  558. int i;
  559. s16 chan_start, chan_end;
  560. u16 wlan_chan;
  561. if (!chan || !IS_CHAN_2GHZ(chan))
  562. return;
  563. if (allow_all)
  564. goto send_wlan_chan;
  565. wlan_chan = chan->channel - 2402;
  566. chan_start = wlan_chan - 10;
  567. chan_end = wlan_chan + 10;
  568. if (chan->chanmode == CHANNEL_G_HT40PLUS)
  569. chan_end += 20;
  570. else if (chan->chanmode == CHANNEL_G_HT40MINUS)
  571. chan_start -= 20;
  572. /* adjust side band */
  573. chan_start -= 7;
  574. chan_end += 7;
  575. if (chan_start <= 0)
  576. chan_start = 0;
  577. if (chan_end >= ATH_MCI_NUM_BT_CHANNELS)
  578. chan_end = ATH_MCI_NUM_BT_CHANNELS - 1;
  579. ath_dbg(ath9k_hw_common(ah), MCI,
  580. "WLAN current channel %d mask BT channel %d - %d\n",
  581. wlan_chan, chan_start, chan_end);
  582. for (i = chan_start; i < chan_end; i++)
  583. MCI_GPM_CLR_CHANNEL_BIT(&channelmap, i);
  584. send_wlan_chan:
  585. /* update and send wlan channels info to BT */
  586. for (i = 0; i < 4; i++)
  587. mci->wlan_channels[i] = channelmap[i];
  588. ar9003_mci_send_wlan_channels(ah);
  589. ar9003_mci_state(ah, MCI_STATE_SEND_VERSION_QUERY);
  590. }
  591. void ath9k_mci_set_txpower(struct ath_softc *sc, bool setchannel,
  592. bool concur_tx)
  593. {
  594. struct ath_hw *ah = sc->sc_ah;
  595. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  596. bool old_concur_tx = mci_hw->concur_tx;
  597. if (!(mci_hw->config & ATH_MCI_CONFIG_CONCUR_TX)) {
  598. mci_hw->concur_tx = false;
  599. return;
  600. }
  601. if (!IS_CHAN_2GHZ(ah->curchan))
  602. return;
  603. if (setchannel) {
  604. struct ath9k_hw_cal_data *caldata = &sc->caldata;
  605. if ((caldata->chanmode == CHANNEL_G_HT40PLUS) &&
  606. (ah->curchan->channel > caldata->channel) &&
  607. (ah->curchan->channel <= caldata->channel + 20))
  608. return;
  609. if ((caldata->chanmode == CHANNEL_G_HT40MINUS) &&
  610. (ah->curchan->channel < caldata->channel) &&
  611. (ah->curchan->channel >= caldata->channel - 20))
  612. return;
  613. mci_hw->concur_tx = false;
  614. } else
  615. mci_hw->concur_tx = concur_tx;
  616. if (old_concur_tx != mci_hw->concur_tx)
  617. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
  618. }
  619. void ath9k_mci_update_rssi(struct ath_softc *sc)
  620. {
  621. struct ath_hw *ah = sc->sc_ah;
  622. struct ath_btcoex *btcoex = &sc->btcoex;
  623. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  624. if (!(mci_hw->config & ATH_MCI_CONFIG_CONCUR_TX))
  625. return;
  626. if (ah->stats.avgbrssi >= 40) {
  627. if (btcoex->rssi_count < 0)
  628. btcoex->rssi_count = 0;
  629. if (++btcoex->rssi_count >= ATH_MCI_CONCUR_TX_SWITCH) {
  630. btcoex->rssi_count = 0;
  631. ath9k_mci_set_txpower(sc, false, true);
  632. }
  633. } else {
  634. if (btcoex->rssi_count > 0)
  635. btcoex->rssi_count = 0;
  636. if (--btcoex->rssi_count <= -ATH_MCI_CONCUR_TX_SWITCH) {
  637. btcoex->rssi_count = 0;
  638. ath9k_mci_set_txpower(sc, false, false);
  639. }
  640. }
  641. }