emu10k1x.c 48 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638
  1. /*
  2. * Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com>
  3. * Driver EMU10K1X chips
  4. *
  5. * Parts of this code were adapted from audigyls.c driver which is
  6. * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
  7. *
  8. * BUGS:
  9. * --
  10. *
  11. * TODO:
  12. *
  13. * Chips (SB0200 model):
  14. * - EMU10K1X-DBQ
  15. * - STAC 9708T
  16. *
  17. * This program is free software; you can redistribute it and/or modify
  18. * it under the terms of the GNU General Public License as published by
  19. * the Free Software Foundation; either version 2 of the License, or
  20. * (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  30. *
  31. */
  32. #include <sound/driver.h>
  33. #include <linux/init.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/pci.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/slab.h>
  38. #include <linux/moduleparam.h>
  39. #include <sound/core.h>
  40. #include <sound/initval.h>
  41. #include <sound/pcm.h>
  42. #include <sound/ac97_codec.h>
  43. #include <sound/info.h>
  44. #include <sound/rawmidi.h>
  45. MODULE_AUTHOR("Francisco Moraes <fmoraes@nc.rr.com>");
  46. MODULE_DESCRIPTION("EMU10K1X");
  47. MODULE_LICENSE("GPL");
  48. MODULE_SUPPORTED_DEVICE("{{Dell Creative Labs,SB Live!}");
  49. // module parameters (see "Module Parameters")
  50. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  51. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  52. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  53. module_param_array(index, int, NULL, 0444);
  54. MODULE_PARM_DESC(index, "Index value for the EMU10K1X soundcard.");
  55. module_param_array(id, charp, NULL, 0444);
  56. MODULE_PARM_DESC(id, "ID string for the EMU10K1X soundcard.");
  57. module_param_array(enable, bool, NULL, 0444);
  58. MODULE_PARM_DESC(enable, "Enable the EMU10K1X soundcard.");
  59. // some definitions were borrowed from emu10k1 driver as they seem to be the same
  60. /************************************************************************************************/
  61. /* PCI function 0 registers, address = <val> + PCIBASE0 */
  62. /************************************************************************************************/
  63. #define PTR 0x00 /* Indexed register set pointer register */
  64. /* NOTE: The CHANNELNUM and ADDRESS words can */
  65. /* be modified independently of each other. */
  66. #define DATA 0x04 /* Indexed register set data register */
  67. #define IPR 0x08 /* Global interrupt pending register */
  68. /* Clear pending interrupts by writing a 1 to */
  69. /* the relevant bits and zero to the other bits */
  70. #define IPR_MIDITRANSBUFEMPTY 0x00000001 /* MIDI UART transmit buffer empty */
  71. #define IPR_MIDIRECVBUFEMPTY 0x00000002 /* MIDI UART receive buffer empty */
  72. #define IPR_CH_0_LOOP 0x00000800 /* Channel 0 loop */
  73. #define IPR_CH_0_HALF_LOOP 0x00000100 /* Channel 0 half loop */
  74. #define IPR_CAP_0_LOOP 0x00080000 /* Channel capture loop */
  75. #define IPR_CAP_0_HALF_LOOP 0x00010000 /* Channel capture half loop */
  76. #define INTE 0x0c /* Interrupt enable register */
  77. #define INTE_MIDITXENABLE 0x00000001 /* Enable MIDI transmit-buffer-empty interrupts */
  78. #define INTE_MIDIRXENABLE 0x00000002 /* Enable MIDI receive-buffer-empty interrupts */
  79. #define INTE_CH_0_LOOP 0x00000800 /* Channel 0 loop */
  80. #define INTE_CH_0_HALF_LOOP 0x00000100 /* Channel 0 half loop */
  81. #define INTE_CAP_0_LOOP 0x00080000 /* Channel capture loop */
  82. #define INTE_CAP_0_HALF_LOOP 0x00010000 /* Channel capture half loop */
  83. #define HCFG 0x14 /* Hardware config register */
  84. #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
  85. /* NOTE: This should generally never be used. */
  86. #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
  87. /* Should be set to 1 when the EMU10K1 is */
  88. /* completely initialized. */
  89. #define GPIO 0x18 /* Defaults: 00001080-Analog, 00001000-SPDIF. */
  90. #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
  91. #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
  92. /********************************************************************************************************/
  93. /* Emu10k1x pointer-offset register set, accessed through the PTR and DATA registers */
  94. /********************************************************************************************************/
  95. #define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */
  96. /* One list entry: 4 bytes for DMA address,
  97. * 4 bytes for period_size << 16.
  98. * One list entry is 8 bytes long.
  99. * One list entry for each period in the buffer.
  100. */
  101. #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
  102. #define PLAYBACK_LIST_PTR 0x02 /* Pointer to the current period being played */
  103. #define PLAYBACK_DMA_ADDR 0x04 /* Playback DMA addresss */
  104. #define PLAYBACK_PERIOD_SIZE 0x05 /* Playback period size */
  105. #define PLAYBACK_POINTER 0x06 /* Playback period pointer. Sample currently in DAC */
  106. #define PLAYBACK_UNKNOWN1 0x07
  107. #define PLAYBACK_UNKNOWN2 0x08
  108. /* Only one capture channel supported */
  109. #define CAPTURE_DMA_ADDR 0x10 /* Capture DMA address */
  110. #define CAPTURE_BUFFER_SIZE 0x11 /* Capture buffer size */
  111. #define CAPTURE_POINTER 0x12 /* Capture buffer pointer. Sample currently in ADC */
  112. #define CAPTURE_UNKNOWN 0x13
  113. /* From 0x20 - 0x3f, last samples played on each channel */
  114. #define TRIGGER_CHANNEL 0x40 /* Trigger channel playback */
  115. #define TRIGGER_CHANNEL_0 0x00000001 /* Trigger channel 0 */
  116. #define TRIGGER_CHANNEL_1 0x00000002 /* Trigger channel 1 */
  117. #define TRIGGER_CHANNEL_2 0x00000004 /* Trigger channel 2 */
  118. #define TRIGGER_CAPTURE 0x00000100 /* Trigger capture channel */
  119. #define ROUTING 0x41 /* Setup sound routing ? */
  120. #define ROUTING_FRONT_LEFT 0x00000001
  121. #define ROUTING_FRONT_RIGHT 0x00000002
  122. #define ROUTING_REAR_LEFT 0x00000004
  123. #define ROUTING_REAR_RIGHT 0x00000008
  124. #define ROUTING_CENTER_LFE 0x00010000
  125. #define SPCS0 0x42 /* SPDIF output Channel Status 0 register */
  126. #define SPCS1 0x43 /* SPDIF output Channel Status 1 register */
  127. #define SPCS2 0x44 /* SPDIF output Channel Status 2 register */
  128. #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
  129. #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
  130. #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
  131. #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
  132. #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
  133. #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
  134. #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
  135. #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
  136. #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
  137. #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
  138. #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
  139. #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
  140. #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
  141. #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
  142. #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
  143. #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
  144. #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
  145. #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
  146. #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
  147. #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
  148. #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
  149. #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
  150. #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
  151. #define SPDIF_SELECT 0x45 /* Enables SPDIF or Analogue outputs 0-Analogue, 0x700-SPDIF */
  152. /* This is the MPU port on the card */
  153. #define MUDATA 0x47
  154. #define MUCMD 0x48
  155. #define MUSTAT MUCMD
  156. /* From 0x50 - 0x5f, last samples captured */
  157. /**
  158. * The hardware has 3 channels for playback and 1 for capture.
  159. * - channel 0 is the front channel
  160. * - channel 1 is the rear channel
  161. * - channel 2 is the center/lfe chanel
  162. * Volume is controlled by the AC97 for the front and rear channels by
  163. * the PCM Playback Volume, Sigmatel Surround Playback Volume and
  164. * Surround Playback Volume. The Sigmatel 4-Speaker Stereo switch affects
  165. * the front/rear channel mixing in the REAR OUT jack. When using the
  166. * 4-Speaker Stereo, both front and rear channels will be mixed in the
  167. * REAR OUT.
  168. * The center/lfe channel has no volume control and cannot be muted during
  169. * playback.
  170. */
  171. struct emu10k1x_voice {
  172. struct emu10k1x *emu;
  173. int number;
  174. int use;
  175. struct emu10k1x_pcm *epcm;
  176. };
  177. struct emu10k1x_pcm {
  178. struct emu10k1x *emu;
  179. struct snd_pcm_substream *substream;
  180. struct emu10k1x_voice *voice;
  181. unsigned short running;
  182. };
  183. struct emu10k1x_midi {
  184. struct emu10k1x *emu;
  185. struct snd_rawmidi *rmidi;
  186. struct snd_rawmidi_substream *substream_input;
  187. struct snd_rawmidi_substream *substream_output;
  188. unsigned int midi_mode;
  189. spinlock_t input_lock;
  190. spinlock_t output_lock;
  191. spinlock_t open_lock;
  192. int tx_enable, rx_enable;
  193. int port;
  194. int ipr_tx, ipr_rx;
  195. void (*interrupt)(struct emu10k1x *emu, unsigned int status);
  196. };
  197. // definition of the chip-specific record
  198. struct emu10k1x {
  199. struct snd_card *card;
  200. struct pci_dev *pci;
  201. unsigned long port;
  202. struct resource *res_port;
  203. int irq;
  204. unsigned int revision; /* chip revision */
  205. unsigned int serial; /* serial number */
  206. unsigned short model; /* subsystem id */
  207. spinlock_t emu_lock;
  208. spinlock_t voice_lock;
  209. struct snd_ac97 *ac97;
  210. struct snd_pcm *pcm;
  211. struct emu10k1x_voice voices[3];
  212. struct emu10k1x_voice capture_voice;
  213. u32 spdif_bits[3]; // SPDIF out setup
  214. struct snd_dma_buffer dma_buffer;
  215. struct emu10k1x_midi midi;
  216. };
  217. /* hardware definition */
  218. static struct snd_pcm_hardware snd_emu10k1x_playback_hw = {
  219. .info = (SNDRV_PCM_INFO_MMAP |
  220. SNDRV_PCM_INFO_INTERLEAVED |
  221. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  222. SNDRV_PCM_INFO_MMAP_VALID),
  223. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  224. .rates = SNDRV_PCM_RATE_48000,
  225. .rate_min = 48000,
  226. .rate_max = 48000,
  227. .channels_min = 2,
  228. .channels_max = 2,
  229. .buffer_bytes_max = (32*1024),
  230. .period_bytes_min = 64,
  231. .period_bytes_max = (16*1024),
  232. .periods_min = 2,
  233. .periods_max = 8,
  234. .fifo_size = 0,
  235. };
  236. static struct snd_pcm_hardware snd_emu10k1x_capture_hw = {
  237. .info = (SNDRV_PCM_INFO_MMAP |
  238. SNDRV_PCM_INFO_INTERLEAVED |
  239. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  240. SNDRV_PCM_INFO_MMAP_VALID),
  241. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  242. .rates = SNDRV_PCM_RATE_48000,
  243. .rate_min = 48000,
  244. .rate_max = 48000,
  245. .channels_min = 2,
  246. .channels_max = 2,
  247. .buffer_bytes_max = (32*1024),
  248. .period_bytes_min = 64,
  249. .period_bytes_max = (16*1024),
  250. .periods_min = 2,
  251. .periods_max = 2,
  252. .fifo_size = 0,
  253. };
  254. static unsigned int snd_emu10k1x_ptr_read(struct emu10k1x * emu,
  255. unsigned int reg,
  256. unsigned int chn)
  257. {
  258. unsigned long flags;
  259. unsigned int regptr, val;
  260. regptr = (reg << 16) | chn;
  261. spin_lock_irqsave(&emu->emu_lock, flags);
  262. outl(regptr, emu->port + PTR);
  263. val = inl(emu->port + DATA);
  264. spin_unlock_irqrestore(&emu->emu_lock, flags);
  265. return val;
  266. }
  267. static void snd_emu10k1x_ptr_write(struct emu10k1x *emu,
  268. unsigned int reg,
  269. unsigned int chn,
  270. unsigned int data)
  271. {
  272. unsigned int regptr;
  273. unsigned long flags;
  274. regptr = (reg << 16) | chn;
  275. spin_lock_irqsave(&emu->emu_lock, flags);
  276. outl(regptr, emu->port + PTR);
  277. outl(data, emu->port + DATA);
  278. spin_unlock_irqrestore(&emu->emu_lock, flags);
  279. }
  280. static void snd_emu10k1x_intr_enable(struct emu10k1x *emu, unsigned int intrenb)
  281. {
  282. unsigned long flags;
  283. unsigned int enable;
  284. spin_lock_irqsave(&emu->emu_lock, flags);
  285. enable = inl(emu->port + INTE) | intrenb;
  286. outl(enable, emu->port + INTE);
  287. spin_unlock_irqrestore(&emu->emu_lock, flags);
  288. }
  289. static void snd_emu10k1x_intr_disable(struct emu10k1x *emu, unsigned int intrenb)
  290. {
  291. unsigned long flags;
  292. unsigned int enable;
  293. spin_lock_irqsave(&emu->emu_lock, flags);
  294. enable = inl(emu->port + INTE) & ~intrenb;
  295. outl(enable, emu->port + INTE);
  296. spin_unlock_irqrestore(&emu->emu_lock, flags);
  297. }
  298. static void snd_emu10k1x_gpio_write(struct emu10k1x *emu, unsigned int value)
  299. {
  300. unsigned long flags;
  301. spin_lock_irqsave(&emu->emu_lock, flags);
  302. outl(value, emu->port + GPIO);
  303. spin_unlock_irqrestore(&emu->emu_lock, flags);
  304. }
  305. static void snd_emu10k1x_pcm_free_substream(struct snd_pcm_runtime *runtime)
  306. {
  307. kfree(runtime->private_data);
  308. }
  309. static void snd_emu10k1x_pcm_interrupt(struct emu10k1x *emu, struct emu10k1x_voice *voice)
  310. {
  311. struct emu10k1x_pcm *epcm;
  312. if ((epcm = voice->epcm) == NULL)
  313. return;
  314. if (epcm->substream == NULL)
  315. return;
  316. #if 0
  317. snd_printk(KERN_INFO "IRQ: position = 0x%x, period = 0x%x, size = 0x%x\n",
  318. epcm->substream->ops->pointer(epcm->substream),
  319. snd_pcm_lib_period_bytes(epcm->substream),
  320. snd_pcm_lib_buffer_bytes(epcm->substream));
  321. #endif
  322. snd_pcm_period_elapsed(epcm->substream);
  323. }
  324. /* open callback */
  325. static int snd_emu10k1x_playback_open(struct snd_pcm_substream *substream)
  326. {
  327. struct emu10k1x *chip = snd_pcm_substream_chip(substream);
  328. struct emu10k1x_pcm *epcm;
  329. struct snd_pcm_runtime *runtime = substream->runtime;
  330. int err;
  331. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) {
  332. return err;
  333. }
  334. if ((err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64)) < 0)
  335. return err;
  336. epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);
  337. if (epcm == NULL)
  338. return -ENOMEM;
  339. epcm->emu = chip;
  340. epcm->substream = substream;
  341. runtime->private_data = epcm;
  342. runtime->private_free = snd_emu10k1x_pcm_free_substream;
  343. runtime->hw = snd_emu10k1x_playback_hw;
  344. return 0;
  345. }
  346. /* close callback */
  347. static int snd_emu10k1x_playback_close(struct snd_pcm_substream *substream)
  348. {
  349. return 0;
  350. }
  351. /* hw_params callback */
  352. static int snd_emu10k1x_pcm_hw_params(struct snd_pcm_substream *substream,
  353. struct snd_pcm_hw_params *hw_params)
  354. {
  355. struct snd_pcm_runtime *runtime = substream->runtime;
  356. struct emu10k1x_pcm *epcm = runtime->private_data;
  357. if (! epcm->voice) {
  358. epcm->voice = &epcm->emu->voices[substream->pcm->device];
  359. epcm->voice->use = 1;
  360. epcm->voice->epcm = epcm;
  361. }
  362. return snd_pcm_lib_malloc_pages(substream,
  363. params_buffer_bytes(hw_params));
  364. }
  365. /* hw_free callback */
  366. static int snd_emu10k1x_pcm_hw_free(struct snd_pcm_substream *substream)
  367. {
  368. struct snd_pcm_runtime *runtime = substream->runtime;
  369. struct emu10k1x_pcm *epcm;
  370. if (runtime->private_data == NULL)
  371. return 0;
  372. epcm = runtime->private_data;
  373. if (epcm->voice) {
  374. epcm->voice->use = 0;
  375. epcm->voice->epcm = NULL;
  376. epcm->voice = NULL;
  377. }
  378. return snd_pcm_lib_free_pages(substream);
  379. }
  380. /* prepare callback */
  381. static int snd_emu10k1x_pcm_prepare(struct snd_pcm_substream *substream)
  382. {
  383. struct emu10k1x *emu = snd_pcm_substream_chip(substream);
  384. struct snd_pcm_runtime *runtime = substream->runtime;
  385. struct emu10k1x_pcm *epcm = runtime->private_data;
  386. int voice = epcm->voice->number;
  387. u32 *table_base = (u32 *)(emu->dma_buffer.area+1024*voice);
  388. u32 period_size_bytes = frames_to_bytes(runtime, runtime->period_size);
  389. int i;
  390. for(i=0; i < runtime->periods; i++) {
  391. *table_base++=runtime->dma_addr+(i*period_size_bytes);
  392. *table_base++=period_size_bytes<<16;
  393. }
  394. snd_emu10k1x_ptr_write(emu, PLAYBACK_LIST_ADDR, voice, emu->dma_buffer.addr+1024*voice);
  395. snd_emu10k1x_ptr_write(emu, PLAYBACK_LIST_SIZE, voice, (runtime->periods - 1) << 19);
  396. snd_emu10k1x_ptr_write(emu, PLAYBACK_LIST_PTR, voice, 0);
  397. snd_emu10k1x_ptr_write(emu, PLAYBACK_POINTER, voice, 0);
  398. snd_emu10k1x_ptr_write(emu, PLAYBACK_UNKNOWN1, voice, 0);
  399. snd_emu10k1x_ptr_write(emu, PLAYBACK_UNKNOWN2, voice, 0);
  400. snd_emu10k1x_ptr_write(emu, PLAYBACK_DMA_ADDR, voice, runtime->dma_addr);
  401. snd_emu10k1x_ptr_write(emu, PLAYBACK_PERIOD_SIZE, voice, frames_to_bytes(runtime, runtime->period_size)<<16);
  402. return 0;
  403. }
  404. /* trigger callback */
  405. static int snd_emu10k1x_pcm_trigger(struct snd_pcm_substream *substream,
  406. int cmd)
  407. {
  408. struct emu10k1x *emu = snd_pcm_substream_chip(substream);
  409. struct snd_pcm_runtime *runtime = substream->runtime;
  410. struct emu10k1x_pcm *epcm = runtime->private_data;
  411. int channel = epcm->voice->number;
  412. int result = 0;
  413. // snd_printk(KERN_INFO "trigger - emu10k1x = 0x%x, cmd = %i, pointer = %d\n", (int)emu, cmd, (int)substream->ops->pointer(substream));
  414. switch (cmd) {
  415. case SNDRV_PCM_TRIGGER_START:
  416. if(runtime->periods == 2)
  417. snd_emu10k1x_intr_enable(emu, (INTE_CH_0_LOOP | INTE_CH_0_HALF_LOOP) << channel);
  418. else
  419. snd_emu10k1x_intr_enable(emu, INTE_CH_0_LOOP << channel);
  420. epcm->running = 1;
  421. snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0)|(TRIGGER_CHANNEL_0<<channel));
  422. break;
  423. case SNDRV_PCM_TRIGGER_STOP:
  424. epcm->running = 0;
  425. snd_emu10k1x_intr_disable(emu, (INTE_CH_0_LOOP | INTE_CH_0_HALF_LOOP) << channel);
  426. snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0) & ~(TRIGGER_CHANNEL_0<<channel));
  427. break;
  428. default:
  429. result = -EINVAL;
  430. break;
  431. }
  432. return result;
  433. }
  434. /* pointer callback */
  435. static snd_pcm_uframes_t
  436. snd_emu10k1x_pcm_pointer(struct snd_pcm_substream *substream)
  437. {
  438. struct emu10k1x *emu = snd_pcm_substream_chip(substream);
  439. struct snd_pcm_runtime *runtime = substream->runtime;
  440. struct emu10k1x_pcm *epcm = runtime->private_data;
  441. int channel = epcm->voice->number;
  442. snd_pcm_uframes_t ptr = 0, ptr1 = 0, ptr2= 0,ptr3 = 0,ptr4 = 0;
  443. if (!epcm->running)
  444. return 0;
  445. ptr3 = snd_emu10k1x_ptr_read(emu, PLAYBACK_LIST_PTR, channel);
  446. ptr1 = snd_emu10k1x_ptr_read(emu, PLAYBACK_POINTER, channel);
  447. ptr4 = snd_emu10k1x_ptr_read(emu, PLAYBACK_LIST_PTR, channel);
  448. if(ptr4 == 0 && ptr1 == frames_to_bytes(runtime, runtime->buffer_size))
  449. return 0;
  450. if (ptr3 != ptr4)
  451. ptr1 = snd_emu10k1x_ptr_read(emu, PLAYBACK_POINTER, channel);
  452. ptr2 = bytes_to_frames(runtime, ptr1);
  453. ptr2 += (ptr4 >> 3) * runtime->period_size;
  454. ptr = ptr2;
  455. if (ptr >= runtime->buffer_size)
  456. ptr -= runtime->buffer_size;
  457. return ptr;
  458. }
  459. /* operators */
  460. static struct snd_pcm_ops snd_emu10k1x_playback_ops = {
  461. .open = snd_emu10k1x_playback_open,
  462. .close = snd_emu10k1x_playback_close,
  463. .ioctl = snd_pcm_lib_ioctl,
  464. .hw_params = snd_emu10k1x_pcm_hw_params,
  465. .hw_free = snd_emu10k1x_pcm_hw_free,
  466. .prepare = snd_emu10k1x_pcm_prepare,
  467. .trigger = snd_emu10k1x_pcm_trigger,
  468. .pointer = snd_emu10k1x_pcm_pointer,
  469. };
  470. /* open_capture callback */
  471. static int snd_emu10k1x_pcm_open_capture(struct snd_pcm_substream *substream)
  472. {
  473. struct emu10k1x *chip = snd_pcm_substream_chip(substream);
  474. struct emu10k1x_pcm *epcm;
  475. struct snd_pcm_runtime *runtime = substream->runtime;
  476. int err;
  477. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  478. return err;
  479. if ((err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64)) < 0)
  480. return err;
  481. epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);
  482. if (epcm == NULL)
  483. return -ENOMEM;
  484. epcm->emu = chip;
  485. epcm->substream = substream;
  486. runtime->private_data = epcm;
  487. runtime->private_free = snd_emu10k1x_pcm_free_substream;
  488. runtime->hw = snd_emu10k1x_capture_hw;
  489. return 0;
  490. }
  491. /* close callback */
  492. static int snd_emu10k1x_pcm_close_capture(struct snd_pcm_substream *substream)
  493. {
  494. return 0;
  495. }
  496. /* hw_params callback */
  497. static int snd_emu10k1x_pcm_hw_params_capture(struct snd_pcm_substream *substream,
  498. struct snd_pcm_hw_params *hw_params)
  499. {
  500. struct snd_pcm_runtime *runtime = substream->runtime;
  501. struct emu10k1x_pcm *epcm = runtime->private_data;
  502. if (! epcm->voice) {
  503. if (epcm->emu->capture_voice.use)
  504. return -EBUSY;
  505. epcm->voice = &epcm->emu->capture_voice;
  506. epcm->voice->epcm = epcm;
  507. epcm->voice->use = 1;
  508. }
  509. return snd_pcm_lib_malloc_pages(substream,
  510. params_buffer_bytes(hw_params));
  511. }
  512. /* hw_free callback */
  513. static int snd_emu10k1x_pcm_hw_free_capture(struct snd_pcm_substream *substream)
  514. {
  515. struct snd_pcm_runtime *runtime = substream->runtime;
  516. struct emu10k1x_pcm *epcm;
  517. if (runtime->private_data == NULL)
  518. return 0;
  519. epcm = runtime->private_data;
  520. if (epcm->voice) {
  521. epcm->voice->use = 0;
  522. epcm->voice->epcm = NULL;
  523. epcm->voice = NULL;
  524. }
  525. return snd_pcm_lib_free_pages(substream);
  526. }
  527. /* prepare capture callback */
  528. static int snd_emu10k1x_pcm_prepare_capture(struct snd_pcm_substream *substream)
  529. {
  530. struct emu10k1x *emu = snd_pcm_substream_chip(substream);
  531. struct snd_pcm_runtime *runtime = substream->runtime;
  532. snd_emu10k1x_ptr_write(emu, CAPTURE_DMA_ADDR, 0, runtime->dma_addr);
  533. snd_emu10k1x_ptr_write(emu, CAPTURE_BUFFER_SIZE, 0, frames_to_bytes(runtime, runtime->buffer_size)<<16); // buffer size in bytes
  534. snd_emu10k1x_ptr_write(emu, CAPTURE_POINTER, 0, 0);
  535. snd_emu10k1x_ptr_write(emu, CAPTURE_UNKNOWN, 0, 0);
  536. return 0;
  537. }
  538. /* trigger_capture callback */
  539. static int snd_emu10k1x_pcm_trigger_capture(struct snd_pcm_substream *substream,
  540. int cmd)
  541. {
  542. struct emu10k1x *emu = snd_pcm_substream_chip(substream);
  543. struct snd_pcm_runtime *runtime = substream->runtime;
  544. struct emu10k1x_pcm *epcm = runtime->private_data;
  545. int result = 0;
  546. switch (cmd) {
  547. case SNDRV_PCM_TRIGGER_START:
  548. snd_emu10k1x_intr_enable(emu, INTE_CAP_0_LOOP |
  549. INTE_CAP_0_HALF_LOOP);
  550. snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0)|TRIGGER_CAPTURE);
  551. epcm->running = 1;
  552. break;
  553. case SNDRV_PCM_TRIGGER_STOP:
  554. epcm->running = 0;
  555. snd_emu10k1x_intr_disable(emu, INTE_CAP_0_LOOP |
  556. INTE_CAP_0_HALF_LOOP);
  557. snd_emu10k1x_ptr_write(emu, TRIGGER_CHANNEL, 0, snd_emu10k1x_ptr_read(emu, TRIGGER_CHANNEL, 0) & ~(TRIGGER_CAPTURE));
  558. break;
  559. default:
  560. result = -EINVAL;
  561. break;
  562. }
  563. return result;
  564. }
  565. /* pointer_capture callback */
  566. static snd_pcm_uframes_t
  567. snd_emu10k1x_pcm_pointer_capture(struct snd_pcm_substream *substream)
  568. {
  569. struct emu10k1x *emu = snd_pcm_substream_chip(substream);
  570. struct snd_pcm_runtime *runtime = substream->runtime;
  571. struct emu10k1x_pcm *epcm = runtime->private_data;
  572. snd_pcm_uframes_t ptr;
  573. if (!epcm->running)
  574. return 0;
  575. ptr = bytes_to_frames(runtime, snd_emu10k1x_ptr_read(emu, CAPTURE_POINTER, 0));
  576. if (ptr >= runtime->buffer_size)
  577. ptr -= runtime->buffer_size;
  578. return ptr;
  579. }
  580. static struct snd_pcm_ops snd_emu10k1x_capture_ops = {
  581. .open = snd_emu10k1x_pcm_open_capture,
  582. .close = snd_emu10k1x_pcm_close_capture,
  583. .ioctl = snd_pcm_lib_ioctl,
  584. .hw_params = snd_emu10k1x_pcm_hw_params_capture,
  585. .hw_free = snd_emu10k1x_pcm_hw_free_capture,
  586. .prepare = snd_emu10k1x_pcm_prepare_capture,
  587. .trigger = snd_emu10k1x_pcm_trigger_capture,
  588. .pointer = snd_emu10k1x_pcm_pointer_capture,
  589. };
  590. static unsigned short snd_emu10k1x_ac97_read(struct snd_ac97 *ac97,
  591. unsigned short reg)
  592. {
  593. struct emu10k1x *emu = ac97->private_data;
  594. unsigned long flags;
  595. unsigned short val;
  596. spin_lock_irqsave(&emu->emu_lock, flags);
  597. outb(reg, emu->port + AC97ADDRESS);
  598. val = inw(emu->port + AC97DATA);
  599. spin_unlock_irqrestore(&emu->emu_lock, flags);
  600. return val;
  601. }
  602. static void snd_emu10k1x_ac97_write(struct snd_ac97 *ac97,
  603. unsigned short reg, unsigned short val)
  604. {
  605. struct emu10k1x *emu = ac97->private_data;
  606. unsigned long flags;
  607. spin_lock_irqsave(&emu->emu_lock, flags);
  608. outb(reg, emu->port + AC97ADDRESS);
  609. outw(val, emu->port + AC97DATA);
  610. spin_unlock_irqrestore(&emu->emu_lock, flags);
  611. }
  612. static int snd_emu10k1x_ac97(struct emu10k1x *chip)
  613. {
  614. struct snd_ac97_bus *pbus;
  615. struct snd_ac97_template ac97;
  616. int err;
  617. static struct snd_ac97_bus_ops ops = {
  618. .write = snd_emu10k1x_ac97_write,
  619. .read = snd_emu10k1x_ac97_read,
  620. };
  621. if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
  622. return err;
  623. pbus->no_vra = 1; /* we don't need VRA */
  624. memset(&ac97, 0, sizeof(ac97));
  625. ac97.private_data = chip;
  626. ac97.scaps = AC97_SCAP_NO_SPDIF;
  627. return snd_ac97_mixer(pbus, &ac97, &chip->ac97);
  628. }
  629. static int snd_emu10k1x_free(struct emu10k1x *chip)
  630. {
  631. snd_emu10k1x_ptr_write(chip, TRIGGER_CHANNEL, 0, 0);
  632. // disable interrupts
  633. outl(0, chip->port + INTE);
  634. // disable audio
  635. outl(HCFG_LOCKSOUNDCACHE, chip->port + HCFG);
  636. // release the i/o port
  637. release_and_free_resource(chip->res_port);
  638. // release the irq
  639. if (chip->irq >= 0)
  640. free_irq(chip->irq, (void *)chip);
  641. // release the DMA
  642. if (chip->dma_buffer.area) {
  643. snd_dma_free_pages(&chip->dma_buffer);
  644. }
  645. pci_disable_device(chip->pci);
  646. // release the data
  647. kfree(chip);
  648. return 0;
  649. }
  650. static int snd_emu10k1x_dev_free(struct snd_device *device)
  651. {
  652. struct emu10k1x *chip = device->device_data;
  653. return snd_emu10k1x_free(chip);
  654. }
  655. static irqreturn_t snd_emu10k1x_interrupt(int irq, void *dev_id)
  656. {
  657. unsigned int status;
  658. struct emu10k1x *chip = dev_id;
  659. struct emu10k1x_voice *pvoice = chip->voices;
  660. int i;
  661. int mask;
  662. status = inl(chip->port + IPR);
  663. if (! status)
  664. return IRQ_NONE;
  665. // capture interrupt
  666. if (status & (IPR_CAP_0_LOOP | IPR_CAP_0_HALF_LOOP)) {
  667. struct emu10k1x_voice *pvoice = &chip->capture_voice;
  668. if (pvoice->use)
  669. snd_emu10k1x_pcm_interrupt(chip, pvoice);
  670. else
  671. snd_emu10k1x_intr_disable(chip,
  672. INTE_CAP_0_LOOP |
  673. INTE_CAP_0_HALF_LOOP);
  674. }
  675. mask = IPR_CH_0_LOOP|IPR_CH_0_HALF_LOOP;
  676. for (i = 0; i < 3; i++) {
  677. if (status & mask) {
  678. if (pvoice->use)
  679. snd_emu10k1x_pcm_interrupt(chip, pvoice);
  680. else
  681. snd_emu10k1x_intr_disable(chip, mask);
  682. }
  683. pvoice++;
  684. mask <<= 1;
  685. }
  686. if (status & (IPR_MIDITRANSBUFEMPTY|IPR_MIDIRECVBUFEMPTY)) {
  687. if (chip->midi.interrupt)
  688. chip->midi.interrupt(chip, status);
  689. else
  690. snd_emu10k1x_intr_disable(chip, INTE_MIDITXENABLE|INTE_MIDIRXENABLE);
  691. }
  692. // acknowledge the interrupt if necessary
  693. outl(status, chip->port + IPR);
  694. // snd_printk(KERN_INFO "interrupt %08x\n", status);
  695. return IRQ_HANDLED;
  696. }
  697. static int __devinit snd_emu10k1x_pcm(struct emu10k1x *emu, int device, struct snd_pcm **rpcm)
  698. {
  699. struct snd_pcm *pcm;
  700. int err;
  701. int capture = 0;
  702. if (rpcm)
  703. *rpcm = NULL;
  704. if (device == 0)
  705. capture = 1;
  706. if ((err = snd_pcm_new(emu->card, "emu10k1x", device, 1, capture, &pcm)) < 0)
  707. return err;
  708. pcm->private_data = emu;
  709. switch(device) {
  710. case 0:
  711. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_emu10k1x_playback_ops);
  712. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_emu10k1x_capture_ops);
  713. break;
  714. case 1:
  715. case 2:
  716. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_emu10k1x_playback_ops);
  717. break;
  718. }
  719. pcm->info_flags = 0;
  720. pcm->dev_subclass = SNDRV_PCM_SUBCLASS_GENERIC_MIX;
  721. switch(device) {
  722. case 0:
  723. strcpy(pcm->name, "EMU10K1X Front");
  724. break;
  725. case 1:
  726. strcpy(pcm->name, "EMU10K1X Rear");
  727. break;
  728. case 2:
  729. strcpy(pcm->name, "EMU10K1X Center/LFE");
  730. break;
  731. }
  732. emu->pcm = pcm;
  733. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  734. snd_dma_pci_data(emu->pci),
  735. 32*1024, 32*1024);
  736. if (rpcm)
  737. *rpcm = pcm;
  738. return 0;
  739. }
  740. static int __devinit snd_emu10k1x_create(struct snd_card *card,
  741. struct pci_dev *pci,
  742. struct emu10k1x **rchip)
  743. {
  744. struct emu10k1x *chip;
  745. int err;
  746. int ch;
  747. static struct snd_device_ops ops = {
  748. .dev_free = snd_emu10k1x_dev_free,
  749. };
  750. *rchip = NULL;
  751. if ((err = pci_enable_device(pci)) < 0)
  752. return err;
  753. if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
  754. pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
  755. snd_printk(KERN_ERR "error to set 28bit mask DMA\n");
  756. pci_disable_device(pci);
  757. return -ENXIO;
  758. }
  759. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  760. if (chip == NULL) {
  761. pci_disable_device(pci);
  762. return -ENOMEM;
  763. }
  764. chip->card = card;
  765. chip->pci = pci;
  766. chip->irq = -1;
  767. spin_lock_init(&chip->emu_lock);
  768. spin_lock_init(&chip->voice_lock);
  769. chip->port = pci_resource_start(pci, 0);
  770. if ((chip->res_port = request_region(chip->port, 8,
  771. "EMU10K1X")) == NULL) {
  772. snd_printk(KERN_ERR "emu10k1x: cannot allocate the port 0x%lx\n", chip->port);
  773. snd_emu10k1x_free(chip);
  774. return -EBUSY;
  775. }
  776. if (request_irq(pci->irq, snd_emu10k1x_interrupt,
  777. IRQF_DISABLED|IRQF_SHARED, "EMU10K1X",
  778. (void *)chip)) {
  779. snd_printk(KERN_ERR "emu10k1x: cannot grab irq %d\n", pci->irq);
  780. snd_emu10k1x_free(chip);
  781. return -EBUSY;
  782. }
  783. chip->irq = pci->irq;
  784. if(snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
  785. 4 * 1024, &chip->dma_buffer) < 0) {
  786. snd_emu10k1x_free(chip);
  787. return -ENOMEM;
  788. }
  789. pci_set_master(pci);
  790. /* read revision & serial */
  791. pci_read_config_byte(pci, PCI_REVISION_ID, (char *)&chip->revision);
  792. pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &chip->serial);
  793. pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &chip->model);
  794. snd_printk(KERN_INFO "Model %04x Rev %08x Serial %08x\n", chip->model,
  795. chip->revision, chip->serial);
  796. outl(0, chip->port + INTE);
  797. for(ch = 0; ch < 3; ch++) {
  798. chip->voices[ch].emu = chip;
  799. chip->voices[ch].number = ch;
  800. }
  801. /*
  802. * Init to 0x02109204 :
  803. * Clock accuracy = 0 (1000ppm)
  804. * Sample Rate = 2 (48kHz)
  805. * Audio Channel = 1 (Left of 2)
  806. * Source Number = 0 (Unspecified)
  807. * Generation Status = 1 (Original for Cat Code 12)
  808. * Cat Code = 12 (Digital Signal Mixer)
  809. * Mode = 0 (Mode 0)
  810. * Emphasis = 0 (None)
  811. * CP = 1 (Copyright unasserted)
  812. * AN = 0 (Audio data)
  813. * P = 0 (Consumer)
  814. */
  815. snd_emu10k1x_ptr_write(chip, SPCS0, 0,
  816. chip->spdif_bits[0] =
  817. SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
  818. SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
  819. SPCS_GENERATIONSTATUS | 0x00001200 |
  820. 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
  821. snd_emu10k1x_ptr_write(chip, SPCS1, 0,
  822. chip->spdif_bits[1] =
  823. SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
  824. SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
  825. SPCS_GENERATIONSTATUS | 0x00001200 |
  826. 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
  827. snd_emu10k1x_ptr_write(chip, SPCS2, 0,
  828. chip->spdif_bits[2] =
  829. SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
  830. SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
  831. SPCS_GENERATIONSTATUS | 0x00001200 |
  832. 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
  833. snd_emu10k1x_ptr_write(chip, SPDIF_SELECT, 0, 0x700); // disable SPDIF
  834. snd_emu10k1x_ptr_write(chip, ROUTING, 0, 0x1003F); // routing
  835. snd_emu10k1x_gpio_write(chip, 0x1080); // analog mode
  836. outl(HCFG_LOCKSOUNDCACHE|HCFG_AUDIOENABLE, chip->port+HCFG);
  837. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  838. chip, &ops)) < 0) {
  839. snd_emu10k1x_free(chip);
  840. return err;
  841. }
  842. *rchip = chip;
  843. return 0;
  844. }
  845. static void snd_emu10k1x_proc_reg_read(struct snd_info_entry *entry,
  846. struct snd_info_buffer *buffer)
  847. {
  848. struct emu10k1x *emu = entry->private_data;
  849. unsigned long value,value1,value2;
  850. unsigned long flags;
  851. int i;
  852. snd_iprintf(buffer, "Registers:\n\n");
  853. for(i = 0; i < 0x20; i+=4) {
  854. spin_lock_irqsave(&emu->emu_lock, flags);
  855. value = inl(emu->port + i);
  856. spin_unlock_irqrestore(&emu->emu_lock, flags);
  857. snd_iprintf(buffer, "Register %02X: %08lX\n", i, value);
  858. }
  859. snd_iprintf(buffer, "\nRegisters\n\n");
  860. for(i = 0; i <= 0x48; i++) {
  861. value = snd_emu10k1x_ptr_read(emu, i, 0);
  862. if(i < 0x10 || (i >= 0x20 && i < 0x40)) {
  863. value1 = snd_emu10k1x_ptr_read(emu, i, 1);
  864. value2 = snd_emu10k1x_ptr_read(emu, i, 2);
  865. snd_iprintf(buffer, "%02X: %08lX %08lX %08lX\n", i, value, value1, value2);
  866. } else {
  867. snd_iprintf(buffer, "%02X: %08lX\n", i, value);
  868. }
  869. }
  870. }
  871. static void snd_emu10k1x_proc_reg_write(struct snd_info_entry *entry,
  872. struct snd_info_buffer *buffer)
  873. {
  874. struct emu10k1x *emu = entry->private_data;
  875. char line[64];
  876. unsigned int reg, channel_id , val;
  877. while (!snd_info_get_line(buffer, line, sizeof(line))) {
  878. if (sscanf(line, "%x %x %x", &reg, &channel_id, &val) != 3)
  879. continue;
  880. if ((reg < 0x49) && (reg >=0) && (val <= 0xffffffff)
  881. && (channel_id >=0) && (channel_id <= 2) )
  882. snd_emu10k1x_ptr_write(emu, reg, channel_id, val);
  883. }
  884. }
  885. static int __devinit snd_emu10k1x_proc_init(struct emu10k1x * emu)
  886. {
  887. struct snd_info_entry *entry;
  888. if(! snd_card_proc_new(emu->card, "emu10k1x_regs", &entry)) {
  889. snd_info_set_text_ops(entry, emu, snd_emu10k1x_proc_reg_read);
  890. entry->c.text.write = snd_emu10k1x_proc_reg_write;
  891. entry->mode |= S_IWUSR;
  892. entry->private_data = emu;
  893. }
  894. return 0;
  895. }
  896. static int snd_emu10k1x_shared_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  897. {
  898. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  899. uinfo->count = 1;
  900. uinfo->value.integer.min = 0;
  901. uinfo->value.integer.max = 1;
  902. return 0;
  903. }
  904. static int snd_emu10k1x_shared_spdif_get(struct snd_kcontrol *kcontrol,
  905. struct snd_ctl_elem_value *ucontrol)
  906. {
  907. struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
  908. ucontrol->value.integer.value[0] = (snd_emu10k1x_ptr_read(emu, SPDIF_SELECT, 0) == 0x700) ? 0 : 1;
  909. return 0;
  910. }
  911. static int snd_emu10k1x_shared_spdif_put(struct snd_kcontrol *kcontrol,
  912. struct snd_ctl_elem_value *ucontrol)
  913. {
  914. struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
  915. unsigned int val;
  916. int change = 0;
  917. val = ucontrol->value.integer.value[0] ;
  918. if (val) {
  919. // enable spdif output
  920. snd_emu10k1x_ptr_write(emu, SPDIF_SELECT, 0, 0x000);
  921. snd_emu10k1x_ptr_write(emu, ROUTING, 0, 0x700);
  922. snd_emu10k1x_gpio_write(emu, 0x1000);
  923. } else {
  924. // disable spdif output
  925. snd_emu10k1x_ptr_write(emu, SPDIF_SELECT, 0, 0x700);
  926. snd_emu10k1x_ptr_write(emu, ROUTING, 0, 0x1003F);
  927. snd_emu10k1x_gpio_write(emu, 0x1080);
  928. }
  929. return change;
  930. }
  931. static struct snd_kcontrol_new snd_emu10k1x_shared_spdif __devinitdata =
  932. {
  933. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  934. .name = "Analog/Digital Output Jack",
  935. .info = snd_emu10k1x_shared_spdif_info,
  936. .get = snd_emu10k1x_shared_spdif_get,
  937. .put = snd_emu10k1x_shared_spdif_put
  938. };
  939. static int snd_emu10k1x_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  940. {
  941. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  942. uinfo->count = 1;
  943. return 0;
  944. }
  945. static int snd_emu10k1x_spdif_get(struct snd_kcontrol *kcontrol,
  946. struct snd_ctl_elem_value *ucontrol)
  947. {
  948. struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
  949. unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  950. ucontrol->value.iec958.status[0] = (emu->spdif_bits[idx] >> 0) & 0xff;
  951. ucontrol->value.iec958.status[1] = (emu->spdif_bits[idx] >> 8) & 0xff;
  952. ucontrol->value.iec958.status[2] = (emu->spdif_bits[idx] >> 16) & 0xff;
  953. ucontrol->value.iec958.status[3] = (emu->spdif_bits[idx] >> 24) & 0xff;
  954. return 0;
  955. }
  956. static int snd_emu10k1x_spdif_get_mask(struct snd_kcontrol *kcontrol,
  957. struct snd_ctl_elem_value *ucontrol)
  958. {
  959. ucontrol->value.iec958.status[0] = 0xff;
  960. ucontrol->value.iec958.status[1] = 0xff;
  961. ucontrol->value.iec958.status[2] = 0xff;
  962. ucontrol->value.iec958.status[3] = 0xff;
  963. return 0;
  964. }
  965. static int snd_emu10k1x_spdif_put(struct snd_kcontrol *kcontrol,
  966. struct snd_ctl_elem_value *ucontrol)
  967. {
  968. struct emu10k1x *emu = snd_kcontrol_chip(kcontrol);
  969. unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  970. int change;
  971. unsigned int val;
  972. val = (ucontrol->value.iec958.status[0] << 0) |
  973. (ucontrol->value.iec958.status[1] << 8) |
  974. (ucontrol->value.iec958.status[2] << 16) |
  975. (ucontrol->value.iec958.status[3] << 24);
  976. change = val != emu->spdif_bits[idx];
  977. if (change) {
  978. snd_emu10k1x_ptr_write(emu, SPCS0 + idx, 0, val);
  979. emu->spdif_bits[idx] = val;
  980. }
  981. return change;
  982. }
  983. static struct snd_kcontrol_new snd_emu10k1x_spdif_mask_control =
  984. {
  985. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  986. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  987. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
  988. .count = 3,
  989. .info = snd_emu10k1x_spdif_info,
  990. .get = snd_emu10k1x_spdif_get_mask
  991. };
  992. static struct snd_kcontrol_new snd_emu10k1x_spdif_control =
  993. {
  994. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  995. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  996. .count = 3,
  997. .info = snd_emu10k1x_spdif_info,
  998. .get = snd_emu10k1x_spdif_get,
  999. .put = snd_emu10k1x_spdif_put
  1000. };
  1001. static int __devinit snd_emu10k1x_mixer(struct emu10k1x *emu)
  1002. {
  1003. int err;
  1004. struct snd_kcontrol *kctl;
  1005. struct snd_card *card = emu->card;
  1006. if ((kctl = snd_ctl_new1(&snd_emu10k1x_spdif_mask_control, emu)) == NULL)
  1007. return -ENOMEM;
  1008. if ((err = snd_ctl_add(card, kctl)))
  1009. return err;
  1010. if ((kctl = snd_ctl_new1(&snd_emu10k1x_shared_spdif, emu)) == NULL)
  1011. return -ENOMEM;
  1012. if ((err = snd_ctl_add(card, kctl)))
  1013. return err;
  1014. if ((kctl = snd_ctl_new1(&snd_emu10k1x_spdif_control, emu)) == NULL)
  1015. return -ENOMEM;
  1016. if ((err = snd_ctl_add(card, kctl)))
  1017. return err;
  1018. return 0;
  1019. }
  1020. #define EMU10K1X_MIDI_MODE_INPUT (1<<0)
  1021. #define EMU10K1X_MIDI_MODE_OUTPUT (1<<1)
  1022. static inline unsigned char mpu401_read(struct emu10k1x *emu, struct emu10k1x_midi *mpu, int idx)
  1023. {
  1024. return (unsigned char)snd_emu10k1x_ptr_read(emu, mpu->port + idx, 0);
  1025. }
  1026. static inline void mpu401_write(struct emu10k1x *emu, struct emu10k1x_midi *mpu, int data, int idx)
  1027. {
  1028. snd_emu10k1x_ptr_write(emu, mpu->port + idx, 0, data);
  1029. }
  1030. #define mpu401_write_data(emu, mpu, data) mpu401_write(emu, mpu, data, 0)
  1031. #define mpu401_write_cmd(emu, mpu, data) mpu401_write(emu, mpu, data, 1)
  1032. #define mpu401_read_data(emu, mpu) mpu401_read(emu, mpu, 0)
  1033. #define mpu401_read_stat(emu, mpu) mpu401_read(emu, mpu, 1)
  1034. #define mpu401_input_avail(emu,mpu) (!(mpu401_read_stat(emu,mpu) & 0x80))
  1035. #define mpu401_output_ready(emu,mpu) (!(mpu401_read_stat(emu,mpu) & 0x40))
  1036. #define MPU401_RESET 0xff
  1037. #define MPU401_ENTER_UART 0x3f
  1038. #define MPU401_ACK 0xfe
  1039. static void mpu401_clear_rx(struct emu10k1x *emu, struct emu10k1x_midi *mpu)
  1040. {
  1041. int timeout = 100000;
  1042. for (; timeout > 0 && mpu401_input_avail(emu, mpu); timeout--)
  1043. mpu401_read_data(emu, mpu);
  1044. #ifdef CONFIG_SND_DEBUG
  1045. if (timeout <= 0)
  1046. snd_printk(KERN_ERR "cmd: clear rx timeout (status = 0x%x)\n", mpu401_read_stat(emu, mpu));
  1047. #endif
  1048. }
  1049. /*
  1050. */
  1051. static void do_emu10k1x_midi_interrupt(struct emu10k1x *emu,
  1052. struct emu10k1x_midi *midi, unsigned int status)
  1053. {
  1054. unsigned char byte;
  1055. if (midi->rmidi == NULL) {
  1056. snd_emu10k1x_intr_disable(emu, midi->tx_enable | midi->rx_enable);
  1057. return;
  1058. }
  1059. spin_lock(&midi->input_lock);
  1060. if ((status & midi->ipr_rx) && mpu401_input_avail(emu, midi)) {
  1061. if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_INPUT)) {
  1062. mpu401_clear_rx(emu, midi);
  1063. } else {
  1064. byte = mpu401_read_data(emu, midi);
  1065. if (midi->substream_input)
  1066. snd_rawmidi_receive(midi->substream_input, &byte, 1);
  1067. }
  1068. }
  1069. spin_unlock(&midi->input_lock);
  1070. spin_lock(&midi->output_lock);
  1071. if ((status & midi->ipr_tx) && mpu401_output_ready(emu, midi)) {
  1072. if (midi->substream_output &&
  1073. snd_rawmidi_transmit(midi->substream_output, &byte, 1) == 1) {
  1074. mpu401_write_data(emu, midi, byte);
  1075. } else {
  1076. snd_emu10k1x_intr_disable(emu, midi->tx_enable);
  1077. }
  1078. }
  1079. spin_unlock(&midi->output_lock);
  1080. }
  1081. static void snd_emu10k1x_midi_interrupt(struct emu10k1x *emu, unsigned int status)
  1082. {
  1083. do_emu10k1x_midi_interrupt(emu, &emu->midi, status);
  1084. }
  1085. static int snd_emu10k1x_midi_cmd(struct emu10k1x * emu,
  1086. struct emu10k1x_midi *midi, unsigned char cmd, int ack)
  1087. {
  1088. unsigned long flags;
  1089. int timeout, ok;
  1090. spin_lock_irqsave(&midi->input_lock, flags);
  1091. mpu401_write_data(emu, midi, 0x00);
  1092. /* mpu401_clear_rx(emu, midi); */
  1093. mpu401_write_cmd(emu, midi, cmd);
  1094. if (ack) {
  1095. ok = 0;
  1096. timeout = 10000;
  1097. while (!ok && timeout-- > 0) {
  1098. if (mpu401_input_avail(emu, midi)) {
  1099. if (mpu401_read_data(emu, midi) == MPU401_ACK)
  1100. ok = 1;
  1101. }
  1102. }
  1103. if (!ok && mpu401_read_data(emu, midi) == MPU401_ACK)
  1104. ok = 1;
  1105. } else {
  1106. ok = 1;
  1107. }
  1108. spin_unlock_irqrestore(&midi->input_lock, flags);
  1109. if (!ok) {
  1110. snd_printk(KERN_ERR "midi_cmd: 0x%x failed at 0x%lx (status = 0x%x, data = 0x%x)!!!\n",
  1111. cmd, emu->port,
  1112. mpu401_read_stat(emu, midi),
  1113. mpu401_read_data(emu, midi));
  1114. return 1;
  1115. }
  1116. return 0;
  1117. }
  1118. static int snd_emu10k1x_midi_input_open(struct snd_rawmidi_substream *substream)
  1119. {
  1120. struct emu10k1x *emu;
  1121. struct emu10k1x_midi *midi = substream->rmidi->private_data;
  1122. unsigned long flags;
  1123. emu = midi->emu;
  1124. snd_assert(emu, return -ENXIO);
  1125. spin_lock_irqsave(&midi->open_lock, flags);
  1126. midi->midi_mode |= EMU10K1X_MIDI_MODE_INPUT;
  1127. midi->substream_input = substream;
  1128. if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_OUTPUT)) {
  1129. spin_unlock_irqrestore(&midi->open_lock, flags);
  1130. if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 1))
  1131. goto error_out;
  1132. if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_ENTER_UART, 1))
  1133. goto error_out;
  1134. } else {
  1135. spin_unlock_irqrestore(&midi->open_lock, flags);
  1136. }
  1137. return 0;
  1138. error_out:
  1139. return -EIO;
  1140. }
  1141. static int snd_emu10k1x_midi_output_open(struct snd_rawmidi_substream *substream)
  1142. {
  1143. struct emu10k1x *emu;
  1144. struct emu10k1x_midi *midi = substream->rmidi->private_data;
  1145. unsigned long flags;
  1146. emu = midi->emu;
  1147. snd_assert(emu, return -ENXIO);
  1148. spin_lock_irqsave(&midi->open_lock, flags);
  1149. midi->midi_mode |= EMU10K1X_MIDI_MODE_OUTPUT;
  1150. midi->substream_output = substream;
  1151. if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_INPUT)) {
  1152. spin_unlock_irqrestore(&midi->open_lock, flags);
  1153. if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 1))
  1154. goto error_out;
  1155. if (snd_emu10k1x_midi_cmd(emu, midi, MPU401_ENTER_UART, 1))
  1156. goto error_out;
  1157. } else {
  1158. spin_unlock_irqrestore(&midi->open_lock, flags);
  1159. }
  1160. return 0;
  1161. error_out:
  1162. return -EIO;
  1163. }
  1164. static int snd_emu10k1x_midi_input_close(struct snd_rawmidi_substream *substream)
  1165. {
  1166. struct emu10k1x *emu;
  1167. struct emu10k1x_midi *midi = substream->rmidi->private_data;
  1168. unsigned long flags;
  1169. int err = 0;
  1170. emu = midi->emu;
  1171. snd_assert(emu, return -ENXIO);
  1172. spin_lock_irqsave(&midi->open_lock, flags);
  1173. snd_emu10k1x_intr_disable(emu, midi->rx_enable);
  1174. midi->midi_mode &= ~EMU10K1X_MIDI_MODE_INPUT;
  1175. midi->substream_input = NULL;
  1176. if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_OUTPUT)) {
  1177. spin_unlock_irqrestore(&midi->open_lock, flags);
  1178. err = snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 0);
  1179. } else {
  1180. spin_unlock_irqrestore(&midi->open_lock, flags);
  1181. }
  1182. return err;
  1183. }
  1184. static int snd_emu10k1x_midi_output_close(struct snd_rawmidi_substream *substream)
  1185. {
  1186. struct emu10k1x *emu;
  1187. struct emu10k1x_midi *midi = substream->rmidi->private_data;
  1188. unsigned long flags;
  1189. int err = 0;
  1190. emu = midi->emu;
  1191. snd_assert(emu, return -ENXIO);
  1192. spin_lock_irqsave(&midi->open_lock, flags);
  1193. snd_emu10k1x_intr_disable(emu, midi->tx_enable);
  1194. midi->midi_mode &= ~EMU10K1X_MIDI_MODE_OUTPUT;
  1195. midi->substream_output = NULL;
  1196. if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_INPUT)) {
  1197. spin_unlock_irqrestore(&midi->open_lock, flags);
  1198. err = snd_emu10k1x_midi_cmd(emu, midi, MPU401_RESET, 0);
  1199. } else {
  1200. spin_unlock_irqrestore(&midi->open_lock, flags);
  1201. }
  1202. return err;
  1203. }
  1204. static void snd_emu10k1x_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
  1205. {
  1206. struct emu10k1x *emu;
  1207. struct emu10k1x_midi *midi = substream->rmidi->private_data;
  1208. emu = midi->emu;
  1209. snd_assert(emu, return);
  1210. if (up)
  1211. snd_emu10k1x_intr_enable(emu, midi->rx_enable);
  1212. else
  1213. snd_emu10k1x_intr_disable(emu, midi->rx_enable);
  1214. }
  1215. static void snd_emu10k1x_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
  1216. {
  1217. struct emu10k1x *emu;
  1218. struct emu10k1x_midi *midi = substream->rmidi->private_data;
  1219. unsigned long flags;
  1220. emu = midi->emu;
  1221. snd_assert(emu, return);
  1222. if (up) {
  1223. int max = 4;
  1224. unsigned char byte;
  1225. /* try to send some amount of bytes here before interrupts */
  1226. spin_lock_irqsave(&midi->output_lock, flags);
  1227. while (max > 0) {
  1228. if (mpu401_output_ready(emu, midi)) {
  1229. if (!(midi->midi_mode & EMU10K1X_MIDI_MODE_OUTPUT) ||
  1230. snd_rawmidi_transmit(substream, &byte, 1) != 1) {
  1231. /* no more data */
  1232. spin_unlock_irqrestore(&midi->output_lock, flags);
  1233. return;
  1234. }
  1235. mpu401_write_data(emu, midi, byte);
  1236. max--;
  1237. } else {
  1238. break;
  1239. }
  1240. }
  1241. spin_unlock_irqrestore(&midi->output_lock, flags);
  1242. snd_emu10k1x_intr_enable(emu, midi->tx_enable);
  1243. } else {
  1244. snd_emu10k1x_intr_disable(emu, midi->tx_enable);
  1245. }
  1246. }
  1247. /*
  1248. */
  1249. static struct snd_rawmidi_ops snd_emu10k1x_midi_output =
  1250. {
  1251. .open = snd_emu10k1x_midi_output_open,
  1252. .close = snd_emu10k1x_midi_output_close,
  1253. .trigger = snd_emu10k1x_midi_output_trigger,
  1254. };
  1255. static struct snd_rawmidi_ops snd_emu10k1x_midi_input =
  1256. {
  1257. .open = snd_emu10k1x_midi_input_open,
  1258. .close = snd_emu10k1x_midi_input_close,
  1259. .trigger = snd_emu10k1x_midi_input_trigger,
  1260. };
  1261. static void snd_emu10k1x_midi_free(struct snd_rawmidi *rmidi)
  1262. {
  1263. struct emu10k1x_midi *midi = rmidi->private_data;
  1264. midi->interrupt = NULL;
  1265. midi->rmidi = NULL;
  1266. }
  1267. static int __devinit emu10k1x_midi_init(struct emu10k1x *emu,
  1268. struct emu10k1x_midi *midi, int device, char *name)
  1269. {
  1270. struct snd_rawmidi *rmidi;
  1271. int err;
  1272. if ((err = snd_rawmidi_new(emu->card, name, device, 1, 1, &rmidi)) < 0)
  1273. return err;
  1274. midi->emu = emu;
  1275. spin_lock_init(&midi->open_lock);
  1276. spin_lock_init(&midi->input_lock);
  1277. spin_lock_init(&midi->output_lock);
  1278. strcpy(rmidi->name, name);
  1279. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_emu10k1x_midi_output);
  1280. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_emu10k1x_midi_input);
  1281. rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
  1282. SNDRV_RAWMIDI_INFO_INPUT |
  1283. SNDRV_RAWMIDI_INFO_DUPLEX;
  1284. rmidi->private_data = midi;
  1285. rmidi->private_free = snd_emu10k1x_midi_free;
  1286. midi->rmidi = rmidi;
  1287. return 0;
  1288. }
  1289. static int __devinit snd_emu10k1x_midi(struct emu10k1x *emu)
  1290. {
  1291. struct emu10k1x_midi *midi = &emu->midi;
  1292. int err;
  1293. if ((err = emu10k1x_midi_init(emu, midi, 0, "EMU10K1X MPU-401 (UART)")) < 0)
  1294. return err;
  1295. midi->tx_enable = INTE_MIDITXENABLE;
  1296. midi->rx_enable = INTE_MIDIRXENABLE;
  1297. midi->port = MUDATA;
  1298. midi->ipr_tx = IPR_MIDITRANSBUFEMPTY;
  1299. midi->ipr_rx = IPR_MIDIRECVBUFEMPTY;
  1300. midi->interrupt = snd_emu10k1x_midi_interrupt;
  1301. return 0;
  1302. }
  1303. static int __devinit snd_emu10k1x_probe(struct pci_dev *pci,
  1304. const struct pci_device_id *pci_id)
  1305. {
  1306. static int dev;
  1307. struct snd_card *card;
  1308. struct emu10k1x *chip;
  1309. int err;
  1310. if (dev >= SNDRV_CARDS)
  1311. return -ENODEV;
  1312. if (!enable[dev]) {
  1313. dev++;
  1314. return -ENOENT;
  1315. }
  1316. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
  1317. if (card == NULL)
  1318. return -ENOMEM;
  1319. if ((err = snd_emu10k1x_create(card, pci, &chip)) < 0) {
  1320. snd_card_free(card);
  1321. return err;
  1322. }
  1323. if ((err = snd_emu10k1x_pcm(chip, 0, NULL)) < 0) {
  1324. snd_card_free(card);
  1325. return err;
  1326. }
  1327. if ((err = snd_emu10k1x_pcm(chip, 1, NULL)) < 0) {
  1328. snd_card_free(card);
  1329. return err;
  1330. }
  1331. if ((err = snd_emu10k1x_pcm(chip, 2, NULL)) < 0) {
  1332. snd_card_free(card);
  1333. return err;
  1334. }
  1335. if ((err = snd_emu10k1x_ac97(chip)) < 0) {
  1336. snd_card_free(card);
  1337. return err;
  1338. }
  1339. if ((err = snd_emu10k1x_mixer(chip)) < 0) {
  1340. snd_card_free(card);
  1341. return err;
  1342. }
  1343. if ((err = snd_emu10k1x_midi(chip)) < 0) {
  1344. snd_card_free(card);
  1345. return err;
  1346. }
  1347. snd_emu10k1x_proc_init(chip);
  1348. strcpy(card->driver, "EMU10K1X");
  1349. strcpy(card->shortname, "Dell Sound Blaster Live!");
  1350. sprintf(card->longname, "%s at 0x%lx irq %i",
  1351. card->shortname, chip->port, chip->irq);
  1352. if ((err = snd_card_register(card)) < 0) {
  1353. snd_card_free(card);
  1354. return err;
  1355. }
  1356. pci_set_drvdata(pci, card);
  1357. dev++;
  1358. return 0;
  1359. }
  1360. static void __devexit snd_emu10k1x_remove(struct pci_dev *pci)
  1361. {
  1362. snd_card_free(pci_get_drvdata(pci));
  1363. pci_set_drvdata(pci, NULL);
  1364. }
  1365. // PCI IDs
  1366. static struct pci_device_id snd_emu10k1x_ids[] = {
  1367. { 0x1102, 0x0006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* Dell OEM version (EMU10K1) */
  1368. { 0, }
  1369. };
  1370. MODULE_DEVICE_TABLE(pci, snd_emu10k1x_ids);
  1371. // pci_driver definition
  1372. static struct pci_driver driver = {
  1373. .name = "EMU10K1X",
  1374. .id_table = snd_emu10k1x_ids,
  1375. .probe = snd_emu10k1x_probe,
  1376. .remove = __devexit_p(snd_emu10k1x_remove),
  1377. };
  1378. // initialization of the module
  1379. static int __init alsa_card_emu10k1x_init(void)
  1380. {
  1381. return pci_register_driver(&driver);
  1382. }
  1383. // clean up the module
  1384. static void __exit alsa_card_emu10k1x_exit(void)
  1385. {
  1386. pci_unregister_driver(&driver);
  1387. }
  1388. module_init(alsa_card_emu10k1x_init)
  1389. module_exit(alsa_card_emu10k1x_exit)